2 ******************************************************************************
4 * @author StarFive Technology
8 ******************************************************************************
11 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
21 #ifndef __SND_SOC_STARFIVE_SPDIF_H
22 #define __SND_SOC_STARFIVE_SPDIF_H
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/types.h>
27 #include <sound/dmaengine_pcm.h>
28 #include <sound/pcm.h>
29 #include <linux/dmaengine.h>
30 #include <linux/types.h>
32 #define SPDIF_CTRL (0x0)
33 #define SPDIF_INT_REG (0x4)
34 #define SPDIF_FIFO_CTRL (0x8)
35 #define SPDIF_STAT_REG (0xC)
37 #define SPDIF_FIFO_ADDR (0x100)
38 #define DMAC_SPDIF_POLLING_LEN (256)
40 ///ctrl: sampled on the rising clock edge
41 #define SPDIF_TSAMPLERATE 0///[SRATEW-1:0]
42 #define SPDIF_SFR_ENABLE (1<<8) ///0:SFR reg reset to defualt value; auto set back to '1' after reset
43 #define SPDIF_ENABLE (1<<9) ///0:reset of SPDIF block, SRF bits are unchanged; 1:enables SPDIF module
44 #define SPDIF_FIFO_ENABLE (1<<10) ///0:FIFO pointers are reset to zero,threshold levels for FIFO are unchaned; auto set back to '1'
45 #define SPDIF_CLK_ENABLE (1<<11) ///1:blocked and the modules are in power save mode; 0:block feeds the modules
46 #define SPDIF_TR_MODE (1<<12) ///0:rx; 1:tx
47 #define SPDIF_PARITCHECK (1<<13) ///0:party bit rx in a sub-frame is repeated on the parity; 1:check on a parity error
48 #define SPDIF_PARITYGEN (1<<14) ///0:parity bit from FIFO is transmitted in sub-frame;1:parity bit generated inside the core and added to a transmitted sub-frame
49 #define SPDIF_VALIDITYCHECK (1<<15) ///0:validity bit in frame isn't checked and all frame are written; 1:validity bit rx is checked
50 #define SPDIF_CHANNEL_MODE (1<<16) ///0:two-channel; 1:single-channel
51 #define SPDIF_DUPLICATE (1<<17) ///only tx -single-channel mode; 0:secondary channel; 1: left(primary) channel
52 #define SPDIF_SETPREAMBB (1<<18) ///only tx; 0:first preamble B after reset tx valid sub-frame; 1:first preamble B is tx after preambleddel(INT_REG)
53 #define SPDIF_USE_FIFO_IF (1<<19) ///0:FIFO disabled ,APB accese FIFO; 1:FIFO enable, APB access to FIFO disable;
54 ///#define RESERVED (1<<20)
55 #define SPDIF_PARITY_MASK (1<<21)
56 #define SPDIF_UNDERR_MASK (1<<22)
57 #define SPDIF_OVRERR_MASK (1<<23)
58 #define SPDIF_EMPTY_MASK (1<<24)
59 #define SPDIF_AEMPTY_MASK (1<<25)
60 #define SPDIF_FULL_MASK (1<<26)
61 #define SPDIF_AFULL_MASK (1<<27)
62 #define SPDIF_SYNCERR_MASK (1<<28)
63 #define SPDIF_LOCK_MASK (1<<29)
64 #define SPDIF_BEGIN_MASK (1<<30)
65 #define SPDIF_INTEREQ_MAKS (1<<31)
67 #define SPDIF_MASK_ENABLE (SPDIF_PARITY_MASK | SPDIF_UNDERR_MASK | SPDIF_OVRERR_MASK | SPDIF_EMPTY_MASK | \
68 SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK | SPDIF_SYNCERR_MASK | \
69 SPDIF_LOCK_MASK | SPDIF_BEGIN_MASK | SPDIF_INTEREQ_MAKS)
71 #define SPDIF_MASK_FIFO (SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK)
74 #define SPDIF_RSAMPLERATE 0 ///[SRATEW-1:0]
75 #define SPDIF_PREAMBLEDEL 8 ///[PDELAYW+7:8] first B delay
76 #define SPDIF_PARITYO (1<<21) ///0:clear parity error
77 #define SPDIF_TDATA_UNDERR (1<<22) ///tx data underrun error;0:clear
78 #define SPDIF_RDATA_OVRERR (1<<23) ///rx data overrun error; 0:clear
79 #define SPDIF_FIFO_EMPTY (1<<24) ///empty; 0:clear
80 #define SPDIF_FIOF_AEMPTY (1<<25) ///almost empty; 0:clear
81 #define SPDIF_FIFO_FULL (1<<26) ///FIFO full; 0:clear
82 #define SPDIF_FIFO_AFULL (1<<27) ///FIFO almost full; 0:clear
83 #define SPDIF_SYNCERR (1<<28) ///sync error; 0:clear
84 #define SPDIF_LOCK (1<<29) ///sync; 0:clear
85 #define SPDIF_BLOCK_BEGIN (1<<30) ///new start block rx data
87 #define SPDIF_INT_REG_BIT (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR | SPDIF_FIFO_EMPTY | \
88 SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL | SPDIF_SYNCERR | \
89 SPDIF_LOCK | SPDIF_BLOCK_BEGIN)
91 #define SPDIF_ERROR_INT_STATUS (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR)
92 #define SPDIF_FIFO_INT_STATUS (SPDIF_FIFO_EMPTY | SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL)
94 #define SPDIF_INT_PARITY_ERROR (-1)
95 #define SPDIF_INT_TDATA_UNDERR (-2)
96 #define SPDIF_INT_RDATA_OVRERR (-3)
97 #define SPDIF_INT_FIFO_EMPTY 1
98 #define SPDIF_INT_FIFO_AEMPTY 2
99 #define SPDIF_INT_FIFO_FULL 3
100 #define SPDIF_INT_FIFO_AFULL 4
101 #define SPDIF_INT_SYNCERR (-4)
102 #define SPDIF_INT_LOCK 5 ///reciever has become synchronized with input data stream
103 #define SPDIF_INT_BLOCK_BEGIN 6 ///start a new block in recieve data, written into FIFO
106 #define SPDIF_AEMPTY_THRESHOLD 0///[depth-1:0]
107 #define SPDIF_AFULL_THRESHOLD 16///[depth+15:16]
110 #define SPDIF_FIFO_LEVEL (1<<0)
111 #define SPDIF_PARITY_FLAG (1<<21) ///1:error; 0:repeated
112 #define SPDIF_UNDERR_FLAG (1<<22) ///1:error
113 #define SPDIF_OVRERR_FLAG (1<<23) ///1:error
114 #define SPDIF_EMPTY_FLAG (1<<24) ///1:fifo empty
115 #define SPDIF_AEMPTY_FLAG (1<<25) ///1:fifo almost empty
116 #define SPDIF_FULL_FLAG (1<<26) ///1:fifo full
117 #define SPDIF_AFULL_FLAG (1<<27) ///1:fifo almost full
118 #define SPDIF_SYNCERR_FLAG (1<<28) ///1:rx sync error
119 #define SPDIF_LOCK_FLAG (1<<29) ///1:RX sync
120 #define SPDIF_BEGIN_FLAG (1<<30) ///1:start a new block
121 #define SPDIF_RIGHT_LEFT (1<<31) ///1:left channel received and tx into FIFO; 0:right channel received and tx into FIFO
123 #define SPDIF_STAT (SPDIF_PARITY_FLAG | SPDIF_UNDERR_FLAG | SPDIF_OVRERR_FLAG | SPDIF_EMPTY_FLAG | \
124 SPDIF_AEMPTY_FLAG | SPDIF_FULL_FLAG | SPDIF_AFULL_FLAG | SPDIF_SYNCERR_FLAG | \
125 SPDIF_LOCK_FLAG | SPDIF_BEGIN_FLAG | SPDIF_RIGHT_LEFT)
126 struct sf_spdif_dev {
127 void __iomem *spdif_base;
128 struct regmap *regmap;
133 /* data related to DMA transfers b/w i2s and DMAC */
134 struct snd_dmaengine_dai_dma_data play_dma_data;
135 struct snd_dmaengine_dai_dma_data capture_dma_data;
138 struct snd_pcm_substream __rcu *tx_substream;
139 struct snd_pcm_substream __rcu *rx_substream;
141 unsigned int (*tx_fn)(struct sf_spdif_dev *dev,
142 struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
143 bool *period_elapsed, snd_pcm_format_t format);
144 unsigned int (*rx_fn)(struct sf_spdif_dev *dev,
145 struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
146 bool *period_elapsed, snd_pcm_format_t format);
148 snd_pcm_format_t format;
149 //unsigned int sample_bits;
153 struct snd_dmaengine_dai_dma_data dma_data;
156 #if IS_ENABLED(CONFIG_SND_STARFIVE_SPDIF_PCM)
157 void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev);
158 void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev);
159 int sf_spdif_pcm_register(struct platform_device *pdev);
161 void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev) { }
162 void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev) { }
163 int sf_spdif_pcm_register(struct platform_device *pdev)
170 #endif /* __SND_SOC_STARFIVE_SPDIF_H */