1 /* SPDX-License-Identifier: GPL-2.0 */
3 * SPDIF driver for the StarFive JH7110 SoC
5 * Copyright (C) 2022 StarFive Technology Co., Ltd.
8 #ifndef __SND_SOC_STARFIVE_SPDIF_H
9 #define __SND_SOC_STARFIVE_SPDIF_H
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/types.h>
14 #include <sound/dmaengine_pcm.h>
15 #include <sound/pcm.h>
16 #include <linux/dmaengine.h>
17 #include <linux/types.h>
19 #define SPDIF_CTRL 0x0
20 #define SPDIF_INT_REG 0x4
21 #define SPDIF_FIFO_CTRL 0x8
22 #define SPDIF_STAT_REG 0xC
24 #define SPDIF_FIFO_ADDR 0x100
25 #define DMAC_SPDIF_POLLING_LEN 256
27 /* ctrl: sampled on the rising clock edge */
28 #define SPDIF_TSAMPLERATE 0 /* [SRATEW-1:0] */
29 #define SPDIF_SFR_ENABLE (1<<8) /* 0:SFR reg reset to defualt value; auto set back to '1' after reset */
30 #define SPDIF_ENABLE (1<<9) /* 0:reset of SPDIF block, SRF bits are unchanged; 1:enables SPDIF module */
31 #define SPDIF_FIFO_ENABLE (1<<10) /* 0:FIFO pointers are reset to zero,threshold levels for FIFO are unchaned; auto set back to '1' */
32 #define SPDIF_CLK_ENABLE (1<<11) /* 1:blocked and the modules are in power save mode; 0:block feeds the modules */
33 #define SPDIF_TR_MODE (1<<12) /* 0:rx; 1:tx */
34 #define SPDIF_PARITCHECK (1<<13) /* 0:party bit rx in a sub-frame is repeated on the parity; 1:check on a parity error */
35 #define SPDIF_PARITYGEN (1<<14) /* 0:parity bit from FIFO is transmitted in sub-frame;1:parity bit generated inside the core and added to a transmitted sub-frame */
36 #define SPDIF_VALIDITYCHECK (1<<15) /* 0:validity bit in frame isn't checked and all frame are written; 1:validity bit rx is checked */
37 #define SPDIF_CHANNEL_MODE (1<<16) /* 0:two-channel; 1:single-channel */
38 #define SPDIF_DUPLICATE (1<<17) /* only tx -single-channel mode; 0:secondary channel; 1: left(primary) channel */
39 #define SPDIF_SETPREAMBB (1<<18) /* only tx; 0:first preamble B after reset tx valid sub-frame; 1:first preamble B is tx after preambleddel(INT_REG) */
40 #define SPDIF_USE_FIFO_IF (1<<19) /* 0:FIFO disabled ,APB accese FIFO; 1:FIFO enable, APB access to FIFO disable; */
41 #define SPDIF_PARITY_MASK (1<<21)
42 #define SPDIF_UNDERR_MASK (1<<22)
43 #define SPDIF_OVRERR_MASK (1<<23)
44 #define SPDIF_EMPTY_MASK (1<<24)
45 #define SPDIF_AEMPTY_MASK (1<<25)
46 #define SPDIF_FULL_MASK (1<<26)
47 #define SPDIF_AFULL_MASK (1<<27)
48 #define SPDIF_SYNCERR_MASK (1<<28)
49 #define SPDIF_LOCK_MASK (1<<29)
50 #define SPDIF_BEGIN_MASK (1<<30)
51 #define SPDIF_INTEREQ_MAKS (1<<31)
53 #define SPDIF_MASK_ENABLE (SPDIF_PARITY_MASK | SPDIF_UNDERR_MASK | \
54 SPDIF_OVRERR_MASK | SPDIF_EMPTY_MASK | \
55 SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | \
56 SPDIF_AFULL_MASK | SPDIF_SYNCERR_MASK | \
57 SPDIF_LOCK_MASK | SPDIF_BEGIN_MASK | \
60 #define SPDIF_MASK_FIFO (SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK | \
61 SPDIF_FULL_MASK | SPDIF_AFULL_MASK)
64 #define SPDIF_RSAMPLERATE 0 /* [SRATEW-1:0] */
65 #define SPDIF_PREAMBLEDEL 8 /* [PDELAYW+7:8] first B delay */
66 #define SPDIF_PARITYO (1<<21) /* 0:clear parity error */
67 #define SPDIF_TDATA_UNDERR (1<<22) /* tx data underrun error;0:clear */
68 #define SPDIF_RDATA_OVRERR (1<<23) /* rx data overrun error; 0:clear */
69 #define SPDIF_FIFO_EMPTY (1<<24) /* empty; 0:clear */
70 #define SPDIF_FIOF_AEMPTY (1<<25) /* almost empty; 0:clear */
71 #define SPDIF_FIFO_FULL (1<<26) /* FIFO full; 0:clear */
72 #define SPDIF_FIFO_AFULL (1<<27) /* FIFO almost full; 0:clear */
73 #define SPDIF_SYNCERR (1<<28) /* sync error; 0:clear */
74 #define SPDIF_LOCK (1<<29) /* sync; 0:clear */
75 #define SPDIF_BLOCK_BEGIN (1<<30) /* new start block rx data */
77 #define SPDIF_INT_REG_BIT (SPDIF_PARITYO | SPDIF_TDATA_UNDERR | \
78 SPDIF_RDATA_OVRERR | SPDIF_FIFO_EMPTY | \
79 SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | \
80 SPDIF_FIFO_AFULL | SPDIF_SYNCERR | \
81 SPDIF_LOCK | SPDIF_BLOCK_BEGIN)
83 #define SPDIF_ERROR_INT_STATUS (SPDIF_PARITYO | \
84 SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR)
85 #define SPDIF_FIFO_INT_STATUS (SPDIF_FIFO_EMPTY | SPDIF_FIOF_AEMPTY | \
86 SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL)
88 #define SPDIF_INT_PARITY_ERROR (-1)
89 #define SPDIF_INT_TDATA_UNDERR (-2)
90 #define SPDIF_INT_RDATA_OVRERR (-3)
91 #define SPDIF_INT_FIFO_EMPTY 1
92 #define SPDIF_INT_FIFO_AEMPTY 2
93 #define SPDIF_INT_FIFO_FULL 3
94 #define SPDIF_INT_FIFO_AFULL 4
95 #define SPDIF_INT_SYNCERR (-4)
96 #define SPDIF_INT_LOCK 5 /* reciever has become synchronized with input data stream */
97 #define SPDIF_INT_BLOCK_BEGIN 6 /* start a new block in recieve data, written into FIFO */
100 #define SPDIF_AEMPTY_THRESHOLD 0 /* [depth-1:0] */
101 #define SPDIF_AFULL_THRESHOLD 16 /* [depth+15:16] */
104 #define SPDIF_FIFO_LEVEL (1<<0)
105 #define SPDIF_PARITY_FLAG (1<<21) /* 1:error; 0:repeated */
106 #define SPDIF_UNDERR_FLAG (1<<22) /* 1:error */
107 #define SPDIF_OVRERR_FLAG (1<<23) /* 1:error */
108 #define SPDIF_EMPTY_FLAG (1<<24) /* 1:fifo empty */
109 #define SPDIF_AEMPTY_FLAG (1<<25) /* 1:fifo almost empty */
110 #define SPDIF_FULL_FLAG (1<<26) /* 1:fifo full */
111 #define SPDIF_AFULL_FLAG (1<<27) /* 1:fifo almost full */
112 #define SPDIF_SYNCERR_FLAG (1<<28) /* 1:rx sync error */
113 #define SPDIF_LOCK_FLAG (1<<29) /* 1:RX sync */
114 #define SPDIF_BEGIN_FLAG (1<<30) /* 1:start a new block */
115 #define SPDIF_RIGHT_LEFT (1<<31) /* 1:left channel received and tx into FIFO; 0:right channel received and tx into FIFO */
117 #define BIT8TO20MASK 0x1FFF
118 #define ALLBITMASK 0xFFFFFFFF
120 #define SPDIF_STAT (SPDIF_PARITY_FLAG | SPDIF_UNDERR_FLAG | \
121 SPDIF_OVRERR_FLAG | SPDIF_EMPTY_FLAG | \
122 SPDIF_AEMPTY_FLAG | SPDIF_FULL_FLAG | \
123 SPDIF_AFULL_FLAG | SPDIF_SYNCERR_FLAG | \
124 SPDIF_LOCK_FLAG | SPDIF_BEGIN_FLAG | \
126 struct sf_spdif_dev {
127 void __iomem *spdif_base;
128 struct regmap *regmap;
133 /* data related to DMA transfers b/w i2s and DMAC */
134 struct snd_dmaengine_dai_dma_data play_dma_data;
135 struct snd_dmaengine_dai_dma_data capture_dma_data;
138 struct snd_pcm_substream __rcu *tx_substream;
139 struct snd_pcm_substream __rcu *rx_substream;
141 unsigned int (*tx_fn)(struct sf_spdif_dev *dev,
142 struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
143 bool *period_elapsed, snd_pcm_format_t format);
144 unsigned int (*rx_fn)(struct sf_spdif_dev *dev,
145 struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
146 bool *period_elapsed, snd_pcm_format_t format);
148 snd_pcm_format_t format;
152 struct clk *spdif_apb;
153 struct clk *spdif_core;
154 struct clk *audio_root;
155 struct clk *mclk_inner;
156 struct reset_control *rst_apb;
158 struct snd_dmaengine_dai_dma_data dma_data;
161 #if IS_ENABLED(CONFIG_SND_SOC_STARFIVE_SPDIF_PCM)
162 void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev);
163 void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev);
164 int sf_spdif_pcm_register(struct platform_device *pdev);
166 void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev) { }
167 void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev) { }
168 int sf_spdif_pcm_register(struct platform_device *pdev)
175 #endif /* __SND_SOC_STARFIVE_SPDIF_H */