sound/soc/starfive/starfive_i2s.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ALSA SoC Synopsys I2S Audio Layer
   4  *
   5  * sound/soc/dwc/designware_i2s.c
   6  *
   7  * Copyright (C) 2010 ST Microelectronics
   8  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2. This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/module.h>
  21 #include <linux/slab.h>
  22 #include <linux/pm_runtime.h>
  23 #include <sound/designware_i2s.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/dmaengine_pcm.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30 #include "starfive_i2s.h"
  31
  32 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
  33 {
  34         writel(val, io_base + reg);
  35 }
  36
  37 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
  38 {
  39         return readl(io_base + reg);
  40 }
  41
  42 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
  43 {
  44         u32 i = 0;
  45
  46         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  47                 for (i = 0; i < 4; i++)
  48                         i2s_write_reg(dev->i2s_base, TER(i), 0);
  49         } else {
  50                 for (i = 0; i < 4; i++)
  51                         i2s_write_reg(dev->i2s_base, RER(i), 0);
  52         }
  53 }
  54
  55 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
  56 {
  57         u32 i = 0;
  58
  59         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  60                 for (i = 0; i < 4; i++)
  61                         i2s_read_reg(dev->i2s_base, TOR(i));
  62         } else {
  63                 for (i = 0; i < 4; i++)
  64                         i2s_read_reg(dev->i2s_base, ROR(i));
  65         }
  66 }
  67
  68 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
  69                                     int chan_nr)
  70 {
  71         u32 i, irq;
  72
  73         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  74                 for (i = 0; i < (chan_nr / 2); i++) {
  75                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  76                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
  77                 }
  78         } else {
  79                 for (i = 0; i < (chan_nr / 2); i++) {
  80                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  81                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
  82                 }
  83         }
  84 }
  85
  86 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
  87                                    int chan_nr)
  88 {
  89         u32 i, irq;
  90
  91         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  92                 for (i = 0; i < (chan_nr / 2); i++) {
  93                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  94                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
  95                 }
  96         } else {
  97                 for (i = 0; i < (chan_nr / 2); i++) {
  98                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  99                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
 100                 }
 101         }
 102 }
 103
 104 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
 105 {
 106         struct dw_i2s_dev *dev = dev_id;
 107         bool irq_valid = false;
 108         u32 isr[4];
 109         int i;
 110
 111         for (i = 0; i < 4; i++)
 112                 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
 113
 114         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
 115         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
 116
 117         for (i = 0; i < 4; i++) {
 118                 /*
 119                  * Check if TX fifo is empty. If empty fill FIFO with samples
 120                  * NOTE: Only two channels supported
 121                  */
 122                 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
 123                         dw_pcm_push_tx(dev);
 124                         irq_valid = true;
 125                 }
 126
 127                 /*
 128                  * Data available. Retrieve samples from FIFO
 129                  * NOTE: Only two channels supported
 130                  */
 131                 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
 132                         dw_pcm_pop_rx(dev);
 133                         irq_valid = true;
 134                 }
 135
 136                 /* Error Handling: TX */
 137                 if (isr[i] & ISR_TXFO) {
 138                         dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
 139                         irq_valid = true;
 140                 }
 141
 142                 /* Error Handling: TX */
 143                 if (isr[i] & ISR_RXFO) {
 144                         dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
 145                         irq_valid = true;
 146                 }
 147         }
 148
 149         if (irq_valid)
 150                 return IRQ_HANDLED;
 151         else
 152                 return IRQ_NONE;
 153 }
 154
 155 static void i2s_start(struct dw_i2s_dev *dev,
 156                       struct snd_pcm_substream *substream)
 157 {
 158         struct i2s_clk_config_data *config = &dev->config;
 159
 160         i2s_write_reg(dev->i2s_base, IER, 1);
 161         i2s_enable_irqs(dev, substream->stream, config->chan_nr);
 162
 163         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 164                 i2s_write_reg(dev->i2s_base, ITER, 1);
 165         else
 166                 i2s_write_reg(dev->i2s_base, IRER, 1);
 167
 168         i2s_write_reg(dev->i2s_base, CER, 1);
 169
 170 }
 171
 172 static void i2s_stop(struct dw_i2s_dev *dev,
 173                 struct snd_pcm_substream *substream)
 174 {
 175         i2s_clear_irqs(dev, substream->stream);
 176         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 177                 i2s_write_reg(dev->i2s_base, ITER, 0);
 178         else
 179                 i2s_write_reg(dev->i2s_base, IRER, 0);
 180
 181         i2s_disable_irqs(dev, substream->stream, 8);
 182
 183         if (!dev->active) {
 184                 i2s_write_reg(dev->i2s_base, CER, 0);
 185                 i2s_write_reg(dev->i2s_base, IER, 0);
 186         }
 187 }
 188
 189 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
 190 {
 191         u32 ch_reg;
 192         struct i2s_clk_config_data *config = &dev->config;
 193
 194         i2s_disable_channels(dev, stream);
 195
 196         for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
 197                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 198                         i2s_write_reg(dev->i2s_base, TCR(ch_reg),
 199                                       dev->xfer_resolution);
 200                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
 201                                       dev->fifo_th - 1);
 202                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
 203                 } else {
 204                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
 205                                       dev->xfer_resolution);
 206                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
 207                                       dev->fifo_th - 1);
 208                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
 209                 }
 210         }
 211 }
 212
 213 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 214                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 215 {
 216         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 217         struct i2s_clk_config_data *config = &dev->config;
 218         int ret;
 219         unsigned int bclk_rate;
 220         union dw_i2s_snd_dma_data *dma_data = NULL;
 221         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 222         struct snd_soc_dai_link *dai_link = rtd->dai_link;
 223
 224         dai_link->stop_dma_first = 1;
 225
 226         switch (params_format(params)) {
 227         case SNDRV_PCM_FORMAT_S16_LE:
 228                 config->data_width = 16;
 229                 dev->ccr = 0x00;
 230                 dev->xfer_resolution = 0x02;
 231                 dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 232                 break;
 233
 234         case SNDRV_PCM_FORMAT_S32_LE:
 235                 config->data_width = 32;
 236                 dev->ccr = 0x10;
 237                 dev->xfer_resolution = 0x05;
 238                 dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 239                 break;
 240
 241         default:
 242                 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
 243                 return -EINVAL;
 244         }
 245
 246         switch (params_rate(params)) {
 247         case 32000:
 248                 bclk_rate = 2048000;
 249                 break;
 250         case 48000:
 251                 bclk_rate = 3072000;
 252                 break;
 253         default:
 254                 dev_err(dai->dev, "%d rate not supported\n",
 255                                 params_rate(params));
 256                 return -EINVAL;
 257         }
 258
 259         config->chan_nr = params_channels(params);
 260
 261         switch (config->chan_nr) {
 262         case EIGHT_CHANNEL_SUPPORT:
 263         case SIX_CHANNEL_SUPPORT:
 264         case FOUR_CHANNEL_SUPPORT:
 265         case TWO_CHANNEL_SUPPORT:
 266                 break;
 267         default:
 268                 dev_err(dev->dev, "channel not supported\n");
 269                 return -EINVAL;
 270         }
 271
 272         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 273                 dma_data = &dev->capture_dma_data;
 274         else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 275                 dma_data = &dev->play_dma_data;
 276         snd_soc_dai_set_dma_data(dai, substream, (void *)dma_data);
 277
 278         dw_i2s_config(dev, substream->stream);
 279
 280         i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
 281
 282         config->sample_rate = params_rate(params);
 283
 284         if (dev->capability & DW_I2S_MASTER) {
 285                 if (dev->i2s_clk_cfg) {
 286                         ret = dev->i2s_clk_cfg(config);
 287                         if (ret < 0) {
 288                                 dev_err(dev->dev, "runtime audio clk config fail\n");
 289                                 goto err_return;
 290                         }
 291                 } else {
 292                         ret = clk_set_parent(dev->clk_mclk, dev->clk_mclk_ext);
 293                         if (ret) {
 294                                 dev_err(dev->dev, "failed to set mclk parent to mclk_ext\n");
 295                                 goto err_return;
 296                         }
 297
 298                         ret = clk_set_rate(dev->clk_i2s_bclk_mst, bclk_rate);
 299                         if (ret) {
 300                                 dev_err(dev->dev, "Can't set i2s bclk: %d\n", ret);
 301                                 goto err_return;
 302                         }
 303
 304                         dev_dbg(dev->dev, "get rate mclk: %ld\n",
 305                                 clk_get_rate(dev->clk_mclk));
 306                         dev_dbg(dev->dev, "get rate bclk:%ld\n",
 307                                 clk_get_rate(dev->clk_i2s_bclk));
 308                         dev_dbg(dev->dev, "get rate lrck:%ld\n",
 309                                 clk_get_rate(dev->clk_i2s_lrck));
 310                 }
 311         }
 312         return 0;
 313
 314 err_return:
 315         return ret;
 316 }
 317
 318 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
 319                           struct snd_soc_dai *dai)
 320 {
 321         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 322
 323         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 324                 i2s_write_reg(dev->i2s_base, TXFFR, 1);
 325         else
 326                 i2s_write_reg(dev->i2s_base, RXFFR, 1);
 327
 328         return 0;
 329 }
 330
 331 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 332                 int cmd, struct snd_soc_dai *dai)
 333 {
 334         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 335         int ret = 0;
 336
 337         switch (cmd) {
 338         case SNDRV_PCM_TRIGGER_START:
 339         case SNDRV_PCM_TRIGGER_RESUME:
 340         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 341                 dev->active++;
 342                 i2s_start(dev, substream);
 343                 break;
 344
 345         case SNDRV_PCM_TRIGGER_STOP:
 346         case SNDRV_PCM_TRIGGER_SUSPEND:
 347         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 348                 dev->active--;
 349                 i2s_stop(dev, substream);
 350                 break;
 351         default:
 352                 ret = -EINVAL;
 353                 break;
 354         }
 355         return ret;
 356 }
 357
 358 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 359 {
 360         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 361         int ret = 0;
 362
 363         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 364         case SND_SOC_DAIFMT_CBM_CFM:
 365                 if (dev->capability & DW_I2S_SLAVE)
 366                         ret = 0;
 367                 else
 368                         ret = -EINVAL;
 369                 break;
 370         case SND_SOC_DAIFMT_CBS_CFS:
 371                 if (dev->capability & DW_I2S_MASTER)
 372                         ret = 0;
 373                 else
 374                         ret = -EINVAL;
 375                 break;
 376         case SND_SOC_DAIFMT_CBM_CFS:
 377         case SND_SOC_DAIFMT_CBS_CFM:
 378                 ret = -EINVAL;
 379                 break;
 380         default:
 381                 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
 382                 ret = -EINVAL;
 383                 break;
 384         }
 385         return ret;
 386 }
 387
 388 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
 389         .hw_params      = dw_i2s_hw_params,
 390         .prepare        = dw_i2s_prepare,
 391         .trigger        = dw_i2s_trigger,
 392         .set_fmt        = dw_i2s_set_fmt,
 393 };
 394
 395 #ifdef CONFIG_PM
 396 static int dw_i2s_runtime_suspend(struct device *dev)
 397 {
 398         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 399
 400         if (dw_dev->capability & DW_I2S_MASTER) {
 401                 clk_disable_unprepare(dw_dev->clk_i2s_lrck);
 402                 clk_disable_unprepare(dw_dev->clk_i2s_bclk);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int dw_i2s_runtime_resume(struct device *dev)
 409 {
 410         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 411         int ret;
 412
 413         if (dw_dev->capability & DW_I2S_MASTER) {
 414                 ret = clk_prepare_enable(dw_dev->clk_i2s_bclk);
 415                 if (ret) {
 416                         dev_err(dw_dev->dev, "Failed to enable clk_i2s_bclk\n");
 417                         return ret;
 418                 }
 419
 420                 ret = clk_prepare_enable(dw_dev->clk_i2s_lrck);
 421                 if (ret) {
 422                         dev_err(dw_dev->dev, "Failed to enable clk_i2s_lrck\n");
 423                         return ret;
 424                 }
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int dw_i2s_suspend(struct snd_soc_component *component)
 431 {
 432         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 433
 434         if (dev->capability & DW_I2S_MASTER) {
 435                 clk_disable_unprepare(dev->clk_i2s_lrck);
 436                 clk_disable_unprepare(dev->clk_i2s_bclk);
 437         }
 438
 439         return 0;
 440 }
 441
 442 static int dw_i2s_resume(struct snd_soc_component *component)
 443 {
 444         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 445         struct snd_soc_dai *dai;
 446         int stream;
 447         int ret;
 448
 449         if (dev->capability & DW_I2S_MASTER) {
 450                 ret = clk_prepare_enable(dev->clk_i2s_bclk);
 451                 if (ret) {
 452                         dev_err(dev->dev, "Failed to enable clk_i2s_bclk\n");
 453                         return ret;
 454                 }
 455
 456                 ret = clk_prepare_enable(dev->clk_i2s_lrck);
 457                 if (ret) {
 458                         dev_err(dev->dev, "Failed to enable clk_i2s_lrck\n");
 459                         return ret;
 460                 }
 461         }
 462
 463         for_each_component_dais(component, dai) {
 464                 for_each_pcm_streams(stream)
 465                         if (snd_soc_dai_stream_active(dai, stream))
 466                                 dw_i2s_config(dev, stream);
 467         }
 468
 469         return 0;
 470 }
 471
 472 #else
 473 #define dw_i2s_suspend  NULL
 474 #define dw_i2s_resume   NULL
 475 #endif
 476
 477 static const struct snd_soc_component_driver dw_i2s_component = {
 478         .name           = "dw-i2s",
 479         .suspend        = dw_i2s_suspend,
 480         .resume         = dw_i2s_resume,
 481 };
 482
 483 static int dw_i2stx_4ch0_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 484 {
 485         int ret = 0;
 486
 487         static struct clk_bulk_data clks[] = {
 488                 { .id = "bclk-mst" },
 489                 { .id = "lrck-mst" },
 490                 { .id = "mclk" },
 491                 { .id = "bclk0" },
 492                 { .id = "lrck0" },
 493                 { .id = "i2s_apb" },
 494                 { .id = "mclk_ext" },
 495         };
 496
 497         ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
 498         if (ret) {
 499                 dev_err(&pdev->dev, "%s: failed to get i2s clocks\n", __func__);
 500                 goto exit;
 501         }
 502
 503         dev->clk_i2s_bclk_mst = clks[0].clk;
 504         dev->clk_i2s_lrck_mst = clks[1].clk;
 505         dev->clk_mclk = clks[2].clk;
 506         dev->clk_i2s_bclk = clks[3].clk;
 507         dev->clk_i2s_lrck = clks[4].clk;
 508         dev->clk_i2s_apb = clks[5].clk;
 509         dev->clk_mclk_ext = clks[6].clk;
 510
 511         dev->rst_i2s_apb = devm_reset_control_get_exclusive(&pdev->dev, "rst_apb");
 512         if (IS_ERR(dev->rst_i2s_apb)) {
 513                 dev_err(&pdev->dev, "failed to get i2s apb reset control\n");
 514                 ret = PTR_ERR(dev->rst_i2s_apb);
 515                 goto exit;
 516         }
 517
 518         dev->rst_i2s_bclk = devm_reset_control_get_exclusive(&pdev->dev, "rst_bclk");
 519         if (IS_ERR(dev->rst_i2s_bclk)) {
 520                 dev_err(&pdev->dev, "failed to get i2s bclk reset control\n");
 521                 ret = PTR_ERR(dev->rst_i2s_bclk);
 522                 goto exit;
 523         }
 524
 525         ret = clk_prepare_enable(dev->clk_i2s_apb);
 526         if (ret) {
 527                 dev_err(&pdev->dev, "failed to prepare enable clk_i2s_apb\n");
 528                 goto exit;
 529         }
 530
 531         ret = clk_set_parent(dev->clk_mclk, dev->clk_mclk_ext);
 532         if (ret) {
 533                 dev_err(&pdev->dev, "failed to set mclk parent to mclk_ext\n");
 534                 goto err_set_parent;
 535         }
 536
 537         ret = clk_prepare_enable(dev->clk_i2s_bclk_mst);
 538         if (ret) {
 539                 dev_err(&pdev->dev, "failed to prepare enable clk_i2srx_3ch_bclk_mst\n");
 540                 goto err_dis_bclk_mst;
 541         }
 542
 543         ret = clk_set_parent(dev->clk_i2s_lrck_mst, dev->clk_i2s_bclk_mst);
 544         if (ret) {
 545                 dev_err(&pdev->dev, "failed to set parent clk_i2s_lrck_mst\n");
 546                 goto err_dis_bclk_mst;
 547         }
 548
 549         ret = clk_set_parent(dev->clk_i2s_bclk, dev->clk_i2s_bclk_mst);
 550         if (ret) {
 551                 dev_err(&pdev->dev, "failed to set parent clk_i2s_bclk\n");
 552                 goto err_dis_bclk_mst;
 553         }
 554
 555         ret = clk_set_parent(dev->clk_i2s_lrck, dev->clk_i2s_lrck_mst);
 556         if (ret) {
 557                 dev_err(&pdev->dev, "failed to set parent clk_i2s_lrck\n");
 558                 goto err_dis_bclk_mst;
 559         }
 560
 561         reset_control_deassert(dev->rst_i2s_apb);
 562         reset_control_deassert(dev->rst_i2s_bclk);
 563
 564         return 0;
 565
 566
 567 err_dis_bclk_mst:
 568 err_set_parent:
 569         clk_disable_unprepare(dev->clk_i2s_apb);
 570 exit:
 571         return ret;
 572 }
 573
 574 /*
 575  * The following tables allow a direct lookup of various parameters
 576  * defined in the I2S block's configuration in terms of sound system
 577  * parameters.  Each table is sized to the number of entries possible
 578  * according to the number of configuration bits describing an I2S
 579  * block parameter.
 580  */
 581
 582 /* Maximum bit resolution of a channel - not uniformly spaced */
 583 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
 584         12, 16, 20, 24, 32, 0, 0, 0
 585 };
 586
 587 /* Width of (DMA) bus */
 588 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
 589         DMA_SLAVE_BUSWIDTH_1_BYTE,
 590         DMA_SLAVE_BUSWIDTH_2_BYTES,
 591         DMA_SLAVE_BUSWIDTH_4_BYTES,
 592         DMA_SLAVE_BUSWIDTH_UNDEFINED
 593 };
 594
 595 /* PCM format to support channel resolution */
 596 static const u32 formats[COMP_MAX_WORDSIZE] = {
 597         SNDRV_PCM_FMTBIT_S16_LE,
 598         SNDRV_PCM_FMTBIT_S16_LE,
 599         SNDRV_PCM_FMTBIT_S24_LE,
 600         SNDRV_PCM_FMTBIT_S24_LE,
 601         SNDRV_PCM_FMTBIT_S32_LE,
 602         0,
 603         0,
 604         0
 605 };
 606
 607 #define SF_PCM_RATE_32000_192000  (SNDRV_PCM_RATE_32000 | \
 608                                    SNDRV_PCM_RATE_44100 | \
 609                                    SNDRV_PCM_RATE_48000 | \
 610                                    SNDRV_PCM_RATE_88200 | \
 611                                    SNDRV_PCM_RATE_96000 | \
 612                                    SNDRV_PCM_RATE_176400 | \
 613                                    SNDRV_PCM_RATE_192000)
 614
 615 static int dw_configure_dai(struct dw_i2s_dev *dev,
 616                                    struct snd_soc_dai_driver *dw_i2s_dai,
 617                                    unsigned int rates)
 618 {
 619         /*
 620          * Read component parameter registers to extract
 621          * the I2S block's configuration.
 622          */
 623         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
 624         u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
 625         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 626         u32 idx;
 627
 628         if (dev->capability & DWC_I2S_RECORD &&
 629                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
 630                 comp1 = comp1 & ~BIT(5);
 631
 632         if (dev->capability & DWC_I2S_PLAY &&
 633                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
 634                 comp1 = comp1 & ~BIT(6);
 635
 636         if (COMP1_TX_ENABLED(comp1)) {
 637                 dev_info(dev->dev, " designware: play supported\n");
 638                 idx = COMP1_TX_WORDSIZE_0(comp1);
 639                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 640                         return -EINVAL;
 641                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
 642                         idx = 1;
 643                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
 644                 dw_i2s_dai->playback.channels_max =
 645                                 (COMP1_TX_CHANNELS(comp1) + 1);
 646                 dw_i2s_dai->playback.formats = formats[idx];
 647                 for (; idx > 0; idx--)
 648                         dw_i2s_dai->playback.formats |= formats[idx - 1];
 649                 dw_i2s_dai->playback.rates = rates;
 650         }
 651
 652         if (COMP1_RX_ENABLED(comp1)) {
 653                 dev_info(dev->dev, "designware: record supported\n");
 654                 idx = COMP2_RX_WORDSIZE_0(comp2);
 655                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 656                         return -EINVAL;
 657                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
 658                         idx = 1;
 659                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
 660                 dw_i2s_dai->capture.channels_max =
 661                                 (COMP1_RX_CHANNELS(comp1) + 1);
 662                 dw_i2s_dai->capture.formats = formats[idx];
 663                 for (; idx > 0; idx--)
 664                         dw_i2s_dai->capture.formats |= formats[idx - 1];
 665                 dw_i2s_dai->capture.rates = rates;
 666         }
 667
 668         dev_dbg(dev->dev, "designware: i2s master mode supported\n");
 669         dev->capability |= DW_I2S_MASTER;
 670
 671         dev->fifo_th = fifo_depth / 2;
 672         dev_dbg(dev->dev, "fifo_th :%d\n", dev->fifo_th);
 673         return 0;
 674 }
 675
 676 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
 677                                    struct snd_soc_dai_driver *dw_i2s_dai,
 678                                    struct resource *res,
 679                                    const struct i2s_platform_data *pdata)
 680 {
 681         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
 682         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 683         int ret;
 684
 685         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 686                 return -EINVAL;
 687
 688         ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
 689         if (ret < 0)
 690                 return ret;
 691
 692         if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
 693                 idx = 1;
 694         /* Set DMA slaves info */
 695         dev->play_dma_data.pd.data = pdata->play_dma_data;
 696         dev->capture_dma_data.pd.data = pdata->capture_dma_data;
 697         dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
 698         dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
 699         dev->play_dma_data.pd.max_burst = 16;
 700         dev->capture_dma_data.pd.max_burst = 16;
 701         dev->play_dma_data.pd.addr_width = bus_widths[idx];
 702         dev->capture_dma_data.pd.addr_width = bus_widths[idx];
 703         dev->play_dma_data.pd.filter = pdata->filter;
 704         dev->capture_dma_data.pd.filter = pdata->filter;
 705
 706         return 0;
 707 }
 708
 709 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
 710                                    struct snd_soc_dai_driver *dw_i2s_dai,
 711                                    struct resource *res)
 712 {
 713         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 714         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
 715         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 716         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 717         u32 idx2;
 718         int ret;
 719
 720         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 721                 return -EINVAL;
 722
 723         ret = dw_configure_dai(dev, dw_i2s_dai,
 724                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000);
 725         if (ret < 0)
 726                 return ret;
 727
 728         if (COMP1_TX_ENABLED(comp1)) {
 729                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
 730
 731                 dev->capability |= DWC_I2S_PLAY;
 732                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
 733                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
 734                 dev->play_dma_data.dt.fifo_size = fifo_depth *
 735                         (fifo_width[idx2]) >> 8;
 736                 dev->play_dma_data.dt.maxburst = 16;
 737         }
 738         if (COMP1_RX_ENABLED(comp1)) {
 739                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
 740
 741                 dev->capability |= DWC_I2S_RECORD;
 742                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
 743                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
 744                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
 745                         (fifo_width[idx2] >> 8);
 746                 dev->capture_dma_data.dt.maxburst = 16;
 747         }
 748
 749         return 0;
 750
 751 }
 752
 753 static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
 754 {
 755         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 756
 757         snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
 758         return 0;
 759 }
 760
 761 static int dw_i2s_probe(struct platform_device *pdev)
 762 {
 763         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
 764         struct device_node *np = pdev->dev.of_node;
 765         struct dw_i2s_dev *dev;
 766         struct resource *res;
 767         int ret, irq;
 768         struct snd_soc_dai_driver *dw_i2s_dai;
 769         const char *clk_id;
 770
 771         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 772         if (!dev)
 773                 return -ENOMEM;
 774
 775         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
 776         if (!dw_i2s_dai)
 777                 return -ENOMEM;
 778
 779         dw_i2s_dai->ops = &dw_i2s_dai_ops;
 780         dw_i2s_dai->probe = dw_i2s_dai_probe;
 781
 782         dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 783         if (IS_ERR(dev->i2s_base))
 784                 return PTR_ERR(dev->i2s_base);
 785
 786         dev->dev = &pdev->dev;
 787
 788         irq = platform_get_irq_optional(pdev, 0);
 789         if (irq >= 0) {
 790                 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
 791                                 pdev->name, dev);
 792                 if (ret < 0) {
 793                         dev_err(&pdev->dev, "failed to request irq\n");
 794                         return ret;
 795                 }
 796         }
 797
 798         if (of_device_is_compatible(np, "starfive,jh7110-i2stx-4ch0")) {
 799                 /* hdmi audio  */
 800                 ret = dw_i2stx_4ch0_clk_init(pdev, dev);
 801                 if (ret < 0)
 802                         goto err_clk_disable;
 803         }
 804
 805         dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
 806         dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
 807
 808         if (pdata) {
 809                 dev->capability = pdata->cap;
 810                 clk_id = NULL;
 811                 dev->quirks = pdata->quirks;
 812                 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
 813                         dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
 814                         dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
 815                 }
 816                 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
 817         } else {
 818                 clk_id = "i2stx_bclk";
 819                 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
 820         }
 821         if (ret < 0)
 822                 return ret;
 823
 824         if (dev->capability & DW_I2S_MASTER) {
 825                 if (pdata) {
 826                         dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
 827                         if (!dev->i2s_clk_cfg) {
 828                                 dev_err(&pdev->dev, "no clock configure method\n");
 829                                 return -ENODEV;
 830                         }
 831                 }
 832         }
 833
 834         dev_set_drvdata(&pdev->dev, dev);
 835         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
 836                                          dw_i2s_dai, 1);
 837         if (ret != 0) {
 838                 dev_err(&pdev->dev, "not able to register dai\n");
 839                 goto err_clk_disable;
 840         }
 841
 842         if (!pdata) {
 843                 if (irq >= 0) {
 844                         ret = dw_pcm_register(pdev);
 845                         dev->use_pio = true;
 846                 } else {
 847                         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
 848                                         0);
 849                         dev->use_pio = false;
 850                 }
 851
 852                 if (ret) {
 853                         dev_err(&pdev->dev, "could not register pcm: %d\n",
 854                                         ret);
 855                         goto err_clk_disable;
 856                 }
 857         }
 858
 859         pm_runtime_enable(&pdev->dev);
 860         return 0;
 861
 862 err_clk_disable:
 863         if (dev->capability & DW_I2S_MASTER)
 864                 clk_disable_unprepare(dev->clk_i2s_bclk_mst);
 865         return ret;
 866 }
 867
 868 static int dw_i2s_remove(struct platform_device *pdev)
 869 {
 870         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
 871
 872         if (dev->capability & DW_I2S_MASTER)
 873                 clk_disable_unprepare(dev->clk_i2s_bclk_mst);
 874
 875         pm_runtime_disable(&pdev->dev);
 876         return 0;
 877 }
 878
 879 #ifdef CONFIG_OF
 880 static const struct of_device_id dw_i2s_of_match[] = {
 881         { .compatible = "starfive,jh7110-i2stx-4ch0", },
 882         {},
 883 };
 884
 885 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
 886 #endif
 887
 888 static const struct dev_pm_ops dwc_pm_ops = {
 889         SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
 890 };
 891
 892 static struct platform_driver dw_i2s_driver = {
 893         .probe          = dw_i2s_probe,
 894         .remove         = dw_i2s_remove,
 895         .driver         = {
 896                 .name   = "starfive-i2s",
 897                 .of_match_table = of_match_ptr(dw_i2s_of_match),
 898                 .pm = &dwc_pm_ops,
 899         },
 900 };
 901
 902 module_platform_driver(dw_i2s_driver);
 903
 904 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
 905 MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
 906 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
 907 MODULE_LICENSE("GPL");
 908 MODULE_ALIAS("platform:designware_i2s");