sound/soc/starfive/i2srx-master.c

   1 /*
   2  * ALSA SoC Synopsys I2S Audio Layer
   3  *
   4  * sound/soc/dwc/designware_i2s.c
   5  *
   6  * Copyright (C) 2010 ST Microelectronics
   7  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/pm_runtime.h>
  22 #include <sound/designware_i2s.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/dmaengine_pcm.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30 #include "i2srx-master.h"
  31
  32 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
  33 {
  34         writel(val, io_base + reg);
  35 }
  36
  37 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
  38 {
  39         return readl(io_base + reg);
  40 }
  41
  42 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
  43 {
  44         u32 i = 0;
  45
  46         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  47                 for (i = 0; i < 4; i++)
  48                         i2s_write_reg(dev->i2s_base, TER(i), 0);
  49         } else {
  50                 for (i = 0; i < 4; i++)
  51                         i2s_write_reg(dev->i2s_base, RER(i), 0);
  52         }
  53 }
  54
  55 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
  56 {
  57         u32 i = 0;
  58
  59         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  60                 for (i = 0; i < 4; i++)
  61                         i2s_read_reg(dev->i2s_base, TOR(i));
  62         } else {
  63                 for (i = 0; i < 4; i++)
  64                         i2s_read_reg(dev->i2s_base, ROR(i));
  65         }
  66 }
  67
  68 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
  69                                     int chan_nr)
  70 {
  71         u32 i, irq;
  72
  73         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  74                 for (i = 0; i < (chan_nr / 2); i++) {
  75                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  76                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
  77                 }
  78         } else {
  79                 for (i = 0; i < (chan_nr / 2); i++) {
  80                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  81                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
  82                 }
  83         }
  84 }
  85
  86 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
  87                                    int chan_nr)
  88 {
  89         u32 i, irq;
  90
  91         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  92                 for (i = 0; i < (chan_nr / 2); i++) {
  93                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  94                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
  95                 }
  96         } else {
  97                 for (i = 0; i < (chan_nr / 2); i++) {
  98                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  99                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
 100                 }
 101         }
 102 }
 103
 104 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
 105 {
 106         struct dw_i2s_dev *dev = dev_id;
 107         bool irq_valid = false;
 108         u32 isr[4];
 109         int i;
 110
 111         for (i = 0; i < 4; i++)
 112                 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
 113
 114         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
 115         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
 116
 117         for (i = 0; i < 4; i++) {
 118                 /*
 119                  * Check if TX fifo is empty. If empty fill FIFO with samples
 120                  * NOTE: Only two channels supported
 121                  */
 122                 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
 123                         dw_pcm_push_tx(dev);
 124                         irq_valid = true;
 125                 }
 126
 127                 /*
 128                  * Data available. Retrieve samples from FIFO
 129                  * NOTE: Only two channels supported
 130                  */
 131                 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
 132                         dw_pcm_pop_rx(dev);
 133                         irq_valid = true;
 134                 }
 135
 136                 /* Error Handling: TX */
 137                 if (isr[i] & ISR_TXFO) {
 138                         dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
 139                         irq_valid = true;
 140                 }
 141
 142                 /* Error Handling: TX */
 143                 if (isr[i] & ISR_RXFO) {
 144                         dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
 145                         irq_valid = true;
 146                 }
 147         }
 148
 149         if (irq_valid)
 150                 return IRQ_HANDLED;
 151         else
 152                 return IRQ_NONE;
 153 }
 154
 155 static void i2s_start(struct dw_i2s_dev *dev,
 156                       struct snd_pcm_substream *substream)
 157 {
 158         struct i2s_clk_config_data *config = &dev->config;
 159
 160         i2s_write_reg(dev->i2s_base, IER, 1);
 161         i2s_enable_irqs(dev, substream->stream, config->chan_nr);
 162
 163         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 164                 i2s_write_reg(dev->i2s_base, ITER, 1);
 165         else
 166                 i2s_write_reg(dev->i2s_base, IRER, 1);
 167
 168         i2s_write_reg(dev->i2s_base, CER, 1);
 169
 170 }
 171
 172 static void i2s_stop(struct dw_i2s_dev *dev,
 173                 struct snd_pcm_substream *substream)
 174 {
 175
 176         i2s_clear_irqs(dev, substream->stream);
 177         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 178                 i2s_write_reg(dev->i2s_base, ITER, 0);
 179         else
 180                 i2s_write_reg(dev->i2s_base, IRER, 0);
 181
 182         i2s_disable_irqs(dev, substream->stream, 8);
 183
 184         if (!dev->active) {
 185                 i2s_write_reg(dev->i2s_base, CER, 0);
 186                 i2s_write_reg(dev->i2s_base, IER, 0);
 187         }
 188 }
 189
 190 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
 191 {
 192         u32 ch_reg;
 193         struct i2s_clk_config_data *config = &dev->config;
 194
 195
 196         i2s_disable_channels(dev, stream);
 197
 198         for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
 199                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 200                         i2s_write_reg(dev->i2s_base, TCR(ch_reg),
 201                                       dev->xfer_resolution);
 202                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
 203                                       dev->fifo_th - 1);
 204                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
 205                 } else {
 206                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
 207                                       dev->xfer_resolution);
 208                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
 209                                       dev->fifo_th - 1);
 210                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
 211                 }
 212
 213         }
 214 }
 215
 216 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 217                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 218 {
 219         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 220         struct i2s_clk_config_data *config = &dev->config;
 221         int ret;
 222         unsigned int bclk_rate;
 223         union dw_i2s_snd_dma_data *dma_data = NULL;
 224
 225         switch (params_format(params)) {
 226         case SNDRV_PCM_FORMAT_S16_LE:
 227                 config->data_width = 16;
 228                 dev->ccr = 0x00;
 229                 dev->xfer_resolution = 0x02;
 230                 dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 231                 break;
 232
 233         /* There is a issue with hardware while using 24-bit  */
 234 /*
 235         case SNDRV_PCM_FORMAT_S24_LE:
 236                 config->data_width = 24;
 237                 dev->ccr = 0x08;
 238                 dev->xfer_resolution = 0x04;
 239                 dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 240                 break;
 241 */
 242
 243         case SNDRV_PCM_FORMAT_S32_LE:
 244                 config->data_width = 32;
 245                 dev->ccr = 0x10;
 246                 dev->xfer_resolution = 0x05;
 247                 dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 248                 break;
 249
 250         default:
 251                 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
 252                 return -EINVAL;
 253         }
 254
 255         switch (params_rate(params)) {
 256         case 8000:
 257                 bclk_rate = 512000;
 258                 break;
 259         case 11025:
 260                 bclk_rate = 705600;
 261                 break;
 262         case 16000:
 263                 bclk_rate = 1024000;
 264                 break;
 265         default:
 266                 dev_err(dai->dev, "%d rate not supported\n",
 267                                 params_rate(params));
 268                 return -EINVAL;
 269         }
 270
 271         config->chan_nr = params_channels(params);
 272
 273         switch (config->chan_nr) {
 274         case EIGHT_CHANNEL_SUPPORT:
 275         case SIX_CHANNEL_SUPPORT:
 276         case FOUR_CHANNEL_SUPPORT:
 277         case TWO_CHANNEL_SUPPORT:
 278                 break;
 279         default:
 280                 dev_err(dev->dev, "channel not supported\n");
 281                 return -EINVAL;
 282         }
 283
 284         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 285                 dma_data = &dev->capture_dma_data;
 286         snd_soc_dai_set_dma_data(dai, substream, (void *)dma_data);
 287
 288         dw_i2s_config(dev, substream->stream);
 289
 290         i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
 291
 292         config->sample_rate = params_rate(params);
 293
 294
 295         if (dev->capability & DW_I2S_MASTER) {
 296                 if (dev->i2s_clk_cfg) {
 297                         ret = dev->i2s_clk_cfg(config);
 298                         if (ret < 0) {
 299                                 dev_err(dev->dev, "runtime audio clk config fail\n");
 300                                 return ret;
 301                         }
 302                 } else {
 303                         ret = clk_set_rate(dev->clk_i2srx_bclk_mst, bclk_rate);
 304                         if (ret) {
 305                                 dev_err(dev->dev, "Can't set i2s bclk: %d\n", ret);
 306                                 return ret;
 307                         }
 308                 }
 309         }
 310         return 0;
 311 }
 312
 313 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
 314                           struct snd_soc_dai *dai)
 315 {
 316         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 317
 318         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 319                 i2s_write_reg(dev->i2s_base, TXFFR, 1);
 320         else
 321                 i2s_write_reg(dev->i2s_base, RXFFR, 1);
 322
 323         return 0;
 324 }
 325
 326 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 327                 int cmd, struct snd_soc_dai *dai)
 328 {
 329         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 330         int ret = 0;
 331
 332         switch (cmd) {
 333         case SNDRV_PCM_TRIGGER_START:
 334         case SNDRV_PCM_TRIGGER_RESUME:
 335         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 336                 dev->active++;
 337                 i2s_start(dev, substream);
 338                 break;
 339
 340         case SNDRV_PCM_TRIGGER_STOP:
 341         case SNDRV_PCM_TRIGGER_SUSPEND:
 342         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 343                 dev->active--;
 344                 i2s_stop(dev, substream);
 345                 break;
 346         default:
 347                 ret = -EINVAL;
 348                 break;
 349         }
 350         return ret;
 351 }
 352
 353 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 354 {
 355         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 356         int ret = 0;
 357
 358         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 359         case SND_SOC_DAIFMT_CBM_CFM:
 360                 if (dev->capability & DW_I2S_SLAVE)
 361                         ret = 0;
 362                 else
 363                         ret = -EINVAL;
 364                 break;
 365         case SND_SOC_DAIFMT_CBS_CFS:
 366                 if (dev->capability & DW_I2S_MASTER)
 367                         ret = 0;
 368                 else
 369                         ret = -EINVAL;
 370                 break;
 371         case SND_SOC_DAIFMT_CBM_CFS:
 372         case SND_SOC_DAIFMT_CBS_CFM:
 373                 ret = -EINVAL;
 374                 break;
 375         default:
 376                 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
 377                 ret = -EINVAL;
 378                 break;
 379         }
 380         return ret;
 381 }
 382
 383 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
 384         .hw_params      = dw_i2s_hw_params,
 385         .prepare        = dw_i2s_prepare,
 386         .trigger        = dw_i2s_trigger,
 387         .set_fmt        = dw_i2s_set_fmt,
 388 };
 389
 390 #ifdef CONFIG_PM
 391 static int dw_i2s_runtime_suspend(struct device *dev)
 392 {
 393         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 394
 395         if (dw_dev->capability & DW_I2S_MASTER) {
 396                 clk_disable_unprepare(dw_dev->clk_i2srx_lrck);
 397                 clk_disable_unprepare(dw_dev->clk_i2srx_bclk);
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int dw_i2s_runtime_resume(struct device *dev)
 404 {
 405         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 406         int ret;
 407
 408         if (dw_dev->capability & DW_I2S_MASTER) {
 409                 ret = clk_prepare_enable(dw_dev->clk_i2srx_bclk);
 410                 if (ret) {
 411                         dev_err(dw_dev->dev, "Failed to enable clk_i2srx_3ch_bclk\n");
 412                         return ret;
 413                 }
 414
 415                 ret = clk_prepare_enable(dw_dev->clk_i2srx_lrck);
 416                 if (ret) {
 417                         dev_err(dw_dev->dev, "Failed to enable clk_i2srx_3ch_lrck\n");
 418                         return ret;
 419                 }
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int dw_i2s_suspend(struct snd_soc_component *component)
 426 {
 427         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 428
 429         if (dev->capability & DW_I2S_MASTER) {
 430                 clk_disable_unprepare(dev->clk_i2srx_lrck);
 431                 clk_disable_unprepare(dev->clk_i2srx_bclk);
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int dw_i2s_resume(struct snd_soc_component *component)
 438 {
 439         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 440         struct snd_soc_dai *dai;
 441         int stream;
 442         int ret;
 443
 444         if (dev->capability & DW_I2S_MASTER) {
 445                 ret = clk_prepare_enable(dev->clk_i2srx_bclk);
 446                 if (ret) {
 447                         dev_err(dev->dev, "Failed to enable clk_i2srx_3ch_bclk\n");
 448                         return ret;
 449                 }
 450
 451                 ret = clk_prepare_enable(dev->clk_i2srx_lrck);
 452                 if (ret) {
 453                         dev_err(dev->dev, "Failed to enable clk_i2srx_3ch_lrck\n");
 454                         return ret;
 455                 }
 456         }
 457
 458         for_each_component_dais(component, dai) {
 459                 for_each_pcm_streams(stream)
 460                         if (snd_soc_dai_stream_active(dai, stream))
 461                                 dw_i2s_config(dev, stream);
 462         }
 463
 464         return 0;
 465 }
 466
 467 #else
 468 #define dw_i2s_suspend  NULL
 469 #define dw_i2s_resume   NULL
 470 #endif
 471
 472 static const struct snd_soc_component_driver dw_i2s_component = {
 473         .name           = "dw-i2s",
 474         .suspend        = dw_i2s_suspend,
 475         .resume         = dw_i2s_resume,
 476 };
 477
 478 static int dw_i2srx_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 479 {
 480         int ret = 0;
 481
 482         static struct clk_bulk_data clks[] = {
 483                 { .id = "apb0" },
 484                 { .id = "i2srx_apb" },
 485                 { .id = "i2srx_bclk_mst" },
 486                 { .id = "i2srx_lrck_mst" },
 487                 { .id = "i2srx_bclk" },
 488                 { .id = "i2srx_lrck" },
 489         };
 490
 491         ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
 492         if (ret) {
 493                 dev_err(&pdev->dev, "%s: failed to get i2srx clocks\n", __func__);
 494                 goto exit;
 495         }
 496
 497         dev->clk_apb0 = clks[0].clk;
 498         dev->clk_i2srx_apb = clks[1].clk;
 499         dev->clk_i2srx_bclk_mst = clks[2].clk;
 500         dev->clk_i2srx_lrck_mst = clks[3].clk;
 501         dev->clk_i2srx_bclk = clks[4].clk;
 502         dev->clk_i2srx_lrck = clks[5].clk;
 503
 504         dev->rst_i2srx_apb = devm_reset_control_get_exclusive(&pdev->dev, "rst_apb_rx");
 505         if (IS_ERR(dev->rst_i2srx_apb)) {
 506                 dev_err(&pdev->dev, "failed to get apb_i2srx reset control\n");
 507                 ret = PTR_ERR(dev->rst_i2srx_apb);
 508                 goto exit;
 509         }
 510
 511         dev->rst_i2srx_bclk = devm_reset_control_get_exclusive(&pdev->dev, "rst_bclk_rx");
 512         if (IS_ERR(dev->rst_i2srx_bclk)) {
 513                 dev_err(&pdev->dev, "failed to get i2s bclk rx reset control\n");
 514                 ret = PTR_ERR(dev->rst_i2srx_bclk);
 515                 goto exit;
 516         }
 517
 518         reset_control_assert(dev->rst_i2srx_apb);
 519         reset_control_assert(dev->rst_i2srx_bclk);
 520
 521         ret = clk_prepare_enable(dev->clk_apb0);
 522         if (ret) {
 523                 dev_err(&pdev->dev, "failed to prepare enable clk_apb0\n");
 524                 goto exit;
 525         }
 526
 527         ret = clk_prepare_enable(dev->clk_i2srx_apb);
 528         if (ret) {
 529                 dev_err(&pdev->dev, "failed to prepare enable clk_i2srx_apb\n");
 530                 goto err_dis_i2srx_apb;
 531         }
 532
 533         ret = clk_prepare_enable(dev->clk_i2srx_bclk_mst);
 534         if (ret) {
 535                 dev_err(&pdev->dev, "failed to prepare enable clk_i2srx_3ch_bclk_mst\n");
 536                 goto err_dis_bclk_mst;
 537         }
 538
 539         ret = clk_prepare_enable(dev->clk_i2srx_lrck_mst);
 540         if (ret) {
 541                 dev_err(&pdev->dev, "failed to prepare enable clk_i2srx_3ch_lrck_mst\n");
 542                 goto err_dis_lrck_mst;
 543         }
 544
 545         ret = clk_prepare_enable(dev->clk_i2srx_bclk);
 546         if (ret) {
 547                 dev_err(&pdev->dev, "failed to prepare enable clk_i2srx_3ch_bclk\n");
 548                 goto err_dis_bclk;
 549         }
 550
 551         ret = clk_prepare_enable(dev->clk_i2srx_lrck);
 552         if (ret) {
 553                 dev_err(&pdev->dev, "failed to prepare enable clk_i2srx_3ch_lrck\n");
 554                 goto err_dis_lrck;
 555         }
 556
 557         reset_control_deassert(dev->rst_i2srx_apb);
 558         reset_control_deassert(dev->rst_i2srx_bclk);
 559
 560         regmap_update_bits(dev->syscon_base, dev->syscon_offset_18,
 561                                 I2SRX_3CH_ADC_MASK, I2SRX_3CH_ADC_EN);
 562         return 0;
 563
 564 err_dis_i2srx_apb:
 565         clk_disable_unprepare(dev->clk_apb0);
 566 err_dis_bclk_mst:
 567         clk_disable_unprepare(dev->clk_i2srx_apb);
 568 err_dis_lrck_mst:
 569         clk_disable_unprepare(dev->clk_i2srx_bclk_mst);
 570 err_dis_bclk:
 571         clk_disable_unprepare(dev->clk_i2srx_lrck_mst);
 572 err_dis_lrck:
 573         clk_disable_unprepare(dev->clk_i2srx_bclk);
 574 exit:
 575         return ret;
 576 }
 577
 578 /*
 579  * The following tables allow a direct lookup of various parameters
 580  * defined in the I2S block's configuration in terms of sound system
 581  * parameters.  Each table is sized to the number of entries possible
 582  * according to the number of configuration bits describing an I2S
 583  * block parameter.
 584  */
 585
 586 /* Maximum bit resolution of a channel - not uniformly spaced */
 587 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
 588         12, 16, 20, 24, 32, 0, 0, 0
 589 };
 590
 591 /* Width of (DMA) bus */
 592 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
 593         DMA_SLAVE_BUSWIDTH_1_BYTE,
 594         DMA_SLAVE_BUSWIDTH_2_BYTES,
 595         DMA_SLAVE_BUSWIDTH_4_BYTES,
 596         DMA_SLAVE_BUSWIDTH_UNDEFINED
 597 };
 598
 599 /* PCM format to support channel resolution */
 600 static const u32 formats[COMP_MAX_WORDSIZE] = {
 601         SNDRV_PCM_FMTBIT_S16_LE,
 602         SNDRV_PCM_FMTBIT_S16_LE,
 603         SNDRV_PCM_FMTBIT_S24_LE,
 604         SNDRV_PCM_FMTBIT_S24_LE,
 605         SNDRV_PCM_FMTBIT_S32_LE,
 606         0,
 607         0,
 608         0
 609 };
 610
 611 #define SF_IIS_FORMATS  (SNDRV_PCM_FMTBIT_S16_LE | \
 612                         SNDRV_PCM_FMTBIT_S32_LE)
 613
 614 static int dw_configure_dai(struct dw_i2s_dev *dev,
 615                                    struct snd_soc_dai_driver *dw_i2s_dai,
 616                                    unsigned int rates)
 617 {
 618         /*
 619          * Read component parameter registers to extract
 620          * the I2S block's configuration.
 621          */
 622         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
 623         u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
 624         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 625         u32 idx;
 626
 627         if (dev->capability & DWC_I2S_RECORD &&
 628                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
 629                 comp1 = comp1 & ~BIT(5);
 630
 631         if (dev->capability & DWC_I2S_PLAY &&
 632                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
 633                 comp1 = comp1 & ~BIT(6);
 634
 635         if (COMP1_TX_ENABLED(comp1)) {
 636                 dev_dbg(dev->dev, " designware: play supported\n");
 637                 idx = COMP1_TX_WORDSIZE_0(comp1);
 638                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 639                         return -EINVAL;
 640                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
 641                         idx = 1;
 642                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
 643                 dw_i2s_dai->playback.channels_max =
 644                                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
 645                 dw_i2s_dai->playback.formats = formats[idx];
 646                 dw_i2s_dai->playback.rates = rates;
 647         }
 648
 649         if (COMP1_RX_ENABLED(comp1)) {
 650                 dev_dbg(dev->dev, "designware: record supported\n");
 651                 idx = COMP2_RX_WORDSIZE_0(comp2);
 652                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 653                         return -EINVAL;
 654                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
 655                         idx = 1;
 656                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
 657                 dw_i2s_dai->capture.channels_max =
 658                                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
 659                 dw_i2s_dai->capture.formats = SF_IIS_FORMATS;
 660                 dw_i2s_dai->capture.rates = rates;
 661         }
 662
 663         dev_dbg(dev->dev, "designware: i2s master mode supported\n");
 664         dev->capability |= DW_I2S_MASTER;
 665         dev->fifo_th = fifo_depth / 2;
 666         return 0;
 667 }
 668
 669 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
 670                                    struct snd_soc_dai_driver *dw_i2s_dai,
 671                                    struct resource *res)
 672 {
 673         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 674         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
 675         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 676         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 677         u32 idx2;
 678         int ret;
 679
 680         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 681                 return -EINVAL;
 682
 683         ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
 684         if (ret < 0)
 685                 return ret;
 686
 687         if (COMP1_TX_ENABLED(comp1)) {
 688                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
 689
 690                 dev->capability |= DWC_I2S_PLAY;
 691                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
 692                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
 693                 dev->play_dma_data.dt.fifo_size = fifo_depth *
 694                         (fifo_width[idx2]) >> 8;
 695                 dev->play_dma_data.dt.maxburst = 16;
 696         }
 697         if (COMP1_RX_ENABLED(comp1)) {
 698                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
 699
 700                 /* force change to 1 */
 701                 idx = 1;
 702                 idx2 = 1;
 703                 dev->capability |= DWC_I2S_RECORD;
 704                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
 705                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
 706                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
 707                         (fifo_width[idx2] >> 8);
 708                 dev->capture_dma_data.dt.maxburst = 16;
 709         }
 710
 711         return 0;
 712
 713 }
 714
 715 static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
 716 {
 717         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 718
 719         snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
 720         return 0;
 721 }
 722
 723 static int dw_i2s_probe(struct platform_device *pdev)
 724 {
 725         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
 726         struct device_node *np = pdev->dev.of_node;
 727         struct of_phandle_args args;
 728         struct dw_i2s_dev *dev;
 729         struct resource *res;
 730         int ret, irq;
 731         struct snd_soc_dai_driver *dw_i2s_dai;
 732         const char *clk_id;
 733
 734         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 735         if (!dev)
 736                 return -ENOMEM;
 737
 738         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
 739         if (!dw_i2s_dai)
 740                 return -ENOMEM;
 741
 742
 743         dw_i2s_dai->ops = &dw_i2s_dai_ops;
 744         dw_i2s_dai->probe = dw_i2s_dai_probe;
 745
 746         dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 747         if (IS_ERR(dev->i2s_base))
 748                 return PTR_ERR(dev->i2s_base);
 749
 750         dev->dev = &pdev->dev;
 751
 752         ret = of_parse_phandle_with_fixed_args(dev->dev->of_node,
 753                                                 "starfive,sys-syscon", 2, 0, &args);
 754         if (ret) {
 755                 dev_err(dev->dev, "Failed to parse starfive,sys-syscon\n");
 756                 return -EINVAL;
 757         }
 758
 759         dev->syscon_base = syscon_node_to_regmap(args.np);
 760         of_node_put(args.np);
 761         if (IS_ERR(dev->syscon_base))
 762                 return PTR_ERR(dev->syscon_base);
 763
 764         dev->syscon_offset_18 = args.args[0];
 765         dev->syscon_offset_34 = args.args[1];
 766
 767         irq = platform_get_irq_optional(pdev, 0);
 768         if (irq >= 0) {
 769                 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
 770                                 pdev->name, dev);
 771                 if (ret < 0) {
 772                         dev_err(&pdev->dev, "failed to request irq\n");
 773                         return ret;
 774                 }
 775         }
 776
 777         if (of_device_is_compatible(np, "starfive,jh7110-i2srx-master")) {
 778                 /* config i2s data source: PDM  */
 779                 regmap_update_bits(dev->syscon_base, dev->syscon_offset_34,
 780                                         AUDIO_SDIN_MUX_MASK, I2SRX_DATA_SRC_PDM);
 781
 782                 ret = dw_i2srx_clk_init(pdev, dev);
 783                 if (ret < 0)
 784                         goto err_clk_disable;
 785         }
 786
 787         dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
 788         dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
 789
 790         clk_id = "i2srx_bclk";
 791         ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
 792         if (ret < 0)
 793                 return ret;
 794
 795         if (dev->capability & DW_I2S_MASTER) {
 796                 if (pdata) {
 797                         dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
 798                         if (!dev->i2s_clk_cfg) {
 799                                 dev_err(&pdev->dev, "no clock configure method\n");
 800                                 return -ENODEV;
 801                         }
 802                 }
 803         }
 804
 805         dev_set_drvdata(&pdev->dev, dev);
 806         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
 807                                          dw_i2s_dai, 1);
 808         if (ret != 0) {
 809                 dev_err(&pdev->dev, "not able to register dai\n");
 810                 goto err_clk_disable;
 811         }
 812
 813         if (!pdata) {
 814                 if (irq >= 0) {
 815                         ret = dw_pcm_register(pdev);
 816                         dev->use_pio = true;
 817                 } else {
 818                         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
 819                                         0);
 820                         dev->use_pio = false;
 821                 }
 822
 823                 if (ret) {
 824                         dev_err(&pdev->dev, "could not register pcm: %d\n",
 825                                         ret);
 826                         goto err_clk_disable;
 827                 }
 828         }
 829
 830         pm_runtime_enable(&pdev->dev);
 831         return 0;
 832
 833 err_clk_disable:
 834         if (dev->capability & DW_I2S_MASTER)
 835                 clk_disable_unprepare(dev->clk_i2srx_bclk_mst);
 836         return ret;
 837 }
 838
 839 static int dw_i2s_remove(struct platform_device *pdev)
 840 {
 841         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
 842
 843         if (dev->capability & DW_I2S_MASTER)
 844                 clk_disable_unprepare(dev->clk_i2srx_bclk_mst);
 845
 846         pm_runtime_disable(&pdev->dev);
 847         return 0;
 848 }
 849
 850 #ifdef CONFIG_OF
 851 static const struct of_device_id dw_i2s_of_match[] = {
 852         { .compatible = "starfive,jh7110-i2srx-master", },
 853         {},
 854 };
 855
 856 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
 857 #endif
 858
 859 static const struct dev_pm_ops dwc_pm_ops = {
 860         SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
 861 };
 862
 863 static struct platform_driver dw_i2s_driver = {
 864         .probe          = dw_i2s_probe,
 865         .remove         = dw_i2s_remove,
 866         .driver         = {
 867                 .name   = "i2srx-master",
 868                 .of_match_table = of_match_ptr(dw_i2s_of_match),
 869                 .pm = &dwc_pm_ops,
 870         },
 871 };
 872
 873 module_platform_driver(dw_i2s_driver);
 874
 875 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
 876 MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
 877 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
 878 MODULE_LICENSE("GPL");
 879 MODULE_ALIAS("platform:designware_i2s");