1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for HDA DSP code loader
18 #include <linux/firmware.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/sof.h>
24 #define HDA_FW_BOOT_ATTEMPTS 3
26 static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
27 unsigned int size, struct snd_dma_buffer *dmab,
30 struct hdac_ext_stream *dsp_stream;
31 struct hdac_stream *hstream;
32 struct pci_dev *pci = to_pci_dev(sdev->dev);
35 if (direction != SNDRV_PCM_STREAM_PLAYBACK) {
36 dev_err(sdev->dev, "error: code loading DMA is playback only\n");
40 dsp_stream = hda_dsp_stream_get(sdev, direction);
43 dev_err(sdev->dev, "error: no stream available\n");
46 hstream = &dsp_stream->hstream;
48 /* allocate DMA buffer */
49 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
51 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
55 hstream->period_bytes = 0;/* initialize period_bytes */
56 hstream->format_val = format;
57 hstream->bufsize = size;
59 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
61 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
65 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
67 return hstream->stream_tag;
70 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
71 snd_dma_free_pages(dmab);
76 * first boot sequence has some extra steps. core 0 waits for power
77 * status on core 1, so power up core 1 also momentarily, keep it in
78 * reset/stall and then turn it off
80 static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
81 u32 fwsize, int stream_tag)
83 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
84 const struct sof_intel_dsp_desc *chip = hda->desc;
89 /* step 1: power up corex */
90 ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
92 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
96 /* DSP is powered up, set all SSPs to slave mode */
97 for (i = 0; i < chip->ssp_count; i++) {
98 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
100 + i * SSP_DEV_MEM_SIZE
106 /* step 2: purge FW request */
107 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
108 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
109 ((stream_tag - 1) << 9)));
111 /* step 3: unset core 0 reset state & unstall/run core 0 */
112 ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
114 dev_err(sdev->dev, "error: dsp core start failed %d\n", ret);
119 /* step 4: wait for IPC DONE bit from ROM */
120 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
121 chip->ipc_ack, status,
122 ((status & chip->ipc_ack_mask)
123 == chip->ipc_ack_mask),
124 HDA_DSP_REG_POLL_INTERVAL_US,
125 HDA_DSP_INIT_TIMEOUT_US);
128 dev_err(sdev->dev, "error: waiting for HIPCIE done\n");
132 /* step 5: power down corex */
133 ret = hda_dsp_core_power_down(sdev,
134 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
136 dev_err(sdev->dev, "error: dsp core x power down failed\n");
140 /* step 6: enable IPC interrupts */
141 hda_dsp_ipc_int_enable(sdev);
143 /* step 7: wait for ROM init */
144 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
145 HDA_DSP_SRAM_REG_ROM_STATUS, status,
146 ((status & HDA_DSP_ROM_STS_MASK)
147 == HDA_DSP_ROM_INIT),
148 HDA_DSP_REG_POLL_INTERVAL_US,
149 chip->rom_init_timeout *
155 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
156 hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
161 static int cl_trigger(struct snd_sof_dev *sdev,
162 struct hdac_ext_stream *stream, int cmd)
164 struct hdac_stream *hstream = &stream->hstream;
165 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
167 /* code loader is special case that reuses stream ops */
169 case SNDRV_PCM_TRIGGER_START:
170 wait_event_timeout(sdev->waitq, !sdev->code_loading,
171 HDA_DSP_CL_TRIGGER_TIMEOUT);
173 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
175 1 << hstream->index);
177 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
179 SOF_HDA_SD_CTL_DMA_START |
180 SOF_HDA_CL_DMA_SD_INT_MASK,
181 SOF_HDA_SD_CTL_DMA_START |
182 SOF_HDA_CL_DMA_SD_INT_MASK);
184 hstream->running = true;
187 return hda_dsp_stream_trigger(sdev, stream, cmd);
191 static struct hdac_ext_stream *get_stream_with_tag(struct snd_sof_dev *sdev,
194 struct hdac_bus *bus = sof_to_bus(sdev);
195 struct hdac_stream *s;
197 /* get stream with tag */
198 list_for_each_entry(s, &bus->stream_list, list) {
199 if (s->direction == SNDRV_PCM_STREAM_PLAYBACK &&
200 s->stream_tag == tag) {
201 return stream_to_hdac_ext_stream(s);
208 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
209 struct hdac_ext_stream *stream)
211 struct hdac_stream *hstream = &stream->hstream;
212 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
215 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
217 hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_PLAYBACK,
218 hstream->stream_tag);
219 hstream->running = 0;
220 hstream->substream = NULL;
222 /* reset BDL address */
223 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
224 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
225 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
226 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
228 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
229 snd_dma_free_pages(dmab);
231 hstream->bufsize = 0;
232 hstream->format_val = 0;
237 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
242 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
244 dev_err(sdev->dev, "error: DMA trigger start failed\n");
248 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
249 HDA_DSP_SRAM_REG_ROM_STATUS, reg,
250 ((reg & HDA_DSP_ROM_STS_MASK)
251 == HDA_DSP_ROM_FW_ENTERED),
252 HDA_DSP_REG_POLL_INTERVAL_US,
253 HDA_DSP_BASEFW_TIMEOUT_US);
255 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
257 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
264 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
266 struct snd_sof_pdata *plat_data = sdev->pdata;
267 const struct sof_dev_desc *desc = plat_data->desc;
268 const struct sof_intel_dsp_desc *chip_info;
269 struct hdac_ext_stream *stream;
270 struct firmware stripped_firmware;
271 int ret, ret1, tag, i;
273 chip_info = desc->chip_info;
275 stripped_firmware.data = plat_data->fw->data;
276 stripped_firmware.size = plat_data->fw->size;
278 /* init for booting wait */
279 init_waitqueue_head(&sdev->boot_wait);
280 sdev->boot_complete = false;
282 /* prepare DMA for code loader stream */
283 tag = cl_stream_prepare(sdev, 0x40, stripped_firmware.size,
284 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
287 dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n",
292 /* get stream with tag */
293 stream = get_stream_with_tag(sdev, tag);
296 "error: could not get stream with stream tag %d\n",
302 memcpy(sdev->dmab.area, stripped_firmware.data,
303 stripped_firmware.size);
305 /* try ROM init a few times before giving up */
306 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
307 ret = cl_dsp_init(sdev, stripped_firmware.data,
308 stripped_firmware.size, tag);
310 /* don't retry anymore if successful */
314 dev_err(sdev->dev, "error: Error code=0x%x: FW status=0x%x\n",
315 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
316 HDA_DSP_SRAM_REG_ROM_ERROR),
317 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
318 HDA_DSP_SRAM_REG_ROM_STATUS));
319 dev_err(sdev->dev, "error: iteration %d of Core En/ROM load failed: %d\n",
323 if (i == HDA_FW_BOOT_ATTEMPTS) {
324 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
330 * at this point DSP ROM has been initialized and
331 * should be ready for code loading and firmware boot
333 ret = cl_copy_fw(sdev, stream);
335 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
337 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
341 * Perform codeloader stream cleanup.
342 * This should be done even if firmware loading fails.
344 ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
346 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
348 /* set return value to indicate cleanup failure */
353 * return master core id if both fw copy
354 * and stream clean up are successful
357 return chip_info->init_core_mask;
359 /* dump dsp registers and disable DSP upon error */
361 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
364 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
365 SOF_HDA_REG_PP_PPCTL,
366 SOF_HDA_PPCTL_GPROCEN, 0);
370 /* pre fw run operations */
371 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
373 /* disable clock gating and power gating */
374 return hda_dsp_ctrl_clock_power_gating(sdev, false);
377 /* post fw run operations */
378 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
380 /* re-enable clock gating and power gating */
381 return hda_dsp_ctrl_clock_power_gating(sdev, true);