1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
11 #ifndef __SOF_AMD_ACP_H
12 #define __SOF_AMD_ACP_H
14 #include "../sof-priv.h"
16 #define ACP_MAX_STREAM 8
20 #define ACP_HW_SEM_RETRY_COUNT 10000
21 #define ACP_REG_POLL_INTERVAL 500
22 #define ACP_REG_POLL_TIMEOUT_US 2000
23 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000
25 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
26 #define ACP_PGFSM_STATUS_MASK 0x03
27 #define ACP_POWERED_ON 0x00
28 #define ACP_ASSERT_RESET 0x01
29 #define ACP_RELEASE_RESET 0x00
30 #define ACP_SOFT_RESET_DONE_MASK 0x00010001
32 #define ACP_DSP_INTR_EN_MASK 0x00000001
33 #define ACP3X_SRAM_PTE_OFFSET 0x02050000
34 #define ACP6X_SRAM_PTE_OFFSET 0x03800000
35 #define PAGE_SIZE_4K_ENABLE 0x2
36 #define ACP_PAGE_SIZE 0x1000
37 #define ACP_DMA_CH_RUN 0x02
38 #define ACP_MAX_DESC_CNT 0x02
39 #define DSP_FW_RUN_ENABLE 0x01
40 #define ACP_SHA_RUN 0x01
41 #define ACP_SHA_RESET 0x02
42 #define ACP_DMA_CH_RST 0x01
43 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10
44 #define ACP_ATU_CACHE_INVALID 0x01
45 #define ACP_MAX_DESC 128
46 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0
48 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000
49 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000
50 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000
51 #define ACP_IRAM_BASE_ADDRESS 0x000000
52 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000
53 #define ACP_DRAM_PAGE_COUNT 128
55 #define ACP_DSP_TO_HOST_IRQ 0x04
57 #define HOST_BRIDGE_CZN 0x1630
58 #define HOST_BRIDGE_RMB 0x14B5
59 #define ACP_SHA_STAT 0x8000
60 #define ACP_PSP_TIMEOUT_COUNTER 5
61 #define ACP_EXT_INTR_ERROR_STAT 0x20000000
62 #define MP0_C2PMSG_114_REG 0x3810AC8
63 #define MP0_C2PMSG_73_REG 0x3810A24
64 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000
65 #define MBOX_DELAY 1000
66 #define MBOX_READY_MASK 0x80000000
67 #define MBOX_STATUS_MASK 0xFFFF
69 #define BOX_SIZE_512 0x200
70 #define BOX_SIZE_1024 0x400
72 #define EXCEPT_MAX_HDR_SIZE 0x400
73 #define AMD_STACK_DUMP_SIZE 32
75 #define SRAM1_SIZE 0x13A000
85 struct acp_atu_grp_pte {
92 unsigned int count : 19;
93 unsigned int reserved : 12;
100 struct dma_descriptor {
101 unsigned int src_addr;
102 unsigned int dest_addr;
103 union dma_tx_cnt tx_cnt;
104 unsigned int reserved;
107 /* Scratch memory structure for communication b/w host and dsp */
108 struct scratch_ipc_conf {
110 u8 sof_debug_box[1024];
111 /* Exception memory*/
112 u8 sof_except_box[1024];
114 u8 sof_stream_box[1024];
116 u8 sof_trace_box[1024];
118 u32 sof_host_msg_write;
120 u32 sof_host_ack_write;
122 u32 sof_dsp_msg_write;
124 u32 sof_dsp_ack_write;
127 struct scratch_reg_conf {
128 struct scratch_ipc_conf info;
129 struct acp_atu_grp_pte grp1_pte[16];
130 struct acp_atu_grp_pte grp2_pte[16];
131 struct acp_atu_grp_pte grp3_pte[16];
132 struct acp_atu_grp_pte grp4_pte[16];
133 struct acp_atu_grp_pte grp5_pte[16];
134 struct acp_atu_grp_pte grp6_pte[16];
135 struct acp_atu_grp_pte grp7_pte[16];
136 struct acp_atu_grp_pte grp8_pte[16];
137 struct dma_descriptor dma_desc[64];
138 unsigned int reg_offset[8];
139 unsigned int buf_size[8];
140 u8 acp_tx_fifo_buf[256];
141 u8 acp_rx_fifo_buf[256];
142 unsigned int reserve[];
145 struct acp_dsp_stream {
146 struct list_head list;
147 struct snd_sof_dev *sdev;
148 struct snd_pcm_substream *substream;
149 struct snd_dma_buffer *dmab;
153 unsigned int reg_offset;
157 struct sof_amd_acp_desc {
159 unsigned int host_bridge_id;
160 unsigned int i2s_mode;
165 u32 i2s_pin_config_offset;
166 u32 hw_semaphore_offset;
168 u32 fusion_dsp_offset;
171 /* Common device data struct for ACP devices */
172 struct acp_dev_data {
173 struct snd_sof_dev *dev;
174 unsigned int fw_bin_size;
175 unsigned int fw_data_bin_size;
176 u32 fw_bin_page_count;
177 dma_addr_t sha_dma_addr;
181 struct dma_descriptor dscr_info[ACP_MAX_DESC];
182 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
183 struct acp_dsp_stream *dtrace_stream;
184 struct pci_dev *smn_dev;
187 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
188 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
190 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
191 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
192 unsigned int dest_addr, int dsp_data_size);
193 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
194 unsigned int start_addr, unsigned int dest_addr,
195 unsigned int image_length);
197 /* ACP device probe/remove */
198 int amd_sof_acp_probe(struct snd_sof_dev *sdev);
199 int amd_sof_acp_remove(struct snd_sof_dev *sdev);
201 /* DSP Loader callbacks */
202 int acp_sof_dsp_run(struct snd_sof_dev *sdev);
203 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
204 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
206 /* Block IO callbacks */
207 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
208 u32 offset, void *src, size_t size);
209 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
210 u32 offset, void *dest, size_t size);
213 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
214 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
216 int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
217 struct snd_pcm_substream *substream,
219 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
220 struct snd_sof_ipc_msg *msg);
221 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
222 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
223 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
224 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
226 /* ACP - DSP stream callbacks */
227 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
228 int acp_dsp_stream_init(struct snd_sof_dev *sdev);
229 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
230 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
233 * DSP PCM Operations.
235 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
236 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
237 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
238 struct snd_pcm_hw_params *params,
239 struct snd_sof_platform_stream_params *platform_params);
241 extern struct snd_sof_dsp_ops sof_acp_common_ops;
243 extern struct snd_sof_dsp_ops sof_renoir_ops;
244 int sof_renoir_ops_init(struct snd_sof_dev *sdev);
245 extern struct snd_sof_dsp_ops sof_rembrandt_ops;
246 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
248 int acp_dai_probe(struct snd_soc_dai *dai);
249 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
250 /* Machine configuration */
251 int snd_amd_acp_find_config(struct pci_dev *pci);
254 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
255 struct sof_ipc_dma_trace_params_ext *dtrace_params);
256 int acp_sof_trace_release(struct snd_sof_dev *sdev);
259 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
260 int amd_sof_acp_resume(struct snd_sof_dev *sdev);
262 void amd_sof_ipc_dump(struct snd_sof_dev *sdev);
263 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
265 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
267 const struct sof_dev_desc *desc = pdata->desc;
269 return desc->chip_info;