sound/soc/sh/rcar/adg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Helper routines for R-Car sound ADG.
   4 //
   5 //  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6
   7 #include <linux/clk-provider.h>
   8 #include "rsnd.h"
   9
  10 #define CLKA    0
  11 #define CLKB    1
  12 #define CLKC    2
  13 #define CLKI    3
  14 #define CLKMAX  4
  15
  16 #define CLKOUT  0
  17 #define CLKOUT1 1
  18 #define CLKOUT2 2
  19 #define CLKOUT3 3
  20 #define CLKOUTMAX 4
  21
  22 #define BRRx_MASK(x) (0x3FF & x)
  23
  24 static struct rsnd_mod_ops adg_ops = {
  25         .name = "adg",
  26 };
  27
  28 struct rsnd_adg {
  29         struct clk *clk[CLKMAX];
  30         struct clk *clkout[CLKOUTMAX];
  31         struct clk_onecell_data onecell;
  32         struct rsnd_mod mod;
  33         int clk_rate[CLKMAX];
  34         u32 flags;
  35         u32 ckr;
  36         u32 rbga;
  37         u32 rbgb;
  38
  39         int rbga_rate_for_441khz; /* RBGA */
  40         int rbgb_rate_for_48khz;  /* RBGB */
  41 };
  42
  43 #define LRCLK_ASYNC     (1 << 0)
  44 #define AUDIO_OUT_48    (1 << 1)
  45
  46 #define for_each_rsnd_clk(pos, adg, i)          \
  47         for (i = 0;                             \
  48              (i < CLKMAX) &&                    \
  49              ((pos) = adg->clk[i]);             \
  50              i++)
  51 #define for_each_rsnd_clkout(pos, adg, i)       \
  52         for (i = 0;                             \
  53              (i < CLKOUTMAX) &&                 \
  54              ((pos) = adg->clkout[i]);  \
  55              i++)
  56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  57
  58 static const char * const clk_name[] = {
  59         [CLKA]  = "clk_a",
  60         [CLKB]  = "clk_b",
  61         [CLKC]  = "clk_c",
  62         [CLKI]  = "clk_i",
  63 };
  64
  65 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  66 {
  67         int i, ratio;
  68
  69         if (!div)
  70                 return 0;
  71
  72         for (i = 3; i >= 0; i--) {
  73                 ratio = 2 << (i * 2);
  74                 if (0 == (div % ratio))
  75                         return (u32)((i << 8) | ((div / ratio) - 1));
  76         }
  77
  78         return ~0;
  79 }
  80
  81 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  82 {
  83         struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
  84         int id = rsnd_mod_id(ssi_mod);
  85         int ws = id;
  86
  87         if (rsnd_ssi_is_pin_sharing(io)) {
  88                 switch (id) {
  89                 case 1:
  90                 case 2:
  91                 case 9:
  92                         ws = 0;
  93                         break;
  94                 case 4:
  95                         ws = 3;
  96                         break;
  97                 case 8:
  98                         ws = 7;
  99                         break;
 100                 }
 101         }
 102
 103         return (0x6 + ws) << 8;
 104 }
 105
 106 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 107                                        struct rsnd_dai_stream *io,
 108                                        unsigned int target_rate,
 109                                        unsigned int *target_val,
 110                                        unsigned int *target_en)
 111 {
 112         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 113         struct device *dev = rsnd_priv_to_dev(priv);
 114         int idx, sel, div, step;
 115         unsigned int val, en;
 116         unsigned int min, diff;
 117         unsigned int sel_rate[] = {
 118                 adg->clk_rate[CLKA],    /* 0000: CLKA */
 119                 adg->clk_rate[CLKB],    /* 0001: CLKB */
 120                 adg->clk_rate[CLKC],    /* 0010: CLKC */
 121                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 122                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 123         };
 124
 125         min = ~0;
 126         val = 0;
 127         en = 0;
 128         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 129                 idx = 0;
 130                 step = 2;
 131
 132                 if (!sel_rate[sel])
 133                         continue;
 134
 135                 for (div = 2; div <= 98304; div += step) {
 136                         diff = abs(target_rate - sel_rate[sel] / div);
 137                         if (min > diff) {
 138                                 val = (sel << 8) | idx;
 139                                 min = diff;
 140                                 en = 1 << (sel + 1); /* fixme */
 141                         }
 142
 143                         /*
 144                          * step of 0_0000 / 0_0001 / 0_1101
 145                          * are out of order
 146                          */
 147                         if ((idx > 2) && (idx % 2))
 148                                 step *= 2;
 149                         if (idx == 0x1c) {
 150                                 div += step;
 151                                 step *= 2;
 152                         }
 153                         idx++;
 154                 }
 155         }
 156
 157         if (min == ~0) {
 158                 dev_err(dev, "no Input clock\n");
 159                 return;
 160         }
 161
 162         *target_val = val;
 163         if (target_en)
 164                 *target_en = en;
 165 }
 166
 167 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 168                                        struct rsnd_dai_stream *io,
 169                                        unsigned int in_rate,
 170                                        unsigned int out_rate,
 171                                        u32 *in, u32 *out, u32 *en)
 172 {
 173         struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
 174         unsigned int target_rate;
 175         u32 *target_val;
 176         u32 _in;
 177         u32 _out;
 178         u32 _en;
 179
 180         /* default = SSI WS */
 181         _in =
 182         _out = rsnd_adg_ssi_ws_timing_gen2(io);
 183
 184         target_rate = 0;
 185         target_val = NULL;
 186         _en = 0;
 187         if (runtime->rate != in_rate) {
 188                 target_rate = out_rate;
 189                 target_val  = &_out;
 190         } else if (runtime->rate != out_rate) {
 191                 target_rate = in_rate;
 192                 target_val  = &_in;
 193         }
 194
 195         if (target_rate)
 196                 __rsnd_adg_get_timesel_ratio(priv, io,
 197                                              target_rate,
 198                                              target_val, &_en);
 199
 200         if (in)
 201                 *in = _in;
 202         if (out)
 203                 *out = _out;
 204         if (en)
 205                 *en = _en;
 206 }
 207
 208 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
 209                                  struct rsnd_dai_stream *io)
 210 {
 211         struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
 212         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 213         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 214         int id = rsnd_mod_id(cmd_mod);
 215         int shift = (id % 2) ? 16 : 0;
 216         u32 mask, val;
 217
 218         rsnd_adg_get_timesel_ratio(priv, io,
 219                                    rsnd_src_get_in_rate(priv, io),
 220                                    rsnd_src_get_out_rate(priv, io),
 221                                    NULL, &val, NULL);
 222
 223         val  = val      << shift;
 224         mask = 0x0f1f   << shift;
 225
 226         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 227
 228         return 0;
 229 }
 230
 231 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
 232                                   struct rsnd_dai_stream *io,
 233                                   unsigned int in_rate,
 234                                   unsigned int out_rate)
 235 {
 236         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 237         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 238         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 239         u32 in, out;
 240         u32 mask, en;
 241         int id = rsnd_mod_id(src_mod);
 242         int shift = (id % 2) ? 16 : 0;
 243
 244         rsnd_mod_confirm_src(src_mod);
 245
 246         rsnd_adg_get_timesel_ratio(priv, io,
 247                                    in_rate, out_rate,
 248                                    &in, &out, &en);
 249
 250         in   = in       << shift;
 251         out  = out      << shift;
 252         mask = 0x0f1f   << shift;
 253
 254         rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2),  mask, in);
 255         rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
 256
 257         if (en)
 258                 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 259
 260         return 0;
 261 }
 262
 263 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 264 {
 265         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 266         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 267         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 268         struct device *dev = rsnd_priv_to_dev(priv);
 269         int id = rsnd_mod_id(ssi_mod);
 270         int shift = (id % 4) * 8;
 271         u32 mask = 0xFF << shift;
 272
 273         rsnd_mod_confirm_ssi(ssi_mod);
 274
 275         val = val << shift;
 276
 277         /*
 278          * SSI 8 is not connected to ADG.
 279          * it works with SSI 7
 280          */
 281         if (id == 8)
 282                 return;
 283
 284         rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
 285
 286         dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
 287 }
 288
 289 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
 290 {
 291         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 292         struct clk *clk;
 293         int i;
 294         int sel_table[] = {
 295                 [CLKA] = 0x1,
 296                 [CLKB] = 0x2,
 297                 [CLKC] = 0x3,
 298                 [CLKI] = 0x0,
 299         };
 300
 301         /*
 302          * find suitable clock from
 303          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 304          */
 305         for_each_rsnd_clk(clk, adg, i) {
 306                 if (rate == adg->clk_rate[i])
 307                         return sel_table[i];
 308         }
 309
 310         /*
 311          * find divided clock from BRGA/BRGB
 312          */
 313         if (rate == adg->rbga_rate_for_441khz)
 314                 return 0x10;
 315
 316         if (rate == adg->rbgb_rate_for_48khz)
 317                 return 0x20;
 318
 319         return -EIO;
 320 }
 321
 322 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
 323 {
 324         rsnd_adg_set_ssi_clk(ssi_mod, 0);
 325
 326         return 0;
 327 }
 328
 329 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
 330 {
 331         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 332         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 333         struct device *dev = rsnd_priv_to_dev(priv);
 334         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 335         int data;
 336         u32 ckr = 0;
 337
 338         data = rsnd_adg_clk_query(priv, rate);
 339         if (data < 0)
 340                 return data;
 341
 342         rsnd_adg_set_ssi_clk(ssi_mod, data);
 343
 344         if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
 345                 if (rsnd_flags_has(adg, AUDIO_OUT_48))
 346                         ckr = 0x80000000;
 347         } else {
 348                 if (0 == (rate % 8000))
 349                         ckr = 0x80000000;
 350         }
 351
 352         rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
 353         rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
 354         rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
 355
 356         dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
 357                 (ckr) ? 'B' : 'A',
 358                 (ckr) ? adg->rbgb_rate_for_48khz :
 359                         adg->rbga_rate_for_441khz);
 360
 361         return 0;
 362 }
 363
 364 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
 365 {
 366         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 367         struct device *dev = rsnd_priv_to_dev(priv);
 368         struct clk *clk;
 369         int i;
 370
 371         for_each_rsnd_clk(clk, adg, i) {
 372                 if (enable) {
 373                         int ret = clk_prepare_enable(clk);
 374
 375                         /*
 376                          * We shouldn't use clk_get_rate() under
 377                          * atomic context. Let's keep it when
 378                          * rsnd_adg_clk_enable() was called
 379                          */
 380                         adg->clk_rate[i] = 0;
 381                         if (ret < 0)
 382                                 dev_warn(dev, "can't use clk %d\n", i);
 383                         else
 384                                 adg->clk_rate[i] = clk_get_rate(clk);
 385                 } else {
 386                         if (adg->clk_rate[i])
 387                                 clk_disable_unprepare(clk);
 388                         adg->clk_rate[i] = 0;
 389                 }
 390         }
 391 }
 392
 393 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 394                                struct rsnd_adg *adg)
 395 {
 396         struct device *dev = rsnd_priv_to_dev(priv);
 397         struct clk *clk;
 398         int i;
 399
 400         for (i = 0; i < CLKMAX; i++) {
 401                 clk = devm_clk_get(dev, clk_name[i]);
 402                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 403         }
 404 }
 405
 406 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 407                                 struct rsnd_adg *adg)
 408 {
 409         struct clk *clk;
 410         struct device *dev = rsnd_priv_to_dev(priv);
 411         struct device_node *np = dev->of_node;
 412         struct property *prop;
 413         u32 ckr, rbgx, rbga, rbgb;
 414         u32 rate, div;
 415 #define REQ_SIZE 2
 416         u32 req_rate[REQ_SIZE] = {};
 417         uint32_t count = 0;
 418         unsigned long req_48kHz_rate, req_441kHz_rate;
 419         int i, req_size;
 420         const char *parent_clk_name = NULL;
 421         static const char * const clkout_name[] = {
 422                 [CLKOUT]  = "audio_clkout",
 423                 [CLKOUT1] = "audio_clkout1",
 424                 [CLKOUT2] = "audio_clkout2",
 425                 [CLKOUT3] = "audio_clkout3",
 426         };
 427         int brg_table[] = {
 428                 [CLKA] = 0x0,
 429                 [CLKB] = 0x1,
 430                 [CLKC] = 0x4,
 431                 [CLKI] = 0x2,
 432         };
 433
 434         ckr = 0;
 435         rbga = 2; /* default 1/6 */
 436         rbgb = 2; /* default 1/6 */
 437
 438         /*
 439          * ADG supports BRRA/BRRB output only
 440          * this means all clkout0/1/2/3 will be same rate
 441          */
 442         prop = of_find_property(np, "clock-frequency", NULL);
 443         if (!prop)
 444                 goto rsnd_adg_get_clkout_end;
 445
 446         req_size = prop->length / sizeof(u32);
 447         if (req_size > REQ_SIZE) {
 448                 dev_err(dev,
 449                         "too many clock-frequency, use top %d\n", REQ_SIZE);
 450                 req_size = REQ_SIZE;
 451         }
 452
 453         of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
 454         req_48kHz_rate = 0;
 455         req_441kHz_rate = 0;
 456         for (i = 0; i < req_size; i++) {
 457                 if (0 == (req_rate[i] % 44100))
 458                         req_441kHz_rate = req_rate[i];
 459                 if (0 == (req_rate[i] % 48000))
 460                         req_48kHz_rate = req_rate[i];
 461         }
 462
 463         if (req_rate[0] % 48000 == 0)
 464                 rsnd_flags_set(adg, AUDIO_OUT_48);
 465
 466         if (of_get_property(np, "clkout-lr-asynchronous", NULL))
 467                 rsnd_flags_set(adg, LRCLK_ASYNC);
 468
 469         /*
 470          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 471          * have 44.1kHz or 48kHz base clocks for now.
 472          *
 473          * SSI itself can divide parent clock by 1/1 - 1/16
 474          * see
 475          *      rsnd_adg_ssi_clk_try_start()
 476          *      rsnd_ssi_master_clk_start()
 477          */
 478         adg->rbga_rate_for_441khz       = 0;
 479         adg->rbgb_rate_for_48khz        = 0;
 480         for_each_rsnd_clk(clk, adg, i) {
 481                 rate = clk_get_rate(clk);
 482
 483                 if (0 == rate) /* not used */
 484                         continue;
 485
 486                 /* RBGA */
 487                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 488                         div = 6;
 489                         if (req_441kHz_rate)
 490                                 div = rate / req_441kHz_rate;
 491                         rbgx = rsnd_adg_calculate_rbgx(div);
 492                         if (BRRx_MASK(rbgx) == rbgx) {
 493                                 rbga = rbgx;
 494                                 adg->rbga_rate_for_441khz = rate / div;
 495                                 ckr |= brg_table[i] << 20;
 496                                 if (req_441kHz_rate &&
 497                                     !rsnd_flags_has(adg, AUDIO_OUT_48))
 498                                         parent_clk_name = __clk_get_name(clk);
 499                         }
 500                 }
 501
 502                 /* RBGB */
 503                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 504                         div = 6;
 505                         if (req_48kHz_rate)
 506                                 div = rate / req_48kHz_rate;
 507                         rbgx = rsnd_adg_calculate_rbgx(div);
 508                         if (BRRx_MASK(rbgx) == rbgx) {
 509                                 rbgb = rbgx;
 510                                 adg->rbgb_rate_for_48khz = rate / div;
 511                                 ckr |= brg_table[i] << 16;
 512                                 if (req_48kHz_rate &&
 513                                     rsnd_flags_has(adg, AUDIO_OUT_48))
 514                                         parent_clk_name = __clk_get_name(clk);
 515                         }
 516                 }
 517         }
 518
 519         /*
 520          * ADG supports BRRA/BRRB output only.
 521          * this means all clkout0/1/2/3 will be * same rate
 522          */
 523
 524         of_property_read_u32(np, "#clock-cells", &count);
 525         /*
 526          * for clkout
 527          */
 528         if (!count) {
 529                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 530                                               parent_clk_name, 0, req_rate[0]);
 531                 if (!IS_ERR(clk)) {
 532                         adg->clkout[CLKOUT] = clk;
 533                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 534                 }
 535         }
 536         /*
 537          * for clkout0/1/2/3
 538          */
 539         else {
 540                 for (i = 0; i < CLKOUTMAX; i++) {
 541                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 542                                                       parent_clk_name, 0,
 543                                                       req_rate[0]);
 544                         if (!IS_ERR(clk))
 545                                 adg->clkout[i] = clk;
 546                 }
 547                 adg->onecell.clks       = adg->clkout;
 548                 adg->onecell.clk_num    = CLKOUTMAX;
 549                 of_clk_add_provider(np, of_clk_src_onecell_get,
 550                                     &adg->onecell);
 551         }
 552
 553 rsnd_adg_get_clkout_end:
 554         adg->ckr = ckr;
 555         adg->rbga = rbga;
 556         adg->rbgb = rbgb;
 557 }
 558
 559 #ifdef DEBUG
 560 static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
 561 {
 562         struct device *dev = rsnd_priv_to_dev(priv);
 563         struct clk *clk;
 564         int i;
 565
 566         for_each_rsnd_clk(clk, adg, i)
 567                 dev_dbg(dev, "%s    : %pa : %ld\n",
 568                         clk_name[i], clk, clk_get_rate(clk));
 569
 570         dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 571                 adg->ckr, adg->rbga, adg->rbgb);
 572         dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
 573         dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
 574
 575         /*
 576          * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
 577          * by BRGCKR::BRGCKR_31
 578          */
 579         for_each_rsnd_clkout(clk, adg, i)
 580                 dev_dbg(dev, "clkout %d : %pa : %ld\n", i,
 581                         clk, clk_get_rate(clk));
 582 }
 583 #else
 584 #define rsnd_adg_clk_dbg_info(priv, adg)
 585 #endif
 586
 587 int rsnd_adg_probe(struct rsnd_priv *priv)
 588 {
 589         struct rsnd_adg *adg;
 590         struct device *dev = rsnd_priv_to_dev(priv);
 591         int ret;
 592
 593         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 594         if (!adg)
 595                 return -ENOMEM;
 596
 597         ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
 598                       NULL, 0, 0);
 599         if (ret)
 600                 return ret;
 601
 602         rsnd_adg_get_clkin(priv, adg);
 603         rsnd_adg_get_clkout(priv, adg);
 604         rsnd_adg_clk_dbg_info(priv, adg);
 605
 606         priv->adg = adg;
 607
 608         rsnd_adg_clk_enable(priv);
 609
 610         return 0;
 611 }
 612
 613 void rsnd_adg_remove(struct rsnd_priv *priv)
 614 {
 615         struct device *dev = rsnd_priv_to_dev(priv);
 616         struct device_node *np = dev->of_node;
 617         struct rsnd_adg *adg = priv->adg;
 618         struct clk *clk;
 619         int i;
 620
 621         for_each_rsnd_clkout(clk, adg, i)
 622                 if (adg->clkout[i])
 623                         clk_unregister_fixed_rate(adg->clkout[i]);
 624
 625         of_clk_del_provider(np);
 626
 627         rsnd_adg_clk_disable(priv);
 628 }