sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/sh_clk.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 struct rsnd_adg {
  20         struct clk *clk[CLKMAX];
  21
  22         int rbga_rate_for_441khz_div_6; /* RBGA */
  23         int rbgb_rate_for_48khz_div_6;  /* RBGB */
  24         u32 ckr;
  25 };
  26
  27 #define for_each_rsnd_clk(pos, adg, i)          \
  28         for (i = 0;                             \
  29              (i < CLKMAX) &&                    \
  30              ((pos) = adg->clk[i]);             \
  31              i++)
  32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  33
  34
  35 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_mod *mod)
  36 {
  37         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  38         int id = rsnd_mod_id(mod);
  39         int ws = id;
  40
  41         if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
  42                 switch (id) {
  43                 case 1:
  44                 case 2:
  45                         ws = 0;
  46                         break;
  47                 case 4:
  48                         ws = 3;
  49                         break;
  50                 case 8:
  51                         ws = 7;
  52                         break;
  53                 }
  54         }
  55
  56         return (0x6 + ws) << 8;
  57 }
  58
  59 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai,
  60                                         struct rsnd_mod *mod,
  61                                         struct rsnd_dai_stream *io,
  62                                         u32 timsel)
  63 {
  64         int is_play = rsnd_dai_is_play(rdai, io);
  65         int id = rsnd_mod_id(mod);
  66         int shift = (id % 2) ? 16 : 0;
  67         u32 mask, ws;
  68         u32 in, out;
  69
  70         ws = rsnd_adg_ssi_ws_timing_gen2(mod);
  71
  72         in  = (is_play) ? timsel : ws;
  73         out = (is_play) ? ws     : timsel;
  74
  75         in   = in       << shift;
  76         out  = out      << shift;
  77         mask = 0xffff   << shift;
  78
  79         switch (id / 2) {
  80         case 0:
  81                 rsnd_mod_bset(mod, SRCIN_TIMSEL0,  mask, in);
  82                 rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
  83                 break;
  84         case 1:
  85                 rsnd_mod_bset(mod, SRCIN_TIMSEL1,  mask, in);
  86                 rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
  87                 break;
  88         case 2:
  89                 rsnd_mod_bset(mod, SRCIN_TIMSEL2,  mask, in);
  90                 rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
  91                 break;
  92         case 3:
  93                 rsnd_mod_bset(mod, SRCIN_TIMSEL3,  mask, in);
  94                 rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
  95                 break;
  96         case 4:
  97                 rsnd_mod_bset(mod, SRCIN_TIMSEL4,  mask, in);
  98                 rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
  99                 break;
 100         }
 101
 102         return 0;
 103 }
 104
 105 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
 106                                   struct rsnd_dai *rdai,
 107                                   struct rsnd_dai_stream *io,
 108                                   unsigned int src_rate,
 109                                   unsigned int dst_rate)
 110 {
 111         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 112         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 113         struct device *dev = rsnd_priv_to_dev(priv);
 114         int idx, sel, div, step, ret;
 115         u32 val, en;
 116         unsigned int min, diff;
 117         unsigned int sel_rate [] = {
 118                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 119                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 120                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 121                 adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
 122                 adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
 123         };
 124
 125         min = ~0;
 126         val = 0;
 127         en = 0;
 128         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 129                 idx = 0;
 130                 step = 2;
 131
 132                 if (!sel_rate[sel])
 133                         continue;
 134
 135                 for (div = 2; div <= 98304; div += step) {
 136                         diff = abs(src_rate - sel_rate[sel] / div);
 137                         if (min > diff) {
 138                                 val = (sel << 8) | idx;
 139                                 min = diff;
 140                                 en = 1 << (sel + 1); /* fixme */
 141                         }
 142
 143                         /*
 144                          * step of 0_0000 / 0_0001 / 0_1101
 145                          * are out of order
 146                          */
 147                         if ((idx > 2) && (idx % 2))
 148                                 step *= 2;
 149                         if (idx == 0x1c) {
 150                                 div += step;
 151                                 step *= 2;
 152                         }
 153                         idx++;
 154                 }
 155         }
 156
 157         if (min == ~0) {
 158                 dev_err(dev, "no Input clock\n");
 159                 return -EIO;
 160         }
 161
 162         ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
 163         if (ret < 0) {
 164                 dev_err(dev, "timsel error\n");
 165                 return ret;
 166         }
 167
 168         rsnd_mod_bset(mod, DIV_EN, en, en);
 169
 170         return 0;
 171 }
 172
 173 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
 174                                      struct rsnd_dai *rdai,
 175                                      struct rsnd_dai_stream *io)
 176 {
 177         u32 val = rsnd_adg_ssi_ws_timing_gen2(mod);
 178
 179         return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
 180 }
 181
 182 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
 183                                   struct rsnd_mod *mod,
 184                                   unsigned int src_rate,
 185                                   unsigned int dst_rate)
 186 {
 187         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 188         struct device *dev = rsnd_priv_to_dev(priv);
 189         int idx, sel, div, shift;
 190         u32 mask, val;
 191         int id = rsnd_mod_id(mod);
 192         unsigned int sel_rate [] = {
 193                 clk_get_rate(adg->clk[CLKA]),   /* 000: CLKA */
 194                 clk_get_rate(adg->clk[CLKB]),   /* 001: CLKB */
 195                 clk_get_rate(adg->clk[CLKC]),   /* 010: CLKC */
 196                 0,                              /* 011: MLBCLK (not used) */
 197                 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
 198                 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
 199         };
 200
 201         /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
 202         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 203                 for (div  = 128,        idx = 0;
 204                      div <= 2048;
 205                      div *= 2,          idx++) {
 206                         if (src_rate == sel_rate[sel] / div) {
 207                                 val = (idx << 4) | sel;
 208                                 goto find_rate;
 209                         }
 210                 }
 211         }
 212         dev_err(dev, "can't find convert src clk\n");
 213         return -EINVAL;
 214
 215 find_rate:
 216         shift   = (id % 4) * 8;
 217         mask    = 0xFF << shift;
 218         val     = val << shift;
 219
 220         dev_dbg(dev, "adg convert src clk = %02x\n", val);
 221
 222         switch (id / 4) {
 223         case 0:
 224                 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
 225                 break;
 226         case 1:
 227                 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
 228                 break;
 229         case 2:
 230                 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
 231                 break;
 232         }
 233
 234         /*
 235          * Gen1 doesn't need dst_rate settings,
 236          * since it uses SSI WS pin.
 237          * see also rsnd_src_set_route_if_gen1()
 238          */
 239
 240         return 0;
 241 }
 242
 243 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
 244 {
 245         int id = rsnd_mod_id(mod);
 246         int shift = (id % 4) * 8;
 247         u32 mask = 0xFF << shift;
 248
 249         val = val << shift;
 250
 251         /*
 252          * SSI 8 is not connected to ADG.
 253          * it works with SSI 7
 254          */
 255         if (id == 8)
 256                 return;
 257
 258         switch (id / 4) {
 259         case 0:
 260                 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
 261                 break;
 262         case 1:
 263                 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
 264                 break;
 265         case 2:
 266                 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
 267                 break;
 268         }
 269 }
 270
 271 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
 272 {
 273         /*
 274          * "mod" = "ssi" here.
 275          * we can get "ssi id" from mod
 276          */
 277         rsnd_adg_set_ssi_clk(mod, 0);
 278
 279         return 0;
 280 }
 281
 282 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
 283 {
 284         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 285         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 286         struct device *dev = rsnd_priv_to_dev(priv);
 287         struct clk *clk;
 288         int i;
 289         u32 data;
 290         int sel_table[] = {
 291                 [CLKA] = 0x1,
 292                 [CLKB] = 0x2,
 293                 [CLKC] = 0x3,
 294                 [CLKI] = 0x0,
 295         };
 296
 297         dev_dbg(dev, "request clock = %d\n", rate);
 298
 299         /*
 300          * find suitable clock from
 301          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 302          */
 303         data = 0;
 304         for_each_rsnd_clk(clk, adg, i) {
 305                 if (rate == clk_get_rate(clk)) {
 306                         data = sel_table[i];
 307                         goto found_clock;
 308                 }
 309         }
 310
 311         /*
 312          * find 1/6 clock from BRGA/BRGB
 313          */
 314         if (rate == adg->rbga_rate_for_441khz_div_6) {
 315                 data = 0x10;
 316                 goto found_clock;
 317         }
 318
 319         if (rate == adg->rbgb_rate_for_48khz_div_6) {
 320                 data = 0x20;
 321                 goto found_clock;
 322         }
 323
 324         return -EIO;
 325
 326 found_clock:
 327
 328         /* see rsnd_adg_ssi_clk_init() */
 329         rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
 330         rsnd_mod_write(mod, BRRA,  0x00000002); /* 1/6 */
 331         rsnd_mod_write(mod, BRRB,  0x00000002); /* 1/6 */
 332
 333         /*
 334          * This "mod" = "ssi" here.
 335          * we can get "ssi id" from mod
 336          */
 337         rsnd_adg_set_ssi_clk(mod, data);
 338
 339         dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
 340                 rsnd_mod_id(mod), i, rate);
 341
 342         return 0;
 343 }
 344
 345 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
 346 {
 347         struct clk *clk;
 348         unsigned long rate;
 349         u32 ckr;
 350         int i;
 351         int brg_table[] = {
 352                 [CLKA] = 0x0,
 353                 [CLKB] = 0x1,
 354                 [CLKC] = 0x4,
 355                 [CLKI] = 0x2,
 356         };
 357
 358         /*
 359          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 360          * have 44.1kHz or 48kHz base clocks for now.
 361          *
 362          * SSI itself can divide parent clock by 1/1 - 1/16
 363          * So,  BRGA outputs 44.1kHz base parent clock 1/32,
 364          * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
 365          * see
 366          *      rsnd_adg_ssi_clk_try_start()
 367          */
 368         ckr = 0;
 369         adg->rbga_rate_for_441khz_div_6 = 0;
 370         adg->rbgb_rate_for_48khz_div_6  = 0;
 371         for_each_rsnd_clk(clk, adg, i) {
 372                 rate = clk_get_rate(clk);
 373
 374                 if (0 == rate) /* not used */
 375                         continue;
 376
 377                 /* RBGA */
 378                 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
 379                         adg->rbga_rate_for_441khz_div_6 = rate / 6;
 380                         ckr |= brg_table[i] << 20;
 381                 }
 382
 383                 /* RBGB */
 384                 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
 385                         adg->rbgb_rate_for_48khz_div_6 = rate / 6;
 386                         ckr |= brg_table[i] << 16;
 387                 }
 388         }
 389
 390         adg->ckr = ckr;
 391 }
 392
 393 int rsnd_adg_probe(struct platform_device *pdev,
 394                    struct rsnd_priv *priv)
 395 {
 396         struct rsnd_adg *adg;
 397         struct device *dev = rsnd_priv_to_dev(priv);
 398         struct clk *clk, *clk_orig;
 399         int i;
 400         bool use_old_style = false;
 401
 402         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 403         if (!adg) {
 404                 dev_err(dev, "ADG allocate failed\n");
 405                 return -ENOMEM;
 406         }
 407
 408         clk_orig        = clk_get(dev, NULL);
 409         adg->clk[CLKA]  = clk_get(dev, "clk_a");
 410         adg->clk[CLKB]  = clk_get(dev, "clk_b");
 411         adg->clk[CLKC]  = clk_get(dev, "clk_c");
 412         adg->clk[CLKI]  = clk_get(dev, "clk_i");
 413
 414         /*
 415          * It request device dependent audio clock.
 416          * But above all clks will indicate rsnd module clock
 417          * if platform doesn't it
 418          */
 419         for_each_rsnd_clk(clk, adg, i) {
 420                 if (clk_orig == clk) {
 421                         dev_warn(dev,
 422                                  "doesn't have device dependent clock, use independent clock\n");
 423                         use_old_style = true;
 424                         break;
 425                 }
 426         }
 427
 428         /*
 429          * note:
 430          * these exist in order to keep compatible with
 431          * platform which has device independent audio clock,
 432          * but will be removed soon
 433          */
 434         if (use_old_style) {
 435                 adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
 436                 adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
 437                 adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
 438                 adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
 439         }
 440
 441         for_each_rsnd_clk(clk, adg, i) {
 442                 if (IS_ERR(clk)) {
 443                         dev_err(dev, "Audio clock failed\n");
 444                         return -EIO;
 445                 }
 446         }
 447
 448         rsnd_adg_ssi_clk_init(priv, adg);
 449
 450         priv->adg = adg;
 451
 452         dev_dbg(dev, "adg probed\n");
 453
 454         return 0;
 455 }
 456
 457 void rsnd_adg_remove(struct platform_device *pdev,
 458                      struct rsnd_priv *priv)
 459 {
 460         struct rsnd_adg *adg = priv->adg;
 461         struct clk *clk;
 462         int i;
 463
 464         for_each_rsnd_clk(clk, adg, i)
 465                 clk_put(clk);
 466 }