1 /* sound/soc/samsung/ac97.c
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassisinghbrar@gmail.com>
8 * Credits: Graeme Gregory, Sean Choi
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
20 #include <sound/soc.h>
23 #include "regs-ac97.h"
24 #include <linux/platform_data/asoc-s3c.h>
28 #define AC_CMD_ADDR(x) (x << 16)
29 #define AC_CMD_DATA(x) (x & 0xffff)
31 #define S3C_AC97_DAI_PCM 0
32 #define S3C_AC97_DAI_MIC 1
34 struct s3c_ac97_info {
38 struct completion done;
40 static struct s3c_ac97_info s3c_ac97;
42 static struct s3c2410_dma_client s3c_dma_client_out = {
46 static struct s3c2410_dma_client s3c_dma_client_in = {
50 static struct s3c2410_dma_client s3c_dma_client_micin = {
54 static struct s3c_dma_params s3c_ac97_pcm_out = {
55 .client = &s3c_dma_client_out,
59 static struct s3c_dma_params s3c_ac97_pcm_in = {
60 .client = &s3c_dma_client_in,
64 static struct s3c_dma_params s3c_ac97_mic_in = {
65 .client = &s3c_dma_client_micin,
69 static void s3c_ac97_activate(struct snd_ac97 *ac97)
73 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
74 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
75 return; /* Return if already active */
77 INIT_COMPLETION(s3c_ac97.done);
79 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
80 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
81 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
84 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
85 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
88 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
89 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
90 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
92 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
93 pr_err("AC97: Unable to activate!");
96 static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
99 u32 ac_glbctrl, ac_codec_cmd;
100 u32 stat, addr, data;
102 mutex_lock(&s3c_ac97.lock);
104 s3c_ac97_activate(ac97);
106 INIT_COMPLETION(s3c_ac97.done);
108 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
109 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
110 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
114 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
115 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
116 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
118 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
119 pr_err("AC97: Unable to read!");
121 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
122 addr = (stat >> 16) & 0x7f;
123 data = (stat & 0xffff);
126 pr_err("ac97: req addr = %02x, rep addr = %02x\n",
129 mutex_unlock(&s3c_ac97.lock);
131 return (unsigned short)data;
134 static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
137 u32 ac_glbctrl, ac_codec_cmd;
139 mutex_lock(&s3c_ac97.lock);
141 s3c_ac97_activate(ac97);
143 INIT_COMPLETION(s3c_ac97.done);
145 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
146 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
147 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
151 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
152 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
153 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
155 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
156 pr_err("AC97: Unable to write!");
158 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
159 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
160 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
162 mutex_unlock(&s3c_ac97.lock);
165 static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
167 pr_debug("AC97: Cold reset\n");
168 writel(S3C_AC97_GLBCTRL_COLDRESET,
169 s3c_ac97.regs + S3C_AC97_GLBCTRL);
172 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
176 static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
180 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
181 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
182 return; /* Return if already active */
184 pr_debug("AC97: Warm reset\n");
186 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
189 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
192 s3c_ac97_activate(ac97);
195 static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
197 u32 ac_glbctrl, ac_glbstat;
199 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
201 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
203 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
204 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
205 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
207 complete(&s3c_ac97.done);
210 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
211 ac_glbctrl |= (1<<30); /* Clear interrupt */
212 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
217 static struct snd_ac97_bus_ops s3c_ac97_ops = {
218 .read = s3c_ac97_read,
219 .write = s3c_ac97_write,
220 .warm_reset = s3c_ac97_warm_reset,
221 .reset = s3c_ac97_cold_reset,
224 static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *dai)
228 struct snd_soc_pcm_runtime *rtd = substream->private_data;
229 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
230 struct s3c_dma_params *dma_data;
232 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
233 dma_data = &s3c_ac97_pcm_out;
235 dma_data = &s3c_ac97_pcm_in;
237 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
242 static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
243 struct snd_soc_dai *dai)
246 struct snd_soc_pcm_runtime *rtd = substream->private_data;
247 struct s3c_dma_params *dma_data =
248 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
250 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
251 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
252 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
254 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
257 case SNDRV_PCM_TRIGGER_START:
258 case SNDRV_PCM_TRIGGER_RESUME:
259 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
260 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
261 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
263 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
266 case SNDRV_PCM_TRIGGER_STOP:
267 case SNDRV_PCM_TRIGGER_SUSPEND:
268 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
272 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
275 dma_data->ops = samsung_dma_get_ops();
277 dma_data->ops->started(dma_data->channel);
282 static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
283 struct snd_pcm_hw_params *params,
284 struct snd_soc_dai *dai)
286 struct snd_soc_pcm_runtime *rtd = substream->private_data;
287 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
289 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
292 snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
297 static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
298 int cmd, struct snd_soc_dai *dai)
301 struct snd_soc_pcm_runtime *rtd = substream->private_data;
302 struct s3c_dma_params *dma_data =
303 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
305 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
306 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
309 case SNDRV_PCM_TRIGGER_START:
310 case SNDRV_PCM_TRIGGER_RESUME:
311 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
312 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
315 case SNDRV_PCM_TRIGGER_STOP:
316 case SNDRV_PCM_TRIGGER_SUSPEND:
317 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
321 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
324 dma_data->ops = samsung_dma_get_ops();
326 dma_data->ops->started(dma_data->channel);
331 static const struct snd_soc_dai_ops s3c_ac97_dai_ops = {
332 .hw_params = s3c_ac97_hw_params,
333 .trigger = s3c_ac97_trigger,
336 static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
337 .hw_params = s3c_ac97_hw_mic_params,
338 .trigger = s3c_ac97_mic_trigger,
341 static struct snd_soc_dai_driver s3c_ac97_dai[] = {
342 [S3C_AC97_DAI_PCM] = {
343 .name = "samsung-ac97",
346 .stream_name = "AC97 Playback",
349 .rates = SNDRV_PCM_RATE_8000_48000,
350 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
352 .stream_name = "AC97 Capture",
355 .rates = SNDRV_PCM_RATE_8000_48000,
356 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
357 .ops = &s3c_ac97_dai_ops,
359 [S3C_AC97_DAI_MIC] = {
360 .name = "samsung-ac97-mic",
363 .stream_name = "AC97 Mic Capture",
366 .rates = SNDRV_PCM_RATE_8000_48000,
367 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
368 .ops = &s3c_ac97_mic_dai_ops,
372 static const struct snd_soc_component_driver s3c_ac97_component = {
376 static int s3c_ac97_probe(struct platform_device *pdev)
378 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
379 struct s3c_audio_pdata *ac97_pdata;
382 ac97_pdata = pdev->dev.platform_data;
383 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
384 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
388 /* Check for availability of necessary resource */
389 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
391 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
395 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
397 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
401 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
403 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
407 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
409 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
413 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
414 s3c_ac97.regs = devm_ioremap_resource(&pdev->dev, mem_res);
415 if (IS_ERR(s3c_ac97.regs))
416 return PTR_ERR(s3c_ac97.regs);
418 s3c_ac97_pcm_out.channel = dmatx_res->start;
419 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
420 s3c_ac97_pcm_in.channel = dmarx_res->start;
421 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
422 s3c_ac97_mic_in.channel = dmamic_res->start;
423 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
425 init_completion(&s3c_ac97.done);
426 mutex_init(&s3c_ac97.lock);
428 s3c_ac97.ac97_clk = devm_clk_get(&pdev->dev, "ac97");
429 if (IS_ERR(s3c_ac97.ac97_clk)) {
430 dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
434 clk_prepare_enable(s3c_ac97.ac97_clk);
436 if (ac97_pdata->cfg_gpio(pdev)) {
437 dev_err(&pdev->dev, "Unable to configure gpio\n");
442 ret = request_irq(irq_res->start, s3c_ac97_irq,
445 dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
449 ret = snd_soc_set_ac97_ops(&s3c_ac97_ops);
451 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
455 ret = snd_soc_register_component(&pdev->dev, &s3c_ac97_component,
456 s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
460 ret = samsung_asoc_dma_platform_register(&pdev->dev);
462 dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
468 snd_soc_unregister_component(&pdev->dev);
470 free_irq(irq_res->start, NULL);
473 clk_disable_unprepare(s3c_ac97.ac97_clk);
475 snd_soc_set_ac97_ops(NULL);
479 static int s3c_ac97_remove(struct platform_device *pdev)
481 struct resource *irq_res;
483 samsung_asoc_dma_platform_unregister(&pdev->dev);
484 snd_soc_unregister_component(&pdev->dev);
486 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
488 free_irq(irq_res->start, NULL);
490 clk_disable_unprepare(s3c_ac97.ac97_clk);
491 snd_soc_set_ac97_ops(NULL);
496 static struct platform_driver s3c_ac97_driver = {
497 .probe = s3c_ac97_probe,
498 .remove = s3c_ac97_remove,
500 .name = "samsung-ac97",
501 .owner = THIS_MODULE,
505 module_platform_driver(s3c_ac97_driver);
507 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
508 MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
509 MODULE_LICENSE("GPL");
510 MODULE_ALIAS("platform:samsung-ac97");