sound/soc/rockchip/rockchip_i2s_tdm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
   3
   4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
   5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
   6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/spinlock.h>
  20 #include <sound/dmaengine_pcm.h>
  21 #include <sound/pcm_params.h>
  22
  23 #include "rockchip_i2s_tdm.h"
  24
  25 #define DRV_NAME "rockchip-i2s-tdm"
  26
  27 #define DEFAULT_MCLK_FS                         256
  28 #define CH_GRP_MAX                              4  /* The max channel 8 / 2 */
  29 #define MULTIPLEX_CH_MAX                        10
  30 #define CLK_PPM_MIN                             -1000
  31 #define CLK_PPM_MAX                             1000
  32
  33 #define TRCM_TXRX 0
  34 #define TRCM_TX 1
  35 #define TRCM_RX 2
  36
  37 struct txrx_config {
  38         u32 addr;
  39         u32 reg;
  40         u32 txonly;
  41         u32 rxonly;
  42 };
  43
  44 struct rk_i2s_soc_data {
  45         u32 softrst_offset;
  46         u32 grf_reg_offset;
  47         u32 grf_shift;
  48         int config_count;
  49         const struct txrx_config *configs;
  50         int (*init)(struct device *dev, u32 addr);
  51 };
  52
  53 struct rk_i2s_tdm_dev {
  54         struct device *dev;
  55         struct clk *hclk;
  56         struct clk *mclk_tx;
  57         struct clk *mclk_rx;
  58         /* The mclk_tx_src is parent of mclk_tx */
  59         struct clk *mclk_tx_src;
  60         /* The mclk_rx_src is parent of mclk_rx */
  61         struct clk *mclk_rx_src;
  62         /*
  63          * The mclk_root0 and mclk_root1 are root parent and supplies for
  64          * the different FS.
  65          *
  66          * e.g:
  67          * mclk_root0 is VPLL0, used for FS=48000Hz
  68          * mclk_root1 is VPLL1, used for FS=44100Hz
  69          */
  70         struct clk *mclk_root0;
  71         struct clk *mclk_root1;
  72         struct regmap *regmap;
  73         struct regmap *grf;
  74         struct snd_dmaengine_dai_dma_data capture_dma_data;
  75         struct snd_dmaengine_dai_dma_data playback_dma_data;
  76         struct reset_control *tx_reset;
  77         struct reset_control *rx_reset;
  78         struct rk_i2s_soc_data *soc_data;
  79         bool is_master_mode;
  80         bool io_multiplex;
  81         bool mclk_calibrate;
  82         bool tdm_mode;
  83         unsigned int mclk_rx_freq;
  84         unsigned int mclk_tx_freq;
  85         unsigned int mclk_root0_freq;
  86         unsigned int mclk_root1_freq;
  87         unsigned int mclk_root0_initial_freq;
  88         unsigned int mclk_root1_initial_freq;
  89         unsigned int frame_width;
  90         unsigned int clk_trcm;
  91         unsigned int i2s_sdis[CH_GRP_MAX];
  92         unsigned int i2s_sdos[CH_GRP_MAX];
  93         int clk_ppm;
  94         int refcount;
  95         spinlock_t lock; /* xfer lock */
  96         bool has_playback;
  97         bool has_capture;
  98         struct snd_soc_dai_driver *dai;
  99 };
 100
 101 static int to_ch_num(unsigned int val)
 102 {
 103         switch (val) {
 104         case I2S_CHN_4:
 105                 return 4;
 106         case I2S_CHN_6:
 107                 return 6;
 108         case I2S_CHN_8:
 109                 return 8;
 110         default:
 111                 return 2;
 112         }
 113 }
 114
 115 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
 116 {
 117         clk_disable_unprepare(i2s_tdm->mclk_tx);
 118         clk_disable_unprepare(i2s_tdm->mclk_rx);
 119         if (i2s_tdm->mclk_calibrate) {
 120                 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
 121                 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
 122                 clk_disable_unprepare(i2s_tdm->mclk_root0);
 123                 clk_disable_unprepare(i2s_tdm->mclk_root1);
 124         }
 125 }
 126
 127 /**
 128  * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
 129  *                               failure.
 130  * @i2s_tdm: rk_i2s_tdm_dev struct
 131  *
 132  * This function attempts to enable all mclk clocks, but cleans up after
 133  * itself on failure. Guarantees to balance its calls.
 134  *
 135  * Returns success (0) or negative errno.
 136  */
 137 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
 138 {
 139         int ret = 0;
 140
 141         ret = clk_prepare_enable(i2s_tdm->mclk_tx);
 142         if (ret)
 143                 goto err_mclk_tx;
 144         ret = clk_prepare_enable(i2s_tdm->mclk_rx);
 145         if (ret)
 146                 goto err_mclk_rx;
 147         if (i2s_tdm->mclk_calibrate) {
 148                 ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
 149                 if (ret)
 150                         goto err_mclk_rx;
 151                 ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
 152                 if (ret)
 153                         goto err_mclk_rx_src;
 154                 ret = clk_prepare_enable(i2s_tdm->mclk_root0);
 155                 if (ret)
 156                         goto err_mclk_root0;
 157                 ret = clk_prepare_enable(i2s_tdm->mclk_root1);
 158                 if (ret)
 159                         goto err_mclk_root1;
 160         }
 161
 162         return 0;
 163
 164 err_mclk_root1:
 165         clk_disable_unprepare(i2s_tdm->mclk_root0);
 166 err_mclk_root0:
 167         clk_disable_unprepare(i2s_tdm->mclk_rx_src);
 168 err_mclk_rx_src:
 169         clk_disable_unprepare(i2s_tdm->mclk_tx_src);
 170 err_mclk_rx:
 171         clk_disable_unprepare(i2s_tdm->mclk_tx);
 172 err_mclk_tx:
 173         return ret;
 174 }
 175
 176 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
 177 {
 178         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
 179
 180         regcache_cache_only(i2s_tdm->regmap, true);
 181         i2s_tdm_disable_unprepare_mclk(i2s_tdm);
 182
 183         clk_disable_unprepare(i2s_tdm->hclk);
 184
 185         return 0;
 186 }
 187
 188 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
 189 {
 190         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
 191         int ret;
 192
 193         ret = clk_prepare_enable(i2s_tdm->hclk);
 194         if (ret)
 195                 goto err_hclk;
 196
 197         ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
 198         if (ret)
 199                 goto err_mclk;
 200
 201         regcache_cache_only(i2s_tdm->regmap, false);
 202         regcache_mark_dirty(i2s_tdm->regmap);
 203
 204         ret = regcache_sync(i2s_tdm->regmap);
 205         if (ret)
 206                 goto err_regcache;
 207
 208         return 0;
 209
 210 err_regcache:
 211         i2s_tdm_disable_unprepare_mclk(i2s_tdm);
 212 err_mclk:
 213         clk_disable_unprepare(i2s_tdm->hclk);
 214 err_hclk:
 215         return ret;
 216 }
 217
 218 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
 219 {
 220         return snd_soc_dai_get_drvdata(dai);
 221 }
 222
 223 /*
 224  * Makes sure that both tx and rx are reset at the same time to sync lrck
 225  * when clk_trcm > 0.
 226  */
 227 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
 228 {
 229         /* This is technically race-y.
 230          *
 231          * In an ideal world, we could atomically assert both resets at the
 232          * same time, through an atomic bulk reset API. This API however does
 233          * not exist, so what the downstream vendor code used to do was
 234          * implement half a reset controller here and require the CRU to be
 235          * passed to the driver as a device tree node. Violating abstractions
 236          * like that is bad, especially when it influences something like the
 237          * bindings which are supposed to describe the hardware, not whatever
 238          * workarounds the driver needs, so it was dropped.
 239          *
 240          * In practice, asserting the resets one by one appears to work just
 241          * fine for playback. During duplex (playback + capture) operation,
 242          * this might become an issue, but that should be solved by the
 243          * implementation of the aforementioned API, not by shoving a reset
 244          * controller into an audio driver.
 245          */
 246
 247         reset_control_assert(i2s_tdm->tx_reset);
 248         reset_control_assert(i2s_tdm->rx_reset);
 249         udelay(10);
 250         reset_control_deassert(i2s_tdm->tx_reset);
 251         reset_control_deassert(i2s_tdm->rx_reset);
 252         udelay(10);
 253 }
 254
 255 static void rockchip_snd_reset(struct reset_control *rc)
 256 {
 257         reset_control_assert(rc);
 258         udelay(10);
 259         reset_control_deassert(rc);
 260         udelay(10);
 261 }
 262
 263 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
 264                                     unsigned int clr)
 265 {
 266         unsigned int xfer_mask = 0;
 267         unsigned int xfer_val = 0;
 268         unsigned int val;
 269         int retry = 10;
 270         bool tx = clr & I2S_CLR_TXC;
 271         bool rx = clr & I2S_CLR_RXC;
 272
 273         if (!(rx || tx))
 274                 return;
 275
 276         if (tx) {
 277                 xfer_mask = I2S_XFER_TXS_START;
 278                 xfer_val = I2S_XFER_TXS_STOP;
 279         }
 280         if (rx) {
 281                 xfer_mask |= I2S_XFER_RXS_START;
 282                 xfer_val |= I2S_XFER_RXS_STOP;
 283         }
 284
 285         regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
 286         udelay(150);
 287         regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
 288
 289         regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
 290         /* Wait on the clear operation to finish */
 291         while (val) {
 292                 udelay(15);
 293                 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
 294                 retry--;
 295                 if (!retry) {
 296                         dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
 297                                  tx ? "tx" : "", rx ? "rx" : "");
 298                         if (rx && tx)
 299                                 rockchip_snd_xfer_sync_reset(i2s_tdm);
 300                         else if (tx)
 301                                 rockchip_snd_reset(i2s_tdm->tx_reset);
 302                         else if (rx)
 303                                 rockchip_snd_reset(i2s_tdm->rx_reset);
 304                         break;
 305                 }
 306         }
 307 }
 308
 309 static inline void rockchip_enable_tde(struct regmap *regmap)
 310 {
 311         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
 312                            I2S_DMACR_TDE_ENABLE);
 313 }
 314
 315 static inline void rockchip_disable_tde(struct regmap *regmap)
 316 {
 317         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
 318                            I2S_DMACR_TDE_DISABLE);
 319 }
 320
 321 static inline void rockchip_enable_rde(struct regmap *regmap)
 322 {
 323         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
 324                            I2S_DMACR_RDE_ENABLE);
 325 }
 326
 327 static inline void rockchip_disable_rde(struct regmap *regmap)
 328 {
 329         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
 330                            I2S_DMACR_RDE_DISABLE);
 331 }
 332
 333 /* only used when clk_trcm > 0 */
 334 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
 335                                   struct snd_soc_dai *dai, int on)
 336 {
 337         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 338         unsigned long flags;
 339
 340         spin_lock_irqsave(&i2s_tdm->lock, flags);
 341         if (on) {
 342                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 343                         rockchip_enable_tde(i2s_tdm->regmap);
 344                 else
 345                         rockchip_enable_rde(i2s_tdm->regmap);
 346
 347                 if (++i2s_tdm->refcount == 1) {
 348                         rockchip_snd_xfer_sync_reset(i2s_tdm);
 349                         regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 350                                            I2S_XFER_TXS_START |
 351                                            I2S_XFER_RXS_START,
 352                                            I2S_XFER_TXS_START |
 353                                            I2S_XFER_RXS_START);
 354                 }
 355         } else {
 356                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 357                         rockchip_disable_tde(i2s_tdm->regmap);
 358                 else
 359                         rockchip_disable_rde(i2s_tdm->regmap);
 360
 361                 if (--i2s_tdm->refcount == 0) {
 362                         rockchip_snd_xfer_clear(i2s_tdm,
 363                                                 I2S_CLR_TXC | I2S_CLR_RXC);
 364                 }
 365         }
 366         spin_unlock_irqrestore(&i2s_tdm->lock, flags);
 367 }
 368
 369 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
 370 {
 371         if (on) {
 372                 rockchip_enable_tde(i2s_tdm->regmap);
 373
 374                 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 375                                    I2S_XFER_TXS_START,
 376                                    I2S_XFER_TXS_START);
 377         } else {
 378                 rockchip_disable_tde(i2s_tdm->regmap);
 379
 380                 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
 381         }
 382 }
 383
 384 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
 385 {
 386         if (on) {
 387                 rockchip_enable_rde(i2s_tdm->regmap);
 388
 389                 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 390                                    I2S_XFER_RXS_START,
 391                                    I2S_XFER_RXS_START);
 392         } else {
 393                 rockchip_disable_rde(i2s_tdm->regmap);
 394
 395                 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
 396         }
 397 }
 398
 399 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
 400                                     unsigned int fmt)
 401 {
 402         struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
 403         unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
 404         int ret;
 405         bool is_tdm = i2s_tdm->tdm_mode;
 406
 407         ret = pm_runtime_resume_and_get(cpu_dai->dev);
 408         if (ret < 0 && ret != -EACCES)
 409                 return ret;
 410
 411         mask = I2S_CKR_MSS_MASK;
 412         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 413         case SND_SOC_DAIFMT_BP_FP:
 414                 val = I2S_CKR_MSS_MASTER;
 415                 i2s_tdm->is_master_mode = true;
 416                 break;
 417         case SND_SOC_DAIFMT_BC_FC:
 418                 val = I2S_CKR_MSS_SLAVE;
 419                 i2s_tdm->is_master_mode = false;
 420                 break;
 421         default:
 422                 ret = -EINVAL;
 423                 goto err_pm_put;
 424         }
 425
 426         regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
 427
 428         mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
 429         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 430         case SND_SOC_DAIFMT_NB_NF:
 431                 val = I2S_CKR_CKP_NORMAL |
 432                       I2S_CKR_TLP_NORMAL |
 433                       I2S_CKR_RLP_NORMAL;
 434                 break;
 435         case SND_SOC_DAIFMT_NB_IF:
 436                 val = I2S_CKR_CKP_NORMAL |
 437                       I2S_CKR_TLP_INVERTED |
 438                       I2S_CKR_RLP_INVERTED;
 439                 break;
 440         case SND_SOC_DAIFMT_IB_NF:
 441                 val = I2S_CKR_CKP_INVERTED |
 442                       I2S_CKR_TLP_NORMAL |
 443                       I2S_CKR_RLP_NORMAL;
 444                 break;
 445         case SND_SOC_DAIFMT_IB_IF:
 446                 val = I2S_CKR_CKP_INVERTED |
 447                       I2S_CKR_TLP_INVERTED |
 448                       I2S_CKR_RLP_INVERTED;
 449                 break;
 450         default:
 451                 ret = -EINVAL;
 452                 goto err_pm_put;
 453         }
 454
 455         regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
 456
 457         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 458         case SND_SOC_DAIFMT_RIGHT_J:
 459                 txcr_val = I2S_TXCR_IBM_RSJM;
 460                 rxcr_val = I2S_RXCR_IBM_RSJM;
 461                 break;
 462         case SND_SOC_DAIFMT_LEFT_J:
 463                 txcr_val = I2S_TXCR_IBM_LSJM;
 464                 rxcr_val = I2S_RXCR_IBM_LSJM;
 465                 break;
 466         case SND_SOC_DAIFMT_I2S:
 467                 txcr_val = I2S_TXCR_IBM_NORMAL;
 468                 rxcr_val = I2S_RXCR_IBM_NORMAL;
 469                 break;
 470         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
 471                 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 472                 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 473                 break;
 474         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 475                 txcr_val = I2S_TXCR_TFS_PCM;
 476                 rxcr_val = I2S_RXCR_TFS_PCM;
 477                 break;
 478         default:
 479                 ret = -EINVAL;
 480                 goto err_pm_put;
 481         }
 482
 483         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 484         regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
 485
 486         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 487         regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
 488
 489         if (is_tdm) {
 490                 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 491                 case SND_SOC_DAIFMT_RIGHT_J:
 492                         val = I2S_TXCR_TFS_TDM_I2S;
 493                         tdm_val = TDM_SHIFT_CTRL(2);
 494                         break;
 495                 case SND_SOC_DAIFMT_LEFT_J:
 496                         val = I2S_TXCR_TFS_TDM_I2S;
 497                         tdm_val = TDM_SHIFT_CTRL(1);
 498                         break;
 499                 case SND_SOC_DAIFMT_I2S:
 500                         val = I2S_TXCR_TFS_TDM_I2S;
 501                         tdm_val = TDM_SHIFT_CTRL(0);
 502                         break;
 503                 case SND_SOC_DAIFMT_DSP_A:
 504                         val = I2S_TXCR_TFS_TDM_PCM;
 505                         tdm_val = TDM_SHIFT_CTRL(0);
 506                         break;
 507                 case SND_SOC_DAIFMT_DSP_B:
 508                         val = I2S_TXCR_TFS_TDM_PCM;
 509                         tdm_val = TDM_SHIFT_CTRL(2);
 510                         break;
 511                 default:
 512                         ret = -EINVAL;
 513                         goto err_pm_put;
 514                 }
 515
 516                 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
 517                 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
 518
 519                 mask = I2S_TXCR_TFS_MASK;
 520                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
 521                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
 522
 523                 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
 524                        TDM_SHIFT_CTRL_MSK;
 525                 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
 526                                    mask, tdm_val);
 527                 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
 528                                    mask, tdm_val);
 529         }
 530
 531 err_pm_put:
 532         pm_runtime_put(cpu_dai->dev);
 533
 534         return ret;
 535 }
 536
 537 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
 538                                         struct rk_i2s_tdm_dev *i2s_tdm)
 539 {
 540         int stream;
 541
 542         stream = SNDRV_PCM_STREAM_LAST - substream->stream;
 543         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 544                 rockchip_disable_tde(i2s_tdm->regmap);
 545         else
 546                 rockchip_disable_rde(i2s_tdm->regmap);
 547
 548         rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
 549 }
 550
 551 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
 552                                          struct rk_i2s_tdm_dev *i2s_tdm)
 553 {
 554         int stream;
 555
 556         stream = SNDRV_PCM_STREAM_LAST - substream->stream;
 557         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 558                 rockchip_enable_tde(i2s_tdm->regmap);
 559         else
 560                 rockchip_enable_rde(i2s_tdm->regmap);
 561
 562         regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 563                            I2S_XFER_TXS_START |
 564                            I2S_XFER_RXS_START,
 565                            I2S_XFER_TXS_START |
 566                            I2S_XFER_RXS_START);
 567 }
 568
 569 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
 570                                          struct clk *clk, unsigned long rate,
 571                                          int ppm)
 572 {
 573         unsigned long rate_target;
 574         int delta, ret;
 575
 576         if (ppm == i2s_tdm->clk_ppm)
 577                 return 0;
 578
 579         if (ppm < 0)
 580                 delta = -1;
 581         else
 582                 delta = 1;
 583
 584         delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
 585                                 1000000);
 586
 587         rate_target = rate + delta;
 588
 589         if (!rate_target)
 590                 return -EINVAL;
 591
 592         ret = clk_set_rate(clk, rate_target);
 593         if (ret)
 594                 return ret;
 595
 596         i2s_tdm->clk_ppm = ppm;
 597
 598         return 0;
 599 }
 600
 601 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
 602                                            struct snd_pcm_substream *substream,
 603                                            unsigned int lrck_freq)
 604 {
 605         struct clk *mclk_root;
 606         struct clk *mclk_parent;
 607         unsigned int mclk_root_freq;
 608         unsigned int mclk_root_initial_freq;
 609         unsigned int mclk_parent_freq;
 610         unsigned int div, delta;
 611         u64 ppm;
 612         int ret;
 613
 614         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 615                 mclk_parent = i2s_tdm->mclk_tx_src;
 616         else
 617                 mclk_parent = i2s_tdm->mclk_rx_src;
 618
 619         switch (lrck_freq) {
 620         case 8000:
 621         case 16000:
 622         case 24000:
 623         case 32000:
 624         case 48000:
 625         case 64000:
 626         case 96000:
 627         case 192000:
 628                 mclk_root = i2s_tdm->mclk_root0;
 629                 mclk_root_freq = i2s_tdm->mclk_root0_freq;
 630                 mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
 631                 mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
 632                 break;
 633         case 11025:
 634         case 22050:
 635         case 44100:
 636         case 88200:
 637         case 176400:
 638                 mclk_root = i2s_tdm->mclk_root1;
 639                 mclk_root_freq = i2s_tdm->mclk_root1_freq;
 640                 mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
 641                 mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
 642                 break;
 643         default:
 644                 dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
 645                         lrck_freq);
 646                 return -EINVAL;
 647         }
 648
 649         ret = clk_set_parent(mclk_parent, mclk_root);
 650         if (ret)
 651                 return ret;
 652
 653         ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
 654                                             mclk_root_freq, 0);
 655         if (ret)
 656                 return ret;
 657
 658         delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
 659         ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
 660
 661         if (ppm) {
 662                 div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
 663                 if (!div)
 664                         return -EINVAL;
 665
 666                 mclk_root_freq = mclk_parent_freq * round_up(div, 2);
 667
 668                 ret = clk_set_rate(mclk_root, mclk_root_freq);
 669                 if (ret)
 670                         return ret;
 671
 672                 i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
 673                 i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
 674         }
 675
 676         return clk_set_rate(mclk_parent, mclk_parent_freq);
 677 }
 678
 679 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
 680                                      struct snd_pcm_substream *substream,
 681                                      struct clk **mclk)
 682 {
 683         unsigned int mclk_freq;
 684         int ret;
 685
 686         if (i2s_tdm->clk_trcm) {
 687                 if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
 688                         dev_err(i2s_tdm->dev,
 689                                 "clk_trcm, tx: %d and rx: %d should be the same\n",
 690                                 i2s_tdm->mclk_tx_freq,
 691                                 i2s_tdm->mclk_rx_freq);
 692                         return -EINVAL;
 693                 }
 694
 695                 ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
 696                 if (ret)
 697                         return ret;
 698
 699                 ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
 700                 if (ret)
 701                         return ret;
 702
 703                 /* mclk_rx is also ok. */
 704                 *mclk = i2s_tdm->mclk_tx;
 705         } else {
 706                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 707                         *mclk = i2s_tdm->mclk_tx;
 708                         mclk_freq = i2s_tdm->mclk_tx_freq;
 709                 } else {
 710                         *mclk = i2s_tdm->mclk_rx;
 711                         mclk_freq = i2s_tdm->mclk_rx_freq;
 712                 }
 713
 714                 ret = clk_set_rate(*mclk, mclk_freq);
 715                 if (ret)
 716                         return ret;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
 723 {
 724         if (substream_capture) {
 725                 switch (ch) {
 726                 case I2S_CHN_4:
 727                         return I2S_IO_6CH_OUT_4CH_IN;
 728                 case I2S_CHN_6:
 729                         return I2S_IO_4CH_OUT_6CH_IN;
 730                 case I2S_CHN_8:
 731                         return I2S_IO_2CH_OUT_8CH_IN;
 732                 default:
 733                         return I2S_IO_8CH_OUT_2CH_IN;
 734                 }
 735         } else {
 736                 switch (ch) {
 737                 case I2S_CHN_4:
 738                         return I2S_IO_4CH_OUT_6CH_IN;
 739                 case I2S_CHN_6:
 740                         return I2S_IO_6CH_OUT_4CH_IN;
 741                 case I2S_CHN_8:
 742                         return I2S_IO_8CH_OUT_2CH_IN;
 743                 default:
 744                         return I2S_IO_2CH_OUT_8CH_IN;
 745                 }
 746         }
 747 }
 748
 749 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
 750                                      struct snd_soc_dai *dai)
 751 {
 752         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 753         int usable_chs = MULTIPLEX_CH_MAX;
 754         unsigned int val = 0;
 755
 756         if (!i2s_tdm->io_multiplex)
 757                 return 0;
 758
 759         if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
 760                 dev_err(i2s_tdm->dev,
 761                         "io multiplex not supported for this device\n");
 762                 return -EINVAL;
 763         }
 764
 765         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 766                 struct snd_pcm_str *playback_str =
 767                         &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
 768
 769                 if (playback_str->substream_opened) {
 770                         regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
 771                         val &= I2S_TXCR_CSR_MASK;
 772                         usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
 773                 }
 774
 775                 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
 776                 val &= I2S_RXCR_CSR_MASK;
 777
 778                 if (to_ch_num(val) > usable_chs) {
 779                         dev_err(i2s_tdm->dev,
 780                                 "Capture channels (%d) > usable channels (%d)\n",
 781                                 to_ch_num(val), usable_chs);
 782                         return -EINVAL;
 783                 }
 784
 785                 rockchip_i2s_ch_to_io(val, true);
 786         } else {
 787                 struct snd_pcm_str *capture_str =
 788                         &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
 789
 790                 if (capture_str->substream_opened) {
 791                         regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
 792                         val &= I2S_RXCR_CSR_MASK;
 793                         usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
 794                 }
 795
 796                 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
 797                 val &= I2S_TXCR_CSR_MASK;
 798
 799                 if (to_ch_num(val) > usable_chs) {
 800                         dev_err(i2s_tdm->dev,
 801                                 "Playback channels (%d) > usable channels (%d)\n",
 802                                 to_ch_num(val), usable_chs);
 803                         return -EINVAL;
 804                 }
 805         }
 806
 807         val <<= i2s_tdm->soc_data->grf_shift;
 808         val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
 809         regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
 810
 811         return 0;
 812 }
 813
 814 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
 815                                   struct snd_soc_dai *dai,
 816                                   unsigned int div_bclk,
 817                                   unsigned int div_lrck,
 818                                   unsigned int fmt)
 819 {
 820         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 821         unsigned long flags;
 822
 823         if (!i2s_tdm->clk_trcm)
 824                 return 0;
 825
 826         spin_lock_irqsave(&i2s_tdm->lock, flags);
 827         if (i2s_tdm->refcount)
 828                 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
 829
 830         regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
 831                            I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
 832                            I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
 833         regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
 834                            I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
 835                            I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
 836
 837         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 838                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
 839                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 840                                    fmt);
 841         else
 842                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
 843                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 844                                    fmt);
 845
 846         if (i2s_tdm->refcount)
 847                 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
 848         spin_unlock_irqrestore(&i2s_tdm->lock, flags);
 849
 850         return 0;
 851 }
 852
 853 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
 854                                       struct snd_pcm_hw_params *params,
 855                                       struct snd_soc_dai *dai)
 856 {
 857         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 858         struct clk *mclk;
 859         int ret = 0;
 860         unsigned int val = 0;
 861         unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
 862
 863         if (i2s_tdm->is_master_mode) {
 864                 if (i2s_tdm->mclk_calibrate)
 865                         rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
 866                                                         params_rate(params));
 867
 868                 ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
 869                 if (ret)
 870                         return ret;
 871
 872                 mclk_rate = clk_get_rate(mclk);
 873                 bclk_rate = i2s_tdm->frame_width * params_rate(params);
 874                 if (!bclk_rate)
 875                         return -EINVAL;
 876
 877                 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
 878                 div_lrck = bclk_rate / params_rate(params);
 879         }
 880
 881         switch (params_format(params)) {
 882         case SNDRV_PCM_FORMAT_S8:
 883                 val |= I2S_TXCR_VDW(8);
 884                 break;
 885         case SNDRV_PCM_FORMAT_S16_LE:
 886                 val |= I2S_TXCR_VDW(16);
 887                 break;
 888         case SNDRV_PCM_FORMAT_S20_3LE:
 889                 val |= I2S_TXCR_VDW(20);
 890                 break;
 891         case SNDRV_PCM_FORMAT_S24_LE:
 892                 val |= I2S_TXCR_VDW(24);
 893                 break;
 894         case SNDRV_PCM_FORMAT_S32_LE:
 895                 val |= I2S_TXCR_VDW(32);
 896                 break;
 897         default:
 898                 return -EINVAL;
 899         }
 900
 901         switch (params_channels(params)) {
 902         case 8:
 903                 val |= I2S_CHN_8;
 904                 break;
 905         case 6:
 906                 val |= I2S_CHN_6;
 907                 break;
 908         case 4:
 909                 val |= I2S_CHN_4;
 910                 break;
 911         case 2:
 912                 val |= I2S_CHN_2;
 913                 break;
 914         default:
 915                 return -EINVAL;
 916         }
 917
 918         if (i2s_tdm->clk_trcm) {
 919                 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
 920         } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 921                 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
 922                                    I2S_CLKDIV_TXM_MASK,
 923                                    I2S_CLKDIV_TXM(div_bclk));
 924                 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
 925                                    I2S_CKR_TSD_MASK,
 926                                    I2S_CKR_TSD(div_lrck));
 927                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
 928                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 929                                    val);
 930         } else {
 931                 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
 932                                    I2S_CLKDIV_RXM_MASK,
 933                                    I2S_CLKDIV_RXM(div_bclk));
 934                 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
 935                                    I2S_CKR_RSD_MASK,
 936                                    I2S_CKR_RSD(div_lrck));
 937                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
 938                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 939                                    val);
 940         }
 941
 942         return rockchip_i2s_io_multiplex(substream, dai);
 943 }
 944
 945 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
 946                                     int cmd, struct snd_soc_dai *dai)
 947 {
 948         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 949
 950         switch (cmd) {
 951         case SNDRV_PCM_TRIGGER_START:
 952         case SNDRV_PCM_TRIGGER_RESUME:
 953         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 954                 if (i2s_tdm->clk_trcm)
 955                         rockchip_snd_txrxctrl(substream, dai, 1);
 956                 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 957                         rockchip_snd_rxctrl(i2s_tdm, 1);
 958                 else
 959                         rockchip_snd_txctrl(i2s_tdm, 1);
 960                 break;
 961         case SNDRV_PCM_TRIGGER_SUSPEND:
 962         case SNDRV_PCM_TRIGGER_STOP:
 963         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 964                 if (i2s_tdm->clk_trcm)
 965                         rockchip_snd_txrxctrl(substream, dai, 0);
 966                 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 967                         rockchip_snd_rxctrl(i2s_tdm, 0);
 968                 else
 969                         rockchip_snd_txctrl(i2s_tdm, 0);
 970                 break;
 971         default:
 972                 return -EINVAL;
 973         }
 974
 975         return 0;
 976 }
 977
 978 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
 979                                        unsigned int freq, int dir)
 980 {
 981         struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
 982
 983         /* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
 984         if (i2s_tdm->clk_trcm) {
 985                 i2s_tdm->mclk_tx_freq = freq;
 986                 i2s_tdm->mclk_rx_freq = freq;
 987         } else {
 988                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 989                         i2s_tdm->mclk_tx_freq = freq;
 990                 else
 991                         i2s_tdm->mclk_rx_freq = freq;
 992         }
 993
 994         dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
 995                 stream ? "rx" : "tx", freq);
 996
 997         return 0;
 998 }
 999
1000 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
1001                                                   struct snd_ctl_elem_info *uinfo)
1002 {
1003         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1004         uinfo->count = 1;
1005         uinfo->value.integer.min = CLK_PPM_MIN;
1006         uinfo->value.integer.max = CLK_PPM_MAX;
1007         uinfo->value.integer.step = 1;
1008
1009         return 0;
1010 }
1011
1012 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1013                                                  struct snd_ctl_elem_value *ucontrol)
1014 {
1015         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1016         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1017
1018         ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1019
1020         return 0;
1021 }
1022
1023 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1024                                                  struct snd_ctl_elem_value *ucontrol)
1025 {
1026         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1027         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1028         int ret = 0, ppm = 0;
1029         int changed = 0;
1030         unsigned long old_rate;
1031
1032         if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
1033             ucontrol->value.integer.value[0] > CLK_PPM_MAX)
1034                 return -EINVAL;
1035
1036         ppm = ucontrol->value.integer.value[0];
1037
1038         old_rate = clk_get_rate(i2s_tdm->mclk_root0);
1039         ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1040                                             i2s_tdm->mclk_root0_freq, ppm);
1041         if (ret)
1042                 return ret;
1043         if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
1044                 changed = 1;
1045
1046         if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1047                 return changed;
1048
1049         old_rate = clk_get_rate(i2s_tdm->mclk_root1);
1050         ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1051                                             i2s_tdm->mclk_root1_freq, ppm);
1052         if (ret)
1053                 return ret;
1054         if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
1055                 changed = 1;
1056
1057         return changed;
1058 }
1059
1060 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1061         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1062         .name = "PCM Clock Compensation in PPM",
1063         .info = rockchip_i2s_tdm_clk_compensation_info,
1064         .get = rockchip_i2s_tdm_clk_compensation_get,
1065         .put = rockchip_i2s_tdm_clk_compensation_put,
1066 };
1067
1068 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1069 {
1070         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1071
1072         if (i2s_tdm->has_capture)
1073                 snd_soc_dai_dma_data_set_capture(dai,  &i2s_tdm->capture_dma_data);
1074         if (i2s_tdm->has_playback)
1075                 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
1076
1077         if (i2s_tdm->mclk_calibrate)
1078                 snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1079
1080         return 0;
1081 }
1082
1083 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1084                                  unsigned int tx_mask, unsigned int rx_mask,
1085                                  int slots, int slot_width)
1086 {
1087         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1088         unsigned int mask, val;
1089
1090         i2s_tdm->tdm_mode = true;
1091         i2s_tdm->frame_width = slots * slot_width;
1092         mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1093         val = TDM_SLOT_BIT_WIDTH(slot_width) |
1094               TDM_FRAME_WIDTH(slots * slot_width);
1095         regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1096                            mask, val);
1097         regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1098                            mask, val);
1099
1100         return 0;
1101 }
1102
1103 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
1104                                            unsigned int ratio)
1105 {
1106         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1107
1108         if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
1109                 return -EINVAL;
1110
1111         i2s_tdm->frame_width = ratio;
1112
1113         return 0;
1114 }
1115
1116 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1117         .probe = rockchip_i2s_tdm_dai_probe,
1118         .hw_params = rockchip_i2s_tdm_hw_params,
1119         .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
1120         .set_sysclk = rockchip_i2s_tdm_set_sysclk,
1121         .set_fmt = rockchip_i2s_tdm_set_fmt,
1122         .set_tdm_slot = rockchip_dai_tdm_slot,
1123         .trigger = rockchip_i2s_tdm_trigger,
1124 };
1125
1126 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1127         .name = DRV_NAME,
1128         .legacy_dai_naming = 1,
1129 };
1130
1131 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
1132 {
1133         switch (reg) {
1134         case I2S_TXCR:
1135         case I2S_RXCR:
1136         case I2S_CKR:
1137         case I2S_DMACR:
1138         case I2S_INTCR:
1139         case I2S_XFER:
1140         case I2S_CLR:
1141         case I2S_TXDR:
1142         case I2S_TDM_TXCR:
1143         case I2S_TDM_RXCR:
1144         case I2S_CLKDIV:
1145                 return true;
1146         default:
1147                 return false;
1148         }
1149 }
1150
1151 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
1152 {
1153         switch (reg) {
1154         case I2S_TXCR:
1155         case I2S_RXCR:
1156         case I2S_CKR:
1157         case I2S_DMACR:
1158         case I2S_INTCR:
1159         case I2S_XFER:
1160         case I2S_CLR:
1161         case I2S_TXDR:
1162         case I2S_RXDR:
1163         case I2S_TXFIFOLR:
1164         case I2S_INTSR:
1165         case I2S_RXFIFOLR:
1166         case I2S_TDM_TXCR:
1167         case I2S_TDM_RXCR:
1168         case I2S_CLKDIV:
1169                 return true;
1170         default:
1171                 return false;
1172         }
1173 }
1174
1175 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
1176 {
1177         switch (reg) {
1178         case I2S_TXFIFOLR:
1179         case I2S_INTSR:
1180         case I2S_CLR:
1181         case I2S_TXDR:
1182         case I2S_RXDR:
1183         case I2S_RXFIFOLR:
1184                 return true;
1185         default:
1186                 return false;
1187         }
1188 }
1189
1190 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
1191 {
1192         if (reg == I2S_RXDR)
1193                 return true;
1194         return false;
1195 }
1196
1197 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
1198         {0x00, 0x7200000f},
1199         {0x04, 0x01c8000f},
1200         {0x08, 0x00001f1f},
1201         {0x10, 0x001f0000},
1202         {0x14, 0x01f00000},
1203         {0x30, 0x00003eff},
1204         {0x34, 0x00003eff},
1205         {0x38, 0x00000707},
1206 };
1207
1208 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
1209         .reg_bits = 32,
1210         .reg_stride = 4,
1211         .val_bits = 32,
1212         .max_register = I2S_CLKDIV,
1213         .reg_defaults = rockchip_i2s_tdm_reg_defaults,
1214         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
1215         .writeable_reg = rockchip_i2s_tdm_wr_reg,
1216         .readable_reg = rockchip_i2s_tdm_rd_reg,
1217         .volatile_reg = rockchip_i2s_tdm_volatile_reg,
1218         .precious_reg = rockchip_i2s_tdm_precious_reg,
1219         .cache_type = REGCACHE_FLAT,
1220 };
1221
1222 static int common_soc_init(struct device *dev, u32 addr)
1223 {
1224         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1225         const struct txrx_config *configs = i2s_tdm->soc_data->configs;
1226         u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1227         int i;
1228
1229         if (trcm == TRCM_TXRX)
1230                 return 0;
1231
1232         if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
1233                 dev_err(i2s_tdm->dev,
1234                         "no grf present but non-txrx TRCM specified\n");
1235                 return -EINVAL;
1236         }
1237
1238         for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
1239                 if (addr != configs[i].addr)
1240                         continue;
1241                 reg = configs[i].reg;
1242                 if (trcm == TRCM_TX)
1243                         val = configs[i].txonly;
1244                 else
1245                         val = configs[i].rxonly;
1246
1247                 if (reg)
1248                         regmap_write(i2s_tdm->grf, reg, val);
1249         }
1250
1251         return 0;
1252 }
1253
1254 static const struct txrx_config px30_txrx_config[] = {
1255         { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
1256 };
1257
1258 static const struct txrx_config rk1808_txrx_config[] = {
1259         { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
1260 };
1261
1262 static const struct txrx_config rk3308_txrx_config[] = {
1263         { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1264         { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1265 };
1266
1267 static const struct txrx_config rk3568_txrx_config[] = {
1268         { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1269         { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1270         { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1271         { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1272         { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1273         { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1274 };
1275
1276 static const struct txrx_config rv1126_txrx_config[] = {
1277         { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1278 };
1279
1280 static struct rk_i2s_soc_data px30_i2s_soc_data = {
1281         .softrst_offset = 0x0300,
1282         .configs = px30_txrx_config,
1283         .config_count = ARRAY_SIZE(px30_txrx_config),
1284         .init = common_soc_init,
1285 };
1286
1287 static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1288         .softrst_offset = 0x0300,
1289         .configs = rk1808_txrx_config,
1290         .config_count = ARRAY_SIZE(rk1808_txrx_config),
1291         .init = common_soc_init,
1292 };
1293
1294 static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1295         .softrst_offset = 0x0400,
1296         .grf_reg_offset = 0x0308,
1297         .grf_shift = 5,
1298         .configs = rk3308_txrx_config,
1299         .config_count = ARRAY_SIZE(rk3308_txrx_config),
1300         .init = common_soc_init,
1301 };
1302
1303 static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1304         .softrst_offset = 0x0400,
1305         .configs = rk3568_txrx_config,
1306         .config_count = ARRAY_SIZE(rk3568_txrx_config),
1307         .init = common_soc_init,
1308 };
1309
1310 static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1311         .softrst_offset = 0x0300,
1312         .configs = rv1126_txrx_config,
1313         .config_count = ARRAY_SIZE(rv1126_txrx_config),
1314         .init = common_soc_init,
1315 };
1316
1317 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1318         { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1319         { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1320         { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1321         { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1322         { .compatible = "rockchip,rk3588-i2s-tdm" },
1323         { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1324         {},
1325 };
1326
1327 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1328         .ops = &rockchip_i2s_tdm_dai_ops,
1329 };
1330
1331 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1332 {
1333         struct snd_soc_dai_driver *dai;
1334         struct property *dma_names;
1335         const char *dma_name;
1336         u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1337                        SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1338                        SNDRV_PCM_FMTBIT_S32_LE);
1339         struct device_node *node = i2s_tdm->dev->of_node;
1340
1341         of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1342                 if (!strcmp(dma_name, "tx"))
1343                         i2s_tdm->has_playback = true;
1344                 if (!strcmp(dma_name, "rx"))
1345                         i2s_tdm->has_capture = true;
1346         }
1347
1348         dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1349                            sizeof(*dai), GFP_KERNEL);
1350         if (!dai)
1351                 return -ENOMEM;
1352
1353         if (i2s_tdm->has_playback) {
1354                 dai->playback.stream_name  = "Playback";
1355                 dai->playback.channels_min = 2;
1356                 dai->playback.channels_max = 8;
1357                 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1358                 dai->playback.formats = formats;
1359         }
1360
1361         if (i2s_tdm->has_capture) {
1362                 dai->capture.stream_name  = "Capture";
1363                 dai->capture.channels_min = 2;
1364                 dai->capture.channels_max = 8;
1365                 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1366                 dai->capture.formats = formats;
1367         }
1368
1369         if (i2s_tdm->clk_trcm != TRCM_TXRX)
1370                 dai->symmetric_rate = 1;
1371
1372         i2s_tdm->dai = dai;
1373
1374         return 0;
1375 }
1376
1377 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1378                                        int num,
1379                                        bool is_rx_path)
1380 {
1381         unsigned int *i2s_data;
1382         int i, j;
1383
1384         if (is_rx_path)
1385                 i2s_data = i2s_tdm->i2s_sdis;
1386         else
1387                 i2s_data = i2s_tdm->i2s_sdos;
1388
1389         for (i = 0; i < num; i++) {
1390                 if (i2s_data[i] > CH_GRP_MAX - 1) {
1391                         dev_err(i2s_tdm->dev,
1392                                 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1393                                 is_rx_path ? "RX" : "TX",
1394                                 i, i2s_data[i], CH_GRP_MAX);
1395                         return -EINVAL;
1396                 }
1397
1398                 for (j = 0; j < num; j++) {
1399                         if (i == j)
1400                                 continue;
1401
1402                         if (i2s_data[i] == i2s_data[j]) {
1403                                 dev_err(i2s_tdm->dev,
1404                                         "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1405                                         is_rx_path ? "RX" : "TX",
1406                                         i, i2s_data[i],
1407                                         j, i2s_data[j]);
1408                                 return -EINVAL;
1409                         }
1410                 }
1411         }
1412
1413         return 0;
1414 }
1415
1416 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1417                                             int num)
1418 {
1419         int idx;
1420
1421         for (idx = 0; idx < num; idx++) {
1422                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1423                                    I2S_TXCR_PATH_MASK(idx),
1424                                    I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1425         }
1426 }
1427
1428 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1429                                             int num)
1430 {
1431         int idx;
1432
1433         for (idx = 0; idx < num; idx++) {
1434                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1435                                    I2S_RXCR_PATH_MASK(idx),
1436                                    I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1437         }
1438 }
1439
1440 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1441                                          int num, bool is_rx_path)
1442 {
1443         if (is_rx_path)
1444                 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1445         else
1446                 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1447 }
1448
1449 static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
1450 {
1451         int num_mclks = 0;
1452
1453         i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
1454         if (!IS_ERR(i2s_tdm->mclk_tx_src))
1455                 num_mclks++;
1456
1457         i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
1458         if (!IS_ERR(i2s_tdm->mclk_rx_src))
1459                 num_mclks++;
1460
1461         i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
1462         if (!IS_ERR(i2s_tdm->mclk_root0))
1463                 num_mclks++;
1464
1465         i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
1466         if (!IS_ERR(i2s_tdm->mclk_root1))
1467                 num_mclks++;
1468
1469         if (num_mclks < 4 && num_mclks != 0)
1470                 return -ENOENT;
1471
1472         if (num_mclks == 4)
1473                 i2s_tdm->mclk_calibrate = 1;
1474
1475         return 0;
1476 }
1477
1478 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1479                                          struct device_node *np,
1480                                          bool is_rx_path)
1481 {
1482         char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1483         char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1484         char *i2s_path_prop;
1485         unsigned int *i2s_data;
1486         int num, ret = 0;
1487
1488         if (is_rx_path) {
1489                 i2s_path_prop = i2s_rx_path_prop;
1490                 i2s_data = i2s_tdm->i2s_sdis;
1491         } else {
1492                 i2s_path_prop = i2s_tx_path_prop;
1493                 i2s_data = i2s_tdm->i2s_sdos;
1494         }
1495
1496         num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1497         if (num < 0) {
1498                 if (num != -ENOENT) {
1499                         dev_err(i2s_tdm->dev,
1500                                 "Failed to read '%s' num: %d\n",
1501                                 i2s_path_prop, num);
1502                         ret = num;
1503                 }
1504                 return ret;
1505         } else if (num != CH_GRP_MAX) {
1506                 dev_err(i2s_tdm->dev,
1507                         "The num: %d should be: %d\n", num, CH_GRP_MAX);
1508                 return -EINVAL;
1509         }
1510
1511         ret = of_property_read_u32_array(np, i2s_path_prop,
1512                                          i2s_data, num);
1513         if (ret < 0) {
1514                 dev_err(i2s_tdm->dev,
1515                         "Failed to read '%s': %d\n",
1516                         i2s_path_prop, ret);
1517                 return ret;
1518         }
1519
1520         ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1521         if (ret < 0) {
1522                 dev_err(i2s_tdm->dev,
1523                         "Failed to check i2s data bus: %d\n", ret);
1524                 return ret;
1525         }
1526
1527         rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1528
1529         return 0;
1530 }
1531
1532 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1533                                             struct device_node *np)
1534 {
1535         return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1536 }
1537
1538 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1539                                             struct device_node *np)
1540 {
1541         return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1542 }
1543
1544 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1545 {
1546         struct device_node *node = pdev->dev.of_node;
1547         const struct of_device_id *of_id;
1548         struct rk_i2s_tdm_dev *i2s_tdm;
1549         struct resource *res;
1550         void __iomem *regs;
1551         int ret;
1552
1553         i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1554         if (!i2s_tdm)
1555                 return -ENOMEM;
1556
1557         i2s_tdm->dev = &pdev->dev;
1558
1559         of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1560         if (!of_id)
1561                 return -EINVAL;
1562
1563         spin_lock_init(&i2s_tdm->lock);
1564         i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
1565
1566         i2s_tdm->frame_width = 64;
1567
1568         i2s_tdm->clk_trcm = TRCM_TXRX;
1569         if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1570                 i2s_tdm->clk_trcm = TRCM_TX;
1571         if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1572                 if (i2s_tdm->clk_trcm) {
1573                         dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1574                         return -EINVAL;
1575                 }
1576                 i2s_tdm->clk_trcm = TRCM_RX;
1577         }
1578
1579         ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1580         if (ret)
1581                 return ret;
1582
1583         i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1584         i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1585                                                                       "tx-m");
1586         if (IS_ERR(i2s_tdm->tx_reset)) {
1587                 ret = PTR_ERR(i2s_tdm->tx_reset);
1588                 return dev_err_probe(i2s_tdm->dev, ret,
1589                                      "Error in tx-m reset control\n");
1590         }
1591
1592         i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1593                                                                       "rx-m");
1594         if (IS_ERR(i2s_tdm->rx_reset)) {
1595                 ret = PTR_ERR(i2s_tdm->rx_reset);
1596                 return dev_err_probe(i2s_tdm->dev, ret,
1597                                      "Error in rx-m reset control\n");
1598         }
1599
1600         i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1601         if (IS_ERR(i2s_tdm->hclk)) {
1602                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1603                                      "Failed to get clock hclk\n");
1604         }
1605
1606         i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1607         if (IS_ERR(i2s_tdm->mclk_tx)) {
1608                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1609                                      "Failed to get clock mclk_tx\n");
1610         }
1611
1612         i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1613         if (IS_ERR(i2s_tdm->mclk_rx)) {
1614                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1615                                      "Failed to get clock mclk_rx\n");
1616         }
1617
1618         i2s_tdm->io_multiplex =
1619                 of_property_read_bool(node, "rockchip,io-multiplex");
1620
1621         ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
1622         if (ret)
1623                 return dev_err_probe(i2s_tdm->dev, ret,
1624                                      "mclk-calibrate clocks missing");
1625
1626         regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1627         if (IS_ERR(regs)) {
1628                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1629                                      "Failed to get resource IORESOURCE_MEM\n");
1630         }
1631
1632         i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1633                                                 &rockchip_i2s_tdm_regmap_config);
1634         if (IS_ERR(i2s_tdm->regmap)) {
1635                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1636                                      "Failed to initialise regmap\n");
1637         }
1638
1639         if (i2s_tdm->has_playback) {
1640                 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1641                 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1642                 i2s_tdm->playback_dma_data.maxburst = 8;
1643         }
1644
1645         if (i2s_tdm->has_capture) {
1646                 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1647                 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1648                 i2s_tdm->capture_dma_data.maxburst = 8;
1649         }
1650
1651         ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1652         if (ret < 0) {
1653                 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1654                 return ret;
1655         }
1656
1657         ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1658         if (ret < 0) {
1659                 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1660                 return ret;
1661         }
1662
1663         dev_set_drvdata(&pdev->dev, i2s_tdm);
1664
1665         ret = clk_prepare_enable(i2s_tdm->hclk);
1666         if (ret) {
1667                 return dev_err_probe(i2s_tdm->dev, ret,
1668                                      "Failed to enable clock hclk\n");
1669         }
1670
1671         ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1672         if (ret) {
1673                 ret = dev_err_probe(i2s_tdm->dev, ret,
1674                                     "Failed to enable one or more mclks\n");
1675                 goto err_disable_hclk;
1676         }
1677
1678         if (i2s_tdm->mclk_calibrate) {
1679                 i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
1680                 i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
1681                 i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
1682                 i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1683         }
1684
1685         pm_runtime_enable(&pdev->dev);
1686
1687         regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1688                            I2S_DMACR_TDL(16));
1689         regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1690                            I2S_DMACR_RDL(16));
1691         regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1692                            i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1693
1694         if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1695                 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1696
1697         ret = devm_snd_soc_register_component(&pdev->dev,
1698                                               &rockchip_i2s_tdm_component,
1699                                               i2s_tdm->dai, 1);
1700
1701         if (ret) {
1702                 dev_err(&pdev->dev, "Could not register DAI\n");
1703                 goto err_suspend;
1704         }
1705
1706         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1707         if (ret) {
1708                 dev_err(&pdev->dev, "Could not register PCM\n");
1709                 goto err_suspend;
1710         }
1711
1712         return 0;
1713
1714 err_suspend:
1715         if (!pm_runtime_status_suspended(&pdev->dev))
1716                 i2s_tdm_runtime_suspend(&pdev->dev);
1717         pm_runtime_disable(&pdev->dev);
1718
1719 err_disable_hclk:
1720         clk_disable_unprepare(i2s_tdm->hclk);
1721
1722         return ret;
1723 }
1724
1725 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
1726 {
1727         if (!pm_runtime_status_suspended(&pdev->dev))
1728                 i2s_tdm_runtime_suspend(&pdev->dev);
1729
1730         pm_runtime_disable(&pdev->dev);
1731
1732         return 0;
1733 }
1734
1735 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1736 {
1737         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1738
1739         regcache_mark_dirty(i2s_tdm->regmap);
1740
1741         return 0;
1742 }
1743
1744 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1745 {
1746         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1747         int ret;
1748
1749         ret = pm_runtime_resume_and_get(dev);
1750         if (ret < 0)
1751                 return ret;
1752         ret = regcache_sync(i2s_tdm->regmap);
1753         pm_runtime_put(dev);
1754
1755         return ret;
1756 }
1757
1758 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1759         SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1760                            NULL)
1761         SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1762                                 rockchip_i2s_tdm_resume)
1763 };
1764
1765 static struct platform_driver rockchip_i2s_tdm_driver = {
1766         .probe = rockchip_i2s_tdm_probe,
1767         .remove = rockchip_i2s_tdm_remove,
1768         .driver = {
1769                 .name = DRV_NAME,
1770                 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
1771                 .pm = &rockchip_i2s_tdm_pm_ops,
1772         },
1773 };
1774 module_platform_driver(rockchip_i2s_tdm_driver);
1775
1776 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1777 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1778 MODULE_LICENSE("GPL v2");
1779 MODULE_ALIAS("platform:" DRV_NAME);
1780 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);