1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __AUDIOREACH_H__
4 #define __AUDIOREACH_H__
5 #include <linux/types.h>
6 #include <linux/soc/qcom/apr.h>
12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001
14 #define MODULE_ID_GAIN 0x07001002
15 #define MODULE_ID_PCM_CNV 0x07001003
16 #define MODULE_ID_PCM_ENC 0x07001004
17 #define MODULE_ID_PCM_DEC 0x07001005
18 #define MODULE_ID_SAL 0x07001010
19 #define MODULE_ID_MFC 0x07001015
20 #define MODULE_ID_CODEC_DMA_SINK 0x07001023
21 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024
22 #define MODULE_ID_I2S_SINK 0x0700100A
23 #define MODULE_ID_I2S_SOURCE 0x0700100B
24 #define MODULE_ID_DATA_LOGGING 0x0700101A
26 #define APM_CMD_GET_SPF_STATE 0x01001021
27 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007
29 #define APM_MODULE_INSTANCE_ID 0x00000001
30 #define PRM_MODULE_INSTANCE_ID 0x00000002
31 #define AMDB_MODULE_INSTANCE_ID 0x00000003
32 #define VCPM_MODULE_INSTANCE_ID 0x00000004
33 #define AR_MODULE_INSTANCE_ID_START 0x00006000
34 #define AR_MODULE_INSTANCE_ID_END 0x00007000
35 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000
36 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000
37 #define AR_CONT_INSTANCE_ID_START 0x00005000
38 #define AR_CONT_INSTANCE_ID_END 0x00006000
39 #define AR_SG_INSTANCE_ID_START 0x00004000
41 #define APM_CMD_GRAPH_OPEN 0x01001000
42 #define APM_CMD_GRAPH_PREPARE 0x01001001
43 #define APM_CMD_GRAPH_START 0x01001002
44 #define APM_CMD_GRAPH_STOP 0x01001003
45 #define APM_CMD_GRAPH_CLOSE 0x01001004
46 #define APM_CMD_GRAPH_FLUSH 0x01001005
47 #define APM_CMD_SET_CFG 0x01001006
48 #define APM_CMD_GET_CFG 0x01001007
49 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C
50 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D
51 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001
52 #define APM_CMD_RSP_GET_CFG 0x02001000
53 #define APM_CMD_CLOSE_ALL 0x01001013
54 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A
56 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3
58 struct apm_cmd_shared_mem_map_regions {
61 uint32_t property_flag;
64 struct apm_shared_map_region_payload {
65 uint32_t shm_addr_lsw;
66 uint32_t shm_addr_msw;
67 uint32_t mem_size_bytes;
70 struct apm_cmd_shared_mem_unmap_regions {
71 uint32_t mem_map_handle;
74 struct apm_cmd_rsp_shared_mem_map_regions {
75 uint32_t mem_map_handle;
79 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005
81 #define APM_PARAM_ID_MODULE_LIST 0x08001002
83 struct apm_param_id_modules_list {
84 uint32_t num_modules_list;
87 #define APM_PARAM_ID_MODULE_PROP 0x08001003
89 struct apm_param_id_module_prop {
90 uint32_t num_modules_prop_cfg;
93 struct apm_module_prop_cfg {
98 #define APM_PARAM_ID_MODULE_CONN 0x08001004
100 struct apm_param_id_module_conn {
101 uint32_t num_connections;
104 struct apm_module_conn_obj {
105 uint32_t src_mod_inst_id;
106 uint32_t src_mod_op_port_id;
107 uint32_t dst_mod_inst_id;
108 uint32_t dst_mod_ip_port_id;
111 #define APM_PARAM_ID_GAIN 0x08001006
113 struct param_id_gain_cfg {
118 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008
120 struct param_id_pcm_output_format_cfg {
121 uint32_t data_format;
123 uint32_t payload_size;
126 struct payload_pcm_output_format_cfg {
129 uint16_t bits_per_sample;
132 uint16_t interleaved;
134 uint16_t num_channels;
135 uint8_t channel_mapping[];
138 #define PARAM_ID_ENC_BITRATE 0x08001052
140 struct param_id_enc_bitrate_param {
144 #define DATA_FORMAT_FIXED_POINT 1
145 #define PCM_LSB_ALIGNED 1
146 #define PCM_MSB_ALIGNED 2
147 #define PCM_LITTLE_ENDIAN 1
148 #define PCM_BIT_ENDIAN 2
150 #define MEDIA_FMT_ID_PCM 0x09001000
151 #define PCM_CHANNEL_L 1
152 #define PCM_CHANNEL_R 2
153 #define SAMPLE_RATE_48K 48000
154 #define BIT_WIDTH_16 16
156 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015
158 struct apm_modules_prop_info {
159 uint32_t max_ip_port;
160 uint32_t max_op_port;
163 /* Shared memory module */
164 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000
165 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31)
166 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30)
167 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29)
168 #define WR_SH_MEM_EP_EOF_FLAG BIT(4)
170 struct apm_data_cmd_wr_sh_mem_ep_data_buffer {
171 uint32_t buf_addr_lsw;
172 uint32_t buf_addr_msw;
173 uint32_t mem_map_handle;
175 uint32_t timestamp_lsw;
176 uint32_t timestamp_msw;
180 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A
182 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 {
183 uint32_t buf_addr_lsw;
184 uint32_t buf_addr_msw;
185 uint32_t mem_map_handle;
187 uint32_t timestamp_lsw;
188 uint32_t timestamp_msw;
190 uint32_t md_addr_lsw;
191 uint32_t md_addr_msw;
192 uint32_t md_map_handle;
193 uint32_t md_buf_size;
196 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000
198 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done {
199 uint32_t buf_addr_lsw;
200 uint32_t buf_addr_msw;
201 uint32_t mem_map_handle;
206 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004
208 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 {
209 uint32_t buf_addr_lsw;
210 uint32_t buf_addr_msw;
211 uint32_t mem_map_handle;
213 uint32_t md_buf_addr_lsw;
214 uint32_t md_buf_addr_msw;
215 uint32_t md_mem_map_handle;
219 #define PARAM_ID_MEDIA_FORMAT 0x0800100C
220 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001
222 struct apm_media_format {
223 uint32_t data_format;
225 uint32_t payload_size;
228 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002
229 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1
230 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2
232 struct data_cmd_wr_sh_mem_ep_eos {
237 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003
239 struct data_cmd_rd_sh_mem_ep_data_buffer {
240 uint32_t buf_addr_lsw;
241 uint32_t buf_addr_msw;
242 uint32_t mem_map_handle;
246 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002
248 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done {
250 uint32_t buf_addr_lsw;
251 uint32_t buf_addr_msw;
252 uint32_t mem_map_handle;
255 uint32_t timestamp_lsw;
256 uint32_t timestamp_msw;
261 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B
263 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 {
264 uint32_t buf_addr_lsw;
265 uint32_t buf_addr_msw;
266 uint32_t mem_map_handle;
268 uint32_t md_buf_addr_lsw;
269 uint32_t md_buf_addr_msw;
270 uint32_t md_mem_map_handle;
271 uint32_t md_buf_size;
274 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005
276 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 {
278 uint32_t buf_addr_lsw;
279 uint32_t buf_addr_msw;
280 uint32_t mem_map_handle;
283 uint32_t timestamp_lsw;
284 uint32_t timestamp_msw;
288 uint32_t md_buf_addr_lsw;
289 uint32_t md_buf_addr_msw;
290 uint32_t md_mem_map_handle;
294 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007
296 struct param_id_rd_sh_mem_cfg {
297 uint32_t num_frames_per_buffer;
298 uint32_t metadata_control_flags;
302 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001
304 struct data_cmd_wr_sh_mem_ep_eos_rendered {
305 uint32_t module_instance_id;
306 uint32_t render_status;
309 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
311 struct apm_cmd_header {
312 uint32_t payload_address_lsw;
313 uint32_t payload_address_msw;
314 uint32_t mem_map_handle;
315 uint32_t payload_size;
318 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header)
320 struct apm_module_param_data {
321 uint32_t module_instance_id;
327 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data)
329 struct apm_module_param_shared_data {
334 struct apm_prop_data {
339 /* Sub-Graph Properties */
340 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001
342 struct apm_param_id_sub_graph_cfg {
343 uint32_t num_sub_graphs;
346 struct apm_sub_graph_cfg {
347 uint32_t sub_graph_id;
348 uint32_t num_sub_graph_prop;
351 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E
353 struct apm_sg_prop_id_perf_mode {
357 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4
359 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F
361 struct apm_sg_prop_id_direction {
365 #define APM_SG_PROP_ID_DIR_SIZE 4
367 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010
368 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
369 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2
370 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3
372 struct apm_sg_prop_id_scenario_id {
373 uint32_t scenario_id;
376 #define APM_SG_PROP_ID_SID_SIZE 4
378 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000
380 struct apm_param_id_container_cfg {
381 uint32_t num_containers;
384 struct apm_container_cfg {
385 uint32_t container_id;
389 struct apm_cont_capability {
390 uint32_t capability_id;
393 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011
394 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8
396 #define APM_PROP_ID_INVALID 0x0
397 #define APM_CONTAINER_CAP_ID_PP 0x1
398 #define APM_CONTAINER_CAP_ID_PP 0x1
400 struct apm_cont_prop_id_cap_list {
401 uint32_t num_capability_id;
404 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012
406 struct apm_cont_prop_id_graph_pos {
410 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013
412 struct apm_cont_prop_id_stack_size {
416 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014
418 struct apm_cont_prop_id_domain {
419 uint32_t proc_domain;
422 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0
423 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1
425 #define PARAM_ID_I2S_INTF_CFG 0x08001019
426 struct param_id_i2s_intf_cfg {
429 uint16_t sd_line_idx;
433 #define I2S_INTF_TYPE_PRIMARY 0
434 #define I2S_INTF_TYPE_SECOINDARY 1
435 #define I2S_INTF_TYPE_TERTINARY 2
436 #define I2S_INTF_TYPE_QUATERNARY 3
437 #define I2S_INTF_TYPE_QUINARY 4
443 #define PORT_ID_I2S_INPUT 2
444 #define PORT_ID_I2S_OUPUT 1
445 #define I2S_STACK_SIZE 2048
447 #define PARAM_ID_HW_EP_MF_CFG 0x08001017
448 struct param_id_hw_ep_mf {
449 uint32_t sample_rate;
451 uint16_t num_channels;
452 uint32_t data_format;
455 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018
457 struct param_id_fram_size_factor {
458 uint32_t frame_size_factor;
461 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB
463 struct apm_cont_prop_id_parent_container {
464 uint32_t parent_container_id;
467 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174
468 #define APM_CONT_HEAP_DEFAULT 0x1
469 #define APM_CONT_HEAP_LOW_POWER 0x2
471 struct apm_cont_prop_id_headp_id {
475 struct apm_modules_list {
476 uint32_t sub_graph_id;
477 uint32_t container_id;
478 uint32_t num_modules;
481 struct apm_module_obj {
483 uint32_t instance_id;
486 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015
487 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8
488 struct apm_module_prop_id_port_info {
489 uint32_t max_ip_port;
490 uint32_t max_op_port;
493 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1
494 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1
495 #define DATA_LOGGING_STACK_SIZE 2048
496 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031
498 struct data_logging_config {
500 uint32_t log_tap_point_id;
504 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016
505 struct param_id_sal_output_config {
506 uint32_t bits_per_sample;
509 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E
510 struct param_id_sal_limiter_enable {
514 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024
516 struct param_id_mfc_media_format {
517 uint32_t sample_rate;
519 uint16_t num_channels;
520 uint16_t channel_mapping[];
523 struct media_format {
524 uint32_t data_format;
526 uint32_t payload_size;
529 struct payload_media_fmt_pcm {
530 uint32_t sample_rate;
533 uint16_t bits_per_sample;
536 uint16_t num_channels;
537 uint8_t channel_mapping[];
540 #define PARAM_ID_MODULE_ENABLE 0x08001026
541 struct param_id_module_enable {
545 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063
547 struct param_id_codec_dma_intf_cfg {
557 * RX2 | TX2 = 3... so on
560 uint32_t active_channels_mask;
563 struct audio_hw_clk_cfg {
566 uint32_t clock_attri;
570 struct audio_hw_clk_rel_cfg {
574 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176
575 #define AR_HW_EP_POWER_MODE_0 0 /* default */
576 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */
577 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */
579 struct param_id_hw_ep_power_mode_cfg {
583 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233
584 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0
585 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1
586 #define AR_PCM_MAX_NUM_CHANNEL 8
588 struct param_id_hw_ep_dma_data_align {
589 uint32_t dma_data_align;
592 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035
593 #define VOL_CTRL_DEFAULT_GAIN 0x2000
595 struct param_id_vol_ctrl_master_gain {
596 uint16_t master_gain;
602 struct audioreach_connection {
604 uint32_t src_mod_inst_id;
605 uint32_t src_mod_op_port_id;
606 uint32_t dst_mod_inst_id;
607 uint32_t dst_mod_ip_port_id;
608 struct list_head node;
611 struct audioreach_graph_info {
613 uint32_t num_sub_graphs;
614 struct list_head sg_list;
615 /* DPCM connection from FE Graph to BE graph */
616 uint32_t src_mod_inst_id;
617 uint32_t src_mod_op_port_id;
618 uint32_t dst_mod_inst_id;
619 uint32_t dst_mod_ip_port_id;
622 struct audioreach_sub_graph {
623 uint32_t sub_graph_id;
626 uint32_t scenario_id;
627 struct list_head node;
629 struct audioreach_graph_info *info;
630 uint32_t num_containers;
631 struct list_head container_list;
634 struct audioreach_container {
635 uint32_t container_id;
636 uint32_t capability_id;
639 uint32_t proc_domain;
640 struct list_head node;
642 uint32_t num_modules;
643 struct list_head modules_list;
644 struct audioreach_sub_graph *sub_graph;
647 #define AR_MAX_MOD_LINKS 8
649 struct audioreach_module {
651 uint32_t instance_id;
653 uint32_t max_ip_port;
654 uint32_t max_op_port;
659 uint32_t num_connections;
661 uint32_t src_mod_inst_id;
662 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS];
663 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS];
664 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS];
666 /* Format specifics */
672 uint32_t hw_interface_idx;
673 uint32_t sd_line_idx;
675 uint32_t frame_size_factor;
676 uint32_t data_format;
677 uint32_t hw_interface_type;
679 /* PCM module specific */
680 uint32_t interleave_type;
682 /* GAIN/Vol Control Module */
687 uint32_t log_tap_point_id;
691 struct list_head node;
692 struct audioreach_container *container;
693 struct snd_soc_dapm_widget *widget;
696 struct audioreach_module_config {
704 u16 active_channels_mask;
707 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL];
710 /* Packet Allocation routines */
711 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t
713 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode,
714 uint32_t token, uint32_t src_port,
716 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token,
718 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode,
719 uint32_t token, uint32_t src_port,
721 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info
723 /* Topology specific */
724 int audioreach_tplg_init(struct snd_soc_component *component);
726 /* Module specific */
727 void audioreach_graph_free_buf(struct q6apm_graph *graph);
728 int audioreach_map_memory_regions(struct q6apm_graph *graph,
729 unsigned int dir, size_t period_sz,
730 unsigned int periods,
732 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result,
733 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait,
734 struct gpr_pkt *pkt, uint32_t rsp_opcode);
735 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt,
736 uint32_t rsp_opcode);
737 int audioreach_set_media_format(struct q6apm_graph *graph,
738 struct audioreach_module *module,
739 struct audioreach_module_config *cfg);
740 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph);
741 int audioreach_gain_set_vol_ctrl(struct q6apm *apm,
742 struct audioreach_module *module, int vol);
743 #endif /* __AUDIOREACH_H__ */