sound/soc/qcom/lpass-platform.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
   4  *
   5  * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
   6  */
   7
   8 #include <linux/dma-mapping.h>
   9 #include <linux/export.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <sound/pcm_params.h>
  14 #include <linux/regmap.h>
  15 #include <sound/soc.h>
  16 #include "lpass-lpaif-reg.h"
  17 #include "lpass.h"
  18
  19 #define DRV_NAME "lpass-platform"
  20
  21 struct lpass_pcm_data {
  22         int dma_ch;
  23         int i2s_port;
  24 };
  25
  26 #define LPASS_PLATFORM_BUFFER_SIZE      (24 *  2 * 1024)
  27 #define LPASS_PLATFORM_PERIODS          2
  28
  29 static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
  30         .info                   =       SNDRV_PCM_INFO_MMAP |
  31                                         SNDRV_PCM_INFO_MMAP_VALID |
  32                                         SNDRV_PCM_INFO_INTERLEAVED |
  33                                         SNDRV_PCM_INFO_PAUSE |
  34                                         SNDRV_PCM_INFO_RESUME,
  35         .formats                =       SNDRV_PCM_FMTBIT_S16 |
  36                                         SNDRV_PCM_FMTBIT_S24 |
  37                                         SNDRV_PCM_FMTBIT_S32,
  38         .rates                  =       SNDRV_PCM_RATE_8000_192000,
  39         .rate_min               =       8000,
  40         .rate_max               =       192000,
  41         .channels_min           =       1,
  42         .channels_max           =       8,
  43         .buffer_bytes_max       =       LPASS_PLATFORM_BUFFER_SIZE,
  44         .period_bytes_max       =       LPASS_PLATFORM_BUFFER_SIZE /
  45                                                 LPASS_PLATFORM_PERIODS,
  46         .period_bytes_min       =       LPASS_PLATFORM_BUFFER_SIZE /
  47                                                 LPASS_PLATFORM_PERIODS,
  48         .periods_min            =       LPASS_PLATFORM_PERIODS,
  49         .periods_max            =       LPASS_PLATFORM_PERIODS,
  50         .fifo_size              =       0,
  51 };
  52
  53 static int lpass_platform_alloc_dmactl_fields(struct device *dev,
  54                                          struct regmap *map)
  55 {
  56         struct lpass_data *drvdata = dev_get_drvdata(dev);
  57         struct lpass_variant *v = drvdata->variant;
  58         struct lpaif_dmactl *rd_dmactl, *wr_dmactl;
  59         int rval;
  60
  61         drvdata->rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
  62                                           GFP_KERNEL);
  63         if (drvdata->rd_dmactl == NULL)
  64                 return -ENOMEM;
  65
  66         drvdata->wr_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
  67                                           GFP_KERNEL);
  68         if (drvdata->wr_dmactl == NULL)
  69                 return -ENOMEM;
  70
  71         rd_dmactl = drvdata->rd_dmactl;
  72         wr_dmactl = drvdata->wr_dmactl;
  73
  74         rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
  75                                             &v->rdma_intf, 6);
  76         if (rval)
  77                 return rval;
  78
  79         return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
  80                                             &v->wrdma_intf, 6);
  81 }
  82
  83 static int lpass_platform_alloc_hdmidmactl_fields(struct device *dev,
  84                                          struct regmap *map)
  85 {
  86         struct lpass_data *drvdata = dev_get_drvdata(dev);
  87         struct lpass_variant *v = drvdata->variant;
  88         struct lpaif_dmactl *rd_dmactl;
  89
  90         rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl), GFP_KERNEL);
  91         if (rd_dmactl == NULL)
  92                 return -ENOMEM;
  93
  94         drvdata->hdmi_rd_dmactl = rd_dmactl;
  95
  96         return devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->bursten,
  97                                             &v->hdmi_rdma_bursten, 8);
  98 }
  99
 100 static int lpass_platform_pcmops_open(struct snd_soc_component *component,
 101                                       struct snd_pcm_substream *substream)
 102 {
 103         struct snd_pcm_runtime *runtime = substream->runtime;
 104         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 105         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 106         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 107         struct lpass_variant *v = drvdata->variant;
 108         int ret, dma_ch, dir = substream->stream;
 109         struct lpass_pcm_data *data;
 110         struct regmap *map;
 111         unsigned int dai_id = cpu_dai->driver->id;
 112
 113         component->id = dai_id;
 114         data = kzalloc(sizeof(*data), GFP_KERNEL);
 115         if (!data)
 116                 return -ENOMEM;
 117
 118         data->i2s_port = cpu_dai->driver->id;
 119         runtime->private_data = data;
 120
 121         if (v->alloc_dma_channel)
 122                 dma_ch = v->alloc_dma_channel(drvdata, dir, dai_id);
 123         else
 124                 dma_ch = 0;
 125
 126         if (dma_ch < 0) {
 127                 kfree(data);
 128                 return dma_ch;
 129         }
 130
 131         if (cpu_dai->driver->id == LPASS_DP_RX) {
 132                 map = drvdata->hdmiif_map;
 133                 drvdata->hdmi_substream[dma_ch] = substream;
 134         } else {
 135                 map = drvdata->lpaif_map;
 136                 drvdata->substream[dma_ch] = substream;
 137         }
 138         data->dma_ch = dma_ch;
 139         ret = regmap_write(map,
 140                         LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0);
 141         if (ret) {
 142                 dev_err(soc_runtime->dev,
 143                         "error writing to rdmactl reg: %d\n", ret);
 144                 return ret;
 145         }
 146         snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
 147
 148         runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
 149
 150         ret = snd_pcm_hw_constraint_integer(runtime,
 151                         SNDRV_PCM_HW_PARAM_PERIODS);
 152         if (ret < 0) {
 153                 kfree(data);
 154                 dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
 155                         ret);
 156                 return -EINVAL;
 157         }
 158
 159         snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
 160
 161         return 0;
 162 }
 163
 164 static int lpass_platform_pcmops_close(struct snd_soc_component *component,
 165                                        struct snd_pcm_substream *substream)
 166 {
 167         struct snd_pcm_runtime *runtime = substream->runtime;
 168         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 169         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 170         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 171         struct lpass_variant *v = drvdata->variant;
 172         struct lpass_pcm_data *data;
 173         unsigned int dai_id = cpu_dai->driver->id;
 174
 175         data = runtime->private_data;
 176         if (dai_id == LPASS_DP_RX)
 177                 drvdata->hdmi_substream[data->dma_ch] = NULL;
 178         else
 179                 drvdata->substream[data->dma_ch] = NULL;
 180         if (v->free_dma_channel)
 181                 v->free_dma_channel(drvdata, data->dma_ch, dai_id);
 182
 183         kfree(data);
 184         return 0;
 185 }
 186
 187 static int lpass_platform_pcmops_hw_params(struct snd_soc_component *component,
 188                                            struct snd_pcm_substream *substream,
 189                                            struct snd_pcm_hw_params *params)
 190 {
 191         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 192         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 193         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 194         struct snd_pcm_runtime *rt = substream->runtime;
 195         struct lpass_pcm_data *pcm_data = rt->private_data;
 196         struct lpass_variant *v = drvdata->variant;
 197         snd_pcm_format_t format = params_format(params);
 198         unsigned int channels = params_channels(params);
 199         unsigned int regval;
 200         struct lpaif_dmactl *dmactl;
 201         int id, dir = substream->stream;
 202         int bitwidth;
 203         int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
 204         unsigned int dai_id = cpu_dai->driver->id;
 205
 206         if (dir ==  SNDRV_PCM_STREAM_PLAYBACK) {
 207                 id = pcm_data->dma_ch;
 208                 if (dai_id == LPASS_DP_RX)
 209                         dmactl = drvdata->hdmi_rd_dmactl;
 210                 else
 211                         dmactl = drvdata->rd_dmactl;
 212
 213         } else {
 214                 dmactl = drvdata->wr_dmactl;
 215                 id = pcm_data->dma_ch - v->wrdma_channel_start;
 216         }
 217
 218         bitwidth = snd_pcm_format_width(format);
 219         if (bitwidth < 0) {
 220                 dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
 221                                 bitwidth);
 222                 return bitwidth;
 223         }
 224
 225         ret = regmap_fields_write(dmactl->bursten, id, LPAIF_DMACTL_BURSTEN_INCR4);
 226         if (ret) {
 227                 dev_err(soc_runtime->dev, "error updating bursten field: %d\n", ret);
 228                 return ret;
 229         }
 230
 231         ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
 232         if (ret) {
 233                 dev_err(soc_runtime->dev, "error updating fifowm field: %d\n", ret);
 234                 return ret;
 235         }
 236
 237         switch (dai_id) {
 238         case LPASS_DP_RX:
 239                 ret = regmap_fields_write(dmactl->burst8, id,
 240                                                         LPAIF_DMACTL_BURSTEN_INCR4);
 241                 if (ret) {
 242                         dev_err(soc_runtime->dev, "error updating burst8en field: %d\n", ret);
 243                         return ret;
 244                 }
 245                 ret = regmap_fields_write(dmactl->burst16, id,
 246                                                         LPAIF_DMACTL_BURSTEN_INCR4);
 247                 if (ret) {
 248                         dev_err(soc_runtime->dev, "error updating burst16en field: %d\n", ret);
 249                         return ret;
 250                 }
 251                 ret = regmap_fields_write(dmactl->dynburst, id,
 252                                                         LPAIF_DMACTL_BURSTEN_INCR4);
 253                 if (ret) {
 254                         dev_err(soc_runtime->dev, "error updating dynbursten field: %d\n", ret);
 255                         return ret;
 256                 }
 257                 break;
 258         case MI2S_PRIMARY:
 259         case MI2S_SECONDARY:
 260                 ret = regmap_fields_write(dmactl->intf, id,
 261                                                 LPAIF_DMACTL_AUDINTF(dma_port));
 262                 if (ret) {
 263                         dev_err(soc_runtime->dev, "error updating audio interface field: %d\n",
 264                                         ret);
 265                         return ret;
 266                 }
 267
 268                 break;
 269         default:
 270                 dev_err(soc_runtime->dev, "%s: invalid  interface: %d\n", __func__, dai_id);
 271                 break;
 272         }
 273         switch (bitwidth) {
 274         case 16:
 275                 switch (channels) {
 276                 case 1:
 277                 case 2:
 278                         regval = LPAIF_DMACTL_WPSCNT_ONE;
 279                         break;
 280                 case 4:
 281                         regval = LPAIF_DMACTL_WPSCNT_TWO;
 282                         break;
 283                 case 6:
 284                         regval = LPAIF_DMACTL_WPSCNT_THREE;
 285                         break;
 286                 case 8:
 287                         regval = LPAIF_DMACTL_WPSCNT_FOUR;
 288                         break;
 289                 default:
 290                         dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
 291                                 bitwidth, channels);
 292                         return -EINVAL;
 293                 }
 294                 break;
 295         case 24:
 296         case 32:
 297                 switch (channels) {
 298                 case 1:
 299                         regval = LPAIF_DMACTL_WPSCNT_ONE;
 300                         break;
 301                 case 2:
 302                         regval = (dai_id == LPASS_DP_RX ?
 303                         LPAIF_DMACTL_WPSCNT_ONE :
 304                         LPAIF_DMACTL_WPSCNT_TWO);
 305                         break;
 306                 case 4:
 307                         regval = (dai_id == LPASS_DP_RX ?
 308                         LPAIF_DMACTL_WPSCNT_TWO :
 309                         LPAIF_DMACTL_WPSCNT_FOUR);
 310                         break;
 311                 case 6:
 312                         regval = (dai_id == LPASS_DP_RX ?
 313                         LPAIF_DMACTL_WPSCNT_THREE :
 314                         LPAIF_DMACTL_WPSCNT_SIX);
 315                         break;
 316                 case 8:
 317                         regval = (dai_id == LPASS_DP_RX ?
 318                         LPAIF_DMACTL_WPSCNT_FOUR :
 319                         LPAIF_DMACTL_WPSCNT_EIGHT);
 320                         break;
 321                 default:
 322                         dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
 323                                 bitwidth, channels);
 324                         return -EINVAL;
 325                 }
 326                 break;
 327         default:
 328                 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
 329                         bitwidth, channels);
 330                 return -EINVAL;
 331         }
 332
 333         ret = regmap_fields_write(dmactl->wpscnt, id, regval);
 334         if (ret) {
 335                 dev_err(soc_runtime->dev, "error writing to dmactl reg: %d\n",
 336                         ret);
 337                 return ret;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static int lpass_platform_pcmops_hw_free(struct snd_soc_component *component,
 344                                          struct snd_pcm_substream *substream)
 345 {
 346         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 347         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 348         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 349         struct snd_pcm_runtime *rt = substream->runtime;
 350         struct lpass_pcm_data *pcm_data = rt->private_data;
 351         struct lpass_variant *v = drvdata->variant;
 352         unsigned int reg;
 353         int ret;
 354         struct regmap *map;
 355         unsigned int dai_id = cpu_dai->driver->id;
 356
 357         if (dai_id == LPASS_DP_RX)
 358                 map = drvdata->hdmiif_map;
 359         else
 360                 map = drvdata->lpaif_map;
 361
 362         reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream, dai_id);
 363         ret = regmap_write(map, reg, 0);
 364         if (ret)
 365                 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
 366                         ret);
 367
 368         return ret;
 369 }
 370
 371 static int lpass_platform_pcmops_prepare(struct snd_soc_component *component,
 372                                          struct snd_pcm_substream *substream)
 373 {
 374         struct snd_pcm_runtime *runtime = substream->runtime;
 375         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 376         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 377         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 378         struct snd_pcm_runtime *rt = substream->runtime;
 379         struct lpass_pcm_data *pcm_data = rt->private_data;
 380         struct lpass_variant *v = drvdata->variant;
 381         struct lpaif_dmactl *dmactl;
 382         struct regmap *map;
 383         int ret, id, ch, dir = substream->stream;
 384         unsigned int dai_id = cpu_dai->driver->id;
 385
 386
 387         ch = pcm_data->dma_ch;
 388         if (dir ==  SNDRV_PCM_STREAM_PLAYBACK) {
 389                 if (dai_id == LPASS_DP_RX) {
 390                         dmactl = drvdata->hdmi_rd_dmactl;
 391                         map = drvdata->hdmiif_map;
 392                 } else {
 393                         dmactl = drvdata->rd_dmactl;
 394                         map = drvdata->lpaif_map;
 395                 }
 396
 397                 id = pcm_data->dma_ch;
 398         } else {
 399                 dmactl = drvdata->wr_dmactl;
 400                 id = pcm_data->dma_ch - v->wrdma_channel_start;
 401                 map = drvdata->lpaif_map;
 402         }
 403
 404         ret = regmap_write(map, LPAIF_DMABASE_REG(v, ch, dir, dai_id),
 405                                 runtime->dma_addr);
 406         if (ret) {
 407                 dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
 408                         ret);
 409                 return ret;
 410         }
 411
 412         ret = regmap_write(map, LPAIF_DMABUFF_REG(v, ch, dir, dai_id),
 413                         (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
 414         if (ret) {
 415                 dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
 416                         ret);
 417                 return ret;
 418         }
 419
 420         ret = regmap_write(map, LPAIF_DMAPER_REG(v, ch, dir, dai_id),
 421                         (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
 422         if (ret) {
 423                 dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
 424                         ret);
 425                 return ret;
 426         }
 427
 428         ret = regmap_fields_write(dmactl->enable, id, LPAIF_DMACTL_ENABLE_ON);
 429         if (ret) {
 430                 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
 431                         ret);
 432                 return ret;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,
 439                                          struct snd_pcm_substream *substream,
 440                                          int cmd)
 441 {
 442         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 443         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 444         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 445         struct snd_pcm_runtime *rt = substream->runtime;
 446         struct lpass_pcm_data *pcm_data = rt->private_data;
 447         struct lpass_variant *v = drvdata->variant;
 448         struct lpaif_dmactl *dmactl;
 449         struct regmap *map;
 450         int ret, ch, id;
 451         int dir = substream->stream;
 452         unsigned int reg_irqclr = 0, val_irqclr = 0;
 453         unsigned int  reg_irqen = 0, val_irqen = 0, val_mask = 0;
 454         unsigned int dai_id = cpu_dai->driver->id;
 455
 456         ch = pcm_data->dma_ch;
 457         if (dir ==  SNDRV_PCM_STREAM_PLAYBACK) {
 458                 id = pcm_data->dma_ch;
 459                 if (dai_id == LPASS_DP_RX) {
 460                         dmactl = drvdata->hdmi_rd_dmactl;
 461                         map = drvdata->hdmiif_map;
 462                 } else {
 463                         dmactl = drvdata->rd_dmactl;
 464                         map = drvdata->lpaif_map;
 465                 }
 466         } else {
 467                 dmactl = drvdata->wr_dmactl;
 468                 id = pcm_data->dma_ch - v->wrdma_channel_start;
 469                 map = drvdata->lpaif_map;
 470         }
 471
 472         switch (cmd) {
 473         case SNDRV_PCM_TRIGGER_START:
 474         case SNDRV_PCM_TRIGGER_RESUME:
 475         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 476                 ret = regmap_fields_write(dmactl->enable, id,
 477                                                  LPAIF_DMACTL_ENABLE_ON);
 478                 if (ret) {
 479                         dev_err(soc_runtime->dev,
 480                                 "error writing to rdmactl reg: %d\n", ret);
 481                         return ret;
 482                 }
 483                 switch (dai_id) {
 484                 case LPASS_DP_RX:
 485                         ret = regmap_fields_write(dmactl->dyncclk, id,
 486                                          LPAIF_DMACTL_DYNCLK_ON);
 487                         if (ret) {
 488                                 dev_err(soc_runtime->dev,
 489                                         "error writing to rdmactl reg: %d\n", ret);
 490                                 return ret;
 491                         }
 492                         reg_irqclr = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
 493                         val_irqclr = (LPAIF_IRQ_ALL(ch) |
 494                                         LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
 495                                         LPAIF_IRQ_HDMI_METADONE |
 496                                         LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
 497
 498                         reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
 499                         val_mask = (LPAIF_IRQ_ALL(ch) |
 500                                         LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
 501                                         LPAIF_IRQ_HDMI_METADONE |
 502                                         LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
 503                         val_irqen = (LPAIF_IRQ_ALL(ch) |
 504                                         LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
 505                                         LPAIF_IRQ_HDMI_METADONE |
 506                                         LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
 507                         break;
 508                 case MI2S_PRIMARY:
 509                 case MI2S_SECONDARY:
 510                         reg_irqclr = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
 511                         val_irqclr = LPAIF_IRQ_ALL(ch);
 512
 513
 514                         reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
 515                         val_mask = LPAIF_IRQ_ALL(ch);
 516                         val_irqen = LPAIF_IRQ_ALL(ch);
 517                         break;
 518                 default:
 519                         dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
 520                         return -EINVAL;
 521                 }
 522
 523                 ret = regmap_write(map, reg_irqclr, val_irqclr);
 524                 if (ret) {
 525                         dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret);
 526                         return ret;
 527                 }
 528                 ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
 529                 if (ret) {
 530                         dev_err(soc_runtime->dev, "error writing to irqen reg: %d\n", ret);
 531                         return ret;
 532                 }
 533                 break;
 534         case SNDRV_PCM_TRIGGER_STOP:
 535         case SNDRV_PCM_TRIGGER_SUSPEND:
 536         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 537                 ret = regmap_fields_write(dmactl->enable, id,
 538                                          LPAIF_DMACTL_ENABLE_OFF);
 539                 if (ret) {
 540                         dev_err(soc_runtime->dev,
 541                                 "error writing to rdmactl reg: %d\n", ret);
 542                         return ret;
 543                 }
 544                 switch (dai_id) {
 545                 case LPASS_DP_RX:
 546                         ret = regmap_fields_write(dmactl->dyncclk, id,
 547                                          LPAIF_DMACTL_DYNCLK_OFF);
 548                         if (ret) {
 549                                 dev_err(soc_runtime->dev,
 550                                         "error writing to rdmactl reg: %d\n", ret);
 551                                 return ret;
 552                         }
 553                         reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
 554                         val_mask = (LPAIF_IRQ_ALL(ch) |
 555                                         LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
 556                                         LPAIF_IRQ_HDMI_METADONE |
 557                                         LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
 558                         val_irqen = 0;
 559                         break;
 560                 case MI2S_PRIMARY:
 561                 case MI2S_SECONDARY:
 562                         reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
 563                         val_mask = LPAIF_IRQ_ALL(ch);
 564                         val_irqen = 0;
 565                         break;
 566                 default:
 567                         dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
 568                         return -EINVAL;
 569                 }
 570
 571                 ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
 572                 if (ret) {
 573                         dev_err(soc_runtime->dev,
 574                                 "error writing to irqen reg: %d\n", ret);
 575                         return ret;
 576                 }
 577                 break;
 578         }
 579
 580         return 0;
 581 }
 582
 583 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
 584                 struct snd_soc_component *component,
 585                 struct snd_pcm_substream *substream)
 586 {
 587         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 588         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 589         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 590         struct snd_pcm_runtime *rt = substream->runtime;
 591         struct lpass_pcm_data *pcm_data = rt->private_data;
 592         struct lpass_variant *v = drvdata->variant;
 593         unsigned int base_addr, curr_addr;
 594         int ret, ch, dir = substream->stream;
 595         struct regmap *map;
 596         unsigned int dai_id = cpu_dai->driver->id;
 597
 598         if (dai_id == LPASS_DP_RX)
 599                 map = drvdata->hdmiif_map;
 600         else
 601                 map = drvdata->lpaif_map;
 602
 603         ch = pcm_data->dma_ch;
 604
 605         ret = regmap_read(map,
 606                         LPAIF_DMABASE_REG(v, ch, dir, dai_id), &base_addr);
 607         if (ret) {
 608                 dev_err(soc_runtime->dev,
 609                         "error reading from rdmabase reg: %d\n", ret);
 610                 return ret;
 611         }
 612
 613         ret = regmap_read(map,
 614                         LPAIF_DMACURR_REG(v, ch, dir, dai_id), &curr_addr);
 615         if (ret) {
 616                 dev_err(soc_runtime->dev,
 617                         "error reading from rdmacurr reg: %d\n", ret);
 618                 return ret;
 619         }
 620
 621         return bytes_to_frames(substream->runtime, curr_addr - base_addr);
 622 }
 623
 624 static int lpass_platform_pcmops_mmap(struct snd_soc_component *component,
 625                                       struct snd_pcm_substream *substream,
 626                                       struct vm_area_struct *vma)
 627 {
 628         struct snd_pcm_runtime *runtime = substream->runtime;
 629
 630         return dma_mmap_coherent(component->dev, vma, runtime->dma_area,
 631                                  runtime->dma_addr, runtime->dma_bytes);
 632 }
 633
 634 static irqreturn_t lpass_dma_interrupt_handler(
 635                         struct snd_pcm_substream *substream,
 636                         struct lpass_data *drvdata,
 637                         int chan, u32 interrupts)
 638 {
 639         struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
 640         struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
 641         struct lpass_variant *v = drvdata->variant;
 642         irqreturn_t ret = IRQ_NONE;
 643         int rv;
 644         unsigned int reg = 0, val = 0;
 645         struct regmap *map;
 646         unsigned int dai_id = cpu_dai->driver->id;
 647
 648         switch (dai_id) {
 649         case LPASS_DP_RX:
 650                 map = drvdata->hdmiif_map;
 651                 reg = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
 652                 val = (LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
 653                 LPAIF_IRQ_HDMI_METADONE |
 654                 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan));
 655         break;
 656         case MI2S_PRIMARY:
 657         case MI2S_SECONDARY:
 658                 map = drvdata->lpaif_map;
 659                 reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
 660                 val = 0;
 661         break;
 662         default:
 663         dev_err(soc_runtime->dev, "%s: invalid  %d interface\n", __func__, dai_id);
 664         return -EINVAL;
 665         }
 666         if (interrupts & LPAIF_IRQ_PER(chan)) {
 667
 668                 rv = regmap_write(map, reg, LPAIF_IRQ_PER(chan) | val);
 669                 if (rv) {
 670                         dev_err(soc_runtime->dev,
 671                                 "error writing to irqclear reg: %d\n", rv);
 672                         return IRQ_NONE;
 673                 }
 674                 snd_pcm_period_elapsed(substream);
 675                 ret = IRQ_HANDLED;
 676         }
 677
 678         if (interrupts & LPAIF_IRQ_XRUN(chan)) {
 679                 rv = regmap_write(map, reg, LPAIF_IRQ_XRUN(chan) | val);
 680                 if (rv) {
 681                         dev_err(soc_runtime->dev,
 682                                 "error writing to irqclear reg: %d\n", rv);
 683                         return IRQ_NONE;
 684                 }
 685                 dev_warn(soc_runtime->dev, "xrun warning\n");
 686                 snd_pcm_stop_xrun(substream);
 687                 ret = IRQ_HANDLED;
 688         }
 689
 690         if (interrupts & LPAIF_IRQ_ERR(chan)) {
 691                 rv = regmap_write(map, reg, LPAIF_IRQ_ERR(chan) | val);
 692                 if (rv) {
 693                         dev_err(soc_runtime->dev,
 694                                 "error writing to irqclear reg: %d\n", rv);
 695                         return IRQ_NONE;
 696                 }
 697                 dev_err(soc_runtime->dev, "bus access error\n");
 698                 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
 699                 ret = IRQ_HANDLED;
 700         }
 701
 702         if (interrupts & val) {
 703                 rv = regmap_write(map, reg, val);
 704                 if (rv) {
 705                         dev_err(soc_runtime->dev,
 706                         "error writing to irqclear reg: %d\n", rv);
 707                         return IRQ_NONE;
 708                 }
 709                 ret = IRQ_HANDLED;
 710         }
 711
 712         return ret;
 713 }
 714
 715 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
 716 {
 717         struct lpass_data *drvdata = data;
 718         struct lpass_variant *v = drvdata->variant;
 719         unsigned int irqs;
 720         int rv, chan;
 721
 722         rv = regmap_read(drvdata->lpaif_map,
 723                         LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
 724         if (rv) {
 725                 pr_err("error reading from irqstat reg: %d\n", rv);
 726                 return IRQ_NONE;
 727         }
 728
 729         /* Handle per channel interrupts */
 730         for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
 731                 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
 732                         rv = lpass_dma_interrupt_handler(
 733                                                 drvdata->substream[chan],
 734                                                 drvdata, chan, irqs);
 735                         if (rv != IRQ_HANDLED)
 736                                 return rv;
 737                 }
 738         }
 739
 740         return IRQ_HANDLED;
 741 }
 742
 743 static irqreturn_t lpass_platform_hdmiif_irq(int irq, void *data)
 744 {
 745         struct lpass_data *drvdata = data;
 746         struct lpass_variant *v = drvdata->variant;
 747         unsigned int irqs;
 748         int rv, chan;
 749
 750         rv = regmap_read(drvdata->hdmiif_map,
 751                         LPASS_HDMITX_APP_IRQSTAT_REG(v), &irqs);
 752         if (rv) {
 753                 pr_err("error reading from irqstat reg: %d\n", rv);
 754                 return IRQ_NONE;
 755         }
 756
 757         /* Handle per channel interrupts */
 758         for (chan = 0; chan < LPASS_MAX_HDMI_DMA_CHANNELS; chan++) {
 759                 if (irqs & (LPAIF_IRQ_ALL(chan) | LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
 760                                 LPAIF_IRQ_HDMI_METADONE |
 761                                 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan))
 762                         && drvdata->hdmi_substream[chan]) {
 763                         rv = lpass_dma_interrupt_handler(
 764                                                 drvdata->hdmi_substream[chan],
 765                                                 drvdata, chan, irqs);
 766                         if (rv != IRQ_HANDLED)
 767                                 return rv;
 768                 }
 769         }
 770
 771         return IRQ_HANDLED;
 772 }
 773
 774 static int lpass_platform_pcm_new(struct snd_soc_component *component,
 775                                   struct snd_soc_pcm_runtime *soc_runtime)
 776 {
 777         struct snd_pcm *pcm = soc_runtime->pcm;
 778         struct snd_pcm_substream *psubstream, *csubstream;
 779         int ret = -EINVAL;
 780         size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
 781
 782         psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
 783         if (psubstream) {
 784                 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 785                                         component->dev,
 786                                         size, &psubstream->dma_buffer);
 787                 if (ret) {
 788                         dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
 789                         return ret;
 790                 }
 791         }
 792
 793         csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
 794         if (csubstream) {
 795                 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 796                                         component->dev,
 797                                         size, &csubstream->dma_buffer);
 798                 if (ret) {
 799                         dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
 800                         if (psubstream)
 801                                 snd_dma_free_pages(&psubstream->dma_buffer);
 802                         return ret;
 803                 }
 804
 805         }
 806
 807         return 0;
 808 }
 809
 810 static void lpass_platform_pcm_free(struct snd_soc_component *component,
 811                                     struct snd_pcm *pcm)
 812 {
 813         struct snd_pcm_substream *substream;
 814         int i;
 815
 816         for_each_pcm_streams(i) {
 817                 substream = pcm->streams[i].substream;
 818                 if (substream) {
 819                         snd_dma_free_pages(&substream->dma_buffer);
 820                         substream->dma_buffer.area = NULL;
 821                         substream->dma_buffer.addr = 0;
 822                 }
 823         }
 824 }
 825
 826 static int lpass_platform_pcmops_suspend(struct snd_soc_component *component)
 827 {
 828         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 829         struct regmap *map;
 830         unsigned int dai_id = component->id;
 831
 832         if (dai_id == LPASS_DP_RX)
 833                 map = drvdata->hdmiif_map;
 834         else
 835                 map = drvdata->lpaif_map;
 836
 837         regcache_cache_only(map, true);
 838         regcache_mark_dirty(map);
 839
 840         return 0;
 841 }
 842
 843 static int lpass_platform_pcmops_resume(struct snd_soc_component *component)
 844 {
 845         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 846         struct regmap *map;
 847         unsigned int dai_id = component->id;
 848
 849         if (dai_id == LPASS_DP_RX)
 850                 map = drvdata->hdmiif_map;
 851         else
 852                 map = drvdata->lpaif_map;
 853
 854         regcache_cache_only(map, false);
 855         return regcache_sync(map);
 856 }
 857
 858
 859 static const struct snd_soc_component_driver lpass_component_driver = {
 860         .name           = DRV_NAME,
 861         .open           = lpass_platform_pcmops_open,
 862         .close          = lpass_platform_pcmops_close,
 863         .hw_params      = lpass_platform_pcmops_hw_params,
 864         .hw_free        = lpass_platform_pcmops_hw_free,
 865         .prepare        = lpass_platform_pcmops_prepare,
 866         .trigger        = lpass_platform_pcmops_trigger,
 867         .pointer        = lpass_platform_pcmops_pointer,
 868         .mmap           = lpass_platform_pcmops_mmap,
 869         .pcm_construct  = lpass_platform_pcm_new,
 870         .pcm_destruct   = lpass_platform_pcm_free,
 871         .suspend                = lpass_platform_pcmops_suspend,
 872         .resume                 = lpass_platform_pcmops_resume,
 873
 874 };
 875
 876 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
 877 {
 878         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 879         struct lpass_variant *v = drvdata->variant;
 880         int ret;
 881
 882         drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
 883         if (drvdata->lpaif_irq < 0)
 884                 return -ENODEV;
 885
 886         /* ensure audio hardware is disabled */
 887         ret = regmap_write(drvdata->lpaif_map,
 888                         LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
 889         if (ret) {
 890                 dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
 891                 return ret;
 892         }
 893
 894         ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
 895                         lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
 896                         "lpass-irq-lpaif", drvdata);
 897         if (ret) {
 898                 dev_err(&pdev->dev, "irq request failed: %d\n", ret);
 899                 return ret;
 900         }
 901
 902         ret = lpass_platform_alloc_dmactl_fields(&pdev->dev,
 903                                                  drvdata->lpaif_map);
 904         if (ret) {
 905                 dev_err(&pdev->dev,
 906                         "error initializing dmactl fields: %d\n", ret);
 907                 return ret;
 908         }
 909
 910         if (drvdata->hdmi_port_enable) {
 911                 drvdata->hdmiif_irq = platform_get_irq_byname(pdev, "lpass-irq-hdmi");
 912                 if (drvdata->hdmiif_irq < 0)
 913                         return -ENODEV;
 914
 915                 ret = devm_request_irq(&pdev->dev, drvdata->hdmiif_irq,
 916                                 lpass_platform_hdmiif_irq, 0, "lpass-irq-hdmi", drvdata);
 917                 if (ret) {
 918                         dev_err(&pdev->dev, "irq hdmi request failed: %d\n", ret);
 919                         return ret;
 920                 }
 921                 ret = regmap_write(drvdata->hdmiif_map,
 922                                 LPASS_HDMITX_APP_IRQEN_REG(v), 0);
 923                 if (ret) {
 924                         dev_err(&pdev->dev, "error writing to hdmi irqen reg: %d\n", ret);
 925                         return ret;
 926                 }
 927
 928                 ret = lpass_platform_alloc_hdmidmactl_fields(&pdev->dev,
 929                                                          drvdata->hdmiif_map);
 930                 if (ret) {
 931                         dev_err(&pdev->dev,
 932                                 "error initializing hdmidmactl fields: %d\n", ret);
 933                         return ret;
 934                 }
 935         }
 936         return devm_snd_soc_register_component(&pdev->dev,
 937                         &lpass_component_driver, NULL, 0);
 938 }
 939 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
 940
 941 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
 942 MODULE_LICENSE("GPL v2");