sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/initval.h>
  35 #include <sound/soc.h>
  36
  37 #include <plat/mcbsp.h>
  38 #include "mcbsp.h"
  39 #include "omap-mcbsp.h"
  40 #include "omap-pcm.h"
  41
  42 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  43
  44 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  45         xhandler_get, xhandler_put) \
  46 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  47         .info = omap_mcbsp_st_info_volsw, \
  48         .get = xhandler_get, .put = xhandler_put, \
  49         .private_value = (unsigned long) &(struct soc_mixer_control) \
  50         {.min = xmin, .max = xmax} }
  51
  52 enum {
  53         OMAP_MCBSP_WORD_8 = 0,
  54         OMAP_MCBSP_WORD_12,
  55         OMAP_MCBSP_WORD_16,
  56         OMAP_MCBSP_WORD_20,
  57         OMAP_MCBSP_WORD_24,
  58         OMAP_MCBSP_WORD_32,
  59 };
  60
  61 /*
  62  * Stream DMA parameters. DMA request line and port address are set runtime
  63  * since they are different between OMAP1 and later OMAPs
  64  */
  65 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  66 {
  67         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  68         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  69         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  70         struct omap_pcm_dma_data *dma_data;
  71         int words;
  72
  73         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  74
  75         /*
  76          * Configure McBSP threshold based on either:
  77          * packet_size, when the sDMA is in packet mode, or based on the
  78          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  79          * for mono streams.
  80          */
  81         if (dma_data->packet_size)
  82                 words = dma_data->packet_size;
  83         else
  84                 words = 1;
  85
  86         /* Configure McBSP internal buffer usage */
  87         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  88                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  89         else
  90                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  91 }
  92
  93 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  94                                     struct snd_pcm_hw_rule *rule)
  95 {
  96         struct snd_interval *buffer_size = hw_param_interval(params,
  97                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
  98         struct snd_interval *channels = hw_param_interval(params,
  99                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 100         struct omap_mcbsp *mcbsp = rule->private;
 101         struct snd_interval frames;
 102         int size;
 103
 104         snd_interval_any(&frames);
 105         size = mcbsp->pdata->buffer_size;
 106
 107         frames.min = size / channels->min;
 108         frames.integer = 1;
 109         return snd_interval_refine(buffer_size, &frames);
 110 }
 111
 112 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 113                                   struct snd_soc_dai *cpu_dai)
 114 {
 115         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 116         int err = 0;
 117
 118         if (!cpu_dai->active)
 119                 err = omap_mcbsp_request(mcbsp);
 120
 121         /*
 122          * OMAP3 McBSP FIFO is word structured.
 123          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 124          * McBSP1,3,4,5 has 128 word long buffer
 125          * This means that the size of the FIFO depends on the sample format.
 126          * For example on McBSP3:
 127          * 16bit samples: size is 128 * 2 = 256 bytes
 128          * 32bit samples: size is 128 * 4 = 512 bytes
 129          * It is simpler to place constraint for buffer and period based on
 130          * channels.
 131          * McBSP3 as example again (16 or 32 bit samples):
 132          * 1 channel (mono): size is 128 frames (128 words)
 133          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 134          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 135          */
 136         if (mcbsp->pdata->buffer_size) {
 137                 /*
 138                 * Rule for the buffer size. We should not allow
 139                 * smaller buffer than the FIFO size to avoid underruns.
 140                 * This applies only for the playback stream.
 141                 */
 142                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 143                         snd_pcm_hw_rule_add(substream->runtime, 0,
 144                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 145                                             omap_mcbsp_hwrule_min_buffersize,
 146                                             mcbsp,
 147                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 148
 149                 /* Make sure, that the period size is always even */
 150                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 151                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 152         }
 153
 154         return err;
 155 }
 156
 157 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 158                                     struct snd_soc_dai *cpu_dai)
 159 {
 160         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 161
 162         if (!cpu_dai->active) {
 163                 omap_mcbsp_free(mcbsp);
 164                 mcbsp->configured = 0;
 165         }
 166 }
 167
 168 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 169                                   struct snd_soc_dai *cpu_dai)
 170 {
 171         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 172         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 173
 174         switch (cmd) {
 175         case SNDRV_PCM_TRIGGER_START:
 176         case SNDRV_PCM_TRIGGER_RESUME:
 177         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 178                 mcbsp->active++;
 179                 omap_mcbsp_start(mcbsp, play, !play);
 180                 break;
 181
 182         case SNDRV_PCM_TRIGGER_STOP:
 183         case SNDRV_PCM_TRIGGER_SUSPEND:
 184         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 185                 omap_mcbsp_stop(mcbsp, play, !play);
 186                 mcbsp->active--;
 187                 break;
 188         default:
 189                 err = -EINVAL;
 190         }
 191
 192         return err;
 193 }
 194
 195 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 196                         struct snd_pcm_substream *substream,
 197                         struct snd_soc_dai *dai)
 198 {
 199         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 200         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 201         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 202         u16 fifo_use;
 203         snd_pcm_sframes_t delay;
 204
 205         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 206                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 207         else
 208                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 209
 210         /*
 211          * Divide the used locations with the channel count to get the
 212          * FIFO usage in samples (don't care about partial samples in the
 213          * buffer).
 214          */
 215         delay = fifo_use / substream->runtime->channels;
 216
 217         return delay;
 218 }
 219
 220 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 221                                     struct snd_pcm_hw_params *params,
 222                                     struct snd_soc_dai *cpu_dai)
 223 {
 224         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 225         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 226         struct omap_pcm_dma_data *dma_data;
 227         int wlen, channels, wpf;
 228         int pkt_size = 0;
 229         unsigned int format, div, framesize, master;
 230
 231         dma_data = &mcbsp->dma_data[substream->stream];
 232         channels = params_channels(params);
 233
 234         switch (params_format(params)) {
 235         case SNDRV_PCM_FORMAT_S16_LE:
 236                 wlen = 16;
 237                 break;
 238         case SNDRV_PCM_FORMAT_S32_LE:
 239                 wlen = 32;
 240                 break;
 241         default:
 242                 return -EINVAL;
 243         }
 244         if (mcbsp->pdata->buffer_size) {
 245                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 246                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 247                         int period_words, max_thrsh;
 248                         int divider = 0;
 249
 250                         period_words = params_period_bytes(params) / (wlen / 8);
 251                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 252                                 max_thrsh = mcbsp->max_tx_thres;
 253                         else
 254                                 max_thrsh = mcbsp->max_rx_thres;
 255                         /*
 256                          * Use sDMA packet mode if McBSP is in threshold mode:
 257                          * If period words less than the FIFO size the packet
 258                          * size is set to the number of period words, otherwise
 259                          * Look for the biggest threshold value which divides
 260                          * the period size evenly.
 261                          */
 262                         divider = period_words / max_thrsh;
 263                         if (period_words % max_thrsh)
 264                                 divider++;
 265                         while (period_words % divider &&
 266                                 divider < period_words)
 267                                 divider++;
 268                         if (divider == period_words)
 269                                 return -EINVAL;
 270
 271                         pkt_size = period_words / divider;
 272                 } else if (channels > 1) {
 273                         /* Use packet mode for non mono streams */
 274                         pkt_size = channels;
 275                 }
 276         }
 277
 278         dma_data->packet_size = pkt_size;
 279
 280         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 281
 282         if (mcbsp->configured) {
 283                 /* McBSP already configured by another stream */
 284                 return 0;
 285         }
 286
 287         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 288         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 289         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 290         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 291         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 292         wpf = channels;
 293         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 294                               format == SND_SOC_DAIFMT_LEFT_J)) {
 295                 /* Use dual-phase frames */
 296                 regs->rcr2      |= RPHASE;
 297                 regs->xcr2      |= XPHASE;
 298                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 299                 wpf--;
 300                 regs->rcr2      |= RFRLEN2(wpf - 1);
 301                 regs->xcr2      |= XFRLEN2(wpf - 1);
 302         }
 303
 304         regs->rcr1      |= RFRLEN1(wpf - 1);
 305         regs->xcr1      |= XFRLEN1(wpf - 1);
 306
 307         switch (params_format(params)) {
 308         case SNDRV_PCM_FORMAT_S16_LE:
 309                 /* Set word lengths */
 310                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 311                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 312                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 313                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 314                 break;
 315         case SNDRV_PCM_FORMAT_S32_LE:
 316                 /* Set word lengths */
 317                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 318                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 319                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 320                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 321                 break;
 322         default:
 323                 /* Unsupported PCM format */
 324                 return -EINVAL;
 325         }
 326
 327         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 328          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 329         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 330         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 331                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 332                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 333
 334                 if (framesize < wlen * channels) {
 335                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 336                                         "channels\n", __func__);
 337                         return -EINVAL;
 338                 }
 339         } else
 340                 framesize = wlen * channels;
 341
 342         /* Set FS period and length in terms of bit clock periods */
 343         regs->srgr2     &= ~FPER(0xfff);
 344         regs->srgr1     &= ~FWID(0xff);
 345         switch (format) {
 346         case SND_SOC_DAIFMT_I2S:
 347         case SND_SOC_DAIFMT_LEFT_J:
 348                 regs->srgr2     |= FPER(framesize - 1);
 349                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 350                 break;
 351         case SND_SOC_DAIFMT_DSP_A:
 352         case SND_SOC_DAIFMT_DSP_B:
 353                 regs->srgr2     |= FPER(framesize - 1);
 354                 regs->srgr1     |= FWID(0);
 355                 break;
 356         }
 357
 358         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 359         mcbsp->wlen = wlen;
 360         mcbsp->configured = 1;
 361
 362         return 0;
 363 }
 364
 365 /*
 366  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 367  * cache is initialized here
 368  */
 369 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 370                                       unsigned int fmt)
 371 {
 372         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 373         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 374         bool inv_fs = false;
 375
 376         if (mcbsp->configured)
 377                 return 0;
 378
 379         mcbsp->fmt = fmt;
 380         memset(regs, 0, sizeof(*regs));
 381         /* Generic McBSP register settings */
 382         regs->spcr2     |= XINTM(3) | FREE;
 383         regs->spcr1     |= RINTM(3);
 384         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
 385         if (!mcbsp->pdata->has_ccr) {
 386                 regs->rcr2      |= RFIG;
 387                 regs->xcr2      |= XFIG;
 388         }
 389
 390         /* Configure XCCR/RCCR only for revisions which have ccr registers */
 391         if (mcbsp->pdata->has_ccr) {
 392                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 393                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 394         }
 395
 396         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 397         case SND_SOC_DAIFMT_I2S:
 398                 /* 1-bit data delay */
 399                 regs->rcr2      |= RDATDLY(1);
 400                 regs->xcr2      |= XDATDLY(1);
 401                 break;
 402         case SND_SOC_DAIFMT_LEFT_J:
 403                 /* 0-bit data delay */
 404                 regs->rcr2      |= RDATDLY(0);
 405                 regs->xcr2      |= XDATDLY(0);
 406                 regs->spcr1     |= RJUST(2);
 407                 /* Invert FS polarity configuration */
 408                 inv_fs = true;
 409                 break;
 410         case SND_SOC_DAIFMT_DSP_A:
 411                 /* 1-bit data delay */
 412                 regs->rcr2      |= RDATDLY(1);
 413                 regs->xcr2      |= XDATDLY(1);
 414                 /* Invert FS polarity configuration */
 415                 inv_fs = true;
 416                 break;
 417         case SND_SOC_DAIFMT_DSP_B:
 418                 /* 0-bit data delay */
 419                 regs->rcr2      |= RDATDLY(0);
 420                 regs->xcr2      |= XDATDLY(0);
 421                 /* Invert FS polarity configuration */
 422                 inv_fs = true;
 423                 break;
 424         default:
 425                 /* Unsupported data format */
 426                 return -EINVAL;
 427         }
 428
 429         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 430         case SND_SOC_DAIFMT_CBS_CFS:
 431                 /* McBSP master. Set FS and bit clocks as outputs */
 432                 regs->pcr0      |= FSXM | FSRM |
 433                                    CLKXM | CLKRM;
 434                 /* Sample rate generator drives the FS */
 435                 regs->srgr2     |= FSGM;
 436                 break;
 437         case SND_SOC_DAIFMT_CBM_CFM:
 438                 /* McBSP slave */
 439                 break;
 440         default:
 441                 /* Unsupported master/slave configuration */
 442                 return -EINVAL;
 443         }
 444
 445         /* Set bit clock (CLKX/CLKR) and FS polarities */
 446         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 447         case SND_SOC_DAIFMT_NB_NF:
 448                 /*
 449                  * Normal BCLK + FS.
 450                  * FS active low. TX data driven on falling edge of bit clock
 451                  * and RX data sampled on rising edge of bit clock.
 452                  */
 453                 regs->pcr0      |= FSXP | FSRP |
 454                                    CLKXP | CLKRP;
 455                 break;
 456         case SND_SOC_DAIFMT_NB_IF:
 457                 regs->pcr0      |= CLKXP | CLKRP;
 458                 break;
 459         case SND_SOC_DAIFMT_IB_NF:
 460                 regs->pcr0      |= FSXP | FSRP;
 461                 break;
 462         case SND_SOC_DAIFMT_IB_IF:
 463                 break;
 464         default:
 465                 return -EINVAL;
 466         }
 467         if (inv_fs == true)
 468                 regs->pcr0 ^= FSXP | FSRP;
 469
 470         return 0;
 471 }
 472
 473 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 474                                      int div_id, int div)
 475 {
 476         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 477         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 478
 479         if (div_id != OMAP_MCBSP_CLKGDV)
 480                 return -ENODEV;
 481
 482         mcbsp->clk_div = div;
 483         regs->srgr1     &= ~CLKGDV(0xff);
 484         regs->srgr1     |= CLKGDV(div - 1);
 485
 486         return 0;
 487 }
 488
 489 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 490                                          int clk_id, unsigned int freq,
 491                                          int dir)
 492 {
 493         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 494         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 495         int err = 0;
 496
 497         if (mcbsp->active) {
 498                 if (freq == mcbsp->in_freq)
 499                         return 0;
 500                 else
 501                         return -EBUSY;
 502         }
 503
 504         mcbsp->in_freq = freq;
 505         regs->srgr2 &= ~CLKSM;
 506         regs->pcr0 &= ~SCLKME;
 507
 508         switch (clk_id) {
 509         case OMAP_MCBSP_SYSCLK_CLK:
 510                 regs->srgr2     |= CLKSM;
 511                 break;
 512         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 513                 if (cpu_class_is_omap1()) {
 514                         err = -EINVAL;
 515                         break;
 516                 }
 517                 err = omap2_mcbsp_set_clks_src(mcbsp,
 518                                                MCBSP_CLKS_PRCM_SRC);
 519                 break;
 520         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 521                 if (cpu_class_is_omap1()) {
 522                         err = 0;
 523                         break;
 524                 }
 525                 err = omap2_mcbsp_set_clks_src(mcbsp,
 526                                                MCBSP_CLKS_PAD_SRC);
 527                 break;
 528
 529         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 530                 regs->srgr2     |= CLKSM;
 531         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 532                 regs->pcr0      |= SCLKME;
 533                 break;
 534         default:
 535                 err = -ENODEV;
 536         }
 537
 538         return err;
 539 }
 540
 541 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 542         .startup        = omap_mcbsp_dai_startup,
 543         .shutdown       = omap_mcbsp_dai_shutdown,
 544         .trigger        = omap_mcbsp_dai_trigger,
 545         .delay          = omap_mcbsp_dai_delay,
 546         .hw_params      = omap_mcbsp_dai_hw_params,
 547         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 548         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 549         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 550 };
 551
 552 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 553 {
 554         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 555
 556         pm_runtime_enable(mcbsp->dev);
 557
 558         return 0;
 559 }
 560
 561 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 562 {
 563         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 564
 565         pm_runtime_disable(mcbsp->dev);
 566
 567         return 0;
 568 }
 569
 570 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 571         .probe = omap_mcbsp_probe,
 572         .remove = omap_mcbsp_remove,
 573         .playback = {
 574                 .channels_min = 1,
 575                 .channels_max = 16,
 576                 .rates = OMAP_MCBSP_RATES,
 577                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 578         },
 579         .capture = {
 580                 .channels_min = 1,
 581                 .channels_max = 16,
 582                 .rates = OMAP_MCBSP_RATES,
 583                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 584         },
 585         .ops = &mcbsp_dai_ops,
 586 };
 587
 588 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 589                         struct snd_ctl_elem_info *uinfo)
 590 {
 591         struct soc_mixer_control *mc =
 592                 (struct soc_mixer_control *)kcontrol->private_value;
 593         int max = mc->max;
 594         int min = mc->min;
 595
 596         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 597         uinfo->count = 1;
 598         uinfo->value.integer.min = min;
 599         uinfo->value.integer.max = max;
 600         return 0;
 601 }
 602
 603 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel)                           \
 604 static int                                                              \
 605 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 606                                         struct snd_ctl_elem_value *uc)  \
 607 {                                                                       \
 608         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 609         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 610         struct soc_mixer_control *mc =                                  \
 611                 (struct soc_mixer_control *)kc->private_value;          \
 612         int max = mc->max;                                              \
 613         int min = mc->min;                                              \
 614         int val = uc->value.integer.value[0];                           \
 615                                                                         \
 616         if (val < min || val > max)                                     \
 617                 return -EINVAL;                                         \
 618                                                                         \
 619         /* OMAP McBSP implementation uses index values 0..4 */          \
 620         return omap_st_set_chgain(mcbsp, channel, val);                 \
 621 }                                                                       \
 622                                                                         \
 623 static int                                                              \
 624 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 625                                         struct snd_ctl_elem_value *uc)  \
 626 {                                                                       \
 627         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 628         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 629         s16 chgain;                                                     \
 630                                                                         \
 631         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 632                 return -EAGAIN;                                         \
 633                                                                         \
 634         uc->value.integer.value[0] = chgain;                            \
 635         return 0;                                                       \
 636 }
 637
 638 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
 639 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
 640
 641 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 642                                 struct snd_ctl_elem_value *ucontrol)
 643 {
 644         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 645         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 646         u8 value = ucontrol->value.integer.value[0];
 647
 648         if (value == omap_st_is_enabled(mcbsp))
 649                 return 0;
 650
 651         if (value)
 652                 omap_st_enable(mcbsp);
 653         else
 654                 omap_st_disable(mcbsp);
 655
 656         return 1;
 657 }
 658
 659 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 660                                 struct snd_ctl_elem_value *ucontrol)
 661 {
 662         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 663         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 664
 665         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 666         return 0;
 667 }
 668
 669 #define OMAP_MCBSP_ST_CONTROLS(port)                                      \
 670 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
 671 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0,              \
 672                omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),           \
 673 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
 674                               -32768, 32767,                              \
 675                               omap_mcbsp_get_st_ch0_volume,               \
 676                               omap_mcbsp_set_st_ch0_volume),              \
 677 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
 678                               -32768, 32767,                              \
 679                               omap_mcbsp_get_st_ch1_volume,               \
 680                               omap_mcbsp_set_st_ch1_volume),              \
 681 }
 682
 683 OMAP_MCBSP_ST_CONTROLS(2);
 684 OMAP_MCBSP_ST_CONTROLS(3);
 685
 686 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 687 {
 688         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 689         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 690
 691         if (!mcbsp->st_data) {
 692                 dev_warn(mcbsp->dev, "No sidetone data for port\n");
 693                 return 0;
 694         }
 695
 696         switch (mcbsp->id) {
 697         case 2: /* McBSP 2 */
 698                 return snd_soc_add_dai_controls(cpu_dai,
 699                                         omap_mcbsp2_st_controls,
 700                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 701         case 3: /* McBSP 3 */
 702                 return snd_soc_add_dai_controls(cpu_dai,
 703                                         omap_mcbsp3_st_controls,
 704                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 705         default:
 706                 break;
 707         }
 708
 709         return -EINVAL;
 710 }
 711 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 712
 713 static struct omap_mcbsp_platform_data omap2420_pdata = {
 714         .reg_step = 4,
 715         .reg_size = 2,
 716 };
 717
 718 static struct omap_mcbsp_platform_data omap2430_pdata = {
 719         .reg_step = 4,
 720         .reg_size = 4,
 721         .has_ccr = true,
 722 };
 723
 724 static struct omap_mcbsp_platform_data omap3_pdata = {
 725         .reg_step = 4,
 726         .reg_size = 4,
 727         .has_ccr = true,
 728         .has_wakeup = true,
 729 };
 730
 731 static struct omap_mcbsp_platform_data omap4_pdata = {
 732         .reg_step = 4,
 733         .reg_size = 4,
 734         .has_ccr = true,
 735         .has_wakeup = true,
 736 };
 737
 738 static const struct of_device_id omap_mcbsp_of_match[] = {
 739         {
 740                 .compatible = "ti,omap2420-mcbsp",
 741                 .data = &omap2420_pdata,
 742         },
 743         {
 744                 .compatible = "ti,omap2430-mcbsp",
 745                 .data = &omap2430_pdata,
 746         },
 747         {
 748                 .compatible = "ti,omap3-mcbsp",
 749                 .data = &omap3_pdata,
 750         },
 751         {
 752                 .compatible = "ti,omap4-mcbsp",
 753                 .data = &omap4_pdata,
 754         },
 755         { },
 756 };
 757 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
 758
 759 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 760 {
 761         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 762         struct omap_mcbsp *mcbsp;
 763         const struct of_device_id *match;
 764         int ret;
 765
 766         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
 767         if (match) {
 768                 struct device_node *node = pdev->dev.of_node;
 769                 int buffer_size;
 770
 771                 pdata = devm_kzalloc(&pdev->dev,
 772                                      sizeof(struct omap_mcbsp_platform_data),
 773                                      GFP_KERNEL);
 774                 if (!pdata)
 775                         return -ENOMEM;
 776
 777                 memcpy(pdata, match->data, sizeof(*pdata));
 778                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
 779                         pdata->buffer_size = buffer_size;
 780         } else if (!pdata) {
 781                 dev_err(&pdev->dev, "missing platform data.\n");
 782                 return -EINVAL;
 783         }
 784         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 785         if (!mcbsp)
 786                 return -ENOMEM;
 787
 788         mcbsp->id = pdev->id;
 789         mcbsp->pdata = pdata;
 790         mcbsp->dev = &pdev->dev;
 791         platform_set_drvdata(pdev, mcbsp);
 792
 793         ret = omap_mcbsp_init(pdev);
 794         if (!ret)
 795                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 796
 797         return ret;
 798 }
 799
 800 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 801 {
 802         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 803
 804         snd_soc_unregister_dai(&pdev->dev);
 805
 806         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 807                 mcbsp->pdata->ops->free(mcbsp->id);
 808
 809         omap_mcbsp_sysfs_remove(mcbsp);
 810
 811         clk_put(mcbsp->fclk);
 812
 813         platform_set_drvdata(pdev, NULL);
 814
 815         return 0;
 816 }
 817
 818 static struct platform_driver asoc_mcbsp_driver = {
 819         .driver = {
 820                         .name = "omap-mcbsp",
 821                         .owner = THIS_MODULE,
 822                         .of_match_table = omap_mcbsp_of_match,
 823         },
 824
 825         .probe = asoc_mcbsp_probe,
 826         .remove = __devexit_p(asoc_mcbsp_remove),
 827 };
 828
 829 module_platform_driver(asoc_mcbsp_driver);
 830
 831 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 832 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 833 MODULE_LICENSE("GPL");
 834 MODULE_ALIAS("platform:omap-mcbsp");