2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/time.h>
29 #include <linux/fsl/mxs-dma.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <asm/mach-types.h>
39 #define MXS_SET_ADDR 0x4
40 #define MXS_CLR_ADDR 0x8
42 static struct mxs_saif *mxs_saif[2];
45 * SAIF is a little different with other normal SOC DAIs on clock using.
47 * For MXS, two SAIF modules are instantiated on-chip.
48 * Each SAIF has a set of clock pins and can be operating in master
49 * mode simultaneously if they are connected to different off-chip codecs.
50 * Also, one of the two SAIFs can master or drive the clock pins while the
51 * other SAIF, in slave mode, receives clocking from the master SAIF.
52 * This also means that both SAIFs must operate at the same sample rate.
54 * We abstract this as each saif has a master, the master could be
55 * himself or other saifs. In the generic saif driver, saif does not need
56 * to know the different clkmux. Saif only needs to know who is his master
57 * and operating his master to generate the proper clock rate for him.
58 * The master id is provided in mach-specific layer according to different
62 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
63 int clk_id, unsigned int freq, int dir)
65 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
78 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
79 * is provided by other SAIF, we provide a interface here to get its master
81 * Note that the master could be himself.
83 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
85 return mxs_saif[saif->master_id];
89 * Set SAIF clock and MCLK
91 static int mxs_saif_set_clk(struct mxs_saif *saif,
97 struct mxs_saif *master_saif;
99 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
101 /* Set master saif to generate proper clock */
102 master_saif = mxs_saif_get_master(saif);
106 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
108 /* Checking if can playback and capture simutaneously */
109 if (master_saif->ongoing && rate != master_saif->cur_rate) {
111 "can not change clock, master saif%d(rate %d) is ongoing\n",
112 master_saif->id, master_saif->cur_rate);
116 scr = __raw_readl(master_saif->base + SAIF_CTRL);
117 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
118 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
123 * The SAIF clock should be either 384*fs or 512*fs.
124 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
125 * For 32x mclk, set saif clk as 512*fs.
126 * For 48x mclk, set saif clk as 384*fs.
128 * If MCLK is not used, we just set saif clk to 512*fs.
130 clk_prepare_enable(master_saif->clk);
132 if (master_saif->mclk_in_use) {
133 if (mclk % 32 == 0) {
134 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
135 ret = clk_set_rate(master_saif->clk, 512 * rate);
136 } else if (mclk % 48 == 0) {
137 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
138 ret = clk_set_rate(master_saif->clk, 384 * rate);
140 /* SAIF MCLK should be either 32x or 48x */
141 clk_disable_unprepare(master_saif->clk);
145 ret = clk_set_rate(master_saif->clk, 512 * rate);
146 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
149 clk_disable_unprepare(master_saif->clk);
154 master_saif->cur_rate = rate;
156 if (!master_saif->mclk_in_use) {
157 __raw_writel(scr, master_saif->base + SAIF_CTRL);
162 * Program the over-sample rate for MCLK output
164 * The available MCLK range is 32x, 48x... 512x. The rate
165 * could be from 8kHz to 192kH.
167 switch (mclk / rate) {
169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
172 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
175 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
178 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
181 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
184 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
187 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
190 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
193 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
199 __raw_writel(scr, master_saif->base + SAIF_CTRL);
205 * Put and disable MCLK.
207 int mxs_saif_put_mclk(unsigned int saif_id)
209 struct mxs_saif *saif = mxs_saif[saif_id];
215 stat = __raw_readl(saif->base + SAIF_STAT);
216 if (stat & BM_SAIF_STAT_BUSY) {
217 dev_err(saif->dev, "error: busy\n");
221 clk_disable_unprepare(saif->clk);
223 /* disable MCLK output */
224 __raw_writel(BM_SAIF_CTRL_CLKGATE,
225 saif->base + SAIF_CTRL + MXS_SET_ADDR);
226 __raw_writel(BM_SAIF_CTRL_RUN,
227 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
229 saif->mclk_in_use = 0;
232 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
235 * Get MCLK and set clock rate, then enable it
237 * This interface is used for codecs who are using MCLK provided
240 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
243 struct mxs_saif *saif = mxs_saif[saif_id];
246 struct mxs_saif *master_saif;
252 __raw_writel(BM_SAIF_CTRL_SFTRST,
253 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
255 /* FIXME: need clear clk gate for register r/w */
256 __raw_writel(BM_SAIF_CTRL_CLKGATE,
257 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
259 master_saif = mxs_saif_get_master(saif);
260 if (saif != master_saif) {
261 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
265 stat = __raw_readl(saif->base + SAIF_STAT);
266 if (stat & BM_SAIF_STAT_BUSY) {
267 dev_err(saif->dev, "error: busy\n");
271 saif->mclk_in_use = 1;
272 ret = mxs_saif_set_clk(saif, mclk, rate);
276 ret = clk_prepare_enable(saif->clk);
280 /* enable MCLK output */
281 __raw_writel(BM_SAIF_CTRL_RUN,
282 saif->base + SAIF_CTRL + MXS_SET_ADDR);
286 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
289 * SAIF DAI format configuration.
290 * Should only be called when port is inactive.
292 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
296 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
298 stat = __raw_readl(saif->base + SAIF_STAT);
299 if (stat & BM_SAIF_STAT_BUSY) {
300 dev_err(cpu_dai->dev, "error: busy\n");
304 scr0 = __raw_readl(saif->base + SAIF_CTRL);
305 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
306 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
310 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
311 case SND_SOC_DAIFMT_I2S:
312 /* data frame low 1clk before data */
313 scr |= BM_SAIF_CTRL_DELAY;
314 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
316 case SND_SOC_DAIFMT_LEFT_J:
317 /* data frame high with data */
318 scr &= ~BM_SAIF_CTRL_DELAY;
319 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
320 scr &= ~BM_SAIF_CTRL_JUSTIFY;
326 /* DAI clock inversion */
327 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
328 case SND_SOC_DAIFMT_IB_IF:
329 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
330 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
332 case SND_SOC_DAIFMT_IB_NF:
333 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
334 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
336 case SND_SOC_DAIFMT_NB_IF:
337 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
338 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
340 case SND_SOC_DAIFMT_NB_NF:
341 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
342 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
347 * Note: We simply just support master mode since SAIF TX can only
349 * Here the master is relative to codec side.
350 * Saif internally could be slave when working on EXTMASTER mode.
351 * We just hide this to machine driver.
353 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
354 case SND_SOC_DAIFMT_CBS_CFS:
355 if (saif->id == saif->master_id)
356 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
358 scr |= BM_SAIF_CTRL_SLAVE_MODE;
360 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
369 static int mxs_saif_startup(struct snd_pcm_substream *substream,
370 struct snd_soc_dai *cpu_dai)
372 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
374 /* clear error status to 0 for each re-open */
375 saif->fifo_underrun = 0;
376 saif->fifo_overrun = 0;
378 /* Clear Reset for normal operations */
379 __raw_writel(BM_SAIF_CTRL_SFTRST,
380 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
382 /* clear clock gate */
383 __raw_writel(BM_SAIF_CTRL_CLKGATE,
384 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
390 * Should only be called when port is inactive.
391 * although can be called multiple times by upper layers.
393 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
394 struct snd_pcm_hw_params *params,
395 struct snd_soc_dai *cpu_dai)
397 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
398 struct mxs_saif *master_saif;
402 master_saif = mxs_saif_get_master(saif);
406 /* mclk should already be set */
407 if (!saif->mclk && saif->mclk_in_use) {
408 dev_err(cpu_dai->dev, "set mclk first\n");
412 stat = __raw_readl(saif->base + SAIF_STAT);
413 if (stat & BM_SAIF_STAT_BUSY) {
414 dev_err(cpu_dai->dev, "error: busy\n");
419 * Set saif clk based on sample rate.
420 * If mclk is used, we also set mclk, if not, saif->mclk is
421 * default 0, means not used.
423 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
425 dev_err(cpu_dai->dev, "unable to get proper clk\n");
429 /* prepare clk in hw_param, enable in trigger */
430 clk_prepare(saif->clk);
431 if (saif != master_saif) {
433 * Set an initial clock rate for the saif internal logic to work
434 * properly. This is important when working in EXTMASTER mode
435 * that uses the other saif's BITCLK&LRCLK but it still needs a
436 * basic clock which should be fast enough for the internal
439 clk_enable(saif->clk);
440 ret = clk_set_rate(saif->clk, 24000000);
441 clk_disable(saif->clk);
445 clk_prepare(master_saif->clk);
448 scr = __raw_readl(saif->base + SAIF_CTRL);
450 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
451 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
452 switch (params_format(params)) {
453 case SNDRV_PCM_FORMAT_S16_LE:
454 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
456 case SNDRV_PCM_FORMAT_S20_3LE:
457 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
458 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
460 case SNDRV_PCM_FORMAT_S24_LE:
461 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
462 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
469 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
471 scr &= ~BM_SAIF_CTRL_READ_MODE;
474 scr |= BM_SAIF_CTRL_READ_MODE;
477 __raw_writel(scr, saif->base + SAIF_CTRL);
481 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
482 struct snd_soc_dai *cpu_dai)
484 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
486 /* enable FIFO error irqs */
487 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
488 saif->base + SAIF_CTRL + MXS_SET_ADDR);
493 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
494 struct snd_soc_dai *cpu_dai)
496 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
497 struct mxs_saif *master_saif;
500 master_saif = mxs_saif_get_master(saif);
505 case SNDRV_PCM_TRIGGER_START:
506 case SNDRV_PCM_TRIGGER_RESUME:
507 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
508 dev_dbg(cpu_dai->dev, "start\n");
510 clk_enable(master_saif->clk);
511 if (!master_saif->mclk_in_use)
512 __raw_writel(BM_SAIF_CTRL_RUN,
513 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
516 * If the saif's master is not himself, we also need to enable
517 * itself clk for its internal basic logic to work.
519 if (saif != master_saif) {
520 clk_enable(saif->clk);
521 __raw_writel(BM_SAIF_CTRL_RUN,
522 saif->base + SAIF_CTRL + MXS_SET_ADDR);
525 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
527 * write data to saif data register to trigger
529 * For 24-bit format the 32-bit FIFO register stores
530 * only one channel, so we need to write twice.
531 * This is also safe for the other non 24-bit formats.
533 __raw_writel(0, saif->base + SAIF_DATA);
534 __raw_writel(0, saif->base + SAIF_DATA);
537 * read data from saif data register to trigger
539 * For 24-bit format the 32-bit FIFO register stores
540 * only one channel, so we need to read twice.
541 * This is also safe for the other non 24-bit formats.
543 __raw_readl(saif->base + SAIF_DATA);
544 __raw_readl(saif->base + SAIF_DATA);
547 master_saif->ongoing = 1;
549 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
550 __raw_readl(saif->base + SAIF_CTRL),
551 __raw_readl(saif->base + SAIF_STAT));
553 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
554 __raw_readl(master_saif->base + SAIF_CTRL),
555 __raw_readl(master_saif->base + SAIF_STAT));
557 case SNDRV_PCM_TRIGGER_SUSPEND:
558 case SNDRV_PCM_TRIGGER_STOP:
559 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
560 dev_dbg(cpu_dai->dev, "stop\n");
562 /* wait a while for the current sample to complete */
563 delay = USEC_PER_SEC / master_saif->cur_rate;
565 if (!master_saif->mclk_in_use) {
566 __raw_writel(BM_SAIF_CTRL_RUN,
567 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
570 clk_disable(master_saif->clk);
572 if (saif != master_saif) {
573 __raw_writel(BM_SAIF_CTRL_RUN,
574 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
576 clk_disable(saif->clk);
579 master_saif->ongoing = 0;
589 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
590 #define MXS_SAIF_FORMATS \
591 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
592 SNDRV_PCM_FMTBIT_S24_LE)
594 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
595 .startup = mxs_saif_startup,
596 .trigger = mxs_saif_trigger,
597 .prepare = mxs_saif_prepare,
598 .hw_params = mxs_saif_hw_params,
599 .set_sysclk = mxs_saif_set_dai_sysclk,
600 .set_fmt = mxs_saif_set_dai_fmt,
603 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
605 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
607 snd_soc_dai_set_drvdata(dai, saif);
608 dai->playback_dma_data = &saif->dma_param;
609 dai->capture_dma_data = &saif->dma_param;
614 static struct snd_soc_dai_driver mxs_saif_dai = {
616 .probe = mxs_saif_dai_probe,
620 .rates = MXS_SAIF_RATES,
621 .formats = MXS_SAIF_FORMATS,
626 .rates = MXS_SAIF_RATES,
627 .formats = MXS_SAIF_FORMATS,
629 .ops = &mxs_saif_dai_ops,
632 static const struct snd_soc_component_driver mxs_saif_component = {
636 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
638 struct mxs_saif *saif = dev_id;
641 stat = __raw_readl(saif->base + SAIF_STAT);
642 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
643 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
646 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
647 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
648 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
649 saif->base + SAIF_STAT + MXS_CLR_ADDR);
652 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
653 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
654 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
655 saif->base + SAIF_STAT + MXS_CLR_ADDR);
658 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
659 __raw_readl(saif->base + SAIF_CTRL),
660 __raw_readl(saif->base + SAIF_STAT));
665 static int mxs_saif_probe(struct platform_device *pdev)
667 struct device_node *np = pdev->dev.of_node;
668 struct resource *iores, *dmares;
669 struct mxs_saif *saif;
670 struct pinctrl *pinctrl;
672 struct device_node *master;
677 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
681 ret = of_alias_get_id(np, "saif");
688 * If there is no "fsl,saif-master" phandle, it's a saif
689 * master. Otherwise, it's a slave and its phandle points
692 master = of_parse_phandle(np, "fsl,saif-master", 0);
694 saif->master_id = saif->id;
696 ret = of_alias_get_id(master, "saif");
700 saif->master_id = ret;
703 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
704 dev_err(&pdev->dev, "get wrong master id\n");
708 mxs_saif[saif->id] = saif;
710 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
711 if (IS_ERR(pinctrl)) {
712 ret = PTR_ERR(pinctrl);
716 saif->clk = devm_clk_get(&pdev->dev, NULL);
717 if (IS_ERR(saif->clk)) {
718 ret = PTR_ERR(saif->clk);
719 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
724 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
726 saif->base = devm_ioremap_resource(&pdev->dev, iores);
727 if (IS_ERR(saif->base))
728 return PTR_ERR(saif->base);
730 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
733 * TODO: This is a temporary solution and should be changed
734 * to use generic DMA binding later when the helplers get in.
736 ret = of_property_read_u32(np, "fsl,saif-dma-channel",
737 &saif->dma_param.chan_num);
739 dev_err(&pdev->dev, "failed to get dma channel\n");
743 saif->dma_param.chan_num = dmares->start;
746 saif->irq = platform_get_irq(pdev, 0);
749 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
754 saif->dev = &pdev->dev;
755 ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0,
758 dev_err(&pdev->dev, "failed to request irq\n");
762 saif->dma_param.dma_data.chan_irq = platform_get_irq(pdev, 1);
763 if (saif->dma_param.dma_data.chan_irq < 0) {
764 ret = saif->dma_param.dma_data.chan_irq;
765 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
770 platform_set_drvdata(pdev, saif);
772 ret = snd_soc_register_component(&pdev->dev, &mxs_saif_component,
775 dev_err(&pdev->dev, "register DAI failed\n");
779 ret = mxs_pcm_platform_register(&pdev->dev);
781 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
782 goto failed_pdev_alloc;
788 snd_soc_unregister_component(&pdev->dev);
793 static int mxs_saif_remove(struct platform_device *pdev)
795 mxs_pcm_platform_unregister(&pdev->dev);
796 snd_soc_unregister_component(&pdev->dev);
801 static const struct of_device_id mxs_saif_dt_ids[] = {
802 { .compatible = "fsl,imx28-saif", },
805 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
807 static struct platform_driver mxs_saif_driver = {
808 .probe = mxs_saif_probe,
809 .remove = mxs_saif_remove,
813 .owner = THIS_MODULE,
814 .of_match_table = mxs_saif_dt_ids,
818 module_platform_driver(mxs_saif_driver);
820 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
821 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
822 MODULE_LICENSE("GPL");
823 MODULE_ALIAS("platform:mxs-saif");