1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2020 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
6 #include <linux/bitfield.h>
8 #include <sound/pcm_params.h>
10 #include <sound/soc-dai.h>
14 #define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
15 #define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
16 #define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
17 #define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
18 #define AIU_RST_SOFT_I2S_FAST BIT(0)
20 #define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2)
21 #define AIU_I2S_MISC_HOLD_EN BIT(2)
22 #define AIU_CLK_CTRL_I2S_DIV_EN BIT(0)
23 #define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2)
24 #define AIU_CLK_CTRL_AOCLK_INVERT BIT(6)
25 #define AIU_CLK_CTRL_LRCLK_INVERT BIT(7)
26 #define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8)
27 #define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6)
28 #define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0)
29 #define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0)
31 static void aiu_encoder_i2s_divider_enable(struct snd_soc_component *component,
34 snd_soc_component_update_bits(component, AIU_CLK_CTRL,
35 AIU_CLK_CTRL_I2S_DIV_EN,
36 enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
39 static void aiu_encoder_i2s_hold(struct snd_soc_component *component,
42 snd_soc_component_update_bits(component, AIU_I2S_MISC,
44 enable ? AIU_I2S_MISC_HOLD_EN : 0);
47 static int aiu_encoder_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
48 struct snd_soc_dai *dai)
50 struct snd_soc_component *component = dai->component;
53 case SNDRV_PCM_TRIGGER_START:
54 case SNDRV_PCM_TRIGGER_RESUME:
55 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
56 aiu_encoder_i2s_hold(component, false);
59 case SNDRV_PCM_TRIGGER_STOP:
60 case SNDRV_PCM_TRIGGER_SUSPEND:
61 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
62 aiu_encoder_i2s_hold(component, true);
70 static int aiu_encoder_i2s_setup_desc(struct snd_soc_component *component,
71 struct snd_pcm_hw_params *params)
73 /* Always operate in split (classic interleaved) mode */
74 unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT;
77 /* Reset required to update the pipeline */
78 snd_soc_component_write(component, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
79 snd_soc_component_read(component, AIU_I2S_SYNC, &val);
81 switch (params_physical_width(params)) {
82 case 16: /* Nothing to do */
86 desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT |
87 AIU_I2S_SOURCE_DESC_MODE_32BIT);
94 switch (params_channels(params)) {
95 case 2: /* Nothing to do */
98 desc |= AIU_I2S_SOURCE_DESC_MODE_8CH;
104 snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC,
105 AIU_I2S_SOURCE_DESC_MODE_8CH |
106 AIU_I2S_SOURCE_DESC_MODE_24BIT |
107 AIU_I2S_SOURCE_DESC_MODE_32BIT |
108 AIU_I2S_SOURCE_DESC_MODE_SPLIT,
114 static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component,
115 struct snd_pcm_hw_params *params)
117 struct aiu *aiu = snd_soc_component_get_drvdata(component);
118 unsigned int srate = params_rate(params);
121 /* Get the oversampling factor */
122 fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate);
127 /* Send data MSB first */
128 snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG,
129 AIU_I2S_DAC_CFG_MSB_FIRST,
130 AIU_I2S_DAC_CFG_MSB_FIRST);
132 /* Set bclk to lrlck ratio */
133 snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL,
134 AIU_CODEC_DAC_LRCLK_CTRL_DIV,
135 FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV,
138 /* Use CLK_MORE for mclk to bclk divider */
139 snd_soc_component_update_bits(component, AIU_CLK_CTRL,
140 AIU_CLK_CTRL_I2S_DIV, 0);
143 * NOTE: this HW is odd.
144 * In most configuration, the i2s divider is 'mclk / blck'.
145 * However, in 16 bits - 8ch mode, this factor needs to be
146 * increased by 50% to get the correct output rate.
150 if (params_width(params) == 16 && params_channels(params) == 8) {
152 dev_err(component->dev,
153 "Cannot increase i2s divider by 50%%\n");
159 snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
160 AIU_CLK_CTRL_MORE_I2S_DIV,
161 FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
164 /* Make sure amclk is used for HDMI i2s as well */
165 snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
166 AIU_CLK_CTRL_MORE_HDMI_AMCLK,
167 AIU_CLK_CTRL_MORE_HDMI_AMCLK);
172 static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream,
173 struct snd_pcm_hw_params *params,
174 struct snd_soc_dai *dai)
176 struct snd_soc_component *component = dai->component;
179 /* Disable the clock while changing the settings */
180 aiu_encoder_i2s_divider_enable(component, false);
182 ret = aiu_encoder_i2s_setup_desc(component, params);
184 dev_err(dai->dev, "setting i2s desc failed\n");
188 ret = aiu_encoder_i2s_set_clocks(component, params);
190 dev_err(dai->dev, "setting i2s clocks failed\n");
194 aiu_encoder_i2s_divider_enable(component, true);
199 static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream,
200 struct snd_soc_dai *dai)
202 struct snd_soc_component *component = dai->component;
204 aiu_encoder_i2s_divider_enable(component, false);
209 static int aiu_encoder_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
211 struct snd_soc_component *component = dai->component;
212 unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK;
213 unsigned int val = 0;
216 /* Only CPU Master / Codec Slave supported ATM */
217 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
220 if (inv == SND_SOC_DAIFMT_NB_IF ||
221 inv == SND_SOC_DAIFMT_IB_IF)
222 val |= AIU_CLK_CTRL_LRCLK_INVERT;
224 if (inv == SND_SOC_DAIFMT_IB_NF ||
225 inv == SND_SOC_DAIFMT_IB_IF)
226 val |= AIU_CLK_CTRL_AOCLK_INVERT;
229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
230 case SND_SOC_DAIFMT_I2S:
231 /* Invert sample clock for i2s */
232 val ^= AIU_CLK_CTRL_LRCLK_INVERT;
235 case SND_SOC_DAIFMT_LEFT_J:
242 val |= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew);
243 snd_soc_component_update_bits(component, AIU_CLK_CTRL,
244 AIU_CLK_CTRL_LRCLK_INVERT |
245 AIU_CLK_CTRL_AOCLK_INVERT |
246 AIU_CLK_CTRL_LRCLK_SKEW,
252 static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
253 unsigned int freq, int dir)
255 struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
258 if (WARN_ON(clk_id != 0))
261 if (dir == SND_SOC_CLOCK_IN)
264 ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq);
266 dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
271 static const unsigned int hw_channels[] = {2, 8};
272 static const struct snd_pcm_hw_constraint_list hw_channel_constraints = {
274 .count = ARRAY_SIZE(hw_channels),
278 static int aiu_encoder_i2s_startup(struct snd_pcm_substream *substream,
279 struct snd_soc_dai *dai)
281 struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
284 /* Make sure the encoder gets either 2 or 8 channels */
285 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
286 SNDRV_PCM_HW_PARAM_CHANNELS,
287 &hw_channel_constraints);
289 dev_err(dai->dev, "adding channels constraints failed\n");
293 ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks);
295 dev_err(dai->dev, "failed to enable i2s clocks\n");
300 static void aiu_encoder_i2s_shutdown(struct snd_pcm_substream *substream,
301 struct snd_soc_dai *dai)
303 struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
305 clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks);
308 const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops = {
309 .trigger = aiu_encoder_i2s_trigger,
310 .hw_params = aiu_encoder_i2s_hw_params,
311 .hw_free = aiu_encoder_i2s_hw_free,
312 .set_fmt = aiu_encoder_i2s_set_fmt,
313 .set_sysclk = aiu_encoder_i2s_set_sysclk,
314 .startup = aiu_encoder_i2s_startup,
315 .shutdown = aiu_encoder_i2s_shutdown,