sound/soc/mediatek/mt8188/mt8188-afe-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek ALSA SoC AFE platform driver for 8188
   4  *
   5  * Copyright (c) 2022 MediaTek Inc.
   6  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
   7  *         Trevor Wu <trevor.wu@mediatek.com>
   8  *         Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
   9  */
  10
  11 #include <linux/arm-smccc.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/module.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/reset.h>
  21 #include <sound/pcm_params.h>
  22 #include "mt8188-afe-common.h"
  23 #include "mt8188-afe-clk.h"
  24 #include "mt8188-reg.h"
  25 #include "../common/mtk-afe-platform-driver.h"
  26 #include "../common/mtk-afe-fe-dai.h"
  27
  28 #define MT8188_MEMIF_BUFFER_BYTES_ALIGN  (0x40)
  29 #define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)
  30
  31 #define MEMIF_AXI_MINLEN 9 /* register default value */
  32
  33 struct mtk_dai_memif_priv {
  34         unsigned int asys_timing_sel;
  35         unsigned int fs_timing;
  36 };
  37
  38 static const struct snd_pcm_hardware mt8188_afe_hardware = {
  39         .info = SNDRV_PCM_INFO_MMAP |
  40                 SNDRV_PCM_INFO_INTERLEAVED |
  41                 SNDRV_PCM_INFO_MMAP_VALID,
  42         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  43                    SNDRV_PCM_FMTBIT_S24_LE |
  44                    SNDRV_PCM_FMTBIT_S32_LE,
  45         .period_bytes_min = 64,
  46         .period_bytes_max = 256 * 1024,
  47         .periods_min = 2,
  48         .periods_max = 256,
  49         .buffer_bytes_max = 256 * 2 * 1024,
  50 };
  51
  52 struct mt8188_afe_rate {
  53         unsigned int rate;
  54         unsigned int reg_value;
  55 };
  56
  57 static const struct mt8188_afe_rate mt8188_afe_rates[] = {
  58         { .rate = 8000, .reg_value = 0, },
  59         { .rate = 12000, .reg_value = 1, },
  60         { .rate = 16000, .reg_value = 2, },
  61         { .rate = 24000, .reg_value = 3, },
  62         { .rate = 32000, .reg_value = 4, },
  63         { .rate = 48000, .reg_value = 5, },
  64         { .rate = 96000, .reg_value = 6, },
  65         { .rate = 192000, .reg_value = 7, },
  66         { .rate = 384000, .reg_value = 8, },
  67         { .rate = 7350, .reg_value = 16, },
  68         { .rate = 11025, .reg_value = 17, },
  69         { .rate = 14700, .reg_value = 18, },
  70         { .rate = 22050, .reg_value = 19, },
  71         { .rate = 29400, .reg_value = 20, },
  72         { .rate = 44100, .reg_value = 21, },
  73         { .rate = 88200, .reg_value = 22, },
  74         { .rate = 176400, .reg_value = 23, },
  75         { .rate = 352800, .reg_value = 24, },
  76 };
  77
  78 int mt8188_afe_fs_timing(unsigned int rate)
  79 {
  80         int i;
  81
  82         for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++)
  83                 if (mt8188_afe_rates[i].rate == rate)
  84                         return mt8188_afe_rates[i].reg_value;
  85
  86         return -EINVAL;
  87 }
  88
  89 static int mt8188_memif_fs(struct snd_pcm_substream *substream,
  90                            unsigned int rate)
  91 {
  92         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  93         struct snd_soc_component *component = NULL;
  94         struct mtk_base_afe *afe = NULL;
  95         struct mt8188_afe_private *afe_priv = NULL;
  96         struct mtk_base_afe_memif *memif = NULL;
  97         struct mtk_dai_memif_priv *memif_priv = NULL;
  98         int fs = mt8188_afe_fs_timing(rate);
  99         int id = asoc_rtd_to_cpu(rtd, 0)->id;
 100
 101         if (id < 0)
 102                 return -EINVAL;
 103
 104         component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
 105         if (!component)
 106                 return -EINVAL;
 107
 108         afe = snd_soc_component_get_drvdata(component);
 109         memif = &afe->memif[id];
 110
 111         switch (memif->data->id) {
 112         case MT8188_AFE_MEMIF_DL10:
 113                 fs = MT8188_ETDM_OUT3_1X_EN;
 114                 break;
 115         case MT8188_AFE_MEMIF_UL8:
 116                 fs = MT8188_ETDM_IN1_NX_EN;
 117                 break;
 118         case MT8188_AFE_MEMIF_UL3:
 119                 fs = MT8188_ETDM_IN2_NX_EN;
 120                 break;
 121         default:
 122                 afe_priv = afe->platform_priv;
 123                 memif_priv = afe_priv->dai_priv[id];
 124                 if (memif_priv->fs_timing)
 125                         fs = memif_priv->fs_timing;
 126                 break;
 127         }
 128
 129         return fs;
 130 }
 131
 132 static int mt8188_irq_fs(struct snd_pcm_substream *substream,
 133                          unsigned int rate)
 134 {
 135         int fs = mt8188_memif_fs(substream, rate);
 136
 137         switch (fs) {
 138         case MT8188_ETDM_IN1_NX_EN:
 139                 fs = MT8188_ETDM_IN1_1X_EN;
 140                 break;
 141         case MT8188_ETDM_IN2_NX_EN:
 142                 fs = MT8188_ETDM_IN2_1X_EN;
 143                 break;
 144         default:
 145                 break;
 146         }
 147
 148         return fs;
 149 }
 150
 151 enum {
 152         MT8188_AFE_CM0,
 153         MT8188_AFE_CM1,
 154         MT8188_AFE_CM2,
 155         MT8188_AFE_CM_NUM,
 156 };
 157
 158 struct mt8188_afe_channel_merge {
 159         int id;
 160         int reg;
 161         unsigned int sel_shift;
 162         unsigned int sel_maskbit;
 163         unsigned int sel_default;
 164         unsigned int ch_num_shift;
 165         unsigned int ch_num_maskbit;
 166         unsigned int en_shift;
 167         unsigned int en_maskbit;
 168         unsigned int update_cnt_shift;
 169         unsigned int update_cnt_maskbit;
 170         unsigned int update_cnt_default;
 171 };
 172
 173 static const struct mt8188_afe_channel_merge
 174         mt8188_afe_cm[MT8188_AFE_CM_NUM] = {
 175         [MT8188_AFE_CM0] = {
 176                 .id = MT8188_AFE_CM0,
 177                 .reg = AFE_CM0_CON,
 178                 .sel_shift = 30,
 179                 .sel_maskbit = 0x1,
 180                 .sel_default = 1,
 181                 .ch_num_shift = 2,
 182                 .ch_num_maskbit = 0x3f,
 183                 .en_shift = 0,
 184                 .en_maskbit = 0x1,
 185                 .update_cnt_shift = 16,
 186                 .update_cnt_maskbit = 0x1fff,
 187                 .update_cnt_default = 0x3,
 188         },
 189         [MT8188_AFE_CM1] = {
 190                 .id = MT8188_AFE_CM1,
 191                 .reg = AFE_CM1_CON,
 192                 .sel_shift = 30,
 193                 .sel_maskbit = 0x1,
 194                 .sel_default = 1,
 195                 .ch_num_shift = 2,
 196                 .ch_num_maskbit = 0x1f,
 197                 .en_shift = 0,
 198                 .en_maskbit = 0x1,
 199                 .update_cnt_shift = 16,
 200                 .update_cnt_maskbit = 0x1fff,
 201                 .update_cnt_default = 0x3,
 202         },
 203         [MT8188_AFE_CM2] = {
 204                 .id = MT8188_AFE_CM2,
 205                 .reg = AFE_CM2_CON,
 206                 .sel_shift = 30,
 207                 .sel_maskbit = 0x1,
 208                 .sel_default = 1,
 209                 .ch_num_shift = 2,
 210                 .ch_num_maskbit = 0x1f,
 211                 .en_shift = 0,
 212                 .en_maskbit = 0x1,
 213                 .update_cnt_shift = 16,
 214                 .update_cnt_maskbit = 0x1fff,
 215                 .update_cnt_default = 0x3,
 216         },
 217 };
 218
 219 static int mt8188_afe_memif_is_ul(int id)
 220 {
 221         if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END)
 222                 return 1;
 223         else
 224                 return 0;
 225 }
 226
 227 static const struct mt8188_afe_channel_merge *
 228         mt8188_afe_found_cm(struct snd_soc_dai *dai)
 229 {
 230         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 231         int id = -EINVAL;
 232
 233         if (mt8188_afe_memif_is_ul(dai->id) == 0)
 234                 return NULL;
 235
 236         switch (dai->id) {
 237         case MT8188_AFE_MEMIF_UL9:
 238                 id = MT8188_AFE_CM0;
 239                 break;
 240         case MT8188_AFE_MEMIF_UL2:
 241                 id = MT8188_AFE_CM1;
 242                 break;
 243         case MT8188_AFE_MEMIF_UL10:
 244                 id = MT8188_AFE_CM2;
 245                 break;
 246         default:
 247                 break;
 248         }
 249
 250         if (id < 0) {
 251                 dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id);
 252                 return NULL;
 253         }
 254
 255         return &mt8188_afe_cm[id];
 256 }
 257
 258 static int mt8188_afe_config_cm(struct mtk_base_afe *afe,
 259                                 const struct mt8188_afe_channel_merge *cm,
 260                                 unsigned int channels)
 261 {
 262         if (!cm)
 263                 return -EINVAL;
 264
 265         regmap_update_bits(afe->regmap,
 266                            cm->reg,
 267                            cm->sel_maskbit << cm->sel_shift,
 268                            cm->sel_default << cm->sel_shift);
 269
 270         regmap_update_bits(afe->regmap,
 271                            cm->reg,
 272                            cm->ch_num_maskbit << cm->ch_num_shift,
 273                            (channels - 1) << cm->ch_num_shift);
 274
 275         regmap_update_bits(afe->regmap,
 276                            cm->reg,
 277                            cm->update_cnt_maskbit << cm->update_cnt_shift,
 278                            cm->update_cnt_default << cm->update_cnt_shift);
 279
 280         return 0;
 281 }
 282
 283 static int mt8188_afe_enable_cm(struct mtk_base_afe *afe,
 284                                 const struct mt8188_afe_channel_merge *cm,
 285                                 bool enable)
 286 {
 287         if (!cm)
 288                 return -EINVAL;
 289
 290         regmap_update_bits(afe->regmap,
 291                            cm->reg,
 292                            cm->en_maskbit << cm->en_shift,
 293                            enable << cm->en_shift);
 294
 295         return 0;
 296 }
 297
 298 static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream,
 299                                  struct snd_soc_dai *dai)
 300 {
 301         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 302         struct snd_pcm_runtime *runtime = substream->runtime;
 303         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 304         int id = asoc_rtd_to_cpu(rtd, 0)->id;
 305         int ret;
 306
 307         ret = mtk_afe_fe_startup(substream, dai);
 308
 309         snd_pcm_hw_constraint_step(runtime, 0,
 310                                    SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 311                                    MT8188_MEMIF_BUFFER_BYTES_ALIGN);
 312
 313         if (id != MT8188_AFE_MEMIF_DL7)
 314                 goto out;
 315
 316         ret = snd_pcm_hw_constraint_minmax(runtime,
 317                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1,
 318                                            MT8188_MEMIF_DL7_MAX_PERIOD_SIZE);
 319         if (ret < 0)
 320                 dev_dbg(afe->dev, "hw_constraint_minmax failed\n");
 321 out:
 322         return ret;
 323 }
 324
 325 static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream,
 326                                    struct snd_soc_dai *dai)
 327 {
 328         mtk_afe_fe_shutdown(substream, dai);
 329 }
 330
 331 static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream,
 332                                    struct snd_pcm_hw_params *params,
 333                                    struct snd_soc_dai *dai)
 334 {
 335         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 336         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 337         int id = asoc_rtd_to_cpu(rtd, 0)->id;
 338         struct mtk_base_afe_memif *memif = &afe->memif[id];
 339         const struct mtk_base_memif_data *data = memif->data;
 340         const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);
 341         unsigned int channels = params_channels(params);
 342
 343         mt8188_afe_config_cm(afe, cm, channels);
 344
 345         if (data->ch_num_reg >= 0) {
 346                 regmap_update_bits(afe->regmap, data->ch_num_reg,
 347                                    data->ch_num_maskbit << data->ch_num_shift,
 348                                    channels << data->ch_num_shift);
 349         }
 350
 351         return mtk_afe_fe_hw_params(substream, params, dai);
 352 }
 353
 354 static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
 355                                  struct snd_soc_dai *dai)
 356 {
 357         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 358         const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);
 359         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 360         struct snd_pcm_runtime * const runtime = substream->runtime;
 361         int id = asoc_rtd_to_cpu(rtd, 0)->id;
 362         struct mtk_base_afe_memif *memif = &afe->memif[id];
 363         struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage];
 364         const struct mtk_base_irq_data *irq_data = irqs->irq_data;
 365         unsigned int counter = runtime->period_size;
 366         int fs;
 367         int ret;
 368
 369         switch (cmd) {
 370         case SNDRV_PCM_TRIGGER_START:
 371         case SNDRV_PCM_TRIGGER_RESUME:
 372                 mt8188_afe_enable_cm(afe, cm, true);
 373
 374                 ret = mtk_memif_set_enable(afe, id);
 375                 if (ret) {
 376                         dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
 377                                 __func__, id, ret);
 378                         return ret;
 379                 }
 380
 381                 /* set irq counter */
 382                 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
 383                                    irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift,
 384                                    counter << irq_data->irq_cnt_shift);
 385
 386                 /* set irq fs */
 387                 fs = afe->irq_fs(substream, runtime->rate);
 388
 389                 if (fs < 0)
 390                         return -EINVAL;
 391
 392                 if (irq_data->irq_fs_reg >= 0)
 393                         regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
 394                                            irq_data->irq_fs_maskbit << irq_data->irq_fs_shift,
 395                                            fs << irq_data->irq_fs_shift);
 396
 397                 /* delay for uplink */
 398                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 399                         u32 sample_delay;
 400
 401                         sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 +
 402                                         (runtime->channels * runtime->sample_bits - 1)) /
 403                                         (runtime->channels * runtime->sample_bits) + 1;
 404
 405                         udelay(sample_delay * 1000000 / runtime->rate);
 406                 }
 407
 408                 /* enable interrupt */
 409                 regmap_set_bits(afe->regmap, irq_data->irq_en_reg,
 410                                 BIT(irq_data->irq_en_shift));
 411                 return 0;
 412         case SNDRV_PCM_TRIGGER_STOP:
 413         case SNDRV_PCM_TRIGGER_SUSPEND:
 414                 mt8188_afe_enable_cm(afe, cm, false);
 415
 416                 ret = mtk_memif_set_disable(afe, id);
 417                 if (ret)
 418                         dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
 419                                 __func__, id, ret);
 420
 421                 /* disable interrupt */
 422
 423                 regmap_clear_bits(afe->regmap, irq_data->irq_en_reg,
 424                                   BIT(irq_data->irq_en_shift));
 425                 /* and clear pending IRQ */
 426                 regmap_write(afe->regmap, irq_data->irq_clr_reg,
 427                              BIT(irq_data->irq_clr_shift));
 428                 return ret;
 429         default:
 430                 return -EINVAL;
 431         }
 432 }
 433
 434 static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = {
 435         .startup        = mt8188_afe_fe_startup,
 436         .shutdown       = mt8188_afe_fe_shutdown,
 437         .hw_params      = mt8188_afe_fe_hw_params,
 438         .hw_free        = mtk_afe_fe_hw_free,
 439         .prepare        = mtk_afe_fe_prepare,
 440         .trigger        = mt8188_afe_fe_trigger,
 441 };
 442
 443 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
 444                        SNDRV_PCM_RATE_88200 |\
 445                        SNDRV_PCM_RATE_96000 |\
 446                        SNDRV_PCM_RATE_176400 |\
 447                        SNDRV_PCM_RATE_192000 |\
 448                        SNDRV_PCM_RATE_352800 |\
 449                        SNDRV_PCM_RATE_384000)
 450
 451 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 452                          SNDRV_PCM_FMTBIT_S24_LE |\
 453                          SNDRV_PCM_FMTBIT_S32_LE)
 454
 455 static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = {
 456         /* FE DAIs: memory intefaces to CPU */
 457         {
 458                 .name = "DL2",
 459                 .id = MT8188_AFE_MEMIF_DL2,
 460                 .playback = {
 461                         .stream_name = "DL2",
 462                         .channels_min = 1,
 463                         .channels_max = 2,
 464                         .rates = MTK_PCM_RATES,
 465                         .formats = MTK_PCM_FORMATS,
 466                 },
 467                 .ops = &mt8188_afe_fe_dai_ops,
 468         },
 469         {
 470                 .name = "DL3",
 471                 .id = MT8188_AFE_MEMIF_DL3,
 472                 .playback = {
 473                         .stream_name = "DL3",
 474                         .channels_min = 1,
 475                         .channels_max = 2,
 476                         .rates = MTK_PCM_RATES,
 477                         .formats = MTK_PCM_FORMATS,
 478                 },
 479                 .ops = &mt8188_afe_fe_dai_ops,
 480         },
 481         {
 482                 .name = "DL6",
 483                 .id = MT8188_AFE_MEMIF_DL6,
 484                 .playback = {
 485                         .stream_name = "DL6",
 486                         .channels_min = 1,
 487                         .channels_max = 2,
 488                         .rates = MTK_PCM_RATES,
 489                         .formats = MTK_PCM_FORMATS,
 490                 },
 491                 .ops = &mt8188_afe_fe_dai_ops,
 492         },
 493         {
 494                 .name = "DL7",
 495                 .id = MT8188_AFE_MEMIF_DL7,
 496                 .playback = {
 497                         .stream_name = "DL7",
 498                         .channels_min = 1,
 499                         .channels_max = 2,
 500                         .rates = MTK_PCM_RATES,
 501                         .formats = MTK_PCM_FORMATS,
 502                 },
 503                 .ops = &mt8188_afe_fe_dai_ops,
 504         },
 505         {
 506                 .name = "DL8",
 507                 .id = MT8188_AFE_MEMIF_DL8,
 508                 .playback = {
 509                         .stream_name = "DL8",
 510                         .channels_min = 1,
 511                         .channels_max = 16,
 512                         .rates = MTK_PCM_RATES,
 513                         .formats = MTK_PCM_FORMATS,
 514                 },
 515                 .ops = &mt8188_afe_fe_dai_ops,
 516         },
 517         {
 518                 .name = "DL10",
 519                 .id = MT8188_AFE_MEMIF_DL10,
 520                 .playback = {
 521                         .stream_name = "DL10",
 522                         .channels_min = 1,
 523                         .channels_max = 8,
 524                         .rates = MTK_PCM_RATES,
 525                         .formats = MTK_PCM_FORMATS,
 526                 },
 527                 .ops = &mt8188_afe_fe_dai_ops,
 528         },
 529         {
 530                 .name = "DL11",
 531                 .id = MT8188_AFE_MEMIF_DL11,
 532                 .playback = {
 533                         .stream_name = "DL11",
 534                         .channels_min = 1,
 535                         .channels_max = 32,
 536                         .rates = MTK_PCM_RATES,
 537                         .formats = MTK_PCM_FORMATS,
 538                 },
 539                 .ops = &mt8188_afe_fe_dai_ops,
 540         },
 541         {
 542                 .name = "UL1",
 543                 .id = MT8188_AFE_MEMIF_UL1,
 544                 .capture = {
 545                         .stream_name = "UL1",
 546                         .channels_min = 1,
 547                         .channels_max = 8,
 548                         .rates = MTK_PCM_RATES,
 549                         .formats = MTK_PCM_FORMATS,
 550                 },
 551                 .ops = &mt8188_afe_fe_dai_ops,
 552         },
 553         {
 554                 .name = "UL2",
 555                 .id = MT8188_AFE_MEMIF_UL2,
 556                 .capture = {
 557                         .stream_name = "UL2",
 558                         .channels_min = 1,
 559                         .channels_max = 8,
 560                         .rates = MTK_PCM_RATES,
 561                         .formats = MTK_PCM_FORMATS,
 562                 },
 563                 .ops = &mt8188_afe_fe_dai_ops,
 564         },
 565         {
 566                 .name = "UL3",
 567                 .id = MT8188_AFE_MEMIF_UL3,
 568                 .capture = {
 569                         .stream_name = "UL3",
 570                         .channels_min = 1,
 571                         .channels_max = 16,
 572                         .rates = MTK_PCM_RATES,
 573                         .formats = MTK_PCM_FORMATS,
 574                 },
 575                 .ops = &mt8188_afe_fe_dai_ops,
 576         },
 577         {
 578                 .name = "UL4",
 579                 .id = MT8188_AFE_MEMIF_UL4,
 580                 .capture = {
 581                         .stream_name = "UL4",
 582                         .channels_min = 1,
 583                         .channels_max = 2,
 584                         .rates = MTK_PCM_RATES,
 585                         .formats = MTK_PCM_FORMATS,
 586                 },
 587                 .ops = &mt8188_afe_fe_dai_ops,
 588         },
 589         {
 590                 .name = "UL5",
 591                 .id = MT8188_AFE_MEMIF_UL5,
 592                 .capture = {
 593                         .stream_name = "UL5",
 594                         .channels_min = 1,
 595                         .channels_max = 2,
 596                         .rates = MTK_PCM_RATES,
 597                         .formats = MTK_PCM_FORMATS,
 598                 },
 599                 .ops = &mt8188_afe_fe_dai_ops,
 600         },
 601         {
 602                 .name = "UL6",
 603                 .id = MT8188_AFE_MEMIF_UL6,
 604                 .capture = {
 605                         .stream_name = "UL6",
 606                         .channels_min = 1,
 607                         .channels_max = 8,
 608                         .rates = MTK_PCM_RATES,
 609                         .formats = MTK_PCM_FORMATS,
 610                 },
 611                 .ops = &mt8188_afe_fe_dai_ops,
 612         },
 613         {
 614                 .name = "UL8",
 615                 .id = MT8188_AFE_MEMIF_UL8,
 616                 .capture = {
 617                         .stream_name = "UL8",
 618                         .channels_min = 1,
 619                         .channels_max = 24,
 620                         .rates = MTK_PCM_RATES,
 621                         .formats = MTK_PCM_FORMATS,
 622                 },
 623                 .ops = &mt8188_afe_fe_dai_ops,
 624         },
 625         {
 626                 .name = "UL9",
 627                 .id = MT8188_AFE_MEMIF_UL9,
 628                 .capture = {
 629                         .stream_name = "UL9",
 630                         .channels_min = 1,
 631                         .channels_max = 32,
 632                         .rates = MTK_PCM_RATES,
 633                         .formats = MTK_PCM_FORMATS,
 634                 },
 635                 .ops = &mt8188_afe_fe_dai_ops,
 636         },
 637         {
 638                 .name = "UL10",
 639                 .id = MT8188_AFE_MEMIF_UL10,
 640                 .capture = {
 641                         .stream_name = "UL10",
 642                         .channels_min = 1,
 643                         .channels_max = 4,
 644                         .rates = MTK_PCM_RATES,
 645                         .formats = MTK_PCM_FORMATS,
 646                 },
 647                 .ops = &mt8188_afe_fe_dai_ops,
 648         },
 649 };
 650
 651 static const struct snd_kcontrol_new o002_mix[] = {
 652         SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),
 653         SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),
 654         SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),
 655         SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
 656         SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),
 657         SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),
 658         SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),
 659 };
 660
 661 static const struct snd_kcontrol_new o003_mix[] = {
 662         SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),
 663         SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),
 664         SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),
 665         SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
 666         SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),
 667         SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),
 668         SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),
 669 };
 670
 671 static const struct snd_kcontrol_new o004_mix[] = {
 672         SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),
 673         SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),
 674         SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),
 675         SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
 676 };
 677
 678 static const struct snd_kcontrol_new o005_mix[] = {
 679         SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),
 680         SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),
 681         SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),
 682         SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
 683 };
 684
 685 static const struct snd_kcontrol_new o006_mix[] = {
 686         SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),
 687         SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),
 688         SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),
 689         SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
 690 };
 691
 692 static const struct snd_kcontrol_new o007_mix[] = {
 693         SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),
 694         SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),
 695         SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),
 696         SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),
 697 };
 698
 699 static const struct snd_kcontrol_new o008_mix[] = {
 700         SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),
 701         SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),
 702         SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),
 703 };
 704
 705 static const struct snd_kcontrol_new o009_mix[] = {
 706         SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),
 707         SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),
 708         SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
 709 };
 710
 711 static const struct snd_kcontrol_new o010_mix[] = {
 712         SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),
 713         SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),
 714         SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),
 715         SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),
 716         SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0),
 717         SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0),
 718 };
 719
 720 static const struct snd_kcontrol_new o011_mix[] = {
 721         SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),
 722         SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),
 723         SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),
 724         SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),
 725         SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0),
 726         SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0),
 727 };
 728
 729 static const struct snd_kcontrol_new o012_mix[] = {
 730         SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),
 731         SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),
 732         SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),
 733         SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),
 734         SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0),
 735         SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0),
 736 };
 737
 738 static const struct snd_kcontrol_new o013_mix[] = {
 739         SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),
 740         SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),
 741         SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),
 742         SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),
 743         SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0),
 744         SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0),
 745 };
 746
 747 static const struct snd_kcontrol_new o014_mix[] = {
 748         SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),
 749         SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),
 750         SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),
 751         SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),
 752         SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0),
 753         SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0),
 754 };
 755
 756 static const struct snd_kcontrol_new o015_mix[] = {
 757         SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),
 758         SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),
 759         SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),
 760         SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),
 761         SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0),
 762         SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0),
 763 };
 764
 765 static const struct snd_kcontrol_new o016_mix[] = {
 766         SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),
 767         SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),
 768         SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),
 769         SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),
 770         SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0),
 771         SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0),
 772 };
 773
 774 static const struct snd_kcontrol_new o017_mix[] = {
 775         SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),
 776         SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),
 777         SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),
 778         SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),
 779         SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0),
 780         SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0),
 781 };
 782
 783 static const struct snd_kcontrol_new o018_mix[] = {
 784         SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),
 785 };
 786
 787 static const struct snd_kcontrol_new o019_mix[] = {
 788         SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),
 789 };
 790
 791 static const struct snd_kcontrol_new o020_mix[] = {
 792         SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),
 793 };
 794
 795 static const struct snd_kcontrol_new o021_mix[] = {
 796         SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),
 797 };
 798
 799 static const struct snd_kcontrol_new o022_mix[] = {
 800         SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),
 801 };
 802
 803 static const struct snd_kcontrol_new o023_mix[] = {
 804         SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),
 805 };
 806
 807 static const struct snd_kcontrol_new o024_mix[] = {
 808         SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),
 809 };
 810
 811 static const struct snd_kcontrol_new o025_mix[] = {
 812         SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),
 813 };
 814
 815 static const struct snd_kcontrol_new o026_mix[] = {
 816         SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),
 817 };
 818
 819 static const struct snd_kcontrol_new o027_mix[] = {
 820         SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),
 821 };
 822
 823 static const struct snd_kcontrol_new o028_mix[] = {
 824         SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),
 825 };
 826
 827 static const struct snd_kcontrol_new o029_mix[] = {
 828         SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),
 829 };
 830
 831 static const struct snd_kcontrol_new o030_mix[] = {
 832         SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),
 833 };
 834
 835 static const struct snd_kcontrol_new o031_mix[] = {
 836         SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),
 837 };
 838
 839 static const struct snd_kcontrol_new o032_mix[] = {
 840         SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),
 841 };
 842
 843 static const struct snd_kcontrol_new o033_mix[] = {
 844         SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),
 845 };
 846
 847 static const struct snd_kcontrol_new o034_mix[] = {
 848         SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),
 849         SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),
 850         SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),
 851         SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),
 852         SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),
 853         SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),
 854         SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),
 855 };
 856
 857 static const struct snd_kcontrol_new o035_mix[] = {
 858         SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),
 859         SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),
 860         SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),
 861         SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),
 862         SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),
 863         SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),
 864         SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),
 865         SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),
 866 };
 867
 868 static const struct snd_kcontrol_new o036_mix[] = {
 869         SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),
 870         SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),
 871         SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),
 872         SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),
 873         SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),
 874 };
 875
 876 static const struct snd_kcontrol_new o037_mix[] = {
 877         SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),
 878         SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),
 879         SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),
 880         SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),
 881         SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),
 882 };
 883
 884 static const struct snd_kcontrol_new o038_mix[] = {
 885         SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),
 886         SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0),
 887 };
 888
 889 static const struct snd_kcontrol_new o039_mix[] = {
 890         SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),
 891         SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0),
 892 };
 893
 894 static const struct snd_kcontrol_new o040_mix[] = {
 895         SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),
 896         SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),
 897         SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),
 898         SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),
 899 };
 900
 901 static const struct snd_kcontrol_new o041_mix[] = {
 902         SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),
 903         SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),
 904         SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),
 905         SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),
 906 };
 907
 908 static const struct snd_kcontrol_new o042_mix[] = {
 909         SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),
 910         SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),
 911 };
 912
 913 static const struct snd_kcontrol_new o043_mix[] = {
 914         SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),
 915         SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),
 916 };
 917
 918 static const struct snd_kcontrol_new o044_mix[] = {
 919         SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),
 920         SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),
 921 };
 922
 923 static const struct snd_kcontrol_new o045_mix[] = {
 924         SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),
 925         SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),
 926 };
 927
 928 static const struct snd_kcontrol_new o046_mix[] = {
 929         SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),
 930         SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),
 931 };
 932
 933 static const struct snd_kcontrol_new o047_mix[] = {
 934         SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),
 935         SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),
 936 };
 937
 938 static const struct snd_kcontrol_new o182_mix[] = {
 939         SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0),
 940         SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0),
 941         SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),
 942 };
 943
 944 static const struct snd_kcontrol_new o183_mix[] = {
 945         SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0),
 946         SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0),
 947         SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),
 948 };
 949
 950 static const char * const dl8_dl11_data_sel_mux_text[] = {
 951         "dl8", "dl11",
 952 };
 953
 954 static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,
 955                             AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);
 956
 957 static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =
 958         SOC_DAPM_ENUM("DL8_DL11 Sink",
 959                       dl8_dl11_data_sel_mux_enum);
 960
 961 static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = {
 962         /* DL6 */
 963         SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),
 964         SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),
 965
 966         /* DL3 */
 967         SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),
 968         SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),
 969
 970         /* DL11 */
 971         SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),
 972         SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),
 973         SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),
 974         SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),
 975         SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),
 976         SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),
 977         SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),
 978         SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),
 979         SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),
 980         SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),
 981         SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
 982         SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
 983         SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),
 984         SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),
 985         SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),
 986         SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),
 987
 988         /* DL11/DL8 */
 989         SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),
 990         SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),
 991         SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),
 992         SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),
 993         SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),
 994         SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),
 995         SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),
 996         SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),
 997         SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),
 998         SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),
 999         SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),
1000         SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),
1001         SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),
1002         SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),
1003         SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),
1004         SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),
1005
1006         /* DL2 */
1007         SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),
1008         SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),
1009
1010         SND_SOC_DAPM_MUX("DL8_DL11 Mux",
1011                          SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),
1012
1013         /* UL9 */
1014         SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,
1015                            o002_mix, ARRAY_SIZE(o002_mix)),
1016         SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,
1017                            o003_mix, ARRAY_SIZE(o003_mix)),
1018         SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,
1019                            o004_mix, ARRAY_SIZE(o004_mix)),
1020         SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,
1021                            o005_mix, ARRAY_SIZE(o005_mix)),
1022         SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,
1023                            o006_mix, ARRAY_SIZE(o006_mix)),
1024         SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,
1025                            o007_mix, ARRAY_SIZE(o007_mix)),
1026         SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,
1027                            o008_mix, ARRAY_SIZE(o008_mix)),
1028         SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,
1029                            o009_mix, ARRAY_SIZE(o009_mix)),
1030         SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,
1031                            o010_mix, ARRAY_SIZE(o010_mix)),
1032         SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,
1033                            o011_mix, ARRAY_SIZE(o011_mix)),
1034         SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,
1035                            o012_mix, ARRAY_SIZE(o012_mix)),
1036         SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,
1037                            o013_mix, ARRAY_SIZE(o013_mix)),
1038         SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,
1039                            o014_mix, ARRAY_SIZE(o014_mix)),
1040         SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,
1041                            o015_mix, ARRAY_SIZE(o015_mix)),
1042         SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,
1043                            o016_mix, ARRAY_SIZE(o016_mix)),
1044         SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,
1045                            o017_mix, ARRAY_SIZE(o017_mix)),
1046         SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
1047                            o018_mix, ARRAY_SIZE(o018_mix)),
1048         SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
1049                            o019_mix, ARRAY_SIZE(o019_mix)),
1050         SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,
1051                            o020_mix, ARRAY_SIZE(o020_mix)),
1052         SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,
1053                            o021_mix, ARRAY_SIZE(o021_mix)),
1054         SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,
1055                            o022_mix, ARRAY_SIZE(o022_mix)),
1056         SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,
1057                            o023_mix, ARRAY_SIZE(o023_mix)),
1058         SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,
1059                            o024_mix, ARRAY_SIZE(o024_mix)),
1060         SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,
1061                            o025_mix, ARRAY_SIZE(o025_mix)),
1062         SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,
1063                            o026_mix, ARRAY_SIZE(o026_mix)),
1064         SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,
1065                            o027_mix, ARRAY_SIZE(o027_mix)),
1066         SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,
1067                            o028_mix, ARRAY_SIZE(o028_mix)),
1068         SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,
1069                            o029_mix, ARRAY_SIZE(o029_mix)),
1070         SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,
1071                            o030_mix, ARRAY_SIZE(o030_mix)),
1072         SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,
1073                            o031_mix, ARRAY_SIZE(o031_mix)),
1074         SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,
1075                            o032_mix, ARRAY_SIZE(o032_mix)),
1076         SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,
1077                            o033_mix, ARRAY_SIZE(o033_mix)),
1078
1079         /* UL4 */
1080         SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,
1081                            o034_mix, ARRAY_SIZE(o034_mix)),
1082         SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,
1083                            o035_mix, ARRAY_SIZE(o035_mix)),
1084
1085         /* UL5 */
1086         SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,
1087                            o036_mix, ARRAY_SIZE(o036_mix)),
1088         SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,
1089                            o037_mix, ARRAY_SIZE(o037_mix)),
1090
1091         /* UL10 */
1092         SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,
1093                            o038_mix, ARRAY_SIZE(o038_mix)),
1094         SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,
1095                            o039_mix, ARRAY_SIZE(o039_mix)),
1096         SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,
1097                            o182_mix, ARRAY_SIZE(o182_mix)),
1098         SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,
1099                            o183_mix, ARRAY_SIZE(o183_mix)),
1100
1101         /* UL2 */
1102         SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,
1103                            o040_mix, ARRAY_SIZE(o040_mix)),
1104         SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,
1105                            o041_mix, ARRAY_SIZE(o041_mix)),
1106         SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,
1107                            o042_mix, ARRAY_SIZE(o042_mix)),
1108         SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,
1109                            o043_mix, ARRAY_SIZE(o043_mix)),
1110         SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,
1111                            o044_mix, ARRAY_SIZE(o044_mix)),
1112         SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,
1113                            o045_mix, ARRAY_SIZE(o045_mix)),
1114         SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,
1115                            o046_mix, ARRAY_SIZE(o046_mix)),
1116         SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,
1117                            o047_mix, ARRAY_SIZE(o047_mix)),
1118 };
1119
1120 static const struct snd_soc_dapm_route mt8188_memif_routes[] = {
1121         {"I000", NULL, "DL6"},
1122         {"I001", NULL, "DL6"},
1123
1124         {"I020", NULL, "DL3"},
1125         {"I021", NULL, "DL3"},
1126
1127         {"I022", NULL, "DL11"},
1128         {"I023", NULL, "DL11"},
1129         {"I024", NULL, "DL11"},
1130         {"I025", NULL, "DL11"},
1131         {"I026", NULL, "DL11"},
1132         {"I027", NULL, "DL11"},
1133         {"I028", NULL, "DL11"},
1134         {"I029", NULL, "DL11"},
1135         {"I030", NULL, "DL11"},
1136         {"I031", NULL, "DL11"},
1137         {"I032", NULL, "DL11"},
1138         {"I033", NULL, "DL11"},
1139         {"I034", NULL, "DL11"},
1140         {"I035", NULL, "DL11"},
1141         {"I036", NULL, "DL11"},
1142         {"I037", NULL, "DL11"},
1143
1144         {"DL8_DL11 Mux", "dl8", "DL8"},
1145         {"DL8_DL11 Mux", "dl11", "DL11"},
1146
1147         {"I046", NULL, "DL8_DL11 Mux"},
1148         {"I047", NULL, "DL8_DL11 Mux"},
1149         {"I048", NULL, "DL8_DL11 Mux"},
1150         {"I049", NULL, "DL8_DL11 Mux"},
1151         {"I050", NULL, "DL8_DL11 Mux"},
1152         {"I051", NULL, "DL8_DL11 Mux"},
1153         {"I052", NULL, "DL8_DL11 Mux"},
1154         {"I053", NULL, "DL8_DL11 Mux"},
1155         {"I054", NULL, "DL8_DL11 Mux"},
1156         {"I055", NULL, "DL8_DL11 Mux"},
1157         {"I056", NULL, "DL8_DL11 Mux"},
1158         {"I057", NULL, "DL8_DL11 Mux"},
1159         {"I058", NULL, "DL8_DL11 Mux"},
1160         {"I059", NULL, "DL8_DL11 Mux"},
1161         {"I060", NULL, "DL8_DL11 Mux"},
1162         {"I061", NULL, "DL8_DL11 Mux"},
1163
1164         {"I070", NULL, "DL2"},
1165         {"I071", NULL, "DL2"},
1166
1167         {"UL9", NULL, "O002"},
1168         {"UL9", NULL, "O003"},
1169         {"UL9", NULL, "O004"},
1170         {"UL9", NULL, "O005"},
1171         {"UL9", NULL, "O006"},
1172         {"UL9", NULL, "O007"},
1173         {"UL9", NULL, "O008"},
1174         {"UL9", NULL, "O009"},
1175         {"UL9", NULL, "O010"},
1176         {"UL9", NULL, "O011"},
1177         {"UL9", NULL, "O012"},
1178         {"UL9", NULL, "O013"},
1179         {"UL9", NULL, "O014"},
1180         {"UL9", NULL, "O015"},
1181         {"UL9", NULL, "O016"},
1182         {"UL9", NULL, "O017"},
1183         {"UL9", NULL, "O018"},
1184         {"UL9", NULL, "O019"},
1185         {"UL9", NULL, "O020"},
1186         {"UL9", NULL, "O021"},
1187         {"UL9", NULL, "O022"},
1188         {"UL9", NULL, "O023"},
1189         {"UL9", NULL, "O024"},
1190         {"UL9", NULL, "O025"},
1191         {"UL9", NULL, "O026"},
1192         {"UL9", NULL, "O027"},
1193         {"UL9", NULL, "O028"},
1194         {"UL9", NULL, "O029"},
1195         {"UL9", NULL, "O030"},
1196         {"UL9", NULL, "O031"},
1197         {"UL9", NULL, "O032"},
1198         {"UL9", NULL, "O033"},
1199
1200         {"UL4", NULL, "O034"},
1201         {"UL4", NULL, "O035"},
1202
1203         {"UL5", NULL, "O036"},
1204         {"UL5", NULL, "O037"},
1205
1206         {"UL10", NULL, "O038"},
1207         {"UL10", NULL, "O039"},
1208         {"UL10", NULL, "O182"},
1209         {"UL10", NULL, "O183"},
1210
1211         {"UL2", NULL, "O040"},
1212         {"UL2", NULL, "O041"},
1213         {"UL2", NULL, "O042"},
1214         {"UL2", NULL, "O043"},
1215         {"UL2", NULL, "O044"},
1216         {"UL2", NULL, "O045"},
1217         {"UL2", NULL, "O046"},
1218         {"UL2", NULL, "O047"},
1219
1220         {"O004", "I000 Switch", "I000"},
1221         {"O005", "I001 Switch", "I001"},
1222
1223         {"O006", "I000 Switch", "I000"},
1224         {"O007", "I001 Switch", "I001"},
1225
1226         {"O010", "I022 Switch", "I022"},
1227         {"O011", "I023 Switch", "I023"},
1228         {"O012", "I024 Switch", "I024"},
1229         {"O013", "I025 Switch", "I025"},
1230         {"O014", "I026 Switch", "I026"},
1231         {"O015", "I027 Switch", "I027"},
1232         {"O016", "I028 Switch", "I028"},
1233         {"O017", "I029 Switch", "I029"},
1234
1235         {"O010", "I046 Switch", "I046"},
1236         {"O011", "I047 Switch", "I047"},
1237         {"O012", "I048 Switch", "I048"},
1238         {"O013", "I049 Switch", "I049"},
1239         {"O014", "I050 Switch", "I050"},
1240         {"O015", "I051 Switch", "I051"},
1241         {"O016", "I052 Switch", "I052"},
1242         {"O017", "I053 Switch", "I053"},
1243
1244         {"O002", "I022 Switch", "I022"},
1245         {"O003", "I023 Switch", "I023"},
1246         {"O004", "I024 Switch", "I024"},
1247         {"O005", "I025 Switch", "I025"},
1248         {"O006", "I026 Switch", "I026"},
1249         {"O007", "I027 Switch", "I027"},
1250         {"O008", "I028 Switch", "I028"},
1251         {"O009", "I029 Switch", "I029"},
1252         {"O010", "I030 Switch", "I030"},
1253         {"O011", "I031 Switch", "I031"},
1254         {"O012", "I032 Switch", "I032"},
1255         {"O013", "I033 Switch", "I033"},
1256         {"O014", "I034 Switch", "I034"},
1257         {"O015", "I035 Switch", "I035"},
1258         {"O016", "I036 Switch", "I036"},
1259         {"O017", "I037 Switch", "I037"},
1260         {"O026", "I046 Switch", "I046"},
1261         {"O027", "I047 Switch", "I047"},
1262         {"O028", "I048 Switch", "I048"},
1263         {"O029", "I049 Switch", "I049"},
1264         {"O030", "I050 Switch", "I050"},
1265         {"O031", "I051 Switch", "I051"},
1266         {"O032", "I052 Switch", "I052"},
1267         {"O033", "I053 Switch", "I053"},
1268
1269         {"O002", "I000 Switch", "I000"},
1270         {"O003", "I001 Switch", "I001"},
1271         {"O002", "I020 Switch", "I020"},
1272         {"O003", "I021 Switch", "I021"},
1273         {"O002", "I070 Switch", "I070"},
1274         {"O003", "I071 Switch", "I071"},
1275
1276         {"O034", "I000 Switch", "I000"},
1277         {"O035", "I001 Switch", "I001"},
1278         {"O034", "I002 Switch", "I002"},
1279         {"O035", "I003 Switch", "I003"},
1280         {"O034", "I012 Switch", "I012"},
1281         {"O035", "I013 Switch", "I013"},
1282         {"O034", "I020 Switch", "I020"},
1283         {"O035", "I021 Switch", "I021"},
1284         {"O034", "I070 Switch", "I070"},
1285         {"O035", "I071 Switch", "I071"},
1286         {"O034", "I072 Switch", "I072"},
1287         {"O035", "I073 Switch", "I073"},
1288
1289         {"O036", "I000 Switch", "I000"},
1290         {"O037", "I001 Switch", "I001"},
1291         {"O036", "I012 Switch", "I012"},
1292         {"O037", "I013 Switch", "I013"},
1293         {"O036", "I020 Switch", "I020"},
1294         {"O037", "I021 Switch", "I021"},
1295         {"O036", "I070 Switch", "I070"},
1296         {"O037", "I071 Switch", "I071"},
1297         {"O036", "I168 Switch", "I168"},
1298         {"O037", "I169 Switch", "I169"},
1299
1300         {"O038", "I022 Switch", "I022"},
1301         {"O039", "I023 Switch", "I023"},
1302         {"O182", "I024 Switch", "I024"},
1303         {"O183", "I025 Switch", "I025"},
1304
1305         {"O038", "I168 Switch", "I168"},
1306         {"O039", "I169 Switch", "I169"},
1307
1308         {"O182", "I020 Switch", "I020"},
1309         {"O183", "I021 Switch", "I021"},
1310
1311         {"O182", "I022 Switch", "I022"},
1312         {"O183", "I023 Switch", "I023"},
1313
1314         {"O040", "I022 Switch", "I022"},
1315         {"O041", "I023 Switch", "I023"},
1316         {"O042", "I024 Switch", "I024"},
1317         {"O043", "I025 Switch", "I025"},
1318         {"O044", "I026 Switch", "I026"},
1319         {"O045", "I027 Switch", "I027"},
1320         {"O046", "I028 Switch", "I028"},
1321         {"O047", "I029 Switch", "I029"},
1322
1323         {"O040", "I002 Switch", "I002"},
1324         {"O041", "I003 Switch", "I003"},
1325
1326         {"O002", "I012 Switch", "I012"},
1327         {"O003", "I013 Switch", "I013"},
1328         {"O004", "I014 Switch", "I014"},
1329         {"O005", "I015 Switch", "I015"},
1330         {"O006", "I016 Switch", "I016"},
1331         {"O007", "I017 Switch", "I017"},
1332         {"O008", "I018 Switch", "I018"},
1333         {"O009", "I019 Switch", "I019"},
1334         {"O010", "I188 Switch", "I188"},
1335         {"O011", "I189 Switch", "I189"},
1336         {"O012", "I190 Switch", "I190"},
1337         {"O013", "I191 Switch", "I191"},
1338         {"O014", "I192 Switch", "I192"},
1339         {"O015", "I193 Switch", "I193"},
1340         {"O016", "I194 Switch", "I194"},
1341         {"O017", "I195 Switch", "I195"},
1342
1343         {"O040", "I012 Switch", "I012"},
1344         {"O041", "I013 Switch", "I013"},
1345         {"O042", "I014 Switch", "I014"},
1346         {"O043", "I015 Switch", "I015"},
1347         {"O044", "I016 Switch", "I016"},
1348         {"O045", "I017 Switch", "I017"},
1349         {"O046", "I018 Switch", "I018"},
1350         {"O047", "I019 Switch", "I019"},
1351
1352         {"O002", "I072 Switch", "I072"},
1353         {"O003", "I073 Switch", "I073"},
1354         {"O004", "I074 Switch", "I074"},
1355         {"O005", "I075 Switch", "I075"},
1356         {"O006", "I076 Switch", "I076"},
1357         {"O007", "I077 Switch", "I077"},
1358         {"O008", "I078 Switch", "I078"},
1359         {"O009", "I079 Switch", "I079"},
1360         {"O010", "I080 Switch", "I080"},
1361         {"O011", "I081 Switch", "I081"},
1362         {"O012", "I082 Switch", "I082"},
1363         {"O013", "I083 Switch", "I083"},
1364         {"O014", "I084 Switch", "I084"},
1365         {"O015", "I085 Switch", "I085"},
1366         {"O016", "I086 Switch", "I086"},
1367         {"O017", "I087 Switch", "I087"},
1368
1369         {"O010", "I072 Switch", "I072"},
1370         {"O011", "I073 Switch", "I073"},
1371         {"O012", "I074 Switch", "I074"},
1372         {"O013", "I075 Switch", "I075"},
1373         {"O014", "I076 Switch", "I076"},
1374         {"O015", "I077 Switch", "I077"},
1375         {"O016", "I078 Switch", "I078"},
1376         {"O017", "I079 Switch", "I079"},
1377         {"O018", "I080 Switch", "I080"},
1378         {"O019", "I081 Switch", "I081"},
1379         {"O020", "I082 Switch", "I082"},
1380         {"O021", "I083 Switch", "I083"},
1381         {"O022", "I084 Switch", "I084"},
1382         {"O023", "I085 Switch", "I085"},
1383         {"O024", "I086 Switch", "I086"},
1384         {"O025", "I087 Switch", "I087"},
1385
1386         {"O002", "I168 Switch", "I168"},
1387         {"O003", "I169 Switch", "I169"},
1388
1389         {"O034", "I168 Switch", "I168"},
1390         {"O035", "I168 Switch", "I168"},
1391         {"O035", "I169 Switch", "I169"},
1392
1393         {"O040", "I168 Switch", "I168"},
1394         {"O041", "I169 Switch", "I169"},
1395 };
1396
1397 static const char * const mt8188_afe_1x_en_sel_text[] = {
1398         "a1sys_a2sys", "a3sys", "a4sys",
1399 };
1400
1401 static const unsigned int mt8188_afe_1x_en_sel_values[] = {
1402         0, 1, 2,
1403 };
1404
1405 static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,
1406                                   A3_A4_TIMING_SEL1, 18, 0x3,
1407                                   mt8188_afe_1x_en_sel_text,
1408                                   mt8188_afe_1x_en_sel_values);
1409 static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,
1410                                   A3_A4_TIMING_SEL1, 20, 0x3,
1411                                   mt8188_afe_1x_en_sel_text,
1412                                   mt8188_afe_1x_en_sel_values);
1413 static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,
1414                                   A3_A4_TIMING_SEL1, 22, 0x3,
1415                                   mt8188_afe_1x_en_sel_text,
1416                                   mt8188_afe_1x_en_sel_values);
1417 static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,
1418                                   A3_A4_TIMING_SEL1, 24, 0x3,
1419                                   mt8188_afe_1x_en_sel_text,
1420                                   mt8188_afe_1x_en_sel_values);
1421 static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,
1422                                   A3_A4_TIMING_SEL1, 26, 0x3,
1423                                   mt8188_afe_1x_en_sel_text,
1424                                   mt8188_afe_1x_en_sel_values);
1425 static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,
1426                                   A3_A4_TIMING_SEL1, 28, 0x3,
1427                                   mt8188_afe_1x_en_sel_text,
1428                                   mt8188_afe_1x_en_sel_values);
1429 static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,
1430                                   A3_A4_TIMING_SEL1, 30, 0x3,
1431                                   mt8188_afe_1x_en_sel_text,
1432                                   mt8188_afe_1x_en_sel_values);
1433 static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,
1434                                   A3_A4_TIMING_SEL1, 0, 0x3,
1435                                   mt8188_afe_1x_en_sel_text,
1436                                   mt8188_afe_1x_en_sel_values);
1437 static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,
1438                                   A3_A4_TIMING_SEL1, 2, 0x3,
1439                                   mt8188_afe_1x_en_sel_text,
1440                                   mt8188_afe_1x_en_sel_values);
1441 static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,
1442                                   A3_A4_TIMING_SEL1, 4, 0x3,
1443                                   mt8188_afe_1x_en_sel_text,
1444                                   mt8188_afe_1x_en_sel_values);
1445 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,
1446                                   A3_A4_TIMING_SEL1, 6, 0x3,
1447                                   mt8188_afe_1x_en_sel_text,
1448                                   mt8188_afe_1x_en_sel_values);
1449 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,
1450                                   A3_A4_TIMING_SEL1, 8, 0x3,
1451                                   mt8188_afe_1x_en_sel_text,
1452                                   mt8188_afe_1x_en_sel_values);
1453 static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,
1454                                   A3_A4_TIMING_SEL1, 10, 0x3,
1455                                   mt8188_afe_1x_en_sel_text,
1456                                   mt8188_afe_1x_en_sel_values);
1457 static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,
1458                                   A3_A4_TIMING_SEL1, 12, 0x3,
1459                                   mt8188_afe_1x_en_sel_text,
1460                                   mt8188_afe_1x_en_sel_values);
1461 static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,
1462                                   A3_A4_TIMING_SEL1, 14, 0x3,
1463                                   mt8188_afe_1x_en_sel_text,
1464                                   mt8188_afe_1x_en_sel_values);
1465 static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,
1466                                   A3_A4_TIMING_SEL1, 16, 0x3,
1467                                   mt8188_afe_1x_en_sel_text,
1468                                   mt8188_afe_1x_en_sel_values);
1469
1470 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,
1471                                   A3_A4_TIMING_SEL6, 0, 0x3,
1472                                   mt8188_afe_1x_en_sel_text,
1473                                   mt8188_afe_1x_en_sel_values);
1474 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,
1475                                   A3_A4_TIMING_SEL6, 2, 0x3,
1476                                   mt8188_afe_1x_en_sel_text,
1477                                   mt8188_afe_1x_en_sel_values);
1478 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,
1479                                   A3_A4_TIMING_SEL6, 4, 0x3,
1480                                   mt8188_afe_1x_en_sel_text,
1481                                   mt8188_afe_1x_en_sel_values);
1482 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,
1483                                   A3_A4_TIMING_SEL6, 6, 0x3,
1484                                   mt8188_afe_1x_en_sel_text,
1485                                   mt8188_afe_1x_en_sel_values);
1486 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,
1487                                   A3_A4_TIMING_SEL6, 8, 0x3,
1488                                   mt8188_afe_1x_en_sel_text,
1489                                   mt8188_afe_1x_en_sel_values);
1490 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,
1491                                   A3_A4_TIMING_SEL6, 10, 0x3,
1492                                   mt8188_afe_1x_en_sel_text,
1493                                   mt8188_afe_1x_en_sel_values);
1494 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,
1495                                   A3_A4_TIMING_SEL6, 12, 0x3,
1496                                   mt8188_afe_1x_en_sel_text,
1497                                   mt8188_afe_1x_en_sel_values);
1498 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,
1499                                   A3_A4_TIMING_SEL6, 14, 0x3,
1500                                   mt8188_afe_1x_en_sel_text,
1501                                   mt8188_afe_1x_en_sel_values);
1502 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,
1503                                   A3_A4_TIMING_SEL6, 16, 0x3,
1504                                   mt8188_afe_1x_en_sel_text,
1505                                   mt8188_afe_1x_en_sel_values);
1506 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,
1507                                   A3_A4_TIMING_SEL6, 18, 0x3,
1508                                   mt8188_afe_1x_en_sel_text,
1509                                   mt8188_afe_1x_en_sel_values);
1510 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,
1511                                   A3_A4_TIMING_SEL6, 20, 0x3,
1512                                   mt8188_afe_1x_en_sel_text,
1513                                   mt8188_afe_1x_en_sel_values);
1514 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,
1515                                   A3_A4_TIMING_SEL6, 22, 0x3,
1516                                   mt8188_afe_1x_en_sel_text,
1517                                   mt8188_afe_1x_en_sel_values);
1518 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,
1519                                   A3_A4_TIMING_SEL6, 24, 0x3,
1520                                   mt8188_afe_1x_en_sel_text,
1521                                   mt8188_afe_1x_en_sel_values);
1522 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,
1523                                   A3_A4_TIMING_SEL6, 26, 0x3,
1524                                   mt8188_afe_1x_en_sel_text,
1525                                   mt8188_afe_1x_en_sel_values);
1526 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,
1527                                   A3_A4_TIMING_SEL6, 28, 0x3,
1528                                   mt8188_afe_1x_en_sel_text,
1529                                   mt8188_afe_1x_en_sel_values);
1530 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,
1531                                   A3_A4_TIMING_SEL6, 30, 0x3,
1532                                   mt8188_afe_1x_en_sel_text,
1533                                   mt8188_afe_1x_en_sel_values);
1534
1535 static const char * const mt8188_afe_fs_timing_sel_text[] = {
1536         "asys",
1537         "etdmout1_1x_en",
1538         "etdmout2_1x_en",
1539         "etdmout3_1x_en",
1540         "etdmin1_1x_en",
1541         "etdmin2_1x_en",
1542         "etdmin1_nx_en",
1543         "etdmin2_nx_en",
1544 };
1545
1546 static const unsigned int mt8188_afe_fs_timing_sel_values[] = {
1547         0,
1548         MT8188_ETDM_OUT1_1X_EN,
1549         MT8188_ETDM_OUT2_1X_EN,
1550         MT8188_ETDM_OUT3_1X_EN,
1551         MT8188_ETDM_IN1_1X_EN,
1552         MT8188_ETDM_IN2_1X_EN,
1553         MT8188_ETDM_IN1_NX_EN,
1554         MT8188_ETDM_IN2_NX_EN,
1555 };
1556
1557 static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum,
1558                                   SND_SOC_NOPM, 0, 0,
1559                                   mt8188_afe_fs_timing_sel_text,
1560                                   mt8188_afe_fs_timing_sel_values);
1561 static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum,
1562                                   SND_SOC_NOPM, 0, 0,
1563                                   mt8188_afe_fs_timing_sel_text,
1564                                   mt8188_afe_fs_timing_sel_values);
1565 static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum,
1566                                   SND_SOC_NOPM, 0, 0,
1567                                   mt8188_afe_fs_timing_sel_text,
1568                                   mt8188_afe_fs_timing_sel_values);
1569 static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum,
1570                                   SND_SOC_NOPM, 0, 0,
1571                                   mt8188_afe_fs_timing_sel_text,
1572                                   mt8188_afe_fs_timing_sel_values);
1573 static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum,
1574                                   SND_SOC_NOPM, 0, 0,
1575                                   mt8188_afe_fs_timing_sel_text,
1576                                   mt8188_afe_fs_timing_sel_values);
1577 static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum,
1578                                   SND_SOC_NOPM, 0, 0,
1579                                   mt8188_afe_fs_timing_sel_text,
1580                                   mt8188_afe_fs_timing_sel_values);
1581 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum,
1582                                   SND_SOC_NOPM, 0, 0,
1583                                   mt8188_afe_fs_timing_sel_text,
1584                                   mt8188_afe_fs_timing_sel_values);
1585 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum,
1586                                   SND_SOC_NOPM, 0, 0,
1587                                   mt8188_afe_fs_timing_sel_text,
1588                                   mt8188_afe_fs_timing_sel_values);
1589 static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum,
1590                                   SND_SOC_NOPM, 0, 0,
1591                                   mt8188_afe_fs_timing_sel_text,
1592                                   mt8188_afe_fs_timing_sel_values);
1593 static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum,
1594                                   SND_SOC_NOPM, 0, 0,
1595                                   mt8188_afe_fs_timing_sel_text,
1596                                   mt8188_afe_fs_timing_sel_values);
1597
1598 static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,
1599                                       struct snd_ctl_elem_value *ucontrol)
1600 {
1601         struct snd_soc_component *component =
1602                 snd_soc_kcontrol_component(kcontrol);
1603         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1604         struct mt8188_afe_private *afe_priv = afe->platform_priv;
1605         struct mtk_dai_memif_priv *memif_priv;
1606         unsigned int dai_id = kcontrol->id.device;
1607         long val = ucontrol->value.integer.value[0];
1608         int ret = 0;
1609
1610         memif_priv = afe_priv->dai_priv[dai_id];
1611
1612         if (val == memif_priv->asys_timing_sel)
1613                 return 0;
1614
1615         ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1616
1617         memif_priv->asys_timing_sel = val;
1618
1619         return ret;
1620 }
1621
1622 static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,
1623                                          struct snd_ctl_elem_value *ucontrol)
1624 {
1625         struct snd_soc_component *component =
1626                 snd_soc_kcontrol_component(kcontrol);
1627         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1628         struct mt8188_afe_private *afe_priv = afe->platform_priv;
1629         unsigned int id = kcontrol->id.device;
1630         long val = ucontrol->value.integer.value[0];
1631         int ret = 0;
1632
1633         if (val == afe_priv->irq_priv[id].asys_timing_sel)
1634                 return 0;
1635
1636         ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1637
1638         afe_priv->irq_priv[id].asys_timing_sel = val;
1639
1640         return ret;
1641 }
1642
1643 static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol,
1644                                           struct snd_ctl_elem_value *ucontrol)
1645 {
1646         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1647         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1648         struct mt8188_afe_private *afe_priv = afe->platform_priv;
1649         struct mtk_dai_memif_priv *memif_priv;
1650         unsigned int dai_id = kcontrol->id.device;
1651         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1652
1653         memif_priv = afe_priv->dai_priv[dai_id];
1654
1655         ucontrol->value.enumerated.item[0] =
1656                 snd_soc_enum_val_to_item(e, memif_priv->fs_timing);
1657
1658         return 0;
1659 }
1660
1661 static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol,
1662                                           struct snd_ctl_elem_value *ucontrol)
1663 {
1664         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1665         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
1666         struct mt8188_afe_private *afe_priv = afe->platform_priv;
1667         struct mtk_dai_memif_priv *memif_priv;
1668         unsigned int dai_id = kcontrol->id.device;
1669         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1670         unsigned int *item = ucontrol->value.enumerated.item;
1671         unsigned int prev_item = 0;
1672
1673         if (item[0] >= e->items)
1674                 return -EINVAL;
1675
1676         memif_priv = afe_priv->dai_priv[dai_id];
1677
1678         prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing);
1679
1680         if (item[0] == prev_item)
1681                 return 0;
1682
1683         memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]);
1684
1685         return 1;
1686 }
1687
1688 static const struct snd_kcontrol_new mt8188_memif_controls[] = {
1689         MT8188_SOC_ENUM_EXT("dl2_1x_en_sel",
1690                             dl2_1x_en_sel_enum,
1691                             snd_soc_get_enum_double,
1692                             mt8188_memif_1x_en_sel_put,
1693                             MT8188_AFE_MEMIF_DL2),
1694         MT8188_SOC_ENUM_EXT("dl3_1x_en_sel",
1695                             dl3_1x_en_sel_enum,
1696                             snd_soc_get_enum_double,
1697                             mt8188_memif_1x_en_sel_put,
1698                             MT8188_AFE_MEMIF_DL3),
1699         MT8188_SOC_ENUM_EXT("dl6_1x_en_sel",
1700                             dl6_1x_en_sel_enum,
1701                             snd_soc_get_enum_double,
1702                             mt8188_memif_1x_en_sel_put,
1703                             MT8188_AFE_MEMIF_DL6),
1704         MT8188_SOC_ENUM_EXT("dl7_1x_en_sel",
1705                             dl7_1x_en_sel_enum,
1706                             snd_soc_get_enum_double,
1707                             mt8188_memif_1x_en_sel_put,
1708                             MT8188_AFE_MEMIF_DL7),
1709         MT8188_SOC_ENUM_EXT("dl8_1x_en_sel",
1710                             dl8_1x_en_sel_enum,
1711                             snd_soc_get_enum_double,
1712                             mt8188_memif_1x_en_sel_put,
1713                             MT8188_AFE_MEMIF_DL8),
1714         MT8188_SOC_ENUM_EXT("dl10_1x_en_sel",
1715                             dl10_1x_en_sel_enum,
1716                             snd_soc_get_enum_double,
1717                             mt8188_memif_1x_en_sel_put,
1718                             MT8188_AFE_MEMIF_DL10),
1719         MT8188_SOC_ENUM_EXT("dl11_1x_en_sel",
1720                             dl11_1x_en_sel_enum,
1721                             snd_soc_get_enum_double,
1722                             mt8188_memif_1x_en_sel_put,
1723                             MT8188_AFE_MEMIF_DL11),
1724         MT8188_SOC_ENUM_EXT("ul1_1x_en_sel",
1725                             ul1_1x_en_sel_enum,
1726                             snd_soc_get_enum_double,
1727                             mt8188_memif_1x_en_sel_put,
1728                             MT8188_AFE_MEMIF_UL1),
1729         MT8188_SOC_ENUM_EXT("ul2_1x_en_sel",
1730                             ul2_1x_en_sel_enum,
1731                             snd_soc_get_enum_double,
1732                             mt8188_memif_1x_en_sel_put,
1733                             MT8188_AFE_MEMIF_UL2),
1734         MT8188_SOC_ENUM_EXT("ul3_1x_en_sel",
1735                             ul3_1x_en_sel_enum,
1736                             snd_soc_get_enum_double,
1737                             mt8188_memif_1x_en_sel_put,
1738                             MT8188_AFE_MEMIF_UL3),
1739         MT8188_SOC_ENUM_EXT("ul4_1x_en_sel",
1740                             ul4_1x_en_sel_enum,
1741                             snd_soc_get_enum_double,
1742                             mt8188_memif_1x_en_sel_put,
1743                             MT8188_AFE_MEMIF_UL4),
1744         MT8188_SOC_ENUM_EXT("ul5_1x_en_sel",
1745                             ul5_1x_en_sel_enum,
1746                             snd_soc_get_enum_double,
1747                             mt8188_memif_1x_en_sel_put,
1748                             MT8188_AFE_MEMIF_UL5),
1749         MT8188_SOC_ENUM_EXT("ul6_1x_en_sel",
1750                             ul6_1x_en_sel_enum,
1751                             snd_soc_get_enum_double,
1752                             mt8188_memif_1x_en_sel_put,
1753                             MT8188_AFE_MEMIF_UL6),
1754         MT8188_SOC_ENUM_EXT("ul8_1x_en_sel",
1755                             ul8_1x_en_sel_enum,
1756                             snd_soc_get_enum_double,
1757                             mt8188_memif_1x_en_sel_put,
1758                             MT8188_AFE_MEMIF_UL8),
1759         MT8188_SOC_ENUM_EXT("ul9_1x_en_sel",
1760                             ul9_1x_en_sel_enum,
1761                             snd_soc_get_enum_double,
1762                             mt8188_memif_1x_en_sel_put,
1763                             MT8188_AFE_MEMIF_UL9),
1764         MT8188_SOC_ENUM_EXT("ul10_1x_en_sel",
1765                             ul10_1x_en_sel_enum,
1766                             snd_soc_get_enum_double,
1767                             mt8188_memif_1x_en_sel_put,
1768                             MT8188_AFE_MEMIF_UL10),
1769         MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel",
1770                             asys_irq1_1x_en_sel_enum,
1771                             snd_soc_get_enum_double,
1772                             mt8188_asys_irq_1x_en_sel_put,
1773                             MT8188_AFE_IRQ_13),
1774         MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel",
1775                             asys_irq2_1x_en_sel_enum,
1776                             snd_soc_get_enum_double,
1777                             mt8188_asys_irq_1x_en_sel_put,
1778                             MT8188_AFE_IRQ_14),
1779         MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel",
1780                             asys_irq3_1x_en_sel_enum,
1781                             snd_soc_get_enum_double,
1782                             mt8188_asys_irq_1x_en_sel_put,
1783                             MT8188_AFE_IRQ_15),
1784         MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel",
1785                             asys_irq4_1x_en_sel_enum,
1786                             snd_soc_get_enum_double,
1787                             mt8188_asys_irq_1x_en_sel_put,
1788                             MT8188_AFE_IRQ_16),
1789         MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel",
1790                             asys_irq5_1x_en_sel_enum,
1791                             snd_soc_get_enum_double,
1792                             mt8188_asys_irq_1x_en_sel_put,
1793                             MT8188_AFE_IRQ_17),
1794         MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel",
1795                             asys_irq6_1x_en_sel_enum,
1796                             snd_soc_get_enum_double,
1797                             mt8188_asys_irq_1x_en_sel_put,
1798                             MT8188_AFE_IRQ_18),
1799         MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel",
1800                             asys_irq7_1x_en_sel_enum,
1801                             snd_soc_get_enum_double,
1802                             mt8188_asys_irq_1x_en_sel_put,
1803                             MT8188_AFE_IRQ_19),
1804         MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel",
1805                             asys_irq8_1x_en_sel_enum,
1806                             snd_soc_get_enum_double,
1807                             mt8188_asys_irq_1x_en_sel_put,
1808                             MT8188_AFE_IRQ_20),
1809         MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel",
1810                             asys_irq9_1x_en_sel_enum,
1811                             snd_soc_get_enum_double,
1812                             mt8188_asys_irq_1x_en_sel_put,
1813                             MT8188_AFE_IRQ_21),
1814         MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel",
1815                             asys_irq10_1x_en_sel_enum,
1816                             snd_soc_get_enum_double,
1817                             mt8188_asys_irq_1x_en_sel_put,
1818                             MT8188_AFE_IRQ_22),
1819         MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel",
1820                             asys_irq11_1x_en_sel_enum,
1821                             snd_soc_get_enum_double,
1822                             mt8188_asys_irq_1x_en_sel_put,
1823                             MT8188_AFE_IRQ_23),
1824         MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel",
1825                             asys_irq12_1x_en_sel_enum,
1826                             snd_soc_get_enum_double,
1827                             mt8188_asys_irq_1x_en_sel_put,
1828                             MT8188_AFE_IRQ_24),
1829         MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel",
1830                             asys_irq13_1x_en_sel_enum,
1831                             snd_soc_get_enum_double,
1832                             mt8188_asys_irq_1x_en_sel_put,
1833                             MT8188_AFE_IRQ_25),
1834         MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel",
1835                             asys_irq14_1x_en_sel_enum,
1836                             snd_soc_get_enum_double,
1837                             mt8188_asys_irq_1x_en_sel_put,
1838                             MT8188_AFE_IRQ_26),
1839         MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel",
1840                             asys_irq15_1x_en_sel_enum,
1841                             snd_soc_get_enum_double,
1842                             mt8188_asys_irq_1x_en_sel_put,
1843                             MT8188_AFE_IRQ_27),
1844         MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel",
1845                             asys_irq16_1x_en_sel_enum,
1846                             snd_soc_get_enum_double,
1847                             mt8188_asys_irq_1x_en_sel_put,
1848                             MT8188_AFE_IRQ_28),
1849         MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel",
1850                             dl2_fs_timing_sel_enum,
1851                             mt8188_memif_fs_timing_sel_get,
1852                             mt8188_memif_fs_timing_sel_put,
1853                             MT8188_AFE_MEMIF_DL2),
1854         MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel",
1855                             dl3_fs_timing_sel_enum,
1856                             mt8188_memif_fs_timing_sel_get,
1857                             mt8188_memif_fs_timing_sel_put,
1858                             MT8188_AFE_MEMIF_DL3),
1859         MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel",
1860                             dl6_fs_timing_sel_enum,
1861                             mt8188_memif_fs_timing_sel_get,
1862                             mt8188_memif_fs_timing_sel_put,
1863                             MT8188_AFE_MEMIF_DL6),
1864         MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel",
1865                             dl8_fs_timing_sel_enum,
1866                             mt8188_memif_fs_timing_sel_get,
1867                             mt8188_memif_fs_timing_sel_put,
1868                             MT8188_AFE_MEMIF_DL8),
1869         MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel",
1870                             dl11_fs_timing_sel_enum,
1871                             mt8188_memif_fs_timing_sel_get,
1872                             mt8188_memif_fs_timing_sel_put,
1873                             MT8188_AFE_MEMIF_DL11),
1874         MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel",
1875                             ul2_fs_timing_sel_enum,
1876                             mt8188_memif_fs_timing_sel_get,
1877                             mt8188_memif_fs_timing_sel_put,
1878                             MT8188_AFE_MEMIF_UL2),
1879         MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel",
1880                             ul4_fs_timing_sel_enum,
1881                             mt8188_memif_fs_timing_sel_get,
1882                             mt8188_memif_fs_timing_sel_put,
1883                             MT8188_AFE_MEMIF_UL4),
1884         MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel",
1885                             ul5_fs_timing_sel_enum,
1886                             mt8188_memif_fs_timing_sel_get,
1887                             mt8188_memif_fs_timing_sel_put,
1888                             MT8188_AFE_MEMIF_UL5),
1889         MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel",
1890                             ul9_fs_timing_sel_enum,
1891                             mt8188_memif_fs_timing_sel_get,
1892                             mt8188_memif_fs_timing_sel_put,
1893                             MT8188_AFE_MEMIF_UL9),
1894         MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel",
1895                             ul10_fs_timing_sel_enum,
1896                             mt8188_memif_fs_timing_sel_get,
1897                             mt8188_memif_fs_timing_sel_put,
1898                             MT8188_AFE_MEMIF_UL10),
1899 };
1900
1901 static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = {
1902         [MT8188_AFE_MEMIF_DL2] = {
1903                 .name = "DL2",
1904                 .id = MT8188_AFE_MEMIF_DL2,
1905                 .reg_ofs_base = AFE_DL2_BASE,
1906                 .reg_ofs_cur = AFE_DL2_CUR,
1907                 .reg_ofs_end = AFE_DL2_END,
1908                 .fs_reg = AFE_MEMIF_AGENT_FS_CON0,
1909                 .fs_shift = 10,
1910                 .fs_maskbit = 0x1f,
1911                 .mono_reg = -1,
1912                 .mono_shift = 0,
1913                 .int_odd_flag_reg = -1,
1914                 .int_odd_flag_shift = 0,
1915                 .enable_reg = AFE_DAC_CON0,
1916                 .enable_shift = 18,
1917                 .hd_reg = AFE_DL2_CON0,
1918                 .hd_shift = 5,
1919                 .agent_disable_reg = AUDIO_TOP_CON5,
1920                 .agent_disable_shift = 18,
1921                 .ch_num_reg = AFE_DL2_CON0,
1922                 .ch_num_shift = 0,
1923                 .ch_num_maskbit = 0x1f,
1924                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
1925                 .msb_shift = 18,
1926                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
1927                 .msb_end_shift = 18,
1928         },
1929         [MT8188_AFE_MEMIF_DL3] = {
1930                 .name = "DL3",
1931                 .id = MT8188_AFE_MEMIF_DL3,
1932                 .reg_ofs_base = AFE_DL3_BASE,
1933                 .reg_ofs_cur = AFE_DL3_CUR,
1934                 .reg_ofs_end = AFE_DL3_END,
1935                 .fs_reg = AFE_MEMIF_AGENT_FS_CON0,
1936                 .fs_shift = 15,
1937                 .fs_maskbit = 0x1f,
1938                 .mono_reg = -1,
1939                 .mono_shift = 0,
1940                 .int_odd_flag_reg = -1,
1941                 .int_odd_flag_shift = 0,
1942                 .enable_reg = AFE_DAC_CON0,
1943                 .enable_shift = 19,
1944                 .hd_reg = AFE_DL3_CON0,
1945                 .hd_shift = 5,
1946                 .agent_disable_reg = AUDIO_TOP_CON5,
1947                 .agent_disable_shift = 19,
1948                 .ch_num_reg = AFE_DL3_CON0,
1949                 .ch_num_shift = 0,
1950                 .ch_num_maskbit = 0x1f,
1951                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
1952                 .msb_shift = 19,
1953                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
1954                 .msb_end_shift = 19,
1955         },
1956         [MT8188_AFE_MEMIF_DL6] = {
1957                 .name = "DL6",
1958                 .id = MT8188_AFE_MEMIF_DL6,
1959                 .reg_ofs_base = AFE_DL6_BASE,
1960                 .reg_ofs_cur = AFE_DL6_CUR,
1961                 .reg_ofs_end = AFE_DL6_END,
1962                 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,
1963                 .fs_shift = 0,
1964                 .fs_maskbit = 0x1f,
1965                 .mono_reg = -1,
1966                 .mono_shift = 0,
1967                 .int_odd_flag_reg = -1,
1968                 .int_odd_flag_shift = 0,
1969                 .enable_reg = AFE_DAC_CON0,
1970                 .enable_shift = 22,
1971                 .hd_reg = AFE_DL6_CON0,
1972                 .hd_shift = 5,
1973                 .agent_disable_reg = AUDIO_TOP_CON5,
1974                 .agent_disable_shift = 22,
1975                 .ch_num_reg = AFE_DL6_CON0,
1976                 .ch_num_shift = 0,
1977                 .ch_num_maskbit = 0x1f,
1978                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
1979                 .msb_shift = 22,
1980                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
1981                 .msb_end_shift = 22,
1982         },
1983         [MT8188_AFE_MEMIF_DL7] = {
1984                 .name = "DL7",
1985                 .id = MT8188_AFE_MEMIF_DL7,
1986                 .reg_ofs_base = AFE_DL7_BASE,
1987                 .reg_ofs_cur = AFE_DL7_CUR,
1988                 .reg_ofs_end = AFE_DL7_END,
1989                 .fs_reg = -1,
1990                 .fs_shift = 0,
1991                 .fs_maskbit = 0,
1992                 .mono_reg = -1,
1993                 .mono_shift = 0,
1994                 .int_odd_flag_reg = -1,
1995                 .int_odd_flag_shift = 0,
1996                 .enable_reg = AFE_DAC_CON0,
1997                 .enable_shift = 23,
1998                 .hd_reg = AFE_DL7_CON0,
1999                 .hd_shift = 5,
2000                 .agent_disable_reg = AUDIO_TOP_CON5,
2001                 .agent_disable_shift = 23,
2002                 .ch_num_reg = AFE_DL7_CON0,
2003                 .ch_num_shift = 0,
2004                 .ch_num_maskbit = 0x1f,
2005                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2006                 .msb_shift = 23,
2007                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2008                 .msb_end_shift = 23,
2009         },
2010         [MT8188_AFE_MEMIF_DL8] = {
2011                 .name = "DL8",
2012                 .id = MT8188_AFE_MEMIF_DL8,
2013                 .reg_ofs_base = AFE_DL8_BASE,
2014                 .reg_ofs_cur = AFE_DL8_CUR,
2015                 .reg_ofs_end = AFE_DL8_END,
2016                 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,
2017                 .fs_shift = 10,
2018                 .fs_maskbit = 0x1f,
2019                 .mono_reg = -1,
2020                 .mono_shift = 0,
2021                 .int_odd_flag_reg = -1,
2022                 .int_odd_flag_shift = 0,
2023                 .enable_reg = AFE_DAC_CON0,
2024                 .enable_shift = 24,
2025                 .hd_reg = AFE_DL8_CON0,
2026                 .hd_shift = 6,
2027                 .agent_disable_reg = AUDIO_TOP_CON5,
2028                 .agent_disable_shift = 24,
2029                 .ch_num_reg = AFE_DL8_CON0,
2030                 .ch_num_shift = 0,
2031                 .ch_num_maskbit = 0x3f,
2032                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2033                 .msb_shift = 24,
2034                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2035                 .msb_end_shift = 24,
2036         },
2037         [MT8188_AFE_MEMIF_DL10] = {
2038                 .name = "DL10",
2039                 .id = MT8188_AFE_MEMIF_DL10,
2040                 .reg_ofs_base = AFE_DL10_BASE,
2041                 .reg_ofs_cur = AFE_DL10_CUR,
2042                 .reg_ofs_end = AFE_DL10_END,
2043                 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,
2044                 .fs_shift = 20,
2045                 .fs_maskbit = 0x1f,
2046                 .mono_reg = -1,
2047                 .mono_shift = 0,
2048                 .int_odd_flag_reg = -1,
2049                 .int_odd_flag_shift = 0,
2050                 .enable_reg = AFE_DAC_CON0,
2051                 .enable_shift = 26,
2052                 .hd_reg = AFE_DL10_CON0,
2053                 .hd_shift = 5,
2054                 .agent_disable_reg = AUDIO_TOP_CON5,
2055                 .agent_disable_shift = 26,
2056                 .ch_num_reg = AFE_DL10_CON0,
2057                 .ch_num_shift = 0,
2058                 .ch_num_maskbit = 0x1f,
2059                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2060                 .msb_shift = 26,
2061                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2062                 .msb_end_shift = 26,
2063         },
2064         [MT8188_AFE_MEMIF_DL11] = {
2065                 .name = "DL11",
2066                 .id = MT8188_AFE_MEMIF_DL11,
2067                 .reg_ofs_base = AFE_DL11_BASE,
2068                 .reg_ofs_cur = AFE_DL11_CUR,
2069                 .reg_ofs_end = AFE_DL11_END,
2070                 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,
2071                 .fs_shift = 25,
2072                 .fs_maskbit = 0x1f,
2073                 .mono_reg = -1,
2074                 .mono_shift = 0,
2075                 .int_odd_flag_reg = -1,
2076                 .int_odd_flag_shift = 0,
2077                 .enable_reg = AFE_DAC_CON0,
2078                 .enable_shift = 27,
2079                 .hd_reg = AFE_DL11_CON0,
2080                 .hd_shift = 7,
2081                 .agent_disable_reg = AUDIO_TOP_CON5,
2082                 .agent_disable_shift = 27,
2083                 .ch_num_reg = AFE_DL11_CON0,
2084                 .ch_num_shift = 0,
2085                 .ch_num_maskbit = 0x7f,
2086                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2087                 .msb_shift = 27,
2088                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2089                 .msb_end_shift = 27,
2090         },
2091         [MT8188_AFE_MEMIF_UL1] = {
2092                 .name = "UL1",
2093                 .id = MT8188_AFE_MEMIF_UL1,
2094                 .reg_ofs_base = AFE_UL1_BASE,
2095                 .reg_ofs_cur = AFE_UL1_CUR,
2096                 .reg_ofs_end = AFE_UL1_END,
2097                 .fs_reg = -1,
2098                 .fs_shift = 0,
2099                 .fs_maskbit = 0,
2100                 .mono_reg = AFE_UL1_CON0,
2101                 .mono_shift = 1,
2102                 .int_odd_flag_reg = AFE_UL1_CON0,
2103                 .int_odd_flag_shift = 0,
2104                 .enable_reg = AFE_DAC_CON0,
2105                 .enable_shift = 1,
2106                 .hd_reg = AFE_UL1_CON0,
2107                 .hd_shift = 5,
2108                 .agent_disable_reg = AUDIO_TOP_CON5,
2109                 .agent_disable_shift = 0,
2110                 .ch_num_reg = -1,
2111                 .ch_num_shift = 0,
2112                 .ch_num_maskbit = 0,
2113                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2114                 .msb_shift = 0,
2115                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2116                 .msb_end_shift = 0,
2117         },
2118         [MT8188_AFE_MEMIF_UL2] = {
2119                 .name = "UL2",
2120                 .id = MT8188_AFE_MEMIF_UL2,
2121                 .reg_ofs_base = AFE_UL2_BASE,
2122                 .reg_ofs_cur = AFE_UL2_CUR,
2123                 .reg_ofs_end = AFE_UL2_END,
2124                 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2125                 .fs_shift = 5,
2126                 .fs_maskbit = 0x1f,
2127                 .mono_reg = AFE_UL2_CON0,
2128                 .mono_shift = 1,
2129                 .int_odd_flag_reg = AFE_UL2_CON0,
2130                 .int_odd_flag_shift = 0,
2131                 .enable_reg = AFE_DAC_CON0,
2132                 .enable_shift = 2,
2133                 .hd_reg = AFE_UL2_CON0,
2134                 .hd_shift = 5,
2135                 .agent_disable_reg = AUDIO_TOP_CON5,
2136                 .agent_disable_shift = 1,
2137                 .ch_num_reg = -1,
2138                 .ch_num_shift = 0,
2139                 .ch_num_maskbit = 0,
2140                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2141                 .msb_shift = 1,
2142                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2143                 .msb_end_shift = 1,
2144         },
2145         [MT8188_AFE_MEMIF_UL3] = {
2146                 .name = "UL3",
2147                 .id = MT8188_AFE_MEMIF_UL3,
2148                 .reg_ofs_base = AFE_UL3_BASE,
2149                 .reg_ofs_cur = AFE_UL3_CUR,
2150                 .reg_ofs_end = AFE_UL3_END,
2151                 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2152                 .fs_shift = 10,
2153                 .fs_maskbit = 0x1f,
2154                 .mono_reg = AFE_UL3_CON0,
2155                 .mono_shift = 1,
2156                 .int_odd_flag_reg = AFE_UL3_CON0,
2157                 .int_odd_flag_shift = 0,
2158                 .enable_reg = AFE_DAC_CON0,
2159                 .enable_shift = 3,
2160                 .hd_reg = AFE_UL3_CON0,
2161                 .hd_shift = 5,
2162                 .agent_disable_reg = AUDIO_TOP_CON5,
2163                 .agent_disable_shift = 2,
2164                 .ch_num_reg = -1,
2165                 .ch_num_shift = 0,
2166                 .ch_num_maskbit = 0,
2167                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2168                 .msb_shift = 2,
2169                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2170                 .msb_end_shift = 2,
2171         },
2172         [MT8188_AFE_MEMIF_UL4] = {
2173                 .name = "UL4",
2174                 .id = MT8188_AFE_MEMIF_UL4,
2175                 .reg_ofs_base = AFE_UL4_BASE,
2176                 .reg_ofs_cur = AFE_UL4_CUR,
2177                 .reg_ofs_end = AFE_UL4_END,
2178                 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2179                 .fs_shift = 15,
2180                 .fs_maskbit = 0x1f,
2181                 .mono_reg = AFE_UL4_CON0,
2182                 .mono_shift = 1,
2183                 .int_odd_flag_reg = AFE_UL4_CON0,
2184                 .int_odd_flag_shift = 0,
2185                 .enable_reg = AFE_DAC_CON0,
2186                 .enable_shift = 4,
2187                 .hd_reg = AFE_UL4_CON0,
2188                 .hd_shift = 5,
2189                 .agent_disable_reg = AUDIO_TOP_CON5,
2190                 .agent_disable_shift = 3,
2191                 .ch_num_reg = -1,
2192                 .ch_num_shift = 0,
2193                 .ch_num_maskbit = 0,
2194                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2195                 .msb_shift = 3,
2196                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2197                 .msb_end_shift = 3,
2198         },
2199         [MT8188_AFE_MEMIF_UL5] = {
2200                 .name = "UL5",
2201                 .id = MT8188_AFE_MEMIF_UL5,
2202                 .reg_ofs_base = AFE_UL5_BASE,
2203                 .reg_ofs_cur = AFE_UL5_CUR,
2204                 .reg_ofs_end = AFE_UL5_END,
2205                 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,
2206                 .fs_shift = 20,
2207                 .fs_maskbit = 0x1f,
2208                 .mono_reg = AFE_UL5_CON0,
2209                 .mono_shift = 1,
2210                 .int_odd_flag_reg = AFE_UL5_CON0,
2211                 .int_odd_flag_shift = 0,
2212                 .enable_reg = AFE_DAC_CON0,
2213                 .enable_shift = 5,
2214                 .hd_reg = AFE_UL5_CON0,
2215                 .hd_shift = 5,
2216                 .agent_disable_reg = AUDIO_TOP_CON5,
2217                 .agent_disable_shift = 4,
2218                 .ch_num_reg = -1,
2219                 .ch_num_shift = 0,
2220                 .ch_num_maskbit = 0,
2221                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2222                 .msb_shift = 4,
2223                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2224                 .msb_end_shift = 4,
2225         },
2226         [MT8188_AFE_MEMIF_UL6] = {
2227                 .name = "UL6",
2228                 .id = MT8188_AFE_MEMIF_UL6,
2229                 .reg_ofs_base = AFE_UL6_BASE,
2230                 .reg_ofs_cur = AFE_UL6_CUR,
2231                 .reg_ofs_end = AFE_UL6_END,
2232                 .fs_reg = -1,
2233                 .fs_shift = 0,
2234                 .fs_maskbit = 0,
2235                 .mono_reg = AFE_UL6_CON0,
2236                 .mono_shift = 1,
2237                 .int_odd_flag_reg = AFE_UL6_CON0,
2238                 .int_odd_flag_shift = 0,
2239                 .enable_reg = AFE_DAC_CON0,
2240                 .enable_shift = 6,
2241                 .hd_reg = AFE_UL6_CON0,
2242                 .hd_shift = 5,
2243                 .agent_disable_reg = AUDIO_TOP_CON5,
2244                 .agent_disable_shift = 5,
2245                 .ch_num_reg = -1,
2246                 .ch_num_shift = 0,
2247                 .ch_num_maskbit = 0,
2248                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2249                 .msb_shift = 5,
2250                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2251                 .msb_end_shift = 5,
2252         },
2253         [MT8188_AFE_MEMIF_UL8] = {
2254                 .name = "UL8",
2255                 .id = MT8188_AFE_MEMIF_UL8,
2256                 .reg_ofs_base = AFE_UL8_BASE,
2257                 .reg_ofs_cur = AFE_UL8_CUR,
2258                 .reg_ofs_end = AFE_UL8_END,
2259                 .fs_reg = AFE_MEMIF_AGENT_FS_CON3,
2260                 .fs_shift = 5,
2261                 .fs_maskbit = 0x1f,
2262                 .mono_reg = AFE_UL8_CON0,
2263                 .mono_shift = 1,
2264                 .int_odd_flag_reg = AFE_UL8_CON0,
2265                 .int_odd_flag_shift = 0,
2266                 .enable_reg = AFE_DAC_CON0,
2267                 .enable_shift = 8,
2268                 .hd_reg = AFE_UL8_CON0,
2269                 .hd_shift = 5,
2270                 .agent_disable_reg = AUDIO_TOP_CON5,
2271                 .agent_disable_shift = 7,
2272                 .ch_num_reg = -1,
2273                 .ch_num_shift = 0,
2274                 .ch_num_maskbit = 0,
2275                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2276                 .msb_shift = 7,
2277                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2278                 .msb_end_shift = 7,
2279         },
2280         [MT8188_AFE_MEMIF_UL9] = {
2281                 .name = "UL9",
2282                 .id = MT8188_AFE_MEMIF_UL9,
2283                 .reg_ofs_base = AFE_UL9_BASE,
2284                 .reg_ofs_cur = AFE_UL9_CUR,
2285                 .reg_ofs_end = AFE_UL9_END,
2286                 .fs_reg = AFE_MEMIF_AGENT_FS_CON3,
2287                 .fs_shift = 10,
2288                 .fs_maskbit = 0x1f,
2289                 .mono_reg = AFE_UL9_CON0,
2290                 .mono_shift = 1,
2291                 .int_odd_flag_reg = AFE_UL9_CON0,
2292                 .int_odd_flag_shift = 0,
2293                 .enable_reg = AFE_DAC_CON0,
2294                 .enable_shift = 9,
2295                 .hd_reg = AFE_UL9_CON0,
2296                 .hd_shift = 5,
2297                 .agent_disable_reg = AUDIO_TOP_CON5,
2298                 .agent_disable_shift = 8,
2299                 .ch_num_reg = -1,
2300                 .ch_num_shift = 0,
2301                 .ch_num_maskbit = 0,
2302                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2303                 .msb_shift = 8,
2304                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2305                 .msb_end_shift = 8,
2306         },
2307         [MT8188_AFE_MEMIF_UL10] = {
2308                 .name = "UL10",
2309                 .id = MT8188_AFE_MEMIF_UL10,
2310                 .reg_ofs_base = AFE_UL10_BASE,
2311                 .reg_ofs_cur = AFE_UL10_CUR,
2312                 .reg_ofs_end = AFE_UL10_END,
2313                 .fs_reg = AFE_MEMIF_AGENT_FS_CON3,
2314                 .fs_shift = 15,
2315                 .fs_maskbit = 0x1f,
2316                 .mono_reg = AFE_UL10_CON0,
2317                 .mono_shift = 1,
2318                 .int_odd_flag_reg = AFE_UL10_CON0,
2319                 .int_odd_flag_shift = 0,
2320                 .enable_reg = AFE_DAC_CON0,
2321                 .enable_shift = 10,
2322                 .hd_reg = AFE_UL10_CON0,
2323                 .hd_shift = 5,
2324                 .agent_disable_reg = AUDIO_TOP_CON5,
2325                 .agent_disable_shift = 9,
2326                 .ch_num_reg = -1,
2327                 .ch_num_shift = 0,
2328                 .ch_num_maskbit = 0,
2329                 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,
2330                 .msb_shift = 9,
2331                 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,
2332                 .msb_end_shift = 9,
2333         },
2334 };
2335
2336 static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = {
2337         [MT8188_AFE_IRQ_1] = {
2338                 .id = MT8188_AFE_IRQ_1,
2339                 .irq_cnt_reg = -1,
2340                 .irq_cnt_shift = 0,
2341                 .irq_cnt_maskbit = 0,
2342                 .irq_fs_reg = -1,
2343                 .irq_fs_shift = 0,
2344                 .irq_fs_maskbit = 0,
2345                 .irq_en_reg = AFE_IRQ1_CON,
2346                 .irq_en_shift = 31,
2347                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
2348                 .irq_clr_shift = 0,
2349                 .irq_status_shift = 16,
2350         },
2351         [MT8188_AFE_IRQ_2] = {
2352                 .id = MT8188_AFE_IRQ_2,
2353                 .irq_cnt_reg = -1,
2354                 .irq_cnt_shift = 0,
2355                 .irq_cnt_maskbit = 0,
2356                 .irq_fs_reg = -1,
2357                 .irq_fs_shift = 0,
2358                 .irq_fs_maskbit = 0,
2359                 .irq_en_reg = AFE_IRQ2_CON,
2360                 .irq_en_shift = 31,
2361                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
2362                 .irq_clr_shift = 1,
2363                 .irq_status_shift = 17,
2364         },
2365         [MT8188_AFE_IRQ_3] = {
2366                 .id = MT8188_AFE_IRQ_3,
2367                 .irq_cnt_reg = AFE_IRQ3_CON,
2368                 .irq_cnt_shift = 0,
2369                 .irq_cnt_maskbit = 0xffffff,
2370                 .irq_fs_reg = -1,
2371                 .irq_fs_shift = 0,
2372                 .irq_fs_maskbit = 0,
2373                 .irq_en_reg = AFE_IRQ3_CON,
2374                 .irq_en_shift = 31,
2375                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
2376                 .irq_clr_shift = 2,
2377                 .irq_status_shift = 18,
2378         },
2379         [MT8188_AFE_IRQ_8] = {
2380                 .id = MT8188_AFE_IRQ_8,
2381                 .irq_cnt_reg = -1,
2382                 .irq_cnt_shift = 0,
2383                 .irq_cnt_maskbit = 0,
2384                 .irq_fs_reg = -1,
2385                 .irq_fs_shift = 0,
2386                 .irq_fs_maskbit = 0,
2387                 .irq_en_reg = AFE_IRQ8_CON,
2388                 .irq_en_shift = 31,
2389                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
2390                 .irq_clr_shift = 7,
2391                 .irq_status_shift = 23,
2392         },
2393         [MT8188_AFE_IRQ_9] = {
2394                 .id = MT8188_AFE_IRQ_9,
2395                 .irq_cnt_reg = AFE_IRQ9_CON,
2396                 .irq_cnt_shift = 0,
2397                 .irq_cnt_maskbit = 0xffffff,
2398                 .irq_fs_reg = -1,
2399                 .irq_fs_shift = 0,
2400                 .irq_fs_maskbit = 0,
2401                 .irq_en_reg = AFE_IRQ9_CON,
2402                 .irq_en_shift = 31,
2403                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
2404                 .irq_clr_shift = 8,
2405                 .irq_status_shift = 24,
2406         },
2407         [MT8188_AFE_IRQ_10] = {
2408                 .id = MT8188_AFE_IRQ_10,
2409                 .irq_cnt_reg = -1,
2410                 .irq_cnt_shift = 0,
2411                 .irq_cnt_maskbit = 0,
2412                 .irq_fs_reg = -1,
2413                 .irq_fs_shift = 0,
2414                 .irq_fs_maskbit = 0,
2415                 .irq_en_reg = AFE_IRQ10_CON,
2416                 .irq_en_shift = 31,
2417                 .irq_clr_reg = AFE_IRQ_MCU_CLR,
2418                 .irq_clr_shift = 9,
2419                 .irq_status_shift = 25,
2420         },
2421         [MT8188_AFE_IRQ_13] = {
2422                 .id = MT8188_AFE_IRQ_13,
2423                 .irq_cnt_reg = ASYS_IRQ1_CON,
2424                 .irq_cnt_shift = 0,
2425                 .irq_cnt_maskbit = 0xffffff,
2426                 .irq_fs_reg = ASYS_IRQ1_CON,
2427                 .irq_fs_shift = 24,
2428                 .irq_fs_maskbit = 0x1ffff,
2429                 .irq_en_reg = ASYS_IRQ1_CON,
2430                 .irq_en_shift = 31,
2431                 .irq_clr_reg =  ASYS_IRQ_CLR,
2432                 .irq_clr_shift = 0,
2433                 .irq_status_shift = 0,
2434         },
2435         [MT8188_AFE_IRQ_14] = {
2436                 .id = MT8188_AFE_IRQ_14,
2437                 .irq_cnt_reg = ASYS_IRQ2_CON,
2438                 .irq_cnt_shift = 0,
2439                 .irq_cnt_maskbit = 0xffffff,
2440                 .irq_fs_reg = ASYS_IRQ2_CON,
2441                 .irq_fs_shift = 24,
2442                 .irq_fs_maskbit = 0x1ffff,
2443                 .irq_en_reg = ASYS_IRQ2_CON,
2444                 .irq_en_shift = 31,
2445                 .irq_clr_reg =  ASYS_IRQ_CLR,
2446                 .irq_clr_shift = 1,
2447                 .irq_status_shift = 1,
2448         },
2449         [MT8188_AFE_IRQ_15] = {
2450                 .id = MT8188_AFE_IRQ_15,
2451                 .irq_cnt_reg = ASYS_IRQ3_CON,
2452                 .irq_cnt_shift = 0,
2453                 .irq_cnt_maskbit = 0xffffff,
2454                 .irq_fs_reg = ASYS_IRQ3_CON,
2455                 .irq_fs_shift = 24,
2456                 .irq_fs_maskbit = 0x1ffff,
2457                 .irq_en_reg = ASYS_IRQ3_CON,
2458                 .irq_en_shift = 31,
2459                 .irq_clr_reg =  ASYS_IRQ_CLR,
2460                 .irq_clr_shift = 2,
2461                 .irq_status_shift = 2,
2462         },
2463         [MT8188_AFE_IRQ_16] = {
2464                 .id = MT8188_AFE_IRQ_16,
2465                 .irq_cnt_reg = ASYS_IRQ4_CON,
2466                 .irq_cnt_shift = 0,
2467                 .irq_cnt_maskbit = 0xffffff,
2468                 .irq_fs_reg = ASYS_IRQ4_CON,
2469                 .irq_fs_shift = 24,
2470                 .irq_fs_maskbit = 0x1ffff,
2471                 .irq_en_reg = ASYS_IRQ4_CON,
2472                 .irq_en_shift = 31,
2473                 .irq_clr_reg =  ASYS_IRQ_CLR,
2474                 .irq_clr_shift = 3,
2475                 .irq_status_shift = 3,
2476         },
2477         [MT8188_AFE_IRQ_17] = {
2478                 .id = MT8188_AFE_IRQ_17,
2479                 .irq_cnt_reg = ASYS_IRQ5_CON,
2480                 .irq_cnt_shift = 0,
2481                 .irq_cnt_maskbit = 0xffffff,
2482                 .irq_fs_reg = ASYS_IRQ5_CON,
2483                 .irq_fs_shift = 24,
2484                 .irq_fs_maskbit = 0x1ffff,
2485                 .irq_en_reg = ASYS_IRQ5_CON,
2486                 .irq_en_shift = 31,
2487                 .irq_clr_reg =  ASYS_IRQ_CLR,
2488                 .irq_clr_shift = 4,
2489                 .irq_status_shift = 4,
2490         },
2491         [MT8188_AFE_IRQ_18] = {
2492                 .id = MT8188_AFE_IRQ_18,
2493                 .irq_cnt_reg = ASYS_IRQ6_CON,
2494                 .irq_cnt_shift = 0,
2495                 .irq_cnt_maskbit = 0xffffff,
2496                 .irq_fs_reg = ASYS_IRQ6_CON,
2497                 .irq_fs_shift = 24,
2498                 .irq_fs_maskbit = 0x1ffff,
2499                 .irq_en_reg = ASYS_IRQ6_CON,
2500                 .irq_en_shift = 31,
2501                 .irq_clr_reg =  ASYS_IRQ_CLR,
2502                 .irq_clr_shift = 5,
2503                 .irq_status_shift = 5,
2504         },
2505         [MT8188_AFE_IRQ_19] = {
2506                 .id = MT8188_AFE_IRQ_19,
2507                 .irq_cnt_reg = ASYS_IRQ7_CON,
2508                 .irq_cnt_shift = 0,
2509                 .irq_cnt_maskbit = 0xffffff,
2510                 .irq_fs_reg = ASYS_IRQ7_CON,
2511                 .irq_fs_shift = 24,
2512                 .irq_fs_maskbit = 0x1ffff,
2513                 .irq_en_reg = ASYS_IRQ7_CON,
2514                 .irq_en_shift = 31,
2515                 .irq_clr_reg =  ASYS_IRQ_CLR,
2516                 .irq_clr_shift = 6,
2517                 .irq_status_shift = 6,
2518         },
2519         [MT8188_AFE_IRQ_20] = {
2520                 .id = MT8188_AFE_IRQ_20,
2521                 .irq_cnt_reg = ASYS_IRQ8_CON,
2522                 .irq_cnt_shift = 0,
2523                 .irq_cnt_maskbit = 0xffffff,
2524                 .irq_fs_reg = ASYS_IRQ8_CON,
2525                 .irq_fs_shift = 24,
2526                 .irq_fs_maskbit = 0x1ffff,
2527                 .irq_en_reg = ASYS_IRQ8_CON,
2528                 .irq_en_shift = 31,
2529                 .irq_clr_reg =  ASYS_IRQ_CLR,
2530                 .irq_clr_shift = 7,
2531                 .irq_status_shift = 7,
2532         },
2533         [MT8188_AFE_IRQ_21] = {
2534                 .id = MT8188_AFE_IRQ_21,
2535                 .irq_cnt_reg = ASYS_IRQ9_CON,
2536                 .irq_cnt_shift = 0,
2537                 .irq_cnt_maskbit = 0xffffff,
2538                 .irq_fs_reg = ASYS_IRQ9_CON,
2539                 .irq_fs_shift = 24,
2540                 .irq_fs_maskbit = 0x1ffff,
2541                 .irq_en_reg = ASYS_IRQ9_CON,
2542                 .irq_en_shift = 31,
2543                 .irq_clr_reg =  ASYS_IRQ_CLR,
2544                 .irq_clr_shift = 8,
2545                 .irq_status_shift = 8,
2546         },
2547         [MT8188_AFE_IRQ_22] = {
2548                 .id = MT8188_AFE_IRQ_22,
2549                 .irq_cnt_reg = ASYS_IRQ10_CON,
2550                 .irq_cnt_shift = 0,
2551                 .irq_cnt_maskbit = 0xffffff,
2552                 .irq_fs_reg = ASYS_IRQ10_CON,
2553                 .irq_fs_shift = 24,
2554                 .irq_fs_maskbit = 0x1ffff,
2555                 .irq_en_reg = ASYS_IRQ10_CON,
2556                 .irq_en_shift = 31,
2557                 .irq_clr_reg =  ASYS_IRQ_CLR,
2558                 .irq_clr_shift = 9,
2559                 .irq_status_shift = 9,
2560         },
2561         [MT8188_AFE_IRQ_23] = {
2562                 .id = MT8188_AFE_IRQ_23,
2563                 .irq_cnt_reg = ASYS_IRQ11_CON,
2564                 .irq_cnt_shift = 0,
2565                 .irq_cnt_maskbit = 0xffffff,
2566                 .irq_fs_reg = ASYS_IRQ11_CON,
2567                 .irq_fs_shift = 24,
2568                 .irq_fs_maskbit = 0x1ffff,
2569                 .irq_en_reg = ASYS_IRQ11_CON,
2570                 .irq_en_shift = 31,
2571                 .irq_clr_reg =  ASYS_IRQ_CLR,
2572                 .irq_clr_shift = 10,
2573                 .irq_status_shift = 10,
2574         },
2575         [MT8188_AFE_IRQ_24] = {
2576                 .id = MT8188_AFE_IRQ_24,
2577                 .irq_cnt_reg = ASYS_IRQ12_CON,
2578                 .irq_cnt_shift = 0,
2579                 .irq_cnt_maskbit = 0xffffff,
2580                 .irq_fs_reg = ASYS_IRQ12_CON,
2581                 .irq_fs_shift = 24,
2582                 .irq_fs_maskbit = 0x1ffff,
2583                 .irq_en_reg = ASYS_IRQ12_CON,
2584                 .irq_en_shift = 31,
2585                 .irq_clr_reg =  ASYS_IRQ_CLR,
2586                 .irq_clr_shift = 11,
2587                 .irq_status_shift = 11,
2588         },
2589         [MT8188_AFE_IRQ_25] = {
2590                 .id = MT8188_AFE_IRQ_25,
2591                 .irq_cnt_reg = ASYS_IRQ13_CON,
2592                 .irq_cnt_shift = 0,
2593                 .irq_cnt_maskbit = 0xffffff,
2594                 .irq_fs_reg = ASYS_IRQ13_CON,
2595                 .irq_fs_shift = 24,
2596                 .irq_fs_maskbit = 0x1ffff,
2597                 .irq_en_reg = ASYS_IRQ13_CON,
2598                 .irq_en_shift = 31,
2599                 .irq_clr_reg =  ASYS_IRQ_CLR,
2600                 .irq_clr_shift = 12,
2601                 .irq_status_shift = 12,
2602         },
2603         [MT8188_AFE_IRQ_26] = {
2604                 .id = MT8188_AFE_IRQ_26,
2605                 .irq_cnt_reg = ASYS_IRQ14_CON,
2606                 .irq_cnt_shift = 0,
2607                 .irq_cnt_maskbit = 0xffffff,
2608                 .irq_fs_reg = ASYS_IRQ14_CON,
2609                 .irq_fs_shift = 24,
2610                 .irq_fs_maskbit = 0x1ffff,
2611                 .irq_en_reg = ASYS_IRQ14_CON,
2612                 .irq_en_shift = 31,
2613                 .irq_clr_reg =  ASYS_IRQ_CLR,
2614                 .irq_clr_shift = 13,
2615                 .irq_status_shift = 13,
2616         },
2617         [MT8188_AFE_IRQ_27] = {
2618                 .id = MT8188_AFE_IRQ_27,
2619                 .irq_cnt_reg = ASYS_IRQ15_CON,
2620                 .irq_cnt_shift = 0,
2621                 .irq_cnt_maskbit = 0xffffff,
2622                 .irq_fs_reg = ASYS_IRQ15_CON,
2623                 .irq_fs_shift = 24,
2624                 .irq_fs_maskbit = 0x1ffff,
2625                 .irq_en_reg = ASYS_IRQ15_CON,
2626                 .irq_en_shift = 31,
2627                 .irq_clr_reg =  ASYS_IRQ_CLR,
2628                 .irq_clr_shift = 14,
2629                 .irq_status_shift = 14,
2630         },
2631         [MT8188_AFE_IRQ_28] = {
2632                 .id = MT8188_AFE_IRQ_28,
2633                 .irq_cnt_reg = ASYS_IRQ16_CON,
2634                 .irq_cnt_shift = 0,
2635                 .irq_cnt_maskbit = 0xffffff,
2636                 .irq_fs_reg = ASYS_IRQ16_CON,
2637                 .irq_fs_shift = 24,
2638                 .irq_fs_maskbit = 0x1ffff,
2639                 .irq_en_reg = ASYS_IRQ16_CON,
2640                 .irq_en_shift = 31,
2641                 .irq_clr_reg =  ASYS_IRQ_CLR,
2642                 .irq_clr_shift = 15,
2643                 .irq_status_shift = 15,
2644         },
2645 };
2646
2647 static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = {
2648         [MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13,
2649         [MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14,
2650         [MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15,
2651         [MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1,
2652         [MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16,
2653         [MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17,
2654         [MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18,
2655         [MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3,
2656         [MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19,
2657         [MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20,
2658         [MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21,
2659         [MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22,
2660         [MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9,
2661         [MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23,
2662         [MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24,
2663         [MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25,
2664 };
2665
2666 static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
2667 {
2668         /* these auto-gen reg has read-only bit, so put it as volatile */
2669         /* volatile reg cannot be cached, so cannot be set when power off */
2670         switch (reg) {
2671         case AUDIO_TOP_CON0:
2672         case AUDIO_TOP_CON1:
2673         case AUDIO_TOP_CON3:
2674         case AUDIO_TOP_CON4:
2675         case AUDIO_TOP_CON5:
2676         case AUDIO_TOP_CON6:
2677         case ASYS_IRQ_CLR:
2678         case ASYS_IRQ_STATUS:
2679         case ASYS_IRQ_MON1:
2680         case ASYS_IRQ_MON2:
2681         case AFE_IRQ_MCU_CLR:
2682         case AFE_IRQ_STATUS:
2683         case AFE_IRQ3_CON_MON:
2684         case AFE_IRQ_MCU_MON2:
2685         case ADSP_IRQ_STATUS:
2686         case AUDIO_TOP_STA0:
2687         case AUDIO_TOP_STA1:
2688         case AFE_GAIN1_CUR:
2689         case AFE_GAIN2_CUR:
2690         case AFE_IEC_BURST_INFO:
2691         case AFE_IEC_CHL_STAT0:
2692         case AFE_IEC_CHL_STAT1:
2693         case AFE_IEC_CHR_STAT0:
2694         case AFE_IEC_CHR_STAT1:
2695         case AFE_SPDIFIN_CHSTS1:
2696         case AFE_SPDIFIN_CHSTS2:
2697         case AFE_SPDIFIN_CHSTS3:
2698         case AFE_SPDIFIN_CHSTS4:
2699         case AFE_SPDIFIN_CHSTS5:
2700         case AFE_SPDIFIN_CHSTS6:
2701         case AFE_SPDIFIN_DEBUG1:
2702         case AFE_SPDIFIN_DEBUG2:
2703         case AFE_SPDIFIN_DEBUG3:
2704         case AFE_SPDIFIN_DEBUG4:
2705         case AFE_SPDIFIN_EC:
2706         case AFE_SPDIFIN_CKLOCK_CFG:
2707         case AFE_SPDIFIN_BR_DBG1:
2708         case AFE_SPDIFIN_CKFBDIV:
2709         case AFE_SPDIFIN_INT_EXT:
2710         case AFE_SPDIFIN_INT_EXT2:
2711         case SPDIFIN_FREQ_STATUS:
2712         case SPDIFIN_USERCODE1:
2713         case SPDIFIN_USERCODE2:
2714         case SPDIFIN_USERCODE3:
2715         case SPDIFIN_USERCODE4:
2716         case SPDIFIN_USERCODE5:
2717         case SPDIFIN_USERCODE6:
2718         case SPDIFIN_USERCODE7:
2719         case SPDIFIN_USERCODE8:
2720         case SPDIFIN_USERCODE9:
2721         case SPDIFIN_USERCODE10:
2722         case SPDIFIN_USERCODE11:
2723         case SPDIFIN_USERCODE12:
2724         case AFE_LINEIN_APLL_TUNER_MON:
2725         case AFE_EARC_APLL_TUNER_MON:
2726         case AFE_CM0_MON:
2727         case AFE_CM1_MON:
2728         case AFE_CM2_MON:
2729         case AFE_MPHONE_MULTI_DET_MON0:
2730         case AFE_MPHONE_MULTI_DET_MON1:
2731         case AFE_MPHONE_MULTI_DET_MON2:
2732         case AFE_MPHONE_MULTI2_DET_MON0:
2733         case AFE_MPHONE_MULTI2_DET_MON1:
2734         case AFE_MPHONE_MULTI2_DET_MON2:
2735         case AFE_ADDA_MTKAIF_MON0:
2736         case AFE_ADDA_MTKAIF_MON1:
2737         case AFE_AUD_PAD_TOP:
2738         case AFE_ADDA6_MTKAIF_MON0:
2739         case AFE_ADDA6_MTKAIF_MON1:
2740         case AFE_ADDA6_SRC_DEBUG_MON0:
2741         case AFE_ADDA6_UL_SRC_MON0:
2742         case AFE_ADDA6_UL_SRC_MON1:
2743         case AFE_ASRC11_NEW_CON8:
2744         case AFE_ASRC11_NEW_CON9:
2745         case AFE_ASRC12_NEW_CON8:
2746         case AFE_ASRC12_NEW_CON9:
2747         case AFE_LRCK_CNT:
2748         case AFE_DAC_MON0:
2749         case AFE_DL2_CUR:
2750         case AFE_DL3_CUR:
2751         case AFE_DL6_CUR:
2752         case AFE_DL7_CUR:
2753         case AFE_DL8_CUR:
2754         case AFE_DL10_CUR:
2755         case AFE_DL11_CUR:
2756         case AFE_UL1_CUR:
2757         case AFE_UL2_CUR:
2758         case AFE_UL3_CUR:
2759         case AFE_UL4_CUR:
2760         case AFE_UL5_CUR:
2761         case AFE_UL6_CUR:
2762         case AFE_UL8_CUR:
2763         case AFE_UL9_CUR:
2764         case AFE_UL10_CUR:
2765         case AFE_DL8_CHK_SUM1:
2766         case AFE_DL8_CHK_SUM2:
2767         case AFE_DL8_CHK_SUM3:
2768         case AFE_DL8_CHK_SUM4:
2769         case AFE_DL8_CHK_SUM5:
2770         case AFE_DL8_CHK_SUM6:
2771         case AFE_DL10_CHK_SUM1:
2772         case AFE_DL10_CHK_SUM2:
2773         case AFE_DL10_CHK_SUM3:
2774         case AFE_DL10_CHK_SUM4:
2775         case AFE_DL10_CHK_SUM5:
2776         case AFE_DL10_CHK_SUM6:
2777         case AFE_DL11_CHK_SUM1:
2778         case AFE_DL11_CHK_SUM2:
2779         case AFE_DL11_CHK_SUM3:
2780         case AFE_DL11_CHK_SUM4:
2781         case AFE_DL11_CHK_SUM5:
2782         case AFE_DL11_CHK_SUM6:
2783         case AFE_UL1_CHK_SUM1:
2784         case AFE_UL1_CHK_SUM2:
2785         case AFE_UL2_CHK_SUM1:
2786         case AFE_UL2_CHK_SUM2:
2787         case AFE_UL3_CHK_SUM1:
2788         case AFE_UL3_CHK_SUM2:
2789         case AFE_UL4_CHK_SUM1:
2790         case AFE_UL4_CHK_SUM2:
2791         case AFE_UL5_CHK_SUM1:
2792         case AFE_UL5_CHK_SUM2:
2793         case AFE_UL6_CHK_SUM1:
2794         case AFE_UL6_CHK_SUM2:
2795         case AFE_UL8_CHK_SUM1:
2796         case AFE_UL8_CHK_SUM2:
2797         case AFE_DL2_CHK_SUM1:
2798         case AFE_DL2_CHK_SUM2:
2799         case AFE_DL3_CHK_SUM1:
2800         case AFE_DL3_CHK_SUM2:
2801         case AFE_DL6_CHK_SUM1:
2802         case AFE_DL6_CHK_SUM2:
2803         case AFE_DL7_CHK_SUM1:
2804         case AFE_DL7_CHK_SUM2:
2805         case AFE_UL9_CHK_SUM1:
2806         case AFE_UL9_CHK_SUM2:
2807         case AFE_BUS_MON1:
2808         case UL1_MOD2AGT_CNT_LAT:
2809         case UL2_MOD2AGT_CNT_LAT:
2810         case UL3_MOD2AGT_CNT_LAT:
2811         case UL4_MOD2AGT_CNT_LAT:
2812         case UL5_MOD2AGT_CNT_LAT:
2813         case UL6_MOD2AGT_CNT_LAT:
2814         case UL8_MOD2AGT_CNT_LAT:
2815         case UL9_MOD2AGT_CNT_LAT:
2816         case UL10_MOD2AGT_CNT_LAT:
2817         case AFE_MEMIF_BUF_FULL_MON:
2818         case AFE_MEMIF_BUF_MON1:
2819         case AFE_MEMIF_BUF_MON3:
2820         case AFE_MEMIF_BUF_MON4:
2821         case AFE_MEMIF_BUF_MON5:
2822         case AFE_MEMIF_BUF_MON6:
2823         case AFE_MEMIF_BUF_MON7:
2824         case AFE_MEMIF_BUF_MON8:
2825         case AFE_MEMIF_BUF_MON9:
2826         case AFE_MEMIF_BUF_MON10:
2827         case DL2_AGENT2MODULE_CNT:
2828         case DL3_AGENT2MODULE_CNT:
2829         case DL6_AGENT2MODULE_CNT:
2830         case DL7_AGENT2MODULE_CNT:
2831         case DL8_AGENT2MODULE_CNT:
2832         case DL10_AGENT2MODULE_CNT:
2833         case DL11_AGENT2MODULE_CNT:
2834         case UL1_MODULE2AGENT_CNT:
2835         case UL2_MODULE2AGENT_CNT:
2836         case UL3_MODULE2AGENT_CNT:
2837         case UL4_MODULE2AGENT_CNT:
2838         case UL5_MODULE2AGENT_CNT:
2839         case UL6_MODULE2AGENT_CNT:
2840         case UL8_MODULE2AGENT_CNT:
2841         case UL9_MODULE2AGENT_CNT:
2842         case UL10_MODULE2AGENT_CNT:
2843         case AFE_DMIC0_SRC_DEBUG_MON0:
2844         case AFE_DMIC0_UL_SRC_MON0:
2845         case AFE_DMIC0_UL_SRC_MON1:
2846         case AFE_DMIC1_SRC_DEBUG_MON0:
2847         case AFE_DMIC1_UL_SRC_MON0:
2848         case AFE_DMIC1_UL_SRC_MON1:
2849         case AFE_DMIC2_SRC_DEBUG_MON0:
2850         case AFE_DMIC2_UL_SRC_MON0:
2851         case AFE_DMIC2_UL_SRC_MON1:
2852         case AFE_DMIC3_SRC_DEBUG_MON0:
2853         case AFE_DMIC3_UL_SRC_MON0:
2854         case AFE_DMIC3_UL_SRC_MON1:
2855         case DMIC_GAIN1_CUR:
2856         case DMIC_GAIN2_CUR:
2857         case DMIC_GAIN3_CUR:
2858         case DMIC_GAIN4_CUR:
2859         case ETDM_IN1_MONITOR:
2860         case ETDM_IN2_MONITOR:
2861         case ETDM_OUT1_MONITOR:
2862         case ETDM_OUT2_MONITOR:
2863         case ETDM_OUT3_MONITOR:
2864         case AFE_ADDA_SRC_DEBUG_MON0:
2865         case AFE_ADDA_SRC_DEBUG_MON1:
2866         case AFE_ADDA_DL_SDM_FIFO_MON:
2867         case AFE_ADDA_DL_SRC_LCH_MON:
2868         case AFE_ADDA_DL_SRC_RCH_MON:
2869         case AFE_ADDA_DL_SDM_OUT_MON:
2870         case AFE_GASRC0_NEW_CON8:
2871         case AFE_GASRC0_NEW_CON9:
2872         case AFE_GASRC0_NEW_CON12:
2873         case AFE_GASRC1_NEW_CON8:
2874         case AFE_GASRC1_NEW_CON9:
2875         case AFE_GASRC1_NEW_CON12:
2876         case AFE_GASRC2_NEW_CON8:
2877         case AFE_GASRC2_NEW_CON9:
2878         case AFE_GASRC2_NEW_CON12:
2879         case AFE_GASRC3_NEW_CON8:
2880         case AFE_GASRC3_NEW_CON9:
2881         case AFE_GASRC3_NEW_CON12:
2882         case AFE_GASRC4_NEW_CON8:
2883         case AFE_GASRC4_NEW_CON9:
2884         case AFE_GASRC4_NEW_CON12:
2885         case AFE_GASRC5_NEW_CON8:
2886         case AFE_GASRC5_NEW_CON9:
2887         case AFE_GASRC5_NEW_CON12:
2888         case AFE_GASRC6_NEW_CON8:
2889         case AFE_GASRC6_NEW_CON9:
2890         case AFE_GASRC6_NEW_CON12:
2891         case AFE_GASRC7_NEW_CON8:
2892         case AFE_GASRC7_NEW_CON9:
2893         case AFE_GASRC7_NEW_CON12:
2894         case AFE_GASRC8_NEW_CON8:
2895         case AFE_GASRC8_NEW_CON9:
2896         case AFE_GASRC8_NEW_CON12:
2897         case AFE_GASRC9_NEW_CON8:
2898         case AFE_GASRC9_NEW_CON9:
2899         case AFE_GASRC9_NEW_CON12:
2900         case AFE_GASRC10_NEW_CON8:
2901         case AFE_GASRC10_NEW_CON9:
2902         case AFE_GASRC10_NEW_CON12:
2903         case AFE_GASRC11_NEW_CON8:
2904         case AFE_GASRC11_NEW_CON9:
2905         case AFE_GASRC11_NEW_CON12:
2906                 return true;
2907         default:
2908                 return false;
2909         };
2910 }
2911
2912 static const struct regmap_config mt8188_afe_regmap_config = {
2913         .reg_bits = 32,
2914         .reg_stride = 4,
2915         .val_bits = 32,
2916         .volatile_reg = mt8188_is_volatile_reg,
2917         .max_register = AFE_MAX_REGISTER,
2918         .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
2919         .cache_type = REGCACHE_FLAT,
2920 };
2921
2922 #define AFE_IRQ_CLR_BITS (0x387)
2923 #define ASYS_IRQ_CLR_BITS (0xffff)
2924
2925 static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id)
2926 {
2927         struct mtk_base_afe *afe = dev_id;
2928         unsigned int val = 0;
2929         unsigned int asys_irq_clr_bits = 0;
2930         unsigned int afe_irq_clr_bits = 0;
2931         unsigned int irq_status_bits = 0;
2932         unsigned int irq_clr_bits = 0;
2933         unsigned int mcu_irq_mask = 0;
2934         int i = 0;
2935         int ret = 0;
2936
2937         ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);
2938         if (ret) {
2939                 dev_err(afe->dev, "%s irq status err\n", __func__);
2940                 afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
2941                 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
2942                 goto err_irq;
2943         }
2944
2945         ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);
2946         if (ret) {
2947                 dev_err(afe->dev, "%s read irq mask err\n", __func__);
2948                 afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
2949                 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
2950                 goto err_irq;
2951         }
2952
2953         /* only clr cpu irq */
2954         val &= mcu_irq_mask;
2955
2956         for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) {
2957                 struct mtk_base_afe_memif *memif = &afe->memif[i];
2958                 struct mtk_base_irq_data const *irq_data;
2959
2960                 if (memif->irq_usage < 0)
2961                         continue;
2962
2963                 irq_data = afe->irqs[memif->irq_usage].irq_data;
2964
2965                 irq_status_bits = BIT(irq_data->irq_status_shift);
2966                 irq_clr_bits = BIT(irq_data->irq_clr_shift);
2967
2968                 if (!(val & irq_status_bits))
2969                         continue;
2970
2971                 if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)
2972                         asys_irq_clr_bits |= irq_clr_bits;
2973                 else
2974                         afe_irq_clr_bits |= irq_clr_bits;
2975
2976                 snd_pcm_period_elapsed(memif->substream);
2977         }
2978
2979 err_irq:
2980         /* clear irq */
2981         if (asys_irq_clr_bits)
2982                 regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);
2983         if (afe_irq_clr_bits)
2984                 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);
2985
2986         return IRQ_HANDLED;
2987 }
2988
2989 static int mt8188_afe_runtime_suspend(struct device *dev)
2990 {
2991         struct mtk_base_afe *afe = dev_get_drvdata(dev);
2992         struct mt8188_afe_private *afe_priv = afe->platform_priv;
2993
2994         if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
2995                 goto skip_regmap;
2996
2997         mt8188_afe_disable_main_clock(afe);
2998
2999         regcache_cache_only(afe->regmap, true);
3000         regcache_mark_dirty(afe->regmap);
3001
3002 skip_regmap:
3003         mt8188_afe_disable_reg_rw_clk(afe);
3004
3005         return 0;
3006 }
3007
3008 static int mt8188_afe_runtime_resume(struct device *dev)
3009 {
3010         struct mtk_base_afe *afe = dev_get_drvdata(dev);
3011         struct mt8188_afe_private *afe_priv = afe->platform_priv;
3012         struct arm_smccc_res res;
3013
3014         arm_smccc_smc(MTK_SIP_AUDIO_CONTROL,
3015                       MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS,
3016                       0, 0, 0, 0, 0, 0, &res);
3017
3018         mt8188_afe_enable_reg_rw_clk(afe);
3019
3020         if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
3021                 goto skip_regmap;
3022
3023         regcache_cache_only(afe->regmap, false);
3024         regcache_sync(afe->regmap);
3025
3026         mt8188_afe_enable_main_clock(afe);
3027 skip_regmap:
3028         return 0;
3029 }
3030
3031 static int mt8188_afe_component_probe(struct snd_soc_component *component)
3032 {
3033         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
3034         int ret;
3035
3036         snd_soc_component_init_regmap(component, afe->regmap);
3037
3038         ret = mtk_afe_add_sub_dai_control(component);
3039
3040         return ret;
3041 }
3042
3043 static const struct snd_soc_component_driver mt8188_afe_component = {
3044         .name = AFE_PCM_NAME,
3045         .pointer       = mtk_afe_pcm_pointer,
3046         .pcm_construct = mtk_afe_pcm_new,
3047         .probe         = mt8188_afe_component_probe,
3048 };
3049
3050 static int init_memif_priv_data(struct mtk_base_afe *afe)
3051 {
3052         struct mt8188_afe_private *afe_priv = afe->platform_priv;
3053         struct mtk_dai_memif_priv *memif_priv;
3054         int i;
3055
3056         for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) {
3057                 memif_priv = devm_kzalloc(afe->dev,
3058                                           sizeof(struct mtk_dai_memif_priv),
3059                                           GFP_KERNEL);
3060                 if (!memif_priv)
3061                         return -ENOMEM;
3062
3063                 afe_priv->dai_priv[i] = memif_priv;
3064         }
3065
3066         return 0;
3067 }
3068
3069 static int mt8188_dai_memif_register(struct mtk_base_afe *afe)
3070 {
3071         struct mtk_base_afe_dai *dai;
3072
3073         dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
3074         if (!dai)
3075                 return -ENOMEM;
3076
3077         list_add(&dai->list, &afe->sub_dais);
3078
3079         dai->dai_drivers = mt8188_memif_dai_driver;
3080         dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver);
3081
3082         dai->dapm_widgets = mt8188_memif_widgets;
3083         dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets);
3084         dai->dapm_routes = mt8188_memif_routes;
3085         dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes);
3086         dai->controls = mt8188_memif_controls;
3087         dai->num_controls = ARRAY_SIZE(mt8188_memif_controls);
3088
3089         return init_memif_priv_data(afe);
3090 }
3091
3092 typedef int (*dai_register_cb)(struct mtk_base_afe *);
3093 static const dai_register_cb dai_register_cbs[] = {
3094         mt8188_dai_adda_register,
3095         mt8188_dai_etdm_register,
3096         mt8188_dai_pcm_register,
3097         mt8188_dai_memif_register,
3098 };
3099
3100 static const struct reg_sequence mt8188_afe_reg_defaults[] = {
3101         { AFE_IRQ_MASK, 0x387ffff },
3102         { AFE_IRQ3_CON, BIT(30) },
3103         { AFE_IRQ9_CON, BIT(30) },
3104         { ETDM_IN1_CON4, 0x12000100 },
3105         { ETDM_IN2_CON4, 0x12000100 },
3106 };
3107
3108 static const struct reg_sequence mt8188_cg_patch[] = {
3109         { AUDIO_TOP_CON0, 0xfffffffb },
3110         { AUDIO_TOP_CON1, 0xfffffff8 },
3111 };
3112
3113 static int mt8188_afe_init_registers(struct mtk_base_afe *afe)
3114 {
3115         return regmap_multi_reg_write(afe->regmap,
3116                                       mt8188_afe_reg_defaults,
3117                                       ARRAY_SIZE(mt8188_afe_reg_defaults));
3118 }
3119
3120 static int mt8188_afe_parse_of(struct mtk_base_afe *afe,
3121                                struct device_node *np)
3122 {
3123 #if IS_ENABLED(CONFIG_SND_SOC_MT6359)
3124         struct mt8188_afe_private *afe_priv = afe->platform_priv;
3125
3126         afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
3127                                                              "mediatek,topckgen");
3128         if (IS_ERR(afe_priv->topckgen))
3129                 return dev_err_probe(afe->dev,  PTR_ERR(afe_priv->topckgen),
3130                                      "%s() Cannot find topckgen controller\n",
3131                                      __func__);
3132 #endif
3133         return 0;
3134 }
3135
3136 static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
3137 {
3138         struct mtk_base_afe *afe;
3139         struct mt8188_afe_private *afe_priv;
3140         struct device *dev;
3141         struct reset_control *rstc;
3142         int i, irq_id, ret;
3143
3144         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
3145         if (ret)
3146                 return ret;
3147
3148         afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
3149         if (!afe)
3150                 return -ENOMEM;
3151
3152         afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
3153                                           GFP_KERNEL);
3154         if (!afe->platform_priv)
3155                 return -ENOMEM;
3156
3157         afe_priv = afe->platform_priv;
3158         afe->dev = &pdev->dev;
3159         dev = afe->dev;
3160
3161         afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
3162         if (IS_ERR(afe->base_addr))
3163                 return dev_err_probe(dev, PTR_ERR(afe->base_addr),
3164                                      "AFE base_addr not found\n");
3165
3166         /* reset controller to reset audio regs before regmap cache */
3167         rstc = devm_reset_control_get_exclusive(dev, "audiosys");
3168         if (IS_ERR(rstc))
3169                 return dev_err_probe(dev, PTR_ERR(rstc),
3170                                      "could not get audiosys reset\n");
3171
3172         ret = reset_control_reset(rstc);
3173         if (ret) {
3174                 dev_err(dev, "failed to trigger audio reset:%d\n", ret);
3175                 return ret;
3176         }
3177
3178         /* initial audio related clock */
3179         ret = mt8188_afe_init_clock(afe);
3180         if (ret)
3181                 return dev_err_probe(dev, ret, "init clock error");
3182
3183         ret = devm_add_action_or_reset(dev, mt8188_afe_deinit_clock, (void *)afe);
3184         if (ret)
3185                 return ret;
3186
3187         spin_lock_init(&afe_priv->afe_ctrl_lock);
3188
3189         mutex_init(&afe->irq_alloc_lock);
3190
3191         /* irq initialize */
3192         afe->irqs_size = MT8188_AFE_IRQ_NUM;
3193         afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
3194                                  GFP_KERNEL);
3195         if (!afe->irqs)
3196                 return -ENOMEM;
3197
3198         for (i = 0; i < afe->irqs_size; i++)
3199                 afe->irqs[i].irq_data = &irq_data[i];
3200
3201         /* init memif */
3202         afe->memif_size = MT8188_AFE_MEMIF_NUM;
3203         afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
3204                                   GFP_KERNEL);
3205         if (!afe->memif)
3206                 return -ENOMEM;
3207
3208         for (i = 0; i < afe->memif_size; i++) {
3209                 afe->memif[i].data = &memif_data[i];
3210                 afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i];
3211                 afe->memif[i].const_irq = 1;
3212                 afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;
3213         }
3214
3215         /* request irq */
3216         irq_id = platform_get_irq(pdev, 0);
3217         if (irq_id < 0)
3218                 return dev_err_probe(dev, irq_id, "no irq found");
3219
3220         ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler,
3221                                IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
3222         if (ret)
3223                 return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n");
3224
3225         /* init sub_dais */
3226         INIT_LIST_HEAD(&afe->sub_dais);
3227
3228         for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
3229                 ret = dai_register_cbs[i](afe);
3230                 if (ret)
3231                         return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
3232         }
3233
3234         /* init dai_driver and component_driver */
3235         ret = mtk_afe_combine_sub_dai(afe);
3236         if (ret)
3237                 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
3238
3239         afe->mtk_afe_hardware = &mt8188_afe_hardware;
3240         afe->memif_fs = mt8188_memif_fs;
3241         afe->irq_fs = mt8188_irq_fs;
3242
3243         afe->runtime_resume = mt8188_afe_runtime_resume;
3244         afe->runtime_suspend = mt8188_afe_runtime_suspend;
3245
3246         platform_set_drvdata(pdev, afe);
3247
3248         ret = mt8188_afe_parse_of(afe, pdev->dev.of_node);
3249         if (ret)
3250                 return ret;
3251
3252         ret = devm_pm_runtime_enable(dev);
3253         if (ret)
3254                 return ret;
3255
3256         /* enable clock for regcache get default value from hw */
3257         afe_priv->pm_runtime_bypass_reg_ctl = true;
3258         ret = pm_runtime_resume_and_get(dev);
3259         if (ret)
3260                 return dev_err_probe(dev, ret, "failed to resume device\n");
3261
3262         afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
3263                                             &mt8188_afe_regmap_config);
3264         if (IS_ERR(afe->regmap)) {
3265                 ret = PTR_ERR(afe->regmap);
3266                 goto err_pm_put;
3267         }
3268
3269         ret = regmap_register_patch(afe->regmap, mt8188_cg_patch,
3270                                     ARRAY_SIZE(mt8188_cg_patch));
3271         if (ret < 0) {
3272                 dev_info(dev, "Failed to apply cg patch\n");
3273                 goto err_pm_put;
3274         }
3275
3276         /* register component */
3277         ret = devm_snd_soc_register_component(dev, &mt8188_afe_component,
3278                                               afe->dai_drivers, afe->num_dai_drivers);
3279         if (ret) {
3280                 dev_warn(dev, "err_platform\n");
3281                 goto err_pm_put;
3282         }
3283
3284         mt8188_afe_init_registers(afe);
3285
3286         pm_runtime_put_sync(&pdev->dev);
3287         afe_priv->pm_runtime_bypass_reg_ctl = false;
3288
3289         regcache_cache_only(afe->regmap, true);
3290         regcache_mark_dirty(afe->regmap);
3291
3292         return 0;
3293 err_pm_put:
3294         pm_runtime_put_sync(dev);
3295
3296         return ret;
3297 }
3298
3299 static const struct of_device_id mt8188_afe_pcm_dt_match[] = {
3300         { .compatible = "mediatek,mt8188-afe", },
3301         {},
3302 };
3303 MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match);
3304
3305 static const struct dev_pm_ops mt8188_afe_pm_ops = {
3306         SET_RUNTIME_PM_OPS(mt8188_afe_runtime_suspend,
3307                            mt8188_afe_runtime_resume, NULL)
3308 };
3309
3310 static struct platform_driver mt8188_afe_pcm_driver = {
3311         .driver = {
3312                    .name = "mt8188-audio",
3313                    .of_match_table = mt8188_afe_pcm_dt_match,
3314                    .pm = &mt8188_afe_pm_ops,
3315         },
3316         .probe = mt8188_afe_pcm_dev_probe,
3317 };
3318
3319 module_platform_driver(mt8188_afe_pcm_driver);
3320
3321 MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188");
3322 MODULE_AUTHOR("Chun-Chia.Chiu <chun-chia.chiu@mediatek.com>");
3323 MODULE_LICENSE("GPL");