1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
6 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/initval.h>
25 #include <sound/dmaengine_pcm.h>
27 #include "jz4740-i2s.h"
29 #define JZ_REG_AIC_CONF 0x00
30 #define JZ_REG_AIC_CTRL 0x04
31 #define JZ_REG_AIC_I2S_FMT 0x10
32 #define JZ_REG_AIC_FIFO_STATUS 0x14
33 #define JZ_REG_AIC_I2S_STATUS 0x1c
34 #define JZ_REG_AIC_CLK_DIV 0x30
35 #define JZ_REG_AIC_FIFO 0x34
37 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
38 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
39 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
40 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
41 #define JZ_AIC_CONF_I2S BIT(4)
42 #define JZ_AIC_CONF_RESET BIT(3)
43 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
44 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
45 #define JZ_AIC_CONF_ENABLE BIT(0)
47 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
48 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
49 #define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
50 #define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
52 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
53 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
54 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
55 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
56 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
57 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
58 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
59 #define JZ_AIC_CTRL_FLUSH BIT(8)
60 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
61 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
62 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
63 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
64 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
65 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
66 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
68 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
69 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
71 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
72 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
73 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
74 #define JZ_AIC_I2S_FMT_MSB BIT(0)
76 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
78 #define JZ_AIC_CLK_DIV_MASK 0xf
79 #define I2SDIV_DV_SHIFT 0
80 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
81 #define I2SDIV_IDV_SHIFT 8
82 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
84 enum jz47xx_i2s_version {
92 enum jz47xx_i2s_version version;
93 struct snd_soc_dai_driver *dai;
104 struct snd_dmaengine_dai_dma_data playback_dma_data;
105 struct snd_dmaengine_dai_dma_data capture_dma_data;
107 const struct i2s_soc_info *soc_info;
110 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
113 return readl(i2s->base + reg);
116 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
117 unsigned int reg, uint32_t value)
119 writel(value, i2s->base + reg);
122 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai)
125 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
129 if (snd_soc_dai_active(dai))
132 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
133 ctrl |= JZ_AIC_CTRL_FLUSH;
134 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
136 ret = clk_prepare_enable(i2s->clk_i2s);
140 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
141 conf |= JZ_AIC_CONF_ENABLE;
142 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
147 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
148 struct snd_soc_dai *dai)
150 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
153 if (snd_soc_dai_active(dai))
156 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
157 conf &= ~JZ_AIC_CONF_ENABLE;
158 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
160 clk_disable_unprepare(i2s->clk_i2s);
163 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
164 struct snd_soc_dai *dai)
166 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
172 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
174 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
176 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
179 case SNDRV_PCM_TRIGGER_START:
180 case SNDRV_PCM_TRIGGER_RESUME:
181 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
184 case SNDRV_PCM_TRIGGER_STOP:
185 case SNDRV_PCM_TRIGGER_SUSPEND:
186 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
193 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
198 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
200 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
205 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
207 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
209 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
210 case SND_SOC_DAIFMT_CBS_CFS:
211 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
212 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
214 case SND_SOC_DAIFMT_CBM_CFS:
215 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
217 case SND_SOC_DAIFMT_CBS_CFM:
218 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
220 case SND_SOC_DAIFMT_CBM_CFM:
226 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
227 case SND_SOC_DAIFMT_MSB:
228 format |= JZ_AIC_I2S_FMT_MSB;
230 case SND_SOC_DAIFMT_I2S:
236 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
237 case SND_SOC_DAIFMT_NB_NF:
243 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
244 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
249 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
250 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
252 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
253 unsigned int sample_size;
254 uint32_t ctrl, div_reg;
257 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
259 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
260 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
262 switch (params_format(params)) {
263 case SNDRV_PCM_FORMAT_S8:
266 case SNDRV_PCM_FORMAT_S16:
273 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
274 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
275 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
276 if (params_channels(params) == 1)
277 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
279 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
281 div_reg &= ~I2SDIV_DV_MASK;
282 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
284 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
285 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
287 if (i2s->soc_info->version >= JZ_I2S_JZ4770) {
288 div_reg &= ~I2SDIV_IDV_MASK;
289 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
291 div_reg &= ~I2SDIV_DV_MASK;
292 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
296 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
297 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
302 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
303 unsigned int freq, int dir)
305 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
310 case JZ4740_I2S_CLKSRC_EXT:
311 parent = clk_get(NULL, "ext");
312 clk_set_parent(i2s->clk_i2s, parent);
314 case JZ4740_I2S_CLKSRC_PLL:
315 parent = clk_get(NULL, "pll half");
316 clk_set_parent(i2s->clk_i2s, parent);
317 ret = clk_set_rate(i2s->clk_i2s, freq);
327 static int jz4740_i2s_suspend(struct snd_soc_component *component)
329 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
332 if (snd_soc_component_active(component)) {
333 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
334 conf &= ~JZ_AIC_CONF_ENABLE;
335 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
337 clk_disable_unprepare(i2s->clk_i2s);
340 clk_disable_unprepare(i2s->clk_aic);
345 static int jz4740_i2s_resume(struct snd_soc_component *component)
347 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
351 ret = clk_prepare_enable(i2s->clk_aic);
355 if (snd_soc_component_active(component)) {
356 ret = clk_prepare_enable(i2s->clk_i2s);
358 clk_disable_unprepare(i2s->clk_aic);
362 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
363 conf |= JZ_AIC_CONF_ENABLE;
364 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
370 static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
372 struct snd_dmaengine_dai_dma_data *dma_data;
375 dma_data = &i2s->playback_dma_data;
376 dma_data->maxburst = 16;
377 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
380 dma_data = &i2s->capture_dma_data;
381 dma_data->maxburst = 16;
382 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
385 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
387 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
391 ret = clk_prepare_enable(i2s->clk_aic);
395 jz4740_i2c_init_pcm_config(i2s);
396 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
397 &i2s->capture_dma_data);
399 if (i2s->soc_info->version >= JZ_I2S_JZ4760) {
400 conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
401 (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
402 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
404 JZ_AIC_CONF_INTERNAL_CODEC;
406 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
407 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
408 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
410 JZ_AIC_CONF_INTERNAL_CODEC;
413 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
414 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
419 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
421 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
423 clk_disable_unprepare(i2s->clk_aic);
427 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
428 .startup = jz4740_i2s_startup,
429 .shutdown = jz4740_i2s_shutdown,
430 .trigger = jz4740_i2s_trigger,
431 .hw_params = jz4740_i2s_hw_params,
432 .set_fmt = jz4740_i2s_set_fmt,
433 .set_sysclk = jz4740_i2s_set_sysclk,
436 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
437 SNDRV_PCM_FMTBIT_S16_LE)
439 static struct snd_soc_dai_driver jz4740_i2s_dai = {
440 .probe = jz4740_i2s_dai_probe,
441 .remove = jz4740_i2s_dai_remove,
445 .rates = SNDRV_PCM_RATE_8000_48000,
446 .formats = JZ4740_I2S_FMTS,
451 .rates = SNDRV_PCM_RATE_8000_48000,
452 .formats = JZ4740_I2S_FMTS,
454 .symmetric_rates = 1,
455 .ops = &jz4740_i2s_dai_ops,
458 static const struct i2s_soc_info jz4740_i2s_soc_info = {
459 .version = JZ_I2S_JZ4740,
460 .dai = &jz4740_i2s_dai,
463 static const struct i2s_soc_info jz4760_i2s_soc_info = {
464 .version = JZ_I2S_JZ4760,
465 .dai = &jz4740_i2s_dai,
468 static struct snd_soc_dai_driver jz4770_i2s_dai = {
469 .probe = jz4740_i2s_dai_probe,
470 .remove = jz4740_i2s_dai_remove,
474 .rates = SNDRV_PCM_RATE_8000_48000,
475 .formats = JZ4740_I2S_FMTS,
480 .rates = SNDRV_PCM_RATE_8000_48000,
481 .formats = JZ4740_I2S_FMTS,
483 .ops = &jz4740_i2s_dai_ops,
486 static const struct i2s_soc_info jz4770_i2s_soc_info = {
487 .version = JZ_I2S_JZ4770,
488 .dai = &jz4770_i2s_dai,
491 static const struct i2s_soc_info jz4780_i2s_soc_info = {
492 .version = JZ_I2S_JZ4780,
493 .dai = &jz4770_i2s_dai,
496 static const struct snd_soc_component_driver jz4740_i2s_component = {
497 .name = "jz4740-i2s",
498 .suspend = jz4740_i2s_suspend,
499 .resume = jz4740_i2s_resume,
502 static const struct of_device_id jz4740_of_matches[] = {
503 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
504 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
505 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
506 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
509 MODULE_DEVICE_TABLE(of, jz4740_of_matches);
511 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
513 struct device *dev = &pdev->dev;
514 struct jz4740_i2s *i2s;
515 struct resource *mem;
518 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
522 i2s->soc_info = device_get_match_data(dev);
524 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 i2s->base = devm_ioremap_resource(dev, mem);
526 if (IS_ERR(i2s->base))
527 return PTR_ERR(i2s->base);
529 i2s->phys_base = mem->start;
531 i2s->clk_aic = devm_clk_get(dev, "aic");
532 if (IS_ERR(i2s->clk_aic))
533 return PTR_ERR(i2s->clk_aic);
535 i2s->clk_i2s = devm_clk_get(dev, "i2s");
536 if (IS_ERR(i2s->clk_i2s))
537 return PTR_ERR(i2s->clk_i2s);
539 platform_set_drvdata(pdev, i2s);
541 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
542 i2s->soc_info->dai, 1);
546 return devm_snd_dmaengine_pcm_register(dev, NULL,
547 SND_DMAENGINE_PCM_FLAG_COMPAT);
550 static struct platform_driver jz4740_i2s_driver = {
551 .probe = jz4740_i2s_dev_probe,
553 .name = "jz4740-i2s",
554 .of_match_table = jz4740_of_matches,
558 module_platform_driver(jz4740_i2s_driver);
560 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
561 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
562 MODULE_LICENSE("GPL");
563 MODULE_ALIAS("platform:jz4740-i2s");