sound/soc/jz4740/jz4740-i2s.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/mod_devicetable.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/slab.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/soc.h>
  23 #include <sound/initval.h>
  24 #include <sound/dmaengine_pcm.h>
  25
  26 #define JZ_REG_AIC_CONF         0x00
  27 #define JZ_REG_AIC_CTRL         0x04
  28 #define JZ_REG_AIC_I2S_FMT      0x10
  29 #define JZ_REG_AIC_FIFO_STATUS  0x14
  30 #define JZ_REG_AIC_I2S_STATUS   0x1c
  31 #define JZ_REG_AIC_CLK_DIV      0x30
  32 #define JZ_REG_AIC_FIFO         0x34
  33
  34 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST  BIT(6)
  35 #define JZ_AIC_CONF_INTERNAL_CODEC      BIT(5)
  36 #define JZ_AIC_CONF_I2S                 BIT(4)
  37 #define JZ_AIC_CONF_RESET               BIT(3)
  38 #define JZ_AIC_CONF_BIT_CLK_MASTER      BIT(2)
  39 #define JZ_AIC_CONF_SYNC_CLK_MASTER     BIT(1)
  40 #define JZ_AIC_CONF_ENABLE              BIT(0)
  41
  42 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE  GENMASK(21, 19)
  43 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE   GENMASK(18, 16)
  44 #define JZ_AIC_CTRL_ENABLE_RX_DMA       BIT(15)
  45 #define JZ_AIC_CTRL_ENABLE_TX_DMA       BIT(14)
  46 #define JZ_AIC_CTRL_MONO_TO_STEREO      BIT(11)
  47 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS   BIT(10)
  48 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED  BIT(9)
  49 #define JZ_AIC_CTRL_TFLUSH              BIT(8)
  50 #define JZ_AIC_CTRL_RFLUSH              BIT(7)
  51 #define JZ_AIC_CTRL_ENABLE_ROR_INT      BIT(6)
  52 #define JZ_AIC_CTRL_ENABLE_TUR_INT      BIT(5)
  53 #define JZ_AIC_CTRL_ENABLE_RFS_INT      BIT(4)
  54 #define JZ_AIC_CTRL_ENABLE_TFS_INT      BIT(3)
  55 #define JZ_AIC_CTRL_ENABLE_LOOPBACK     BIT(2)
  56 #define JZ_AIC_CTRL_ENABLE_PLAYBACK     BIT(1)
  57 #define JZ_AIC_CTRL_ENABLE_CAPTURE      BIT(0)
  58
  59 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK  BIT(12)
  60 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
  61 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK   BIT(4)
  62 #define JZ_AIC_I2S_FMT_MSB              BIT(0)
  63
  64 #define JZ_AIC_I2S_STATUS_BUSY          BIT(2)
  65
  66 struct i2s_soc_info {
  67         struct snd_soc_dai_driver *dai;
  68
  69         struct reg_field field_rx_fifo_thresh;
  70         struct reg_field field_tx_fifo_thresh;
  71         struct reg_field field_i2sdiv_capture;
  72         struct reg_field field_i2sdiv_playback;
  73
  74         bool shared_fifo_flush;
  75 };
  76
  77 struct jz4740_i2s {
  78         struct regmap *regmap;
  79
  80         struct regmap_field *field_rx_fifo_thresh;
  81         struct regmap_field *field_tx_fifo_thresh;
  82         struct regmap_field *field_i2sdiv_capture;
  83         struct regmap_field *field_i2sdiv_playback;
  84
  85         struct clk *clk_aic;
  86         struct clk *clk_i2s;
  87
  88         struct snd_dmaengine_dai_dma_data playback_dma_data;
  89         struct snd_dmaengine_dai_dma_data capture_dma_data;
  90
  91         const struct i2s_soc_info *soc_info;
  92 };
  93
  94 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
  95         struct snd_soc_dai *dai)
  96 {
  97         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  98         int ret;
  99
 100         /*
 101          * When we can flush FIFOs independently, only flush the FIFO
 102          * that is starting up. We can do this when the DAI is active
 103          * because it does not disturb other active substreams.
 104          */
 105         if (!i2s->soc_info->shared_fifo_flush) {
 106                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 107                         regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH);
 108                 else
 109                         regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH);
 110         }
 111
 112         if (snd_soc_dai_active(dai))
 113                 return 0;
 114
 115         /*
 116          * When there is a shared flush bit for both FIFOs, the TFLUSH
 117          * bit flushes both FIFOs. Flushing while the DAI is active would
 118          * cause FIFO underruns in other active substreams so we have to
 119          * guard this behind the snd_soc_dai_active() check.
 120          */
 121         if (i2s->soc_info->shared_fifo_flush)
 122                 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH);
 123
 124         ret = clk_prepare_enable(i2s->clk_i2s);
 125         if (ret)
 126                 return ret;
 127
 128         regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
 129         return 0;
 130 }
 131
 132 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
 133         struct snd_soc_dai *dai)
 134 {
 135         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 136
 137         if (snd_soc_dai_active(dai))
 138                 return;
 139
 140         regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
 141
 142         clk_disable_unprepare(i2s->clk_i2s);
 143 }
 144
 145 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 146         struct snd_soc_dai *dai)
 147 {
 148         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 149         uint32_t mask;
 150
 151         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 152                 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
 153         else
 154                 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
 155
 156         switch (cmd) {
 157         case SNDRV_PCM_TRIGGER_START:
 158         case SNDRV_PCM_TRIGGER_RESUME:
 159         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 160                 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask);
 161                 break;
 162         case SNDRV_PCM_TRIGGER_STOP:
 163         case SNDRV_PCM_TRIGGER_SUSPEND:
 164         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 165                 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask);
 166                 break;
 167         default:
 168                 return -EINVAL;
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 175 {
 176         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 177         const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER |
 178                                        JZ_AIC_CONF_SYNC_CLK_MASTER;
 179         unsigned int conf = 0, format = 0;
 180
 181         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 182         case SND_SOC_DAIFMT_BP_FP:
 183                 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
 184                 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
 185                 break;
 186         case SND_SOC_DAIFMT_BC_FP:
 187                 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
 188                 break;
 189         case SND_SOC_DAIFMT_BP_FC:
 190                 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
 191                 break;
 192         case SND_SOC_DAIFMT_BC_FC:
 193                 break;
 194         default:
 195                 return -EINVAL;
 196         }
 197
 198         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 199         case SND_SOC_DAIFMT_MSB:
 200                 format |= JZ_AIC_I2S_FMT_MSB;
 201                 break;
 202         case SND_SOC_DAIFMT_I2S:
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 209         case SND_SOC_DAIFMT_NB_NF:
 210                 break;
 211         default:
 212                 return -EINVAL;
 213         }
 214
 215         regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf);
 216         regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format);
 217
 218         return 0;
 219 }
 220
 221 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
 222         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 223 {
 224         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 225         struct regmap_field *div_field;
 226         unsigned int sample_size;
 227         uint32_t ctrl;
 228         int div;
 229
 230         regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl);
 231
 232         div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
 233
 234         switch (params_format(params)) {
 235         case SNDRV_PCM_FORMAT_S8:
 236                 sample_size = 0;
 237                 break;
 238         case SNDRV_PCM_FORMAT_S16_LE:
 239                 sample_size = 1;
 240                 break;
 241         case SNDRV_PCM_FORMAT_S20_LE:
 242                 sample_size = 3;
 243                 break;
 244         case SNDRV_PCM_FORMAT_S24_LE:
 245                 sample_size = 4;
 246                 break;
 247         default:
 248                 return -EINVAL;
 249         }
 250
 251         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 252                 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE;
 253                 ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size);
 254
 255                 if (params_channels(params) == 1)
 256                         ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
 257                 else
 258                         ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
 259
 260                 div_field = i2s->field_i2sdiv_playback;
 261         } else {
 262                 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE;
 263                 ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size);
 264
 265                 div_field = i2s->field_i2sdiv_capture;
 266         }
 267
 268         regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl);
 269         regmap_field_write(div_field, div - 1);
 270
 271         return 0;
 272 }
 273
 274 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
 275 {
 276         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 277
 278         snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
 279                 &i2s->capture_dma_data);
 280
 281         return 0;
 282 }
 283
 284 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
 285         .startup = jz4740_i2s_startup,
 286         .shutdown = jz4740_i2s_shutdown,
 287         .trigger = jz4740_i2s_trigger,
 288         .hw_params = jz4740_i2s_hw_params,
 289         .set_fmt = jz4740_i2s_set_fmt,
 290 };
 291
 292 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
 293                          SNDRV_PCM_FMTBIT_S16_LE | \
 294                          SNDRV_PCM_FMTBIT_S20_LE | \
 295                          SNDRV_PCM_FMTBIT_S24_LE)
 296
 297 static struct snd_soc_dai_driver jz4740_i2s_dai = {
 298         .probe = jz4740_i2s_dai_probe,
 299         .playback = {
 300                 .channels_min = 1,
 301                 .channels_max = 2,
 302                 .rates = SNDRV_PCM_RATE_CONTINUOUS,
 303                 .formats = JZ4740_I2S_FMTS,
 304         },
 305         .capture = {
 306                 .channels_min = 2,
 307                 .channels_max = 2,
 308                 .rates = SNDRV_PCM_RATE_CONTINUOUS,
 309                 .formats = JZ4740_I2S_FMTS,
 310         },
 311         .symmetric_rate = 1,
 312         .ops = &jz4740_i2s_dai_ops,
 313 };
 314
 315 static const struct i2s_soc_info jz4740_i2s_soc_info = {
 316         .dai                    = &jz4740_i2s_dai,
 317         .field_rx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 12, 15),
 318         .field_tx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 8, 11),
 319         .field_i2sdiv_capture   = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
 320         .field_i2sdiv_playback  = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
 321         .shared_fifo_flush      = true,
 322 };
 323
 324 static const struct i2s_soc_info jz4760_i2s_soc_info = {
 325         .dai                    = &jz4740_i2s_dai,
 326         .field_rx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
 327         .field_tx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
 328         .field_i2sdiv_capture   = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
 329         .field_i2sdiv_playback  = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
 330 };
 331
 332 static const struct i2s_soc_info x1000_i2s_soc_info = {
 333         .dai = &jz4740_i2s_dai,
 334         .field_rx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
 335         .field_tx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
 336         .field_i2sdiv_capture   = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 8),
 337         .field_i2sdiv_playback  = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 8),
 338 };
 339
 340 static struct snd_soc_dai_driver jz4770_i2s_dai = {
 341         .probe = jz4740_i2s_dai_probe,
 342         .playback = {
 343                 .channels_min = 1,
 344                 .channels_max = 2,
 345                 .rates = SNDRV_PCM_RATE_CONTINUOUS,
 346                 .formats = JZ4740_I2S_FMTS,
 347         },
 348         .capture = {
 349                 .channels_min = 2,
 350                 .channels_max = 2,
 351                 .rates = SNDRV_PCM_RATE_CONTINUOUS,
 352                 .formats = JZ4740_I2S_FMTS,
 353         },
 354         .ops = &jz4740_i2s_dai_ops,
 355 };
 356
 357 static const struct i2s_soc_info jz4770_i2s_soc_info = {
 358         .dai                    = &jz4770_i2s_dai,
 359         .field_rx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
 360         .field_tx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
 361         .field_i2sdiv_capture   = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11),
 362         .field_i2sdiv_playback  = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
 363 };
 364
 365 static const struct i2s_soc_info jz4780_i2s_soc_info = {
 366         .dai                    = &jz4770_i2s_dai,
 367         .field_rx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
 368         .field_tx_fifo_thresh   = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
 369         .field_i2sdiv_capture   = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11),
 370         .field_i2sdiv_playback  = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
 371 };
 372
 373 static int jz4740_i2s_suspend(struct snd_soc_component *component)
 374 {
 375         struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
 376
 377         if (snd_soc_component_active(component)) {
 378                 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
 379                 clk_disable_unprepare(i2s->clk_i2s);
 380         }
 381
 382         clk_disable_unprepare(i2s->clk_aic);
 383
 384         return 0;
 385 }
 386
 387 static int jz4740_i2s_resume(struct snd_soc_component *component)
 388 {
 389         struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
 390         int ret;
 391
 392         ret = clk_prepare_enable(i2s->clk_aic);
 393         if (ret)
 394                 return ret;
 395
 396         if (snd_soc_component_active(component)) {
 397                 ret = clk_prepare_enable(i2s->clk_i2s);
 398                 if (ret) {
 399                         clk_disable_unprepare(i2s->clk_aic);
 400                         return ret;
 401                 }
 402
 403                 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
 404         }
 405
 406         return 0;
 407 }
 408
 409 static int jz4740_i2s_probe(struct snd_soc_component *component)
 410 {
 411         struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
 412         int ret;
 413
 414         ret = clk_prepare_enable(i2s->clk_aic);
 415         if (ret)
 416                 return ret;
 417
 418         regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
 419
 420         regmap_write(i2s->regmap, JZ_REG_AIC_CONF,
 421                      JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
 422                      JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC);
 423
 424         regmap_field_write(i2s->field_rx_fifo_thresh, 7);
 425         regmap_field_write(i2s->field_tx_fifo_thresh, 8);
 426
 427         return 0;
 428 }
 429
 430 static void jz4740_i2s_remove(struct snd_soc_component *component)
 431 {
 432         struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
 433
 434         clk_disable_unprepare(i2s->clk_aic);
 435 }
 436
 437 static const struct snd_soc_component_driver jz4740_i2s_component = {
 438         .name                   = "jz4740-i2s",
 439         .probe                  = jz4740_i2s_probe,
 440         .remove                 = jz4740_i2s_remove,
 441         .suspend                = jz4740_i2s_suspend,
 442         .resume                 = jz4740_i2s_resume,
 443         .legacy_dai_naming      = 1,
 444 };
 445
 446 static const struct of_device_id jz4740_of_matches[] = {
 447         { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
 448         { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
 449         { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
 450         { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
 451         { .compatible = "ingenic,x1000-i2s", .data = &x1000_i2s_soc_info },
 452         { /* sentinel */ }
 453 };
 454 MODULE_DEVICE_TABLE(of, jz4740_of_matches);
 455
 456 static int jz4740_i2s_init_regmap_fields(struct device *dev,
 457                                          struct jz4740_i2s *i2s)
 458 {
 459         i2s->field_rx_fifo_thresh =
 460                 devm_regmap_field_alloc(dev, i2s->regmap,
 461                                         i2s->soc_info->field_rx_fifo_thresh);
 462         if (IS_ERR(i2s->field_rx_fifo_thresh))
 463                 return PTR_ERR(i2s->field_rx_fifo_thresh);
 464
 465         i2s->field_tx_fifo_thresh =
 466                 devm_regmap_field_alloc(dev, i2s->regmap,
 467                                         i2s->soc_info->field_tx_fifo_thresh);
 468         if (IS_ERR(i2s->field_tx_fifo_thresh))
 469                 return PTR_ERR(i2s->field_tx_fifo_thresh);
 470
 471         i2s->field_i2sdiv_capture =
 472                 devm_regmap_field_alloc(dev, i2s->regmap,
 473                                         i2s->soc_info->field_i2sdiv_capture);
 474         if (IS_ERR(i2s->field_i2sdiv_capture))
 475                 return PTR_ERR(i2s->field_i2sdiv_capture);
 476
 477         i2s->field_i2sdiv_playback =
 478                 devm_regmap_field_alloc(dev, i2s->regmap,
 479                                         i2s->soc_info->field_i2sdiv_playback);
 480         if (IS_ERR(i2s->field_i2sdiv_playback))
 481                 return PTR_ERR(i2s->field_i2sdiv_playback);
 482
 483         return 0;
 484 }
 485
 486 static const struct regmap_config jz4740_i2s_regmap_config = {
 487         .reg_bits       = 32,
 488         .reg_stride     = 4,
 489         .val_bits       = 32,
 490         .max_register   = JZ_REG_AIC_FIFO,
 491 };
 492
 493 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
 494 {
 495         struct device *dev = &pdev->dev;
 496         struct jz4740_i2s *i2s;
 497         struct resource *mem;
 498         void __iomem *regs;
 499         int ret;
 500
 501         i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
 502         if (!i2s)
 503                 return -ENOMEM;
 504
 505         i2s->soc_info = device_get_match_data(dev);
 506
 507         regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
 508         if (IS_ERR(regs))
 509                 return PTR_ERR(regs);
 510
 511         i2s->playback_dma_data.maxburst = 16;
 512         i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
 513
 514         i2s->capture_dma_data.maxburst = 16;
 515         i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
 516
 517         i2s->clk_aic = devm_clk_get(dev, "aic");
 518         if (IS_ERR(i2s->clk_aic))
 519                 return PTR_ERR(i2s->clk_aic);
 520
 521         i2s->clk_i2s = devm_clk_get(dev, "i2s");
 522         if (IS_ERR(i2s->clk_i2s))
 523                 return PTR_ERR(i2s->clk_i2s);
 524
 525         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 526                                             &jz4740_i2s_regmap_config);
 527         if (IS_ERR(i2s->regmap))
 528                 return PTR_ERR(i2s->regmap);
 529
 530         ret = jz4740_i2s_init_regmap_fields(dev, i2s);
 531         if (ret)
 532                 return ret;
 533
 534         platform_set_drvdata(pdev, i2s);
 535
 536         ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
 537                                               i2s->soc_info->dai, 1);
 538         if (ret)
 539                 return ret;
 540
 541         return devm_snd_dmaengine_pcm_register(dev, NULL,
 542                 SND_DMAENGINE_PCM_FLAG_COMPAT);
 543 }
 544
 545 static struct platform_driver jz4740_i2s_driver = {
 546         .probe = jz4740_i2s_dev_probe,
 547         .driver = {
 548                 .name = "jz4740-i2s",
 549                 .of_match_table = jz4740_of_matches,
 550         },
 551 };
 552
 553 module_platform_driver(jz4740_i2s_driver);
 554
 555 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
 556 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
 557 MODULE_LICENSE("GPL");
 558 MODULE_ALIAS("platform:jz4740-i2s");