sound/soc/intel/skylake/skl-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   4  *
   5  *  Copyright (C) 2014-2015 Intel Corp
   6  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/delay.h>
  16 #include <sound/pcm_params.h>
  17 #include <sound/soc.h>
  18 #include "skl.h"
  19 #include "skl-topology.h"
  20 #include "skl-sst-dsp.h"
  21 #include "skl-sst-ipc.h"
  22
  23 #define HDA_MONO 1
  24 #define HDA_STEREO 2
  25 #define HDA_QUAD 4
  26 #define HDA_MAX 8
  27
  28 static const struct snd_pcm_hardware azx_pcm_hw = {
  29         .info =                 (SNDRV_PCM_INFO_MMAP |
  30                                  SNDRV_PCM_INFO_INTERLEAVED |
  31                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  32                                  SNDRV_PCM_INFO_MMAP_VALID |
  33                                  SNDRV_PCM_INFO_PAUSE |
  34                                  SNDRV_PCM_INFO_RESUME |
  35                                  SNDRV_PCM_INFO_SYNC_START |
  36                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  37                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  38                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  39         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  40                                 SNDRV_PCM_FMTBIT_S32_LE |
  41                                 SNDRV_PCM_FMTBIT_S24_LE,
  42         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  43                                 SNDRV_PCM_RATE_8000,
  44         .rate_min =             8000,
  45         .rate_max =             48000,
  46         .channels_min =         1,
  47         .channels_max =         8,
  48         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  49         .period_bytes_min =     128,
  50         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  51         .periods_min =          2,
  52         .periods_max =          AZX_MAX_FRAG,
  53         .fifo_size =            0,
  54 };
  55
  56 static inline
  57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  58 {
  59         return substream->runtime->private_data;
  60 }
  61
  62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  63 {
  64         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  65         struct hdac_stream *hstream = hdac_stream(stream);
  66         struct hdac_bus *bus = hstream->bus;
  67         return bus;
  68 }
  69
  70 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  71                                  struct snd_pcm_substream *substream,
  72                                  size_t size)
  73 {
  74         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  75
  76         hdac_stream(stream)->bufsize = 0;
  77         hdac_stream(stream)->period_bytes = 0;
  78         hdac_stream(stream)->format_val = 0;
  79
  80         return 0;
  81 }
  82
  83 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  84                                  struct snd_pcm_runtime *runtime)
  85 {
  86         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  87
  88         /* avoid wrap-around with wall-clock */
  89         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
  90                                      20, 178000000);
  91 }
  92
  93 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
  94 {
  95         if (bus->ppcap)
  96                 return HDAC_EXT_STREAM_TYPE_HOST;
  97         else
  98                 return HDAC_EXT_STREAM_TYPE_COUPLED;
  99 }
 100
 101 /*
 102  * check if the stream opened is marked as ignore_suspend by machine, if so
 103  * then enable suspend_active refcount
 104  *
 105  * The count supend_active does not need lock as it is used in open/close
 106  * and suspend context
 107  */
 108 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 109                                          struct snd_soc_dai *dai, bool enable)
 110 {
 111         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 112         struct snd_soc_dapm_widget *w;
 113         struct skl_dev *skl = bus_to_skl(bus);
 114
 115         w = snd_soc_dai_get_widget(dai, substream->stream);
 116
 117         if (w->ignore_suspend && enable)
 118                 skl->supend_active++;
 119         else if (w->ignore_suspend && !enable)
 120                 skl->supend_active--;
 121 }
 122
 123 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 124 {
 125         struct hdac_bus *bus = dev_get_drvdata(dev);
 126         struct skl_dev *skl = bus_to_skl(bus);
 127         unsigned int format_val;
 128         struct hdac_stream *hstream;
 129         struct hdac_ext_stream *stream;
 130         int err;
 131
 132         hstream = snd_hdac_get_stream(bus, params->stream,
 133                                         params->host_dma_id + 1);
 134         if (!hstream)
 135                 return -EINVAL;
 136
 137         stream = stream_to_hdac_ext_stream(hstream);
 138         snd_hdac_ext_stream_decouple(bus, stream, true);
 139
 140         format_val = snd_hdac_calc_stream_format(params->s_freq,
 141                         params->ch, params->format, params->host_bps, 0);
 142
 143         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 144                 format_val, params->s_freq, params->ch, params->format);
 145
 146         snd_hdac_stream_reset(hdac_stream(stream));
 147         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 148         if (err < 0)
 149                 return err;
 150
 151         /*
 152          * The recommended SDxFMT programming sequence for BXT
 153          * platforms is to couple the stream before writing the format
 154          */
 155         if (IS_BXT(skl->pci)) {
 156                 snd_hdac_ext_stream_decouple(bus, stream, false);
 157                 err = snd_hdac_stream_setup(hdac_stream(stream));
 158                 snd_hdac_ext_stream_decouple(bus, stream, true);
 159         } else {
 160                 err = snd_hdac_stream_setup(hdac_stream(stream));
 161         }
 162
 163         if (err < 0)
 164                 return err;
 165
 166         hdac_stream(stream)->prepared = 1;
 167
 168         return 0;
 169 }
 170
 171 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 172 {
 173         struct hdac_bus *bus = dev_get_drvdata(dev);
 174         unsigned int format_val;
 175         struct hdac_stream *hstream;
 176         struct hdac_ext_stream *stream;
 177         struct hdac_ext_link *link;
 178         unsigned char stream_tag;
 179
 180         hstream = snd_hdac_get_stream(bus, params->stream,
 181                                         params->link_dma_id + 1);
 182         if (!hstream)
 183                 return -EINVAL;
 184
 185         stream = stream_to_hdac_ext_stream(hstream);
 186         snd_hdac_ext_stream_decouple(bus, stream, true);
 187         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 188                                         params->format, params->link_bps, 0);
 189
 190         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 191                 format_val, params->s_freq, params->ch, params->format);
 192
 193         snd_hdac_ext_stream_reset(stream);
 194
 195         snd_hdac_ext_stream_setup(stream, format_val);
 196
 197         stream_tag = hstream->stream_tag;
 198         if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
 199                 list_for_each_entry(link, &bus->hlink_list, list) {
 200                         if (link->index == params->link_index)
 201                                 snd_hdac_ext_bus_link_set_stream_id(link,
 202                                                                     stream_tag);
 203                 }
 204         }
 205
 206         stream->link_prepared = 1;
 207
 208         return 0;
 209 }
 210
 211 static int skl_pcm_open(struct snd_pcm_substream *substream,
 212                 struct snd_soc_dai *dai)
 213 {
 214         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 215         struct hdac_ext_stream *stream;
 216         struct snd_pcm_runtime *runtime = substream->runtime;
 217         struct skl_dma_params *dma_params;
 218         struct skl_dev *skl = get_skl_ctx(dai->dev);
 219         struct skl_module_cfg *mconfig;
 220
 221         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 222
 223         stream = snd_hdac_ext_stream_assign(bus, substream,
 224                                         skl_get_host_stream_type(bus));
 225         if (stream == NULL)
 226                 return -EBUSY;
 227
 228         skl_set_pcm_constrains(bus, runtime);
 229
 230         /*
 231          * disable WALLCLOCK timestamps for capture streams
 232          * until we figure out how to handle digital inputs
 233          */
 234         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 235                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 236                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 237         }
 238
 239         runtime->private_data = stream;
 240
 241         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 242         if (!dma_params)
 243                 return -ENOMEM;
 244
 245         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 246         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 247
 248         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 249                                  dma_params->stream_tag);
 250         skl_set_suspend_active(substream, dai, true);
 251         snd_pcm_set_sync(substream);
 252
 253         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 254         if (!mconfig)
 255                 return -EINVAL;
 256
 257         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 258
 259         return 0;
 260 }
 261
 262 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 263                 struct snd_soc_dai *dai)
 264 {
 265         struct skl_dev *skl = get_skl_ctx(dai->dev);
 266         struct skl_module_cfg *mconfig;
 267         int ret;
 268
 269         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 270
 271         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 272
 273         /*
 274          * In case of XRUN recovery or in the case when the application
 275          * calls prepare another time, reset the FW pipe to clean state
 276          */
 277         if (mconfig &&
 278                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
 279                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 280                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 281
 282                 ret = skl_reset_pipe(skl, mconfig->pipe);
 283
 284                 if (ret < 0)
 285                         return ret;
 286
 287                 ret = skl_pcm_host_dma_prepare(dai->dev,
 288                                         mconfig->pipe->p_params);
 289                 if (ret < 0)
 290                         return ret;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 297                                 struct snd_pcm_hw_params *params,
 298                                 struct snd_soc_dai *dai)
 299 {
 300         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 301         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 302         struct snd_pcm_runtime *runtime = substream->runtime;
 303         struct skl_pipe_params p_params = {0};
 304         struct skl_module_cfg *m_cfg;
 305         int ret, dma_id;
 306
 307         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 308         ret = skl_substream_alloc_pages(bus, substream,
 309                                           params_buffer_bytes(params));
 310         if (ret < 0)
 311                 return ret;
 312
 313         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 314                         runtime->rate, runtime->channels, runtime->format);
 315
 316         dma_id = hdac_stream(stream)->stream_tag - 1;
 317         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 318
 319         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 320         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 321         p_params.ch = params_channels(params);
 322         p_params.s_freq = params_rate(params);
 323         p_params.host_dma_id = dma_id;
 324         p_params.stream = substream->stream;
 325         p_params.format = params_format(params);
 326         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 327                 p_params.host_bps = dai->driver->playback.sig_bits;
 328         else
 329                 p_params.host_bps = dai->driver->capture.sig_bits;
 330
 331
 332         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 333         if (m_cfg)
 334                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 335
 336         return 0;
 337 }
 338
 339 static void skl_pcm_close(struct snd_pcm_substream *substream,
 340                 struct snd_soc_dai *dai)
 341 {
 342         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 343         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 344         struct skl_dma_params *dma_params = NULL;
 345         struct skl_dev *skl = bus_to_skl(bus);
 346         struct skl_module_cfg *mconfig;
 347
 348         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 349
 350         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 351
 352         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 353         /*
 354          * now we should set this to NULL as we are freeing by the
 355          * dma_params
 356          */
 357         snd_soc_dai_set_dma_data(dai, substream, NULL);
 358         skl_set_suspend_active(substream, dai, false);
 359
 360         /*
 361          * check if close is for "Reference Pin" and set back the
 362          * CGCTL.MISCBDCGE if disabled by driver
 363          */
 364         if (!strncmp(dai->name, "Reference Pin", 13) &&
 365                         skl->miscbdcg_disabled) {
 366                 skl->enable_miscbdcge(dai->dev, true);
 367                 skl->miscbdcg_disabled = false;
 368         }
 369
 370         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 371         if (mconfig)
 372                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 373
 374         kfree(dma_params);
 375 }
 376
 377 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 378                 struct snd_soc_dai *dai)
 379 {
 380         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 381         struct skl_dev *skl = get_skl_ctx(dai->dev);
 382         struct skl_module_cfg *mconfig;
 383         int ret;
 384
 385         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 386
 387         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 388
 389         if (mconfig) {
 390                 ret = skl_reset_pipe(skl, mconfig->pipe);
 391                 if (ret < 0)
 392                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 393                                                 __func__, ret);
 394         }
 395
 396         snd_hdac_stream_cleanup(hdac_stream(stream));
 397         hdac_stream(stream)->prepared = 0;
 398
 399         return 0;
 400 }
 401
 402 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 403                                 struct snd_pcm_hw_params *params,
 404                                 struct snd_soc_dai *dai)
 405 {
 406         struct skl_pipe_params p_params = {0};
 407
 408         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 409         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 410         p_params.ch = params_channels(params);
 411         p_params.s_freq = params_rate(params);
 412         p_params.stream = substream->stream;
 413
 414         return skl_tplg_be_update_params(dai, &p_params);
 415 }
 416
 417 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 418                 int cmd)
 419 {
 420         struct hdac_bus *bus = get_bus_ctx(substream);
 421         struct hdac_ext_stream *stream;
 422         int start;
 423         unsigned long cookie;
 424         struct hdac_stream *hstr;
 425
 426         stream = get_hdac_ext_stream(substream);
 427         hstr = hdac_stream(stream);
 428
 429         if (!hstr->prepared)
 430                 return -EPIPE;
 431
 432         switch (cmd) {
 433         case SNDRV_PCM_TRIGGER_START:
 434         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 435         case SNDRV_PCM_TRIGGER_RESUME:
 436                 start = 1;
 437                 break;
 438
 439         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 440         case SNDRV_PCM_TRIGGER_SUSPEND:
 441         case SNDRV_PCM_TRIGGER_STOP:
 442                 start = 0;
 443                 break;
 444
 445         default:
 446                 return -EINVAL;
 447         }
 448
 449         spin_lock_irqsave(&bus->reg_lock, cookie);
 450
 451         if (start) {
 452                 snd_hdac_stream_start(hdac_stream(stream));
 453                 snd_hdac_stream_timecounter_init(hstr, 0);
 454         } else {
 455                 snd_hdac_stream_stop(hdac_stream(stream));
 456         }
 457
 458         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 459
 460         return 0;
 461 }
 462
 463 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 464                 struct snd_soc_dai *dai)
 465 {
 466         struct skl_dev *skl = get_skl_ctx(dai->dev);
 467         struct skl_module_cfg *mconfig;
 468         struct hdac_bus *bus = get_bus_ctx(substream);
 469         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 470         struct hdac_stream *hstream = hdac_stream(stream);
 471         struct snd_soc_dapm_widget *w;
 472         int ret;
 473
 474         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 475         if (!mconfig)
 476                 return -EIO;
 477
 478         w = snd_soc_dai_get_widget(dai, substream->stream);
 479
 480         switch (cmd) {
 481         case SNDRV_PCM_TRIGGER_RESUME:
 482                 if (!w->ignore_suspend) {
 483                         /*
 484                          * enable DMA Resume enable bit for the stream, set the
 485                          * dpib & lpib position to resume before starting the
 486                          * DMA
 487                          */
 488                         snd_hdac_stream_drsm_enable(bus, true, hstream->index);
 489                         snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
 490                         snd_hdac_stream_set_lpib(hstream, hstream->lpib);
 491                 }
 492                 fallthrough;
 493
 494         case SNDRV_PCM_TRIGGER_START:
 495         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 496                 /*
 497                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 498                  * there are no underrun/overrun in the case when the FE
 499                  * pipeline is started but there is a delay in starting the
 500                  * DMA channel on the host.
 501                  */
 502                 ret = skl_decoupled_trigger(substream, cmd);
 503                 if (ret < 0)
 504                         return ret;
 505                 return skl_run_pipe(skl, mconfig->pipe);
 506
 507         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 508         case SNDRV_PCM_TRIGGER_SUSPEND:
 509         case SNDRV_PCM_TRIGGER_STOP:
 510                 /*
 511                  * Stop FE Pipe first and stop DMA. This is to make sure that
 512                  * there are no underrun/overrun in the case if there is a delay
 513                  * between the two operations.
 514                  */
 515                 ret = skl_stop_pipe(skl, mconfig->pipe);
 516                 if (ret < 0)
 517                         return ret;
 518
 519                 ret = skl_decoupled_trigger(substream, cmd);
 520                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 521                         /* save the dpib and lpib positions */
 522                         hstream->dpib = readl(bus->remap_addr +
 523                                         AZX_REG_VS_SDXDPIB_XBASE +
 524                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 525                                         hstream->index));
 526
 527                         hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
 528
 529                         snd_hdac_ext_stream_decouple(bus, stream, false);
 530                 }
 531                 break;
 532
 533         default:
 534                 return -EINVAL;
 535         }
 536
 537         return 0;
 538 }
 539
 540
 541 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 542                                 struct snd_pcm_hw_params *params,
 543                                 struct snd_soc_dai *dai)
 544 {
 545         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 546         struct hdac_ext_stream *link_dev;
 547         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 548         struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
 549         struct skl_pipe_params p_params = {0};
 550         struct hdac_ext_link *link;
 551         int stream_tag;
 552
 553         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 554                                         HDAC_EXT_STREAM_TYPE_LINK);
 555         if (!link_dev)
 556                 return -EBUSY;
 557
 558         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 559
 560         link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
 561         if (!link)
 562                 return -EINVAL;
 563
 564         stream_tag = hdac_stream(link_dev)->stream_tag;
 565
 566         /* set the hdac_stream in the codec dai */
 567         snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
 568
 569         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 570         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 571         p_params.ch = params_channels(params);
 572         p_params.s_freq = params_rate(params);
 573         p_params.stream = substream->stream;
 574         p_params.link_dma_id = stream_tag - 1;
 575         p_params.link_index = link->index;
 576         p_params.format = params_format(params);
 577
 578         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 579                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 580         else
 581                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 582
 583         return skl_tplg_be_update_params(dai, &p_params);
 584 }
 585
 586 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 587                 struct snd_soc_dai *dai)
 588 {
 589         struct skl_dev *skl = get_skl_ctx(dai->dev);
 590         struct skl_module_cfg *mconfig = NULL;
 591
 592         /* In case of XRUN recovery, reset the FW pipe to clean state */
 593         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 594         if (mconfig && !mconfig->pipe->passthru &&
 595                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
 596                 skl_reset_pipe(skl, mconfig->pipe);
 597
 598         return 0;
 599 }
 600
 601 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 602         int cmd, struct snd_soc_dai *dai)
 603 {
 604         struct hdac_ext_stream *link_dev =
 605                                 snd_soc_dai_get_dma_data(dai, substream);
 606         struct hdac_bus *bus = get_bus_ctx(substream);
 607         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 608
 609         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 610         switch (cmd) {
 611         case SNDRV_PCM_TRIGGER_RESUME:
 612         case SNDRV_PCM_TRIGGER_START:
 613         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 614                 snd_hdac_ext_stream_start(link_dev);
 615                 break;
 616
 617         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 618         case SNDRV_PCM_TRIGGER_SUSPEND:
 619         case SNDRV_PCM_TRIGGER_STOP:
 620                 snd_hdac_ext_stream_clear(link_dev);
 621                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 622                         snd_hdac_ext_stream_decouple(bus, stream, false);
 623                 break;
 624
 625         default:
 626                 return -EINVAL;
 627         }
 628         return 0;
 629 }
 630
 631 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 632                 struct snd_soc_dai *dai)
 633 {
 634         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 635         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 636         struct hdac_ext_stream *link_dev =
 637                                 snd_soc_dai_get_dma_data(dai, substream);
 638         struct hdac_ext_link *link;
 639         unsigned char stream_tag;
 640
 641         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 642
 643         link_dev->link_prepared = 0;
 644
 645         link = snd_hdac_ext_bus_get_hlink_by_name(bus, asoc_rtd_to_codec(rtd, 0)->component->name);
 646         if (!link)
 647                 return -EINVAL;
 648
 649         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 650                 stream_tag = hdac_stream(link_dev)->stream_tag;
 651                 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
 652         }
 653
 654         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 655         return 0;
 656 }
 657
 658 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 659         .startup = skl_pcm_open,
 660         .shutdown = skl_pcm_close,
 661         .prepare = skl_pcm_prepare,
 662         .hw_params = skl_pcm_hw_params,
 663         .hw_free = skl_pcm_hw_free,
 664         .trigger = skl_pcm_trigger,
 665 };
 666
 667 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 668         .hw_params = skl_be_hw_params,
 669 };
 670
 671 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 672         .hw_params = skl_be_hw_params,
 673 };
 674
 675 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 676         .prepare = skl_link_pcm_prepare,
 677         .hw_params = skl_link_hw_params,
 678         .hw_free = skl_link_hw_free,
 679         .trigger = skl_link_pcm_trigger,
 680 };
 681
 682 static struct snd_soc_dai_driver skl_fe_dai[] = {
 683 {
 684         .name = "System Pin",
 685         .ops = &skl_pcm_dai_ops,
 686         .playback = {
 687                 .stream_name = "System Playback",
 688                 .channels_min = HDA_MONO,
 689                 .channels_max = HDA_STEREO,
 690                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 691                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 692                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 693                 .sig_bits = 32,
 694         },
 695         .capture = {
 696                 .stream_name = "System Capture",
 697                 .channels_min = HDA_MONO,
 698                 .channels_max = HDA_STEREO,
 699                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 700                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 701                 .sig_bits = 32,
 702         },
 703 },
 704 {
 705         .name = "System Pin2",
 706         .ops = &skl_pcm_dai_ops,
 707         .playback = {
 708                 .stream_name = "Headset Playback",
 709                 .channels_min = HDA_MONO,
 710                 .channels_max = HDA_STEREO,
 711                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 712                         SNDRV_PCM_RATE_8000,
 713                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 714                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 715         },
 716 },
 717 {
 718         .name = "Echoref Pin",
 719         .ops = &skl_pcm_dai_ops,
 720         .capture = {
 721                 .stream_name = "Echoreference Capture",
 722                 .channels_min = HDA_STEREO,
 723                 .channels_max = HDA_STEREO,
 724                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 725                         SNDRV_PCM_RATE_8000,
 726                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 727                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 728         },
 729 },
 730 {
 731         .name = "Reference Pin",
 732         .ops = &skl_pcm_dai_ops,
 733         .capture = {
 734                 .stream_name = "Reference Capture",
 735                 .channels_min = HDA_MONO,
 736                 .channels_max = HDA_QUAD,
 737                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 738                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 739                 .sig_bits = 32,
 740         },
 741 },
 742 {
 743         .name = "Deepbuffer Pin",
 744         .ops = &skl_pcm_dai_ops,
 745         .playback = {
 746                 .stream_name = "Deepbuffer Playback",
 747                 .channels_min = HDA_STEREO,
 748                 .channels_max = HDA_STEREO,
 749                 .rates = SNDRV_PCM_RATE_48000,
 750                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 751                 .sig_bits = 32,
 752         },
 753 },
 754 {
 755         .name = "LowLatency Pin",
 756         .ops = &skl_pcm_dai_ops,
 757         .playback = {
 758                 .stream_name = "Low Latency Playback",
 759                 .channels_min = HDA_STEREO,
 760                 .channels_max = HDA_STEREO,
 761                 .rates = SNDRV_PCM_RATE_48000,
 762                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 763                 .sig_bits = 32,
 764         },
 765 },
 766 {
 767         .name = "DMIC Pin",
 768         .ops = &skl_pcm_dai_ops,
 769         .capture = {
 770                 .stream_name = "DMIC Capture",
 771                 .channels_min = HDA_MONO,
 772                 .channels_max = HDA_QUAD,
 773                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 774                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 775                 .sig_bits = 32,
 776         },
 777 },
 778 {
 779         .name = "HDMI1 Pin",
 780         .ops = &skl_pcm_dai_ops,
 781         .playback = {
 782                 .stream_name = "HDMI1 Playback",
 783                 .channels_min = HDA_STEREO,
 784                 .channels_max = 8,
 785                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 786                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 787                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 788                         SNDRV_PCM_RATE_192000,
 789                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 790                         SNDRV_PCM_FMTBIT_S32_LE,
 791                 .sig_bits = 32,
 792         },
 793 },
 794 {
 795         .name = "HDMI2 Pin",
 796         .ops = &skl_pcm_dai_ops,
 797         .playback = {
 798                 .stream_name = "HDMI2 Playback",
 799                 .channels_min = HDA_STEREO,
 800                 .channels_max = 8,
 801                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 802                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 803                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 804                         SNDRV_PCM_RATE_192000,
 805                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 806                         SNDRV_PCM_FMTBIT_S32_LE,
 807                 .sig_bits = 32,
 808         },
 809 },
 810 {
 811         .name = "HDMI3 Pin",
 812         .ops = &skl_pcm_dai_ops,
 813         .playback = {
 814                 .stream_name = "HDMI3 Playback",
 815                 .channels_min = HDA_STEREO,
 816                 .channels_max = 8,
 817                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 818                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 819                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 820                         SNDRV_PCM_RATE_192000,
 821                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 822                         SNDRV_PCM_FMTBIT_S32_LE,
 823                 .sig_bits = 32,
 824         },
 825 },
 826 };
 827
 828 /* BE CPU  Dais */
 829 static struct snd_soc_dai_driver skl_platform_dai[] = {
 830 {
 831         .name = "SSP0 Pin",
 832         .ops = &skl_be_ssp_dai_ops,
 833         .playback = {
 834                 .stream_name = "ssp0 Tx",
 835                 .channels_min = HDA_STEREO,
 836                 .channels_max = HDA_STEREO,
 837                 .rates = SNDRV_PCM_RATE_48000,
 838                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 839         },
 840         .capture = {
 841                 .stream_name = "ssp0 Rx",
 842                 .channels_min = HDA_STEREO,
 843                 .channels_max = HDA_STEREO,
 844                 .rates = SNDRV_PCM_RATE_48000,
 845                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 846         },
 847 },
 848 {
 849         .name = "SSP1 Pin",
 850         .ops = &skl_be_ssp_dai_ops,
 851         .playback = {
 852                 .stream_name = "ssp1 Tx",
 853                 .channels_min = HDA_STEREO,
 854                 .channels_max = HDA_STEREO,
 855                 .rates = SNDRV_PCM_RATE_48000,
 856                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 857         },
 858         .capture = {
 859                 .stream_name = "ssp1 Rx",
 860                 .channels_min = HDA_STEREO,
 861                 .channels_max = HDA_STEREO,
 862                 .rates = SNDRV_PCM_RATE_48000,
 863                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 864         },
 865 },
 866 {
 867         .name = "SSP2 Pin",
 868         .ops = &skl_be_ssp_dai_ops,
 869         .playback = {
 870                 .stream_name = "ssp2 Tx",
 871                 .channels_min = HDA_STEREO,
 872                 .channels_max = HDA_STEREO,
 873                 .rates = SNDRV_PCM_RATE_48000,
 874                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 875         },
 876         .capture = {
 877                 .stream_name = "ssp2 Rx",
 878                 .channels_min = HDA_STEREO,
 879                 .channels_max = HDA_STEREO,
 880                 .rates = SNDRV_PCM_RATE_48000,
 881                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 882         },
 883 },
 884 {
 885         .name = "SSP3 Pin",
 886         .ops = &skl_be_ssp_dai_ops,
 887         .playback = {
 888                 .stream_name = "ssp3 Tx",
 889                 .channels_min = HDA_STEREO,
 890                 .channels_max = HDA_STEREO,
 891                 .rates = SNDRV_PCM_RATE_48000,
 892                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 893         },
 894         .capture = {
 895                 .stream_name = "ssp3 Rx",
 896                 .channels_min = HDA_STEREO,
 897                 .channels_max = HDA_STEREO,
 898                 .rates = SNDRV_PCM_RATE_48000,
 899                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 900         },
 901 },
 902 {
 903         .name = "SSP4 Pin",
 904         .ops = &skl_be_ssp_dai_ops,
 905         .playback = {
 906                 .stream_name = "ssp4 Tx",
 907                 .channels_min = HDA_STEREO,
 908                 .channels_max = HDA_STEREO,
 909                 .rates = SNDRV_PCM_RATE_48000,
 910                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 911         },
 912         .capture = {
 913                 .stream_name = "ssp4 Rx",
 914                 .channels_min = HDA_STEREO,
 915                 .channels_max = HDA_STEREO,
 916                 .rates = SNDRV_PCM_RATE_48000,
 917                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 918         },
 919 },
 920 {
 921         .name = "SSP5 Pin",
 922         .ops = &skl_be_ssp_dai_ops,
 923         .playback = {
 924                 .stream_name = "ssp5 Tx",
 925                 .channels_min = HDA_STEREO,
 926                 .channels_max = HDA_STEREO,
 927                 .rates = SNDRV_PCM_RATE_48000,
 928                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 929         },
 930         .capture = {
 931                 .stream_name = "ssp5 Rx",
 932                 .channels_min = HDA_STEREO,
 933                 .channels_max = HDA_STEREO,
 934                 .rates = SNDRV_PCM_RATE_48000,
 935                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 936         },
 937 },
 938 {
 939         .name = "iDisp1 Pin",
 940         .ops = &skl_link_dai_ops,
 941         .playback = {
 942                 .stream_name = "iDisp1 Tx",
 943                 .channels_min = HDA_STEREO,
 944                 .channels_max = 8,
 945                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 946                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 947                         SNDRV_PCM_FMTBIT_S24_LE,
 948         },
 949 },
 950 {
 951         .name = "iDisp2 Pin",
 952         .ops = &skl_link_dai_ops,
 953         .playback = {
 954                 .stream_name = "iDisp2 Tx",
 955                 .channels_min = HDA_STEREO,
 956                 .channels_max = 8,
 957                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 958                         SNDRV_PCM_RATE_48000,
 959                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 960                         SNDRV_PCM_FMTBIT_S24_LE,
 961         },
 962 },
 963 {
 964         .name = "iDisp3 Pin",
 965         .ops = &skl_link_dai_ops,
 966         .playback = {
 967                 .stream_name = "iDisp3 Tx",
 968                 .channels_min = HDA_STEREO,
 969                 .channels_max = 8,
 970                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 971                         SNDRV_PCM_RATE_48000,
 972                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 973                         SNDRV_PCM_FMTBIT_S24_LE,
 974         },
 975 },
 976 {
 977         .name = "DMIC01 Pin",
 978         .ops = &skl_dmic_dai_ops,
 979         .capture = {
 980                 .stream_name = "DMIC01 Rx",
 981                 .channels_min = HDA_MONO,
 982                 .channels_max = HDA_QUAD,
 983                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 984                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 985         },
 986 },
 987 {
 988         .name = "DMIC16k Pin",
 989         .ops = &skl_dmic_dai_ops,
 990         .capture = {
 991                 .stream_name = "DMIC16k Rx",
 992                 .channels_min = HDA_MONO,
 993                 .channels_max = HDA_QUAD,
 994                 .rates = SNDRV_PCM_RATE_16000,
 995                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 996         },
 997 },
 998 {
 999         .name = "Analog CPU DAI",
1000         .ops = &skl_link_dai_ops,
1001         .playback = {
1002                 .stream_name = "Analog CPU Playback",
1003                 .channels_min = HDA_MONO,
1004                 .channels_max = HDA_MAX,
1005                 .rates = SNDRV_PCM_RATE_8000_192000,
1006                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1007                         SNDRV_PCM_FMTBIT_S32_LE,
1008         },
1009         .capture = {
1010                 .stream_name = "Analog CPU Capture",
1011                 .channels_min = HDA_MONO,
1012                 .channels_max = HDA_MAX,
1013                 .rates = SNDRV_PCM_RATE_8000_192000,
1014                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1015                         SNDRV_PCM_FMTBIT_S32_LE,
1016         },
1017 },
1018 {
1019         .name = "Alt Analog CPU DAI",
1020         .ops = &skl_link_dai_ops,
1021         .playback = {
1022                 .stream_name = "Alt Analog CPU Playback",
1023                 .channels_min = HDA_MONO,
1024                 .channels_max = HDA_MAX,
1025                 .rates = SNDRV_PCM_RATE_8000_192000,
1026                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1027                         SNDRV_PCM_FMTBIT_S32_LE,
1028         },
1029         .capture = {
1030                 .stream_name = "Alt Analog CPU Capture",
1031                 .channels_min = HDA_MONO,
1032                 .channels_max = HDA_MAX,
1033                 .rates = SNDRV_PCM_RATE_8000_192000,
1034                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1035                         SNDRV_PCM_FMTBIT_S32_LE,
1036         },
1037 },
1038 {
1039         .name = "Digital CPU DAI",
1040         .ops = &skl_link_dai_ops,
1041         .playback = {
1042                 .stream_name = "Digital CPU Playback",
1043                 .channels_min = HDA_MONO,
1044                 .channels_max = HDA_MAX,
1045                 .rates = SNDRV_PCM_RATE_8000_192000,
1046                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1047                         SNDRV_PCM_FMTBIT_S32_LE,
1048         },
1049         .capture = {
1050                 .stream_name = "Digital CPU Capture",
1051                 .channels_min = HDA_MONO,
1052                 .channels_max = HDA_MAX,
1053                 .rates = SNDRV_PCM_RATE_8000_192000,
1054                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1055                         SNDRV_PCM_FMTBIT_S32_LE,
1056         },
1057 },
1058 };
1059
1060 int skl_dai_load(struct snd_soc_component *cmp, int index,
1061                         struct snd_soc_dai_driver *dai_drv,
1062                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1063 {
1064         dai_drv->ops = &skl_pcm_dai_ops;
1065
1066         return 0;
1067 }
1068
1069 static int skl_platform_soc_open(struct snd_soc_component *component,
1070                                  struct snd_pcm_substream *substream)
1071 {
1072         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1073         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1074
1075         dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1076                                         dai_link->cpus->dai_name);
1077
1078         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1079
1080         return 0;
1081 }
1082
1083 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1084                                         int cmd)
1085 {
1086         struct hdac_bus *bus = get_bus_ctx(substream);
1087         struct hdac_ext_stream *stream;
1088         struct snd_pcm_substream *s;
1089         bool start;
1090         int sbits = 0;
1091         unsigned long cookie;
1092         struct hdac_stream *hstr;
1093
1094         stream = get_hdac_ext_stream(substream);
1095         hstr = hdac_stream(stream);
1096
1097         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1098
1099         if (!hstr->prepared)
1100                 return -EPIPE;
1101
1102         switch (cmd) {
1103         case SNDRV_PCM_TRIGGER_START:
1104         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1105         case SNDRV_PCM_TRIGGER_RESUME:
1106                 start = true;
1107                 break;
1108
1109         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1110         case SNDRV_PCM_TRIGGER_SUSPEND:
1111         case SNDRV_PCM_TRIGGER_STOP:
1112                 start = false;
1113                 break;
1114
1115         default:
1116                 return -EINVAL;
1117         }
1118
1119         snd_pcm_group_for_each_entry(s, substream) {
1120                 if (s->pcm->card != substream->pcm->card)
1121                         continue;
1122                 stream = get_hdac_ext_stream(s);
1123                 sbits |= 1 << hdac_stream(stream)->index;
1124                 snd_pcm_trigger_done(s, substream);
1125         }
1126
1127         spin_lock_irqsave(&bus->reg_lock, cookie);
1128
1129         /* first, set SYNC bits of corresponding streams */
1130         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1131
1132         snd_pcm_group_for_each_entry(s, substream) {
1133                 if (s->pcm->card != substream->pcm->card)
1134                         continue;
1135                 stream = get_hdac_ext_stream(s);
1136                 if (start)
1137                         snd_hdac_stream_start(hdac_stream(stream));
1138                 else
1139                         snd_hdac_stream_stop(hdac_stream(stream));
1140         }
1141         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1142
1143         snd_hdac_stream_sync(hstr, start, sbits);
1144
1145         spin_lock_irqsave(&bus->reg_lock, cookie);
1146
1147         /* reset SYNC bits */
1148         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1149         if (start)
1150                 snd_hdac_stream_timecounter_init(hstr, sbits);
1151         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1152
1153         return 0;
1154 }
1155
1156 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1157                                     struct snd_pcm_substream *substream,
1158                                     int cmd)
1159 {
1160         struct hdac_bus *bus = get_bus_ctx(substream);
1161
1162         if (!bus->ppcap)
1163                 return skl_coupled_trigger(substream, cmd);
1164
1165         return 0;
1166 }
1167
1168 static snd_pcm_uframes_t skl_platform_soc_pointer(
1169         struct snd_soc_component *component,
1170         struct snd_pcm_substream *substream)
1171 {
1172         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1173         struct hdac_bus *bus = get_bus_ctx(substream);
1174         unsigned int pos;
1175
1176         /*
1177          * Use DPIB for Playback stream as the periodic DMA Position-in-
1178          * Buffer Writes may be scheduled at the same time or later than
1179          * the MSI and does not guarantee to reflect the Position of the
1180          * last buffer that was transferred. Whereas DPIB register in
1181          * HAD space reflects the actual data that is transferred.
1182          * Use the position buffer for capture, as DPIB write gets
1183          * completed earlier than the actual data written to the DDR.
1184          *
1185          * For capture stream following workaround is required to fix the
1186          * incorrect position reporting.
1187          *
1188          * 1. Wait for 20us before reading the DMA position in buffer once
1189          * the interrupt is generated for stream completion as update happens
1190          * on the HDA frame boundary i.e. 20.833uSec.
1191          * 2. Read DPIB register to flush the DMA position value. This dummy
1192          * read is required to flush DMA position value.
1193          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1194          * or greater than period boundary.
1195          */
1196
1197         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1198                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1199                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1200                                 hdac_stream(hstream)->index));
1201         } else {
1202                 udelay(20);
1203                 readl(bus->remap_addr +
1204                                 AZX_REG_VS_SDXDPIB_XBASE +
1205                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1206                                  hdac_stream(hstream)->index));
1207                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1208         }
1209
1210         if (pos >= hdac_stream(hstream)->bufsize)
1211                 pos = 0;
1212
1213         return bytes_to_frames(substream->runtime, pos);
1214 }
1215
1216 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1217                                 u64 nsec)
1218 {
1219         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1220         struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
1221         u64 codec_frames, codec_nsecs;
1222
1223         if (!codec_dai->driver->ops->delay)
1224                 return nsec;
1225
1226         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1227         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1228                               substream->runtime->rate);
1229
1230         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1231                 return nsec + codec_nsecs;
1232
1233         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1234 }
1235
1236 static int skl_platform_soc_get_time_info(
1237                         struct snd_soc_component *component,
1238                         struct snd_pcm_substream *substream,
1239                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
1240                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1241                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1242 {
1243         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1244         struct hdac_stream *hstr = hdac_stream(sstream);
1245         u64 nsec;
1246
1247         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1248                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1249
1250                 snd_pcm_gettime(substream->runtime, system_ts);
1251
1252                 nsec = timecounter_read(&hstr->tc);
1253                 if (audio_tstamp_config->report_delay)
1254                         nsec = skl_adjust_codec_delay(substream, nsec);
1255
1256                 *audio_ts = ns_to_timespec64(nsec);
1257
1258                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1259                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1260                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1261
1262         } else {
1263                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1264         }
1265
1266         return 0;
1267 }
1268
1269 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1270
1271 static int skl_platform_soc_new(struct snd_soc_component *component,
1272                                 struct snd_soc_pcm_runtime *rtd)
1273 {
1274         struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
1275         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1276         struct snd_pcm *pcm = rtd->pcm;
1277         unsigned int size;
1278         struct skl_dev *skl = bus_to_skl(bus);
1279
1280         if (dai->driver->playback.channels_min ||
1281                 dai->driver->capture.channels_min) {
1282                 /* buffer pre-allocation */
1283                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1284                 if (size > MAX_PREALLOC_SIZE)
1285                         size = MAX_PREALLOC_SIZE;
1286                 snd_pcm_set_managed_buffer_all(pcm,
1287                                                SNDRV_DMA_TYPE_DEV_SG,
1288                                                &skl->pci->dev,
1289                                                size, MAX_PREALLOC_SIZE);
1290         }
1291
1292         return 0;
1293 }
1294
1295 static int skl_get_module_info(struct skl_dev *skl,
1296                 struct skl_module_cfg *mconfig)
1297 {
1298         struct skl_module_inst_id *pin_id;
1299         guid_t *uuid_mod, *uuid_tplg;
1300         struct skl_module *skl_module;
1301         struct uuid_module *module;
1302         int i, ret = -EIO;
1303
1304         uuid_mod = (guid_t *)mconfig->guid;
1305
1306         if (list_empty(&skl->uuid_list)) {
1307                 dev_err(skl->dev, "Module list is empty\n");
1308                 return -EIO;
1309         }
1310
1311         for (i = 0; i < skl->nr_modules; i++) {
1312                 skl_module = skl->modules[i];
1313                 uuid_tplg = &skl_module->uuid;
1314                 if (guid_equal(uuid_mod, uuid_tplg)) {
1315                         mconfig->module = skl_module;
1316                         ret = 0;
1317                         break;
1318                 }
1319         }
1320
1321         if (skl->nr_modules && ret)
1322                 return ret;
1323
1324         ret = -EIO;
1325         list_for_each_entry(module, &skl->uuid_list, list) {
1326                 if (guid_equal(uuid_mod, &module->uuid)) {
1327                         mconfig->id.module_id = module->id;
1328                         mconfig->module->loadable = module->is_loadable;
1329                         ret = 0;
1330                 }
1331
1332                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1333                         pin_id = &mconfig->m_in_pin[i].id;
1334                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1335                                 pin_id->module_id = module->id;
1336                 }
1337
1338                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1339                         pin_id = &mconfig->m_out_pin[i].id;
1340                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1341                                 pin_id->module_id = module->id;
1342                 }
1343         }
1344
1345         return ret;
1346 }
1347
1348 static int skl_populate_modules(struct skl_dev *skl)
1349 {
1350         struct skl_pipeline *p;
1351         struct skl_pipe_module *m;
1352         struct snd_soc_dapm_widget *w;
1353         struct skl_module_cfg *mconfig;
1354         int ret = 0;
1355
1356         list_for_each_entry(p, &skl->ppl_list, node) {
1357                 list_for_each_entry(m, &p->pipe->w_list, node) {
1358                         w = m->w;
1359                         mconfig = w->priv;
1360
1361                         ret = skl_get_module_info(skl, mconfig);
1362                         if (ret < 0) {
1363                                 dev_err(skl->dev,
1364                                         "query module info failed\n");
1365                                 return ret;
1366                         }
1367
1368                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1369                 }
1370         }
1371
1372         return ret;
1373 }
1374
1375 static int skl_platform_soc_probe(struct snd_soc_component *component)
1376 {
1377         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1378         struct skl_dev *skl = bus_to_skl(bus);
1379         const struct skl_dsp_ops *ops;
1380         int ret;
1381
1382         ret = pm_runtime_resume_and_get(component->dev);
1383         if (ret < 0 && ret != -EACCES)
1384                 return ret;
1385
1386         if (bus->ppcap) {
1387                 skl->component = component;
1388
1389                 /* init debugfs */
1390                 skl->debugfs = skl_debugfs_init(skl);
1391
1392                 ret = skl_tplg_init(component, bus);
1393                 if (ret < 0) {
1394                         dev_err(component->dev, "Failed to init topology!\n");
1395                         return ret;
1396                 }
1397
1398                 /* load the firmwares, since all is set */
1399                 ops = skl_get_dsp_ops(skl->pci->device);
1400                 if (!ops)
1401                         return -EIO;
1402
1403                 /*
1404                  * Disable dynamic clock and power gating during firmware
1405                  * and library download
1406                  */
1407                 skl->enable_miscbdcge(component->dev, false);
1408                 skl->clock_power_gating(component->dev, false);
1409
1410                 ret = ops->init_fw(component->dev, skl);
1411                 skl->enable_miscbdcge(component->dev, true);
1412                 skl->clock_power_gating(component->dev, true);
1413                 if (ret < 0) {
1414                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1415                         return ret;
1416                 }
1417                 skl_populate_modules(skl);
1418                 skl->update_d0i3c = skl_update_d0i3c;
1419
1420                 if (skl->cfg.astate_cfg != NULL) {
1421                         skl_dsp_set_astate_cfg(skl,
1422                                         skl->cfg.astate_cfg->count,
1423                                         skl->cfg.astate_cfg);
1424                 }
1425         }
1426         pm_runtime_mark_last_busy(component->dev);
1427         pm_runtime_put_autosuspend(component->dev);
1428
1429         return 0;
1430 }
1431
1432 static void skl_platform_soc_remove(struct snd_soc_component *component)
1433 {
1434         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1435         struct skl_dev *skl = bus_to_skl(bus);
1436
1437         skl_tplg_exit(component, bus);
1438
1439         skl_debugfs_exit(skl);
1440 }
1441
1442 static const struct snd_soc_component_driver skl_component  = {
1443         .name           = "pcm",
1444         .probe          = skl_platform_soc_probe,
1445         .remove         = skl_platform_soc_remove,
1446         .open           = skl_platform_soc_open,
1447         .trigger        = skl_platform_soc_trigger,
1448         .pointer        = skl_platform_soc_pointer,
1449         .get_time_info  = skl_platform_soc_get_time_info,
1450         .pcm_construct  = skl_platform_soc_new,
1451         .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1452 };
1453
1454 int skl_platform_register(struct device *dev)
1455 {
1456         int ret;
1457         struct snd_soc_dai_driver *dais;
1458         int num_dais = ARRAY_SIZE(skl_platform_dai);
1459         struct hdac_bus *bus = dev_get_drvdata(dev);
1460         struct skl_dev *skl = bus_to_skl(bus);
1461
1462         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1463                             GFP_KERNEL);
1464         if (!skl->dais) {
1465                 ret = -ENOMEM;
1466                 goto err;
1467         }
1468
1469         if (!skl->use_tplg_pcm) {
1470                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1471                                 sizeof(skl_platform_dai), GFP_KERNEL);
1472                 if (!dais) {
1473                         ret = -ENOMEM;
1474                         goto err;
1475                 }
1476
1477                 skl->dais = dais;
1478                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1479                        sizeof(skl_fe_dai));
1480                 num_dais += ARRAY_SIZE(skl_fe_dai);
1481         }
1482
1483         ret = devm_snd_soc_register_component(dev, &skl_component,
1484                                          skl->dais, num_dais);
1485         if (ret)
1486                 dev_err(dev, "soc component registration failed %d\n", ret);
1487 err:
1488         return ret;
1489 }
1490
1491 int skl_platform_unregister(struct device *dev)
1492 {
1493         struct hdac_bus *bus = dev_get_drvdata(dev);
1494         struct skl_dev *skl = bus_to_skl(bus);
1495         struct skl_module_deferred_bind *modules, *tmp;
1496
1497         list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1498                 list_del(&modules->node);
1499                 kfree(modules);
1500         }
1501
1502         kfree(skl->dais);
1503
1504         return 0;
1505 }