1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
9 // Krzysztof Hejmowski <krzysztof.hejmowski@intel.com>
10 // Michal Sienkiewicz <michal.sienkiewicz@intel.com>
13 // for sharing Intel AudioDSP expertise and helping shape the very
14 // foundation of this driver
17 #include <linux/pci.h>
18 #include <sound/hdaudio.h>
22 avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
24 struct pci_dev *pci = to_pci_dev(bus->dev);
27 pci_read_config_dword(pci, reg, &data);
29 data |= (value & mask);
30 pci_write_config_dword(pci, reg, data);
33 void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
37 value = enable ? 0 : AZX_PGCTL_LSRMD_MASK;
38 avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL,
39 AZX_PGCTL_LSRMD_MASK, value);
42 static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
46 value = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
47 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, value);
50 void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
52 avs_hdac_clock_gating_enable(&adev->base.core, enable);
55 void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
59 value = enable ? AZX_VS_EM2_L1SEN : 0;
60 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value);