1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
9 // Krzysztof Hejmowski <krzysztof.hejmowski@intel.com>
10 // Michal Sienkiewicz <michal.sienkiewicz@intel.com>
13 // for sharing Intel AudioDSP expertise and helping shape the very
14 // foundation of this driver
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <sound/hda_codec.h>
20 #include <sound/hda_i915.h>
21 #include <sound/hda_register.h>
22 #include <sound/hdaudio.h>
23 #include <sound/hdaudio_ext.h>
24 #include <sound/intel-dsp-config.h>
25 #include <sound/intel-nhlt.h>
26 #include "../../codecs/hda.h"
30 static u32 pgctl_mask = AZX_PGCTL_LSRMD_MASK;
31 module_param(pgctl_mask, uint, 0444);
32 MODULE_PARM_DESC(pgctl_mask, "PCI PGCTL policy override");
34 static u32 cgctl_mask = AZX_CGCTL_MISCBDCGE_MASK;
35 module_param(cgctl_mask, uint, 0444);
36 MODULE_PARM_DESC(cgctl_mask, "PCI CGCTL policy override");
39 avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
41 struct pci_dev *pci = to_pci_dev(bus->dev);
44 pci_read_config_dword(pci, reg, &data);
46 data |= (value & mask);
47 pci_write_config_dword(pci, reg, data);
50 void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
52 u32 value = enable ? 0 : pgctl_mask;
54 avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL, pgctl_mask, value);
57 static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
59 u32 value = enable ? cgctl_mask : 0;
61 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, cgctl_mask, value);
64 void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
66 avs_hdac_clock_gating_enable(&adev->base.core, enable);
69 void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
71 u32 value = enable ? AZX_VS_EM2_L1SEN : 0;
73 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value);
76 static int avs_hdac_bus_init_streams(struct hdac_bus *bus)
78 unsigned int cp_streams, pb_streams;
81 gcap = snd_hdac_chip_readw(bus, GCAP);
82 cp_streams = (gcap >> 8) & 0x0F;
83 pb_streams = (gcap >> 12) & 0x0F;
84 bus->num_streams = cp_streams + pb_streams;
86 snd_hdac_ext_stream_init_all(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
87 snd_hdac_ext_stream_init_all(bus, cp_streams, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
89 return snd_hdac_bus_alloc_stream_pages(bus);
92 static bool avs_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
94 struct hdac_ext_link *hlink;
97 avs_hdac_clock_gating_enable(bus, false);
98 ret = snd_hdac_bus_init_chip(bus, full_reset);
100 /* Reset stream-to-link mapping */
101 list_for_each_entry(hlink, &bus->hlink_list, list)
102 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
104 avs_hdac_clock_gating_enable(bus, true);
106 /* Set DUM bit to address incorrect position reporting for capture
107 * streams. In order to do so, CTRL needs to be out of reset state
109 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
114 static int probe_codec(struct hdac_bus *bus, int addr)
116 struct hda_codec *codec;
117 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
118 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
119 unsigned int res = -1;
122 mutex_lock(&bus->cmd_mutex);
123 snd_hdac_bus_send_cmd(bus, cmd);
124 snd_hdac_bus_get_response(bus, addr, &res);
125 mutex_unlock(&bus->cmd_mutex);
129 dev_dbg(bus->dev, "codec #%d probed OK: 0x%x\n", addr, res);
131 codec = snd_hda_codec_device_init(to_hda_bus(bus), addr, "hdaudioB%dD%d", bus->idx, addr);
133 dev_err(bus->dev, "init codec failed: %ld\n", PTR_ERR(codec));
134 return PTR_ERR(codec);
137 * Allow avs_core suspend by forcing suspended state on all
138 * of its codec child devices. Component interested in
139 * dealing with hda codecs directly takes pm responsibilities
141 pm_runtime_set_suspended(hda_codec_dev(codec));
143 /* configure effectively creates new ASoC component */
144 ret = snd_hda_codec_configure(codec);
146 dev_err(bus->dev, "failed to config codec %d\n", ret);
153 static void avs_hdac_bus_probe_codecs(struct hdac_bus *bus)
157 /* First try to probe all given codec slots */
158 for (c = 0; c < HDA_MAX_CODECS; c++) {
159 if (!(bus->codec_mask & BIT(c)))
162 if (!probe_codec(bus, c))
163 /* success, continue probing */
167 * Some BIOSen give you wrong codec addresses
170 dev_warn(bus->dev, "Codec #%d probe error; disabling it...\n", c);
171 bus->codec_mask &= ~BIT(c);
173 * More badly, accessing to a non-existing
174 * codec often screws up the controller bus,
175 * and disturbs the further communications.
176 * Thus if an error occurs during probing,
177 * better to reset the controller bus to get
178 * back to the sanity state.
180 snd_hdac_bus_stop_chip(bus);
181 avs_hdac_bus_init_chip(bus, true);
185 static void avs_hda_probe_work(struct work_struct *work)
187 struct avs_dev *adev = container_of(work, struct avs_dev, probe_work);
188 struct hdac_bus *bus = &adev->base.core;
189 struct hdac_ext_link *hlink;
192 pm_runtime_set_active(bus->dev); /* clear runtime_error flag */
194 ret = snd_hdac_i915_init(bus);
196 dev_info(bus->dev, "i915 init unsuccessful: %d\n", ret);
198 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
199 avs_hdac_bus_init_chip(bus, true);
200 avs_hdac_bus_probe_codecs(bus);
201 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
203 /* with all codecs probed, links can be powered down */
204 list_for_each_entry(hlink, &bus->hlink_list, list)
205 snd_hdac_ext_bus_link_put(bus, hlink);
207 snd_hdac_ext_bus_ppcap_enable(bus, true);
208 snd_hdac_ext_bus_ppcap_int_enable(bus, true);
210 ret = avs_dsp_first_boot_firmware(adev);
214 adev->nhlt = intel_nhlt_init(adev->dev);
216 dev_info(bus->dev, "platform has no NHLT\n");
218 avs_register_all_boards(adev);
221 pm_runtime_set_autosuspend_delay(bus->dev, 2000);
222 pm_runtime_use_autosuspend(bus->dev);
223 pm_runtime_mark_last_busy(bus->dev);
224 pm_runtime_put_autosuspend(bus->dev);
225 pm_runtime_allow(bus->dev);
228 static void hdac_stream_update_pos(struct hdac_stream *stream, u64 buffer_size)
230 u64 prev_pos, pos, num_bytes;
232 div64_u64_rem(stream->curr_pos, buffer_size, &prev_pos);
233 pos = snd_hdac_stream_get_pos_posbuf(stream);
236 num_bytes = (buffer_size - prev_pos) + pos;
238 num_bytes = pos - prev_pos;
240 stream->curr_pos += num_bytes;
243 /* called from IRQ */
244 static void hdac_update_stream(struct hdac_bus *bus, struct hdac_stream *stream)
246 if (stream->substream) {
247 snd_pcm_period_elapsed(stream->substream);
248 } else if (stream->cstream) {
249 u64 buffer_size = stream->cstream->runtime->buffer_size;
251 hdac_stream_update_pos(stream, buffer_size);
252 snd_compr_fragment_elapsed(stream->cstream);
256 static irqreturn_t hdac_bus_irq_handler(int irq, void *context)
258 struct hdac_bus *bus = context;
259 u32 mask, int_enable;
263 if (!pm_runtime_active(bus->dev))
266 spin_lock(&bus->reg_lock);
268 status = snd_hdac_chip_readl(bus, INTSTS);
269 if (status == 0 || status == UINT_MAX) {
270 spin_unlock(&bus->reg_lock);
275 status = snd_hdac_chip_readb(bus, RIRBSTS);
276 if (status & RIRB_INT_MASK) {
277 if (status & RIRB_INT_RESPONSE)
278 snd_hdac_bus_update_rirb(bus);
279 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
282 mask = (0x1 << bus->num_streams) - 1;
284 status = snd_hdac_chip_readl(bus, INTSTS);
287 /* Disable stream interrupts; Re-enable in bottom half */
288 int_enable = snd_hdac_chip_readl(bus, INTCTL);
289 snd_hdac_chip_writel(bus, INTCTL, (int_enable & (~mask)));
290 ret = IRQ_WAKE_THREAD;
295 spin_unlock(&bus->reg_lock);
299 static irqreturn_t hdac_bus_irq_thread(int irq, void *context)
301 struct hdac_bus *bus = context;
307 status = snd_hdac_chip_readl(bus, INTSTS);
309 snd_hdac_bus_handle_stream_irq(bus, status, hdac_update_stream);
311 /* Re-enable stream interrupts */
312 mask = (0x1 << bus->num_streams) - 1;
313 spin_lock_irqsave(&bus->reg_lock, flags);
314 int_enable = snd_hdac_chip_readl(bus, INTCTL);
315 snd_hdac_chip_writel(bus, INTCTL, (int_enable | mask));
316 spin_unlock_irqrestore(&bus->reg_lock, flags);
321 static int avs_hdac_acquire_irq(struct avs_dev *adev)
323 struct hdac_bus *bus = &adev->base.core;
324 struct pci_dev *pci = to_pci_dev(bus->dev);
327 /* request one and check that we only got one interrupt */
328 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI | PCI_IRQ_LEGACY);
330 dev_err(adev->dev, "Failed to allocate IRQ vector: %d\n", ret);
334 ret = pci_request_irq(pci, 0, hdac_bus_irq_handler, hdac_bus_irq_thread, bus,
337 dev_err(adev->dev, "Failed to request stream IRQ handler: %d\n", ret);
341 ret = pci_request_irq(pci, 0, avs_dsp_irq_handler, avs_dsp_irq_thread, adev,
344 dev_err(adev->dev, "Failed to request IPC IRQ handler: %d\n", ret);
345 goto free_stream_irq;
351 pci_free_irq(pci, 0, bus);
353 pci_free_irq_vectors(pci);
357 static int avs_bus_init(struct avs_dev *adev, struct pci_dev *pci, const struct pci_device_id *id)
359 struct hda_bus *bus = &adev->base;
361 struct device *dev = &pci->dev;
364 ret = snd_hdac_ext_bus_init(&bus->core, dev, NULL, &soc_hda_ext_bus_ops);
368 bus->core.use_posbuf = 1;
369 bus->core.bdl_pos_adj = 0;
370 bus->core.sync_write = 1;
372 bus->mixer_assigned = -1;
373 mutex_init(&bus->prepare_mutex);
375 ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL);
378 ret = avs_ipc_init(ipc, dev);
383 adev->spec = (const struct avs_spec *)id->driver_data;
385 adev->hw_cfg.dsp_cores = hweight_long(AVS_MAIN_CORE_MASK);
386 INIT_WORK(&adev->probe_work, avs_hda_probe_work);
387 INIT_LIST_HEAD(&adev->comp_list);
388 INIT_LIST_HEAD(&adev->path_list);
389 INIT_LIST_HEAD(&adev->fw_list);
390 init_completion(&adev->fw_ready);
391 spin_lock_init(&adev->path_list_lock);
392 mutex_init(&adev->modres_mutex);
393 mutex_init(&adev->comp_list_mutex);
394 mutex_init(&adev->path_mutex);
399 static int avs_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
401 struct hdac_bus *bus;
402 struct avs_dev *adev;
403 struct device *dev = &pci->dev;
406 ret = snd_intel_dsp_driver_probe(pci);
407 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_AVS)
410 ret = pcim_enable_device(pci);
414 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
417 ret = avs_bus_init(adev, pci, id);
419 dev_err(dev, "failed to init avs bus: %d\n", ret);
423 ret = pci_request_regions(pci, "AVS HDAudio");
427 bus = &adev->base.core;
428 bus->addr = pci_resource_start(pci, 0);
429 bus->remap_addr = pci_ioremap_bar(pci, 0);
430 if (!bus->remap_addr) {
431 dev_err(bus->dev, "ioremap error\n");
436 adev->dsp_ba = pci_ioremap_bar(pci, 4);
438 dev_err(bus->dev, "ioremap error\n");
443 snd_hdac_bus_parse_capabilities(bus);
445 snd_hdac_ext_bus_get_ml_capabilities(bus);
447 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))
448 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
449 dma_set_max_seg_size(dev, UINT_MAX);
451 ret = avs_hdac_bus_init_streams(bus);
453 dev_err(dev, "failed to init streams: %d\n", ret);
454 goto err_init_streams;
457 ret = avs_hdac_acquire_irq(adev);
459 dev_err(bus->dev, "failed to acquire irq: %d\n", ret);
460 goto err_acquire_irq;
464 pci_set_drvdata(pci, bus);
465 device_disable_async_suspend(dev);
467 schedule_work(&adev->probe_work);
472 snd_hdac_bus_free_stream_pages(bus);
473 snd_hdac_ext_stream_free_all(bus);
475 iounmap(adev->dsp_ba);
477 iounmap(bus->remap_addr);
479 pci_release_regions(pci);
483 static void avs_pci_remove(struct pci_dev *pci)
485 struct hdac_device *hdev, *save;
486 struct hdac_bus *bus = pci_get_drvdata(pci);
487 struct avs_dev *adev = hdac_to_avs(bus);
489 cancel_work_sync(&adev->probe_work);
490 avs_ipc_block(adev->ipc);
492 avs_unregister_all_boards(adev);
495 intel_nhlt_free(adev->nhlt);
497 if (avs_platattr_test(adev, CLDMA))
498 hda_cldma_free(&code_loader);
500 snd_hdac_stop_streams_and_chip(bus);
501 avs_dsp_op(adev, int_control, false);
502 snd_hdac_ext_bus_ppcap_int_enable(bus, false);
504 /* it is safe to remove all codecs from the system now */
505 list_for_each_entry_safe(hdev, save, &bus->codec_list, list)
506 snd_hda_codec_unregister(hdac_to_hda_codec(hdev));
508 snd_hdac_bus_free_stream_pages(bus);
509 snd_hdac_ext_stream_free_all(bus);
510 /* reverse ml_capabilities */
511 snd_hdac_ext_link_free_all(bus);
512 snd_hdac_ext_bus_exit(bus);
514 avs_dsp_core_disable(adev, GENMASK(adev->hw_cfg.dsp_cores - 1, 0));
515 snd_hdac_ext_bus_ppcap_enable(bus, false);
517 /* snd_hdac_stop_streams_and_chip does that already? */
518 snd_hdac_bus_stop_chip(bus);
519 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
520 if (bus->audio_component)
521 snd_hdac_i915_exit(bus);
523 avs_module_info_free(adev);
524 pci_free_irq(pci, 0, adev);
525 pci_free_irq(pci, 0, bus);
526 pci_free_irq_vectors(pci);
527 iounmap(bus->remap_addr);
528 iounmap(adev->dsp_ba);
529 pci_release_regions(pci);
531 /* Firmware is not needed anymore */
532 avs_release_firmwares(adev);
534 /* pm_runtime_forbid() can rpm_resume() which we do not want */
535 pm_runtime_disable(&pci->dev);
536 pm_runtime_forbid(&pci->dev);
537 pm_runtime_enable(&pci->dev);
538 pm_runtime_get_noresume(&pci->dev);
541 static int avs_suspend_standby(struct avs_dev *adev)
543 struct hdac_bus *bus = &adev->base.core;
544 struct pci_dev *pci = adev->base.pci;
546 if (bus->cmd_dma_state)
547 snd_hdac_bus_stop_cmd_io(bus);
549 snd_hdac_ext_bus_link_power_down_all(bus);
551 enable_irq_wake(pci->irq);
557 static int __maybe_unused avs_suspend_common(struct avs_dev *adev, bool low_power)
559 struct hdac_bus *bus = &adev->base.core;
562 flush_work(&adev->probe_work);
563 if (low_power && adev->num_lp_paths)
564 return avs_suspend_standby(adev);
566 snd_hdac_ext_bus_link_power_down_all(bus);
568 ret = avs_ipc_set_dx(adev, AVS_MAIN_CORE_MASK, false);
570 * pm_runtime is blocked on DSP failure but system-wide suspend is not.
571 * Do not block entire system from suspending if that's the case.
573 if (ret && ret != -EPERM) {
574 dev_err(adev->dev, "set dx failed: %d\n", ret);
575 return AVS_IPC_RET(ret);
578 avs_ipc_block(adev->ipc);
579 avs_dsp_op(adev, int_control, false);
580 snd_hdac_ext_bus_ppcap_int_enable(bus, false);
582 ret = avs_dsp_core_disable(adev, AVS_MAIN_CORE_MASK);
584 dev_err(adev->dev, "core_mask %ld disable failed: %d\n", AVS_MAIN_CORE_MASK, ret);
588 snd_hdac_ext_bus_ppcap_enable(bus, false);
589 /* disable LP SRAM retention */
590 avs_hda_power_gating_enable(adev, false);
591 snd_hdac_bus_stop_chip(bus);
592 /* disable CG when putting controller to reset */
593 avs_hdac_clock_gating_enable(bus, false);
594 snd_hdac_bus_enter_link_reset(bus);
595 avs_hdac_clock_gating_enable(bus, true);
597 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
602 static int avs_resume_standby(struct avs_dev *adev)
604 struct hdac_bus *bus = &adev->base.core;
605 struct pci_dev *pci = adev->base.pci;
607 pci_restore_state(pci);
608 disable_irq_wake(pci->irq);
610 snd_hdac_ext_bus_link_power_up_all(bus);
612 if (bus->cmd_dma_state)
613 snd_hdac_bus_init_cmd_io(bus);
618 static int __maybe_unused avs_resume_common(struct avs_dev *adev, bool low_power, bool purge)
620 struct hdac_bus *bus = &adev->base.core;
623 if (low_power && adev->num_lp_paths)
624 return avs_resume_standby(adev);
626 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
627 avs_hdac_bus_init_chip(bus, true);
629 snd_hdac_ext_bus_ppcap_enable(bus, true);
630 snd_hdac_ext_bus_ppcap_int_enable(bus, true);
632 ret = avs_dsp_boot_firmware(adev, purge);
634 dev_err(adev->dev, "firmware boot failed: %d\n", ret);
641 static int __maybe_unused avs_suspend(struct device *dev)
643 return avs_suspend_common(to_avs_dev(dev), true);
646 static int __maybe_unused avs_resume(struct device *dev)
648 return avs_resume_common(to_avs_dev(dev), true, true);
651 static int __maybe_unused avs_runtime_suspend(struct device *dev)
653 return avs_suspend_common(to_avs_dev(dev), true);
656 static int __maybe_unused avs_runtime_resume(struct device *dev)
658 return avs_resume_common(to_avs_dev(dev), true, false);
661 static int __maybe_unused avs_freeze(struct device *dev)
663 return avs_suspend_common(to_avs_dev(dev), false);
665 static int __maybe_unused avs_thaw(struct device *dev)
667 return avs_resume_common(to_avs_dev(dev), false, true);
670 static int __maybe_unused avs_poweroff(struct device *dev)
672 return avs_suspend_common(to_avs_dev(dev), false);
675 static int __maybe_unused avs_restore(struct device *dev)
677 return avs_resume_common(to_avs_dev(dev), false, true);
680 static const struct dev_pm_ops avs_dev_pm = {
681 .suspend = avs_suspend,
682 .resume = avs_resume,
683 .freeze = avs_freeze,
685 .poweroff = avs_poweroff,
686 .restore = avs_restore,
687 SET_RUNTIME_PM_OPS(avs_runtime_suspend, avs_runtime_resume, NULL)
690 static const struct avs_spec skl_desc = {
698 .dsp_ops = &skl_dsp_ops,
700 .attributes = AVS_PLATATTR_CLDMA,
701 .sram_base_offset = SKL_ADSP_SRAM_BASE_OFFSET,
702 .sram_window_size = SKL_ADSP_SRAM_WINDOW_SIZE,
703 .rom_status = SKL_ADSP_SRAM_BASE_OFFSET,
706 static const struct avs_spec apl_desc = {
714 .dsp_ops = &apl_dsp_ops,
716 .attributes = AVS_PLATATTR_IMR,
717 .sram_base_offset = APL_ADSP_SRAM_BASE_OFFSET,
718 .sram_window_size = APL_ADSP_SRAM_WINDOW_SIZE,
719 .rom_status = APL_ADSP_SRAM_BASE_OFFSET,
722 static const struct pci_device_id avs_ids[] = {
723 { PCI_VDEVICE(INTEL, 0x9d70), (unsigned long)&skl_desc }, /* SKL */
724 { PCI_VDEVICE(INTEL, 0xa170), (unsigned long)&skl_desc }, /* SKL-H */
725 { PCI_VDEVICE(INTEL, 0x9d71), (unsigned long)&skl_desc }, /* KBL */
726 { PCI_VDEVICE(INTEL, 0xa171), (unsigned long)&skl_desc }, /* KBL-H */
727 { PCI_VDEVICE(INTEL, 0xa2f0), (unsigned long)&skl_desc }, /* KBL-S */
728 { PCI_VDEVICE(INTEL, 0xa3f0), (unsigned long)&skl_desc }, /* CML-V */
729 { PCI_VDEVICE(INTEL, 0x5a98), (unsigned long)&apl_desc }, /* APL */
730 { PCI_VDEVICE(INTEL, 0x3198), (unsigned long)&apl_desc }, /* GML */
733 MODULE_DEVICE_TABLE(pci, avs_ids);
735 static struct pci_driver avs_pci_driver = {
736 .name = KBUILD_MODNAME,
738 .probe = avs_pci_probe,
739 .remove = avs_pci_remove,
744 module_pci_driver(avs_pci_driver);
746 MODULE_AUTHOR("Cezary Rojewski <cezary.rojewski@intel.com>");
747 MODULE_AUTHOR("Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>");
748 MODULE_DESCRIPTION("Intel cAVS sound driver");
749 MODULE_LICENSE("GPL");