2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * The SSI has a limitation in that the samples must be in the same byte
71 * order as the host CPU. This is because when multiple bytes are written
72 * to the STX register, the bytes and bits must be written in the same
73 * order. The STX is a shift register, so all the bits need to be aligned
74 * (bit-endianness must match byte-endianness). Processors typically write
75 * the bits within a byte in the same order that the bytes of a word are
76 * written in. So if the host CPU is big-endian, then only big-endian
77 * samples will be written to STX properly.
80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
103 struct fsl_ssi_reg_val {
110 struct fsl_ssi_rxtx_reg_val {
111 struct fsl_ssi_reg_val rx;
112 struct fsl_ssi_reg_val tx;
115 static const struct reg_default fsl_ssi_reg_defaults[] = {
116 {CCSR_SSI_SCR, 0x00000000},
117 {CCSR_SSI_SIER, 0x00003003},
118 {CCSR_SSI_STCR, 0x00000200},
119 {CCSR_SSI_SRCR, 0x00000200},
120 {CCSR_SSI_STCCR, 0x00040000},
121 {CCSR_SSI_SRCCR, 0x00040000},
122 {CCSR_SSI_SACNT, 0x00000000},
123 {CCSR_SSI_STMSK, 0x00000000},
124 {CCSR_SSI_SRMSK, 0x00000000},
125 {CCSR_SSI_SACCEN, 0x00000000},
126 {CCSR_SSI_SACCDIS, 0x00000000},
129 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
132 case CCSR_SSI_SACCEN:
133 case CCSR_SSI_SACCDIS:
140 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
150 case CCSR_SSI_SACADD:
151 case CCSR_SSI_SACDAT:
153 case CCSR_SSI_SACCST:
160 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
165 case CCSR_SSI_SACCST:
172 static const struct regmap_config fsl_ssi_regconfig = {
173 .max_register = CCSR_SSI_SACCDIS,
177 .val_format_endian = REGMAP_ENDIAN_NATIVE,
178 .reg_defaults = fsl_ssi_reg_defaults,
179 .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
180 .readable_reg = fsl_ssi_readable_reg,
181 .volatile_reg = fsl_ssi_volatile_reg,
182 .writeable_reg = fsl_ssi_writeable_reg,
183 .cache_type = REGCACHE_RBTREE,
186 struct fsl_ssi_soc_data {
193 * fsl_ssi_private: per-SSI private data
195 * @reg: Pointer to the regmap registers
196 * @irq: IRQ of this SSI
197 * @cpu_dai_drv: CPU DAI driver for this device
199 * @dai_fmt: DAI configuration this device is currently used with
200 * @i2s_mode: i2s and network mode configuration of the device. Is used to
201 * switch between normal and i2s/network mode
202 * mode depending on the number of channels
203 * @use_dma: DMA is used or FIQ with stream filter
204 * @use_dual_fifo: DMA with support for both FIFOs used
205 * @fifo_deph: Depth of the SSI FIFOs
206 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
209 * @baudclk: SSI baud clock for master mode
210 * @baudclk_streams: Active streams that are using baudclk
211 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
213 * @dma_params_tx: DMA transmit parameters
214 * @dma_params_rx: DMA receive parameters
215 * @ssi_phys: physical address of the SSI registers
217 * @fiq_params: FIQ stream filtering parameters
219 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
221 * @dbg_stats: Debugging statistics
223 * @soc: SoC specific data
225 struct fsl_ssi_private {
228 struct snd_soc_dai_driver cpu_dai_drv;
230 unsigned int dai_fmt;
234 bool has_ipg_clk_name;
235 unsigned int fifo_depth;
236 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
240 unsigned int baudclk_streams;
241 unsigned int bitclk_freq;
243 /* regcache for volatile regs */
248 struct snd_dmaengine_dai_dma_data dma_params_tx;
249 struct snd_dmaengine_dai_dma_data dma_params_rx;
252 /* params for non-dma FIQ stream filtered mode */
253 struct imx_pcm_fiq_params fiq_params;
255 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
256 * should be replaced with simple-sound-card. */
257 struct platform_device *pdev;
259 struct fsl_ssi_dbg dbg_stats;
261 const struct fsl_ssi_soc_data *soc;
265 * imx51 and later SoCs have a slightly different IP that allows the
266 * SSI configuration while the SSI unit is running.
268 * More important, it is necessary on those SoCs to configure the
269 * sperate TX/RX DMA bits just before starting the stream
270 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
271 * sends any DMA requests to the SDMA unit, otherwise it is not defined
272 * how the SDMA unit handles the DMA request.
274 * SDMA units are present on devices starting at imx35 but the imx35
275 * reference manual states that the DMA bits should not be changed
276 * while the SSI unit is running (SSIEN). So we support the necessary
277 * online configuration of fsl-ssi starting at imx51.
280 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
282 .offline_config = true,
283 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
284 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
285 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
288 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
290 .offline_config = true,
291 .sisr_write_mask = 0,
294 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
296 .offline_config = true,
297 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
298 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
299 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
302 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
304 .offline_config = false,
305 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
306 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
309 static const struct of_device_id fsl_ssi_ids[] = {
310 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
311 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
312 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
313 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
316 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
318 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
320 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
324 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
326 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
327 SND_SOC_DAIFMT_CBS_CFS;
330 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
332 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
333 SND_SOC_DAIFMT_CBM_CFS;
336 * fsl_ssi_isr: SSI interrupt handler
338 * Although it's possible to use the interrupt handler to send and receive
339 * data to/from the SSI, we use the DMA instead. Programming is more
340 * complicated, but the performance is much better.
342 * This interrupt handler is used only to gather statistics.
344 * @irq: IRQ of the SSI device
345 * @dev_id: pointer to the ssi_private structure for this SSI device
347 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
349 struct fsl_ssi_private *ssi_private = dev_id;
350 struct regmap *regs = ssi_private->regs;
354 /* We got an interrupt, so read the status register to see what we
355 were interrupted for. We mask it with the Interrupt Enable register
356 so that we only check for events that we're interested in.
358 regmap_read(regs, CCSR_SSI_SISR, &sisr);
360 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
361 /* Clear the bits that we set */
363 regmap_write(regs, CCSR_SSI_SISR, sisr2);
365 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
371 * Enable/Disable all rx/tx config flags at once.
373 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
376 struct regmap *regs = ssi_private->regs;
377 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
380 regmap_update_bits(regs, CCSR_SSI_SIER,
381 vals->rx.sier | vals->tx.sier,
382 vals->rx.sier | vals->tx.sier);
383 regmap_update_bits(regs, CCSR_SSI_SRCR,
384 vals->rx.srcr | vals->tx.srcr,
385 vals->rx.srcr | vals->tx.srcr);
386 regmap_update_bits(regs, CCSR_SSI_STCR,
387 vals->rx.stcr | vals->tx.stcr,
388 vals->rx.stcr | vals->tx.stcr);
390 regmap_update_bits(regs, CCSR_SSI_SRCR,
391 vals->rx.srcr | vals->tx.srcr, 0);
392 regmap_update_bits(regs, CCSR_SSI_STCR,
393 vals->rx.stcr | vals->tx.stcr, 0);
394 regmap_update_bits(regs, CCSR_SSI_SIER,
395 vals->rx.sier | vals->tx.sier, 0);
400 * Calculate the bits that have to be disabled for the current stream that is
401 * getting disabled. This keeps the bits enabled that are necessary for the
402 * second stream to work if 'stream_active' is true.
404 * Detailed calculation:
405 * These are the values that need to be active after disabling. For non-active
406 * second stream, this is 0:
407 * vals_stream * !!stream_active
409 * The following computes the overall differences between the setup for the
410 * to-disable stream and the active stream, a simple XOR:
411 * vals_disable ^ (vals_stream * !!(stream_active))
413 * The full expression adds a mask on all values we care about
415 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
417 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
420 * Enable/Disable a ssi configuration. You have to pass either
421 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
423 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
424 struct fsl_ssi_reg_val *vals)
426 struct regmap *regs = ssi_private->regs;
427 struct fsl_ssi_reg_val *avals;
428 int nr_active_streams;
432 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
434 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
435 !!(scr_val & CCSR_SSI_SCR_RE);
437 if (nr_active_streams - 1 > 0)
442 /* Find the other direction values rx or tx which we do not want to
444 if (&ssi_private->rxtx_reg_val.rx == vals)
445 avals = &ssi_private->rxtx_reg_val.tx;
447 avals = &ssi_private->rxtx_reg_val.rx;
449 /* If vals should be disabled, start with disabling the unit */
451 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
453 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
457 * We are running on a SoC which does not support online SSI
458 * reconfiguration, so we have to enable all necessary flags at once
459 * even if we do not use them later (capture and playback configuration)
461 if (ssi_private->soc->offline_config) {
462 if ((enable && !nr_active_streams) ||
463 (!enable && !keep_active))
464 fsl_ssi_rxtx_config(ssi_private, enable);
470 * Configure single direction units while the SSI unit is running
471 * (online configuration)
474 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
475 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
476 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
483 * Disabling the necessary flags for one of rx/tx while the
484 * other stream is active is a little bit more difficult. We
485 * have to disable only those flags that differ between both
486 * streams (rx XOR tx) and that are set in the stream that is
487 * disabled now. Otherwise we could alter flags of the other
491 /* These assignments are simply vals without bits set in avals*/
492 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
494 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
496 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
499 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
500 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
501 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
505 /* Enabling of subunits is done after configuration */
507 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
511 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
513 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
516 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
518 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
522 * Setup rx/tx register values used to enable/disable the streams. These will
523 * be used later in fsl_ssi_config to setup the streams without the need to
524 * check for all different SSI modes.
526 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
528 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
530 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
531 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
533 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
534 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
537 if (!fsl_ssi_is_ac97(ssi_private)) {
538 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
539 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
540 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
541 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
544 if (ssi_private->use_dma) {
545 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
546 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
548 reg->rx.sier |= CCSR_SSI_SIER_RIE;
549 reg->tx.sier |= CCSR_SSI_SIER_TIE;
552 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
553 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
556 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
558 struct regmap *regs = ssi_private->regs;
561 * Setup the clock control register
563 regmap_write(regs, CCSR_SSI_STCCR,
564 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
565 regmap_write(regs, CCSR_SSI_SRCCR,
566 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
569 * Enable AC97 mode and startup the SSI
571 regmap_write(regs, CCSR_SSI_SACNT,
572 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
573 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
574 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
577 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
578 * codec before a stream is started.
580 regmap_update_bits(regs, CCSR_SSI_SCR,
581 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
582 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
584 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
588 * fsl_ssi_startup: create a new substream
590 * This is the first function called when a stream is opened.
592 * If this is the first stream open, then grab the IRQ and program most of
595 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
596 struct snd_soc_dai *dai)
598 struct snd_soc_pcm_runtime *rtd = substream->private_data;
599 struct fsl_ssi_private *ssi_private =
600 snd_soc_dai_get_drvdata(rtd->cpu_dai);
603 ret = clk_prepare_enable(ssi_private->clk);
607 /* When using dual fifo mode, it is safer to ensure an even period
608 * size. If appearing to an odd number while DMA always starts its
609 * task from fifo0, fifo1 would be neglected at the end of each
610 * period. But SSI would still access fifo1 with an invalid data.
612 if (ssi_private->use_dual_fifo)
613 snd_pcm_hw_constraint_step(substream->runtime, 0,
614 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
620 * fsl_ssi_shutdown: shutdown the SSI
623 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
624 struct snd_soc_dai *dai)
626 struct snd_soc_pcm_runtime *rtd = substream->private_data;
627 struct fsl_ssi_private *ssi_private =
628 snd_soc_dai_get_drvdata(rtd->cpu_dai);
630 clk_disable_unprepare(ssi_private->clk);
635 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
637 * Note: This function can be only called when using SSI as DAI master
639 * Quick instruction for parameters:
640 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
641 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
643 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
644 struct snd_soc_dai *cpu_dai,
645 struct snd_pcm_hw_params *hw_params)
647 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
648 struct regmap *regs = ssi_private->regs;
649 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
650 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
651 unsigned long clkrate, baudrate, tmprate;
652 u64 sub, savesub = 100000;
654 bool baudclk_is_used;
656 /* Prefer the explicitly set bitclock frequency */
657 if (ssi_private->bitclk_freq)
658 freq = ssi_private->bitclk_freq;
660 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
662 /* Don't apply it to any non-baudclk circumstance */
663 if (IS_ERR(ssi_private->baudclk))
666 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
668 /* It should be already enough to divide clock by setting pm alone */
672 factor = (div2 + 1) * (7 * psr + 1) * 2;
674 for (i = 0; i < 255; i++) {
675 tmprate = freq * factor * (i + 1);
678 clkrate = clk_get_rate(ssi_private->baudclk);
680 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
683 * Hardware limitation: The bclk rate must be
684 * never greater than 1/5 IPG clock rate
686 if (clkrate * 5 > clk_get_rate(ssi_private->clk))
690 afreq = clkrate / (i + 1);
694 else if (freq / afreq == 1)
696 else if (afreq / freq == 1)
701 /* Calculate the fraction */
705 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
716 /* No proper pm found if it is still remaining the initial value */
718 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
722 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
723 (psr ? CCSR_SSI_SxCCR_PSR : 0);
724 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
728 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
730 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
732 if (!baudclk_is_used) {
733 ret = clk_set_rate(ssi_private->baudclk, baudrate);
735 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
743 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
744 int clk_id, unsigned int freq, int dir)
746 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
748 ssi_private->bitclk_freq = freq;
754 * fsl_ssi_hw_params - program the sample size
756 * Most of the SSI registers have been programmed in the startup function,
757 * but the word length must be programmed here. Unfortunately, programming
758 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
759 * cause a problem with supporting simultaneous playback and capture. If
760 * the SSI is already playing a stream, then that stream may be temporarily
761 * stopped when you start capture.
763 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
766 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
767 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
769 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
770 struct regmap *regs = ssi_private->regs;
771 unsigned int channels = params_channels(hw_params);
772 unsigned int sample_size = params_width(hw_params);
773 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
778 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
779 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
782 * If we're in synchronous mode, and the SSI is already enabled,
783 * then STCCR is already set properly.
785 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
788 if (fsl_ssi_is_i2s_master(ssi_private)) {
789 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
793 /* Do not enable the clock if it is already enabled */
794 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
795 ret = clk_prepare_enable(ssi_private->baudclk);
799 ssi_private->baudclk_streams |= BIT(substream->stream);
803 if (!fsl_ssi_is_ac97(ssi_private)) {
806 * Switch to normal net mode in order to have a frame sync
807 * signal every 32 bits instead of 16 bits
809 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
810 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
813 i2smode = ssi_private->i2s_mode;
815 regmap_update_bits(regs, CCSR_SSI_SCR,
816 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
817 channels == 1 ? 0 : i2smode);
821 * FIXME: The documentation says that SxCCR[WL] should not be
822 * modified while the SSI is enabled. The only time this can
823 * happen is if we're trying to do simultaneous playback and
824 * capture in asynchronous mode. Unfortunately, I have been enable
825 * to get that to work at all on the P1022DS. Therefore, we don't
826 * bother to disable/enable the SSI when setting SxCCR[WL], because
827 * the SSI will stop anyway. Maybe one day, this will get fixed.
830 /* In synchronous mode, the SSI uses STCCR for capture */
831 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
832 ssi_private->cpu_dai_drv.symmetric_rates)
833 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
836 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
842 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
843 struct snd_soc_dai *cpu_dai)
845 struct snd_soc_pcm_runtime *rtd = substream->private_data;
846 struct fsl_ssi_private *ssi_private =
847 snd_soc_dai_get_drvdata(rtd->cpu_dai);
849 if (fsl_ssi_is_i2s_master(ssi_private) &&
850 ssi_private->baudclk_streams & BIT(substream->stream)) {
851 clk_disable_unprepare(ssi_private->baudclk);
852 ssi_private->baudclk_streams &= ~BIT(substream->stream);
858 static int _fsl_ssi_set_dai_fmt(struct device *dev,
859 struct fsl_ssi_private *ssi_private,
862 struct regmap *regs = ssi_private->regs;
863 u32 strcr = 0, stcr, srcr, scr, mask;
866 ssi_private->dai_fmt = fmt;
868 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
869 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
873 fsl_ssi_setup_reg_vals(ssi_private);
875 regmap_read(regs, CCSR_SSI_SCR, &scr);
876 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
877 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
879 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
880 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
882 regmap_read(regs, CCSR_SSI_STCR, &stcr);
883 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
887 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
888 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
889 case SND_SOC_DAIFMT_I2S:
890 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
891 case SND_SOC_DAIFMT_CBM_CFS:
892 case SND_SOC_DAIFMT_CBS_CFS:
893 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
894 regmap_update_bits(regs, CCSR_SSI_STCCR,
895 CCSR_SSI_SxCCR_DC_MASK,
896 CCSR_SSI_SxCCR_DC(2));
897 regmap_update_bits(regs, CCSR_SSI_SRCCR,
898 CCSR_SSI_SxCCR_DC_MASK,
899 CCSR_SSI_SxCCR_DC(2));
901 case SND_SOC_DAIFMT_CBM_CFM:
902 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
908 /* Data on rising edge of bclk, frame low, 1clk before data */
909 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
910 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
912 case SND_SOC_DAIFMT_LEFT_J:
913 /* Data on rising edge of bclk, frame high */
914 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
916 case SND_SOC_DAIFMT_DSP_A:
917 /* Data on rising edge of bclk, frame high, 1clk before data */
918 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
919 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
921 case SND_SOC_DAIFMT_DSP_B:
922 /* Data on rising edge of bclk, frame high */
923 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
924 CCSR_SSI_STCR_TXBIT0;
926 case SND_SOC_DAIFMT_AC97:
927 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
932 scr |= ssi_private->i2s_mode;
934 /* DAI clock inversion */
935 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
936 case SND_SOC_DAIFMT_NB_NF:
937 /* Nothing to do for both normal cases */
939 case SND_SOC_DAIFMT_IB_NF:
940 /* Invert bit clock */
941 strcr ^= CCSR_SSI_STCR_TSCKP;
943 case SND_SOC_DAIFMT_NB_IF:
944 /* Invert frame clock */
945 strcr ^= CCSR_SSI_STCR_TFSI;
947 case SND_SOC_DAIFMT_IB_IF:
948 /* Invert both clocks */
949 strcr ^= CCSR_SSI_STCR_TSCKP;
950 strcr ^= CCSR_SSI_STCR_TFSI;
956 /* DAI clock master masks */
957 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
958 case SND_SOC_DAIFMT_CBS_CFS:
959 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
960 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
962 case SND_SOC_DAIFMT_CBM_CFM:
963 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
965 case SND_SOC_DAIFMT_CBM_CFS:
966 strcr &= ~CCSR_SSI_STCR_TXDIR;
967 strcr |= CCSR_SSI_STCR_TFDIR;
968 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
971 if (!fsl_ssi_is_ac97(ssi_private))
978 if (ssi_private->cpu_dai_drv.symmetric_rates
979 || fsl_ssi_is_ac97(ssi_private)) {
980 /* Need to clear RXDIR when using SYNC or AC97 mode */
981 srcr &= ~CCSR_SSI_SRCR_RXDIR;
982 scr |= CCSR_SSI_SCR_SYN;
985 regmap_write(regs, CCSR_SSI_STCR, stcr);
986 regmap_write(regs, CCSR_SSI_SRCR, srcr);
987 regmap_write(regs, CCSR_SSI_SCR, scr);
990 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
991 * use FIFO 1. We program the transmit water to signal a DMA transfer
992 * if there are only two (or fewer) elements left in the FIFO. Two
993 * elements equals one frame (left channel, right channel). This value,
994 * however, depends on the depth of the transmit buffer.
996 * We set the watermark on the same level as the DMA burstsize. For
997 * fiq it is probably better to use the biggest possible watermark
1000 if (ssi_private->use_dma)
1001 wm = ssi_private->fifo_depth - 2;
1003 wm = ssi_private->fifo_depth;
1005 regmap_write(regs, CCSR_SSI_SFCSR,
1006 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1007 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1009 if (ssi_private->use_dual_fifo) {
1010 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1011 CCSR_SSI_SRCR_RFEN1);
1012 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1013 CCSR_SSI_STCR_TFEN1);
1014 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1015 CCSR_SSI_SCR_TCH_EN);
1018 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1019 fsl_ssi_setup_ac97(ssi_private);
1026 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1028 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1030 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1032 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1036 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1038 * Note: This function can be only called when using SSI as DAI master
1040 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1041 u32 rx_mask, int slots, int slot_width)
1043 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1044 struct regmap *regs = ssi_private->regs;
1047 /* The slot number should be >= 2 if using Network mode or I2S mode */
1048 regmap_read(regs, CCSR_SSI_SCR, &val);
1049 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1050 if (val && slots < 2) {
1051 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1055 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1056 CCSR_SSI_SxCCR_DC(slots));
1057 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1058 CCSR_SSI_SxCCR_DC(slots));
1060 /* The register SxMSKs needs SSI to provide essential clock due to
1061 * hardware design. So we here temporarily enable SSI to set them.
1063 regmap_read(regs, CCSR_SSI_SCR, &val);
1064 val &= CCSR_SSI_SCR_SSIEN;
1065 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1066 CCSR_SSI_SCR_SSIEN);
1068 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1069 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1071 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1077 * fsl_ssi_trigger: start and stop the DMA transfer.
1079 * This function is called by ALSA to start, stop, pause, and resume the DMA
1082 * The DMA channel is in external master start and pause mode, which
1083 * means the SSI completely controls the flow of data.
1085 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1086 struct snd_soc_dai *dai)
1088 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1089 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1090 struct regmap *regs = ssi_private->regs;
1093 case SNDRV_PCM_TRIGGER_START:
1094 case SNDRV_PCM_TRIGGER_RESUME:
1095 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1096 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1097 fsl_ssi_tx_config(ssi_private, true);
1099 fsl_ssi_rx_config(ssi_private, true);
1102 case SNDRV_PCM_TRIGGER_STOP:
1103 case SNDRV_PCM_TRIGGER_SUSPEND:
1104 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1105 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1106 fsl_ssi_tx_config(ssi_private, false);
1108 fsl_ssi_rx_config(ssi_private, false);
1115 if (fsl_ssi_is_ac97(ssi_private)) {
1116 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1117 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1119 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1125 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1127 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1129 if (ssi_private->soc->imx && ssi_private->use_dma) {
1130 dai->playback_dma_data = &ssi_private->dma_params_tx;
1131 dai->capture_dma_data = &ssi_private->dma_params_rx;
1137 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1138 .startup = fsl_ssi_startup,
1139 .shutdown = fsl_ssi_shutdown,
1140 .hw_params = fsl_ssi_hw_params,
1141 .hw_free = fsl_ssi_hw_free,
1142 .set_fmt = fsl_ssi_set_dai_fmt,
1143 .set_sysclk = fsl_ssi_set_dai_sysclk,
1144 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1145 .trigger = fsl_ssi_trigger,
1148 /* Template for the CPU dai driver structure */
1149 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1150 .probe = fsl_ssi_dai_probe,
1152 .stream_name = "CPU-Playback",
1155 .rates = FSLSSI_I2S_RATES,
1156 .formats = FSLSSI_I2S_FORMATS,
1159 .stream_name = "CPU-Capture",
1162 .rates = FSLSSI_I2S_RATES,
1163 .formats = FSLSSI_I2S_FORMATS,
1165 .ops = &fsl_ssi_dai_ops,
1168 static const struct snd_soc_component_driver fsl_ssi_component = {
1172 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1173 .bus_control = true,
1174 .probe = fsl_ssi_dai_probe,
1176 .stream_name = "AC97 Playback",
1179 .rates = SNDRV_PCM_RATE_8000_48000,
1180 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1183 .stream_name = "AC97 Capture",
1186 .rates = SNDRV_PCM_RATE_48000,
1187 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1189 .ops = &fsl_ssi_dai_ops,
1193 static struct fsl_ssi_private *fsl_ac97_data;
1195 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1198 struct regmap *regs = fsl_ac97_data->regs;
1206 ret = clk_prepare_enable(fsl_ac97_data->clk);
1208 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1214 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1217 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1219 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1223 clk_disable_unprepare(fsl_ac97_data->clk);
1226 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1229 struct regmap *regs = fsl_ac97_data->regs;
1231 unsigned short val = -1;
1236 ret = clk_prepare_enable(fsl_ac97_data->clk);
1238 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1243 lreg = (reg & 0x7f) << 12;
1244 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1245 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1250 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1251 val = (reg_val >> 4) & 0xffff;
1253 clk_disable_unprepare(fsl_ac97_data->clk);
1258 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1259 .read = fsl_ssi_ac97_read,
1260 .write = fsl_ssi_ac97_write,
1264 * Make every character in a string lower-case
1266 static void make_lowercase(char *s)
1272 if ((c >= 'A') && (c <= 'Z'))
1273 *p = c + ('a' - 'A');
1278 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1279 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1281 struct device_node *np = pdev->dev.of_node;
1285 if (ssi_private->has_ipg_clk_name)
1286 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1288 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1289 if (IS_ERR(ssi_private->clk)) {
1290 ret = PTR_ERR(ssi_private->clk);
1291 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1295 if (!ssi_private->has_ipg_clk_name) {
1296 ret = clk_prepare_enable(ssi_private->clk);
1298 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1303 /* For those SLAVE implementations, we ignore non-baudclk cases
1304 * and, instead, abandon MASTER mode that needs baud clock.
1306 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1307 if (IS_ERR(ssi_private->baudclk))
1308 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1309 PTR_ERR(ssi_private->baudclk));
1312 * We have burstsize be "fifo_depth - 2" to match the SSI
1313 * watermark setting in fsl_ssi_startup().
1315 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1316 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1317 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1318 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1320 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1321 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1322 ssi_private->use_dual_fifo = true;
1323 /* When using dual fifo mode, we need to keep watermark
1324 * as even numbers due to dma script limitation.
1326 ssi_private->dma_params_tx.maxburst &= ~0x1;
1327 ssi_private->dma_params_rx.maxburst &= ~0x1;
1330 if (!ssi_private->use_dma) {
1333 * Some boards use an incompatible codec. To get it
1334 * working, we are using imx-fiq-pcm-audio, that
1335 * can handle those codecs. DMA is not possible in this
1339 ssi_private->fiq_params.irq = ssi_private->irq;
1340 ssi_private->fiq_params.base = iomem;
1341 ssi_private->fiq_params.dma_params_rx =
1342 &ssi_private->dma_params_rx;
1343 ssi_private->fiq_params.dma_params_tx =
1344 &ssi_private->dma_params_tx;
1346 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1350 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1359 if (!ssi_private->has_ipg_clk_name)
1360 clk_disable_unprepare(ssi_private->clk);
1364 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1365 struct fsl_ssi_private *ssi_private)
1367 if (!ssi_private->use_dma)
1368 imx_pcm_fiq_exit(pdev);
1369 if (!ssi_private->has_ipg_clk_name)
1370 clk_disable_unprepare(ssi_private->clk);
1373 static int fsl_ssi_probe(struct platform_device *pdev)
1375 struct fsl_ssi_private *ssi_private;
1377 struct device_node *np = pdev->dev.of_node;
1378 const struct of_device_id *of_id;
1379 const char *p, *sprop;
1380 const uint32_t *iprop;
1381 struct resource *res;
1382 void __iomem *iomem;
1385 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1386 if (!of_id || !of_id->data)
1389 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1392 dev_err(&pdev->dev, "could not allocate DAI object\n");
1396 ssi_private->soc = of_id->data;
1398 sprop = of_get_property(np, "fsl,mode", NULL);
1400 if (!strcmp(sprop, "ac97-slave"))
1401 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1404 ssi_private->use_dma = !of_property_read_bool(np,
1405 "fsl,fiq-stream-filter");
1407 if (fsl_ssi_is_ac97(ssi_private)) {
1408 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1409 sizeof(fsl_ssi_ac97_dai));
1411 fsl_ac97_data = ssi_private;
1413 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1415 dev_err(&pdev->dev, "could not set AC'97 ops\n");
1419 /* Initialize this copy of the CPU DAI driver structure */
1420 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1421 sizeof(fsl_ssi_dai_template));
1423 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1426 iomem = devm_ioremap_resource(&pdev->dev, res);
1428 return PTR_ERR(iomem);
1429 ssi_private->ssi_phys = res->start;
1431 ret = of_property_match_string(np, "clock-names", "ipg");
1433 ssi_private->has_ipg_clk_name = false;
1434 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1435 &fsl_ssi_regconfig);
1437 ssi_private->has_ipg_clk_name = true;
1438 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1439 "ipg", iomem, &fsl_ssi_regconfig);
1441 if (IS_ERR(ssi_private->regs)) {
1442 dev_err(&pdev->dev, "Failed to init register map\n");
1443 return PTR_ERR(ssi_private->regs);
1446 ssi_private->irq = platform_get_irq(pdev, 0);
1447 if (ssi_private->irq < 0) {
1448 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1449 return ssi_private->irq;
1452 /* Are the RX and the TX clocks locked? */
1453 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1454 if (!fsl_ssi_is_ac97(ssi_private))
1455 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1457 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1458 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1461 /* Determine the FIFO depth. */
1462 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1464 ssi_private->fifo_depth = be32_to_cpup(iprop);
1466 /* Older 8610 DTs didn't have the fifo-depth property */
1467 ssi_private->fifo_depth = 8;
1469 dev_set_drvdata(&pdev->dev, ssi_private);
1471 if (ssi_private->soc->imx) {
1472 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1477 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1478 &ssi_private->cpu_dai_drv, 1);
1480 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1481 goto error_asoc_register;
1484 if (ssi_private->use_dma) {
1485 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1486 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1489 dev_err(&pdev->dev, "could not claim irq %u\n",
1491 goto error_asoc_register;
1495 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1497 goto error_asoc_register;
1500 * If codec-handle property is missing from SSI node, we assume
1501 * that the machine driver uses new binding which does not require
1502 * SSI driver to trigger machine driver's probe.
1504 if (!of_get_property(np, "codec-handle", NULL))
1507 /* Trigger the machine driver's probe function. The platform driver
1508 * name of the machine driver is taken from /compatible property of the
1509 * device tree. We also pass the address of the CPU DAI driver
1512 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1513 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1514 p = strrchr(sprop, ',');
1517 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1518 make_lowercase(name);
1521 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1522 if (IS_ERR(ssi_private->pdev)) {
1523 ret = PTR_ERR(ssi_private->pdev);
1524 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1525 goto error_sound_card;
1529 if (ssi_private->dai_fmt)
1530 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1531 ssi_private->dai_fmt);
1533 if (fsl_ssi_is_ac97(ssi_private)) {
1536 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1538 dev_err(&pdev->dev, "cannot get SSI index property\n");
1539 goto error_sound_card;
1543 platform_device_register_data(NULL,
1544 "ac97-codec", ssi_idx, NULL, 0);
1545 if (IS_ERR(ssi_private->pdev)) {
1546 ret = PTR_ERR(ssi_private->pdev);
1548 "failed to register AC97 codec platform: %d\n",
1550 goto error_sound_card;
1557 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1559 error_asoc_register:
1560 if (ssi_private->soc->imx)
1561 fsl_ssi_imx_clean(pdev, ssi_private);
1566 static int fsl_ssi_remove(struct platform_device *pdev)
1568 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1570 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1572 if (ssi_private->pdev)
1573 platform_device_unregister(ssi_private->pdev);
1575 if (ssi_private->soc->imx)
1576 fsl_ssi_imx_clean(pdev, ssi_private);
1578 if (fsl_ssi_is_ac97(ssi_private))
1579 snd_soc_set_ac97_ops(NULL);
1584 #ifdef CONFIG_PM_SLEEP
1585 static int fsl_ssi_suspend(struct device *dev)
1587 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1588 struct regmap *regs = ssi_private->regs;
1590 regmap_read(regs, CCSR_SSI_SFCSR,
1591 &ssi_private->regcache_sfcsr);
1592 regmap_read(regs, CCSR_SSI_SACNT,
1593 &ssi_private->regcache_sacnt);
1595 regcache_cache_only(regs, true);
1596 regcache_mark_dirty(regs);
1601 static int fsl_ssi_resume(struct device *dev)
1603 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1604 struct regmap *regs = ssi_private->regs;
1606 regcache_cache_only(regs, false);
1608 regmap_update_bits(regs, CCSR_SSI_SFCSR,
1609 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1610 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1611 ssi_private->regcache_sfcsr);
1612 regmap_write(regs, CCSR_SSI_SACNT,
1613 ssi_private->regcache_sacnt);
1615 return regcache_sync(regs);
1617 #endif /* CONFIG_PM_SLEEP */
1619 static const struct dev_pm_ops fsl_ssi_pm = {
1620 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1623 static struct platform_driver fsl_ssi_driver = {
1625 .name = "fsl-ssi-dai",
1626 .of_match_table = fsl_ssi_ids,
1629 .probe = fsl_ssi_probe,
1630 .remove = fsl_ssi_remove,
1633 module_platform_driver(fsl_ssi_driver);
1635 MODULE_ALIAS("platform:fsl-ssi-dai");
1636 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1637 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1638 MODULE_LICENSE("GPL v2");