1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_qos.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/time.h>
18 #include <sound/core.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
30 static const unsigned int fsl_sai_rates[] = {
31 8000, 11025, 12000, 16000, 22050,
32 24000, 32000, 44100, 48000, 64000,
33 88200, 96000, 176400, 192000
36 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
37 .count = ARRAY_SIZE(fsl_sai_rates),
38 .list = fsl_sai_rates,
42 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
44 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
45 * or Receiver's for both streams. This function is used to check if clocks of
46 * the stream's are synced by the opposite stream.
49 * @dir: stream direction
51 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
53 int adir = (dir == TX) ? RX : TX;
55 /* current dir in async mode while opposite dir in sync mode */
56 return !sai->synchronous[dir] && sai->synchronous[adir];
59 static irqreturn_t fsl_sai_isr(int irq, void *devid)
61 struct fsl_sai *sai = (struct fsl_sai *)devid;
62 unsigned int ofs = sai->soc_data->reg_offset;
63 struct device *dev = &sai->pdev->dev;
64 u32 flags, xcsr, mask;
68 * Both IRQ status bits and IRQ mask bits are in the xCSR but
69 * different shifts. And we here create a mask only for those
70 * IRQs that we activated.
72 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
75 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
83 if (flags & FSL_SAI_CSR_WSF)
84 dev_dbg(dev, "isr: Start of Tx word detected\n");
86 if (flags & FSL_SAI_CSR_SEF)
87 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
89 if (flags & FSL_SAI_CSR_FEF) {
90 dev_dbg(dev, "isr: Transmit underrun detected\n");
91 /* FIFO reset for safety */
92 xcsr |= FSL_SAI_CSR_FR;
95 if (flags & FSL_SAI_CSR_FWF)
96 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
98 if (flags & FSL_SAI_CSR_FRF)
99 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
101 flags &= FSL_SAI_CSR_xF_W_MASK;
102 xcsr &= ~FSL_SAI_CSR_xF_MASK;
105 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
109 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
117 if (flags & FSL_SAI_CSR_WSF)
118 dev_dbg(dev, "isr: Start of Rx word detected\n");
120 if (flags & FSL_SAI_CSR_SEF)
121 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
123 if (flags & FSL_SAI_CSR_FEF) {
124 dev_dbg(dev, "isr: Receive overflow detected\n");
125 /* FIFO reset for safety */
126 xcsr |= FSL_SAI_CSR_FR;
129 if (flags & FSL_SAI_CSR_FWF)
130 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
132 if (flags & FSL_SAI_CSR_FRF)
133 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
135 flags &= FSL_SAI_CSR_xF_W_MASK;
136 xcsr &= ~FSL_SAI_CSR_xF_MASK;
139 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
148 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
149 u32 rx_mask, int slots, int slot_width)
151 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
154 sai->slot_width = slot_width;
159 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
162 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
164 sai->bclk_ratio = ratio;
169 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
170 int clk_id, unsigned int freq, int fsl_dir)
172 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
173 unsigned int ofs = sai->soc_data->reg_offset;
174 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
178 case FSL_SAI_CLK_BUS:
179 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
181 case FSL_SAI_CLK_MAST1:
182 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
184 case FSL_SAI_CLK_MAST2:
185 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
187 case FSL_SAI_CLK_MAST3:
188 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
194 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
195 FSL_SAI_CR2_MSEL_MASK, val_cr2);
200 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
201 int clk_id, unsigned int freq, int dir)
205 if (dir == SND_SOC_CLOCK_IN)
208 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
209 FSL_FMT_TRANSMITTER);
211 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
215 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
218 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
223 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
224 unsigned int fmt, int fsl_dir)
226 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
227 unsigned int ofs = sai->soc_data->reg_offset;
228 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
229 u32 val_cr2 = 0, val_cr4 = 0;
231 if (!sai->is_lsb_first)
232 val_cr4 |= FSL_SAI_CR4_MF;
235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
236 case SND_SOC_DAIFMT_I2S:
238 * Frame low, 1clk before data, one word length for frame sync,
239 * frame sync starts one serial clock cycle earlier,
240 * that is, together with the last bit of the previous
243 val_cr2 |= FSL_SAI_CR2_BCP;
244 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
246 case SND_SOC_DAIFMT_LEFT_J:
248 * Frame high, one word length for frame sync,
249 * frame sync asserts with the first bit of the frame.
251 val_cr2 |= FSL_SAI_CR2_BCP;
253 case SND_SOC_DAIFMT_DSP_A:
255 * Frame high, 1clk before data, one bit for frame sync,
256 * frame sync starts one serial clock cycle earlier,
257 * that is, together with the last bit of the previous
260 val_cr2 |= FSL_SAI_CR2_BCP;
261 val_cr4 |= FSL_SAI_CR4_FSE;
262 sai->is_dsp_mode = true;
264 case SND_SOC_DAIFMT_DSP_B:
266 * Frame high, one bit for frame sync,
267 * frame sync asserts with the first bit of the frame.
269 val_cr2 |= FSL_SAI_CR2_BCP;
270 sai->is_dsp_mode = true;
272 case SND_SOC_DAIFMT_RIGHT_J:
278 /* DAI clock inversion */
279 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
280 case SND_SOC_DAIFMT_IB_IF:
281 /* Invert both clocks */
282 val_cr2 ^= FSL_SAI_CR2_BCP;
283 val_cr4 ^= FSL_SAI_CR4_FSP;
285 case SND_SOC_DAIFMT_IB_NF:
286 /* Invert bit clock */
287 val_cr2 ^= FSL_SAI_CR2_BCP;
289 case SND_SOC_DAIFMT_NB_IF:
290 /* Invert frame clock */
291 val_cr4 ^= FSL_SAI_CR4_FSP;
293 case SND_SOC_DAIFMT_NB_NF:
294 /* Nothing to do for both normal cases */
300 /* DAI clock master masks */
301 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
302 case SND_SOC_DAIFMT_CBS_CFS:
303 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
304 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
305 sai->is_slave_mode = false;
307 case SND_SOC_DAIFMT_CBM_CFM:
308 sai->is_slave_mode = true;
310 case SND_SOC_DAIFMT_CBS_CFM:
311 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
312 sai->is_slave_mode = false;
314 case SND_SOC_DAIFMT_CBM_CFS:
315 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
316 sai->is_slave_mode = true;
322 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
323 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
324 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
325 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
326 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
331 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
335 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
337 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
341 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
343 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
348 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
350 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
351 unsigned int ofs = sai->soc_data->reg_offset;
352 unsigned long clk_rate;
353 u32 savediv = 0, ratio, savesub = freq;
354 int adir = tx ? RX : TX;
355 int dir = tx ? TX : RX;
359 /* Don't apply to slave mode */
360 if (sai->is_slave_mode)
364 * There is no point in polling MCLK0 if it is identical to MCLK1.
365 * And given that MQS use case has to use MCLK1 though two clocks
366 * are the same, we simply skip MCLK0 and start to find from MCLK1.
368 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
370 for (; id < FSL_SAI_MCLK_MAX; id++) {
371 clk_rate = clk_get_rate(sai->mclk_clk[id]);
375 ratio = clk_rate / freq;
377 ret = clk_rate - ratio * freq;
380 * Drop the source that can not be
381 * divided into the required rate.
383 if (ret != 0 && clk_rate / ret < 1000)
387 "ratio %d for freq %dHz based on clock %ldHz\n",
388 ratio, freq, clk_rate);
390 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
397 sai->mclk_id[tx] = id;
406 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
407 tx ? 'T' : 'R', freq);
412 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
413 * set TCR2 register for playback.
414 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
416 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
418 * 4) For Tx and Rx are both Synchronous with another SAI, we just
421 if (fsl_sai_dir_is_synced(sai, adir)) {
422 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
423 FSL_SAI_CR2_MSEL_MASK,
424 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
425 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
426 FSL_SAI_CR2_DIV_MASK, savediv - 1);
427 } else if (!sai->synchronous[dir]) {
428 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
429 FSL_SAI_CR2_MSEL_MASK,
430 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
431 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
432 FSL_SAI_CR2_DIV_MASK, savediv - 1);
435 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
436 sai->mclk_id[tx], savediv, savesub);
441 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
442 struct snd_pcm_hw_params *params,
443 struct snd_soc_dai *cpu_dai)
445 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
446 unsigned int ofs = sai->soc_data->reg_offset;
447 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
448 unsigned int channels = params_channels(params);
449 u32 word_width = params_width(params);
450 u32 val_cr4 = 0, val_cr5 = 0;
451 u32 slots = (channels == 1) ? 2 : channels;
452 u32 slot_width = word_width;
453 int adir = tx ? RX : TX;
461 slot_width = sai->slot_width;
463 pins = DIV_ROUND_UP(channels, slots);
465 if (!sai->is_slave_mode) {
467 ret = fsl_sai_set_bclk(cpu_dai, tx,
469 params_rate(params));
471 ret = fsl_sai_set_bclk(cpu_dai, tx,
473 params_rate(params));
477 /* Do not enable the clock if it is already enabled */
478 if (!(sai->mclk_streams & BIT(substream->stream))) {
479 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
483 sai->mclk_streams |= BIT(substream->stream);
487 if (!sai->is_dsp_mode)
488 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
490 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
491 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
493 if (sai->is_lsb_first)
494 val_cr5 |= FSL_SAI_CR5_FBT(0);
496 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
498 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
500 /* Set to output mode to avoid tri-stated data pins */
502 val_cr4 |= FSL_SAI_CR4_CHMOD;
505 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
506 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
507 * RCR5(TCR5) for playback(capture), or there will be sync error.
510 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
511 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
512 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
513 FSL_SAI_CR4_CHMOD_MASK,
515 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
516 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
517 FSL_SAI_CR5_FBT_MASK, val_cr5);
520 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
521 FSL_SAI_CR3_TRCE_MASK,
522 FSL_SAI_CR3_TRCE((1 << pins) - 1));
523 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
524 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
525 FSL_SAI_CR4_CHMOD_MASK,
527 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
528 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
529 FSL_SAI_CR5_FBT_MASK, val_cr5);
530 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
531 ~0UL - ((1 << min(channels, slots)) - 1));
536 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
537 struct snd_soc_dai *cpu_dai)
539 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
540 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
541 unsigned int ofs = sai->soc_data->reg_offset;
543 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
544 FSL_SAI_CR3_TRCE_MASK, 0);
546 if (!sai->is_slave_mode &&
547 sai->mclk_streams & BIT(substream->stream)) {
548 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
549 sai->mclk_streams &= ~BIT(substream->stream);
555 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
557 unsigned int ofs = sai->soc_data->reg_offset;
559 u32 xcsr, count = 100;
561 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
562 FSL_SAI_CSR_TERE, 0);
564 /* TERE will remain set till the end of current frame */
567 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
568 } while (--count && xcsr & FSL_SAI_CSR_TERE);
570 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
571 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
574 * For sai master mode, after several open/close sai,
575 * there will be no frame clock, and can't recover
576 * anymore. Add software reset to fix this issue.
577 * This is a hardware bug, and will be fix in the
580 if (!sai->is_slave_mode) {
582 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
583 /* Clear SR bit to finish the reset */
584 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
588 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
589 struct snd_soc_dai *cpu_dai)
591 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
592 unsigned int ofs = sai->soc_data->reg_offset;
594 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
595 int adir = tx ? RX : TX;
596 int dir = tx ? TX : RX;
600 * Asynchronous mode: Clear SYNC for both Tx and Rx.
601 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
602 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
604 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
605 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
606 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
607 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
610 * It is recommended that the transmitter is the last enabled
611 * and the first disabled.
614 case SNDRV_PCM_TRIGGER_START:
615 case SNDRV_PCM_TRIGGER_RESUME:
616 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
617 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
618 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
620 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
621 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
623 * Enable the opposite direction for synchronous mode
624 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
625 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
627 * RM recommends to enable RE after TE for case 1 and to enable
628 * TE after RE for case 2, but we here may not always guarantee
629 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
630 * TE after RE, which is against what RM recommends but should
631 * be safe to do, judging by years of testing results.
633 if (fsl_sai_dir_is_synced(sai, adir))
634 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
635 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
637 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
638 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
640 case SNDRV_PCM_TRIGGER_STOP:
641 case SNDRV_PCM_TRIGGER_SUSPEND:
642 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
643 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
644 FSL_SAI_CSR_FRDE, 0);
645 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
646 FSL_SAI_CSR_xIE_MASK, 0);
648 /* Check if the opposite FRDE is also disabled */
649 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
652 * If opposite stream provides clocks for synchronous mode and
653 * it is inactive, disable it before disabling the current one
655 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
656 fsl_sai_config_disable(sai, adir);
659 * Disable current stream if either of:
660 * 1. current stream doesn't provide clocks for synchronous mode
661 * 2. current stream provides clocks for synchronous mode but no
662 * more stream is active.
664 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
665 fsl_sai_config_disable(sai, dir);
675 static int fsl_sai_startup(struct snd_pcm_substream *substream,
676 struct snd_soc_dai *cpu_dai)
678 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
679 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
683 * EDMA controller needs period size to be a multiple of
686 if (sai->soc_data->use_edma)
687 snd_pcm_hw_constraint_step(substream->runtime, 0,
688 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
689 tx ? sai->dma_params_tx.maxburst :
690 sai->dma_params_rx.maxburst);
692 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
693 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
698 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
699 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
700 .set_sysclk = fsl_sai_set_dai_sysclk,
701 .set_fmt = fsl_sai_set_dai_fmt,
702 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
703 .hw_params = fsl_sai_hw_params,
704 .hw_free = fsl_sai_hw_free,
705 .trigger = fsl_sai_trigger,
706 .startup = fsl_sai_startup,
709 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
711 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
712 unsigned int ofs = sai->soc_data->reg_offset;
714 /* Software Reset for both Tx and Rx */
715 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
716 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
717 /* Clear SR bit to finish the reset */
718 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
719 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
721 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
722 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
723 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
724 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
725 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
726 FSL_SAI_MAXBURST_RX - 1);
728 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
729 &sai->dma_params_rx);
734 static struct snd_soc_dai_driver fsl_sai_dai_template = {
735 .probe = fsl_sai_dai_probe,
737 .stream_name = "CPU-Playback",
742 .rates = SNDRV_PCM_RATE_KNOT,
743 .formats = FSL_SAI_FORMATS,
746 .stream_name = "CPU-Capture",
751 .rates = SNDRV_PCM_RATE_KNOT,
752 .formats = FSL_SAI_FORMATS,
754 .ops = &fsl_sai_pcm_dai_ops,
757 static const struct snd_soc_component_driver fsl_component = {
761 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
762 {FSL_SAI_TCR1(0), 0},
763 {FSL_SAI_TCR2(0), 0},
764 {FSL_SAI_TCR3(0), 0},
765 {FSL_SAI_TCR4(0), 0},
766 {FSL_SAI_TCR5(0), 0},
776 {FSL_SAI_RCR1(0), 0},
777 {FSL_SAI_RCR2(0), 0},
778 {FSL_SAI_RCR3(0), 0},
779 {FSL_SAI_RCR4(0), 0},
780 {FSL_SAI_RCR5(0), 0},
784 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
785 {FSL_SAI_TCR1(8), 0},
786 {FSL_SAI_TCR2(8), 0},
787 {FSL_SAI_TCR3(8), 0},
788 {FSL_SAI_TCR4(8), 0},
789 {FSL_SAI_TCR5(8), 0},
799 {FSL_SAI_RCR1(8), 0},
800 {FSL_SAI_RCR2(8), 0},
801 {FSL_SAI_RCR3(8), 0},
802 {FSL_SAI_RCR4(8), 0},
803 {FSL_SAI_RCR5(8), 0},
809 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
811 struct fsl_sai *sai = dev_get_drvdata(dev);
812 unsigned int ofs = sai->soc_data->reg_offset;
814 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
817 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
865 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
867 struct fsl_sai *sai = dev_get_drvdata(dev);
868 unsigned int ofs = sai->soc_data->reg_offset;
870 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
873 /* Set VERID and PARAM be volatile for reading value in probe */
874 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
908 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
910 struct fsl_sai *sai = dev_get_drvdata(dev);
911 unsigned int ofs = sai->soc_data->reg_offset;
913 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
916 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
940 static struct regmap_config fsl_sai_regmap_config = {
946 .max_register = FSL_SAI_RMR,
947 .reg_defaults = fsl_sai_reg_defaults_ofs0,
948 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
949 .readable_reg = fsl_sai_readable_reg,
950 .volatile_reg = fsl_sai_volatile_reg,
951 .writeable_reg = fsl_sai_writeable_reg,
952 .cache_type = REGCACHE_FLAT,
955 static int fsl_sai_check_version(struct device *dev)
957 struct fsl_sai *sai = dev_get_drvdata(dev);
958 unsigned char ofs = sai->soc_data->reg_offset;
962 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
965 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
969 dev_dbg(dev, "VERID: 0x%016X\n", val);
971 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
972 FSL_SAI_VERID_MAJOR_SHIFT;
973 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
974 FSL_SAI_VERID_MINOR_SHIFT;
975 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
977 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
981 dev_dbg(dev, "PARAM: 0x%016X\n", val);
983 /* Max slots per frame, power of 2 */
984 sai->param.slot_num = 1 <<
985 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
987 /* Words per fifo, power of 2 */
988 sai->param.fifo_depth = 1 <<
989 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
991 /* Number of datalines implemented */
992 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
997 static int fsl_sai_runtime_suspend(struct device *dev);
998 static int fsl_sai_runtime_resume(struct device *dev);
1000 static int fsl_sai_probe(struct platform_device *pdev)
1002 struct device_node *np = pdev->dev.of_node;
1003 struct fsl_sai *sai;
1005 struct resource *res;
1011 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1016 sai->soc_data = of_device_get_match_data(&pdev->dev);
1018 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1020 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1022 return PTR_ERR(base);
1024 if (sai->soc_data->reg_offset == 8) {
1025 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1026 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1027 fsl_sai_regmap_config.num_reg_defaults =
1028 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1031 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, &fsl_sai_regmap_config);
1032 if (IS_ERR(sai->regmap)) {
1033 dev_err(&pdev->dev, "regmap init failed\n");
1034 return PTR_ERR(sai->regmap);
1037 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
1038 /* Compatible with old DTB cases */
1039 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1040 sai->bus_clk = devm_clk_get(&pdev->dev, "sai");
1041 if (IS_ERR(sai->bus_clk)) {
1042 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
1043 PTR_ERR(sai->bus_clk));
1045 return PTR_ERR(sai->bus_clk);
1048 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1049 sprintf(tmp, "mclk%d", i);
1050 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
1051 if (IS_ERR(sai->mclk_clk[i])) {
1052 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
1053 i + 1, PTR_ERR(sai->mclk_clk[i]));
1054 sai->mclk_clk[i] = NULL;
1058 if (sai->soc_data->mclk0_is_mclk1)
1059 sai->mclk_clk[0] = sai->mclk_clk[1];
1061 sai->mclk_clk[0] = sai->bus_clk;
1063 irq = platform_get_irq(pdev, 0);
1067 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED,
1070 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
1074 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
1075 sizeof(fsl_sai_dai_template));
1077 /* Sync Tx with Rx as default by following old DT binding */
1078 sai->synchronous[RX] = true;
1079 sai->synchronous[TX] = false;
1080 sai->cpu_dai_drv.symmetric_rate = 1;
1081 sai->cpu_dai_drv.symmetric_channels = 1;
1082 sai->cpu_dai_drv.symmetric_sample_bits = 1;
1084 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
1085 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
1086 /* error out if both synchronous and asynchronous are present */
1087 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
1091 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
1092 /* Sync Rx with Tx */
1093 sai->synchronous[RX] = false;
1094 sai->synchronous[TX] = true;
1095 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
1096 /* Discard all settings for asynchronous mode */
1097 sai->synchronous[RX] = false;
1098 sai->synchronous[TX] = false;
1099 sai->cpu_dai_drv.symmetric_rate = 0;
1100 sai->cpu_dai_drv.symmetric_channels = 0;
1101 sai->cpu_dai_drv.symmetric_sample_bits = 0;
1104 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
1105 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1106 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1108 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
1109 return PTR_ERR(gpr);
1112 index = of_alias_get_id(np, "sai");
1116 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1120 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
1121 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
1122 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
1123 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
1125 platform_set_drvdata(pdev, sai);
1126 pm_runtime_enable(&pdev->dev);
1127 if (!pm_runtime_enabled(&pdev->dev)) {
1128 ret = fsl_sai_runtime_resume(&pdev->dev);
1130 goto err_pm_disable;
1133 ret = pm_runtime_get_sync(&pdev->dev);
1135 pm_runtime_put_noidle(&pdev->dev);
1136 goto err_pm_get_sync;
1139 /* Get sai version */
1140 ret = fsl_sai_check_version(&pdev->dev);
1142 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
1144 /* Select MCLK direction */
1145 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
1146 sai->verid.major >= 3 && sai->verid.minor >= 1) {
1147 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1148 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1151 ret = pm_runtime_put_sync(&pdev->dev);
1153 goto err_pm_get_sync;
1156 * Register platform component before registering cpu dai for there
1157 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1159 if (sai->soc_data->use_imx_pcm) {
1160 ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
1162 goto err_pm_get_sync;
1164 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1166 goto err_pm_get_sync;
1169 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
1170 &sai->cpu_dai_drv, 1);
1172 goto err_pm_get_sync;
1177 if (!pm_runtime_status_suspended(&pdev->dev))
1178 fsl_sai_runtime_suspend(&pdev->dev);
1180 pm_runtime_disable(&pdev->dev);
1185 static int fsl_sai_remove(struct platform_device *pdev)
1187 pm_runtime_disable(&pdev->dev);
1188 if (!pm_runtime_status_suspended(&pdev->dev))
1189 fsl_sai_runtime_suspend(&pdev->dev);
1194 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1195 .use_imx_pcm = false,
1199 .mclk0_is_mclk1 = false,
1203 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1204 .use_imx_pcm = true,
1208 .mclk0_is_mclk1 = true,
1212 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1213 .use_imx_pcm = true,
1217 .mclk0_is_mclk1 = false,
1218 .flags = PMQOS_CPU_LATENCY,
1221 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1222 .use_imx_pcm = true,
1226 .mclk0_is_mclk1 = false,
1230 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1231 .use_imx_pcm = true,
1235 .mclk0_is_mclk1 = false,
1239 static const struct of_device_id fsl_sai_ids[] = {
1240 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1241 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1242 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1243 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1244 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1245 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1248 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1250 static int fsl_sai_runtime_suspend(struct device *dev)
1252 struct fsl_sai *sai = dev_get_drvdata(dev);
1254 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1255 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1257 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1258 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1260 clk_disable_unprepare(sai->bus_clk);
1262 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1263 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1265 regcache_cache_only(sai->regmap, true);
1270 static int fsl_sai_runtime_resume(struct device *dev)
1272 struct fsl_sai *sai = dev_get_drvdata(dev);
1273 unsigned int ofs = sai->soc_data->reg_offset;
1276 ret = clk_prepare_enable(sai->bus_clk);
1278 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1282 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1283 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1285 goto disable_bus_clk;
1288 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1289 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1291 goto disable_tx_clk;
1294 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1295 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1297 regcache_cache_only(sai->regmap, false);
1298 regcache_mark_dirty(sai->regmap);
1299 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1300 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1301 usleep_range(1000, 2000);
1302 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1303 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1305 ret = regcache_sync(sai->regmap);
1307 goto disable_rx_clk;
1312 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1313 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1315 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1316 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1318 clk_disable_unprepare(sai->bus_clk);
1323 static const struct dev_pm_ops fsl_sai_pm_ops = {
1324 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1325 fsl_sai_runtime_resume, NULL)
1326 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1327 pm_runtime_force_resume)
1330 static struct platform_driver fsl_sai_driver = {
1331 .probe = fsl_sai_probe,
1332 .remove = fsl_sai_remove,
1335 .pm = &fsl_sai_pm_ops,
1336 .of_match_table = fsl_sai_ids,
1339 module_platform_driver(fsl_sai_driver);
1341 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1342 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1343 MODULE_ALIAS("platform:fsl-sai");
1344 MODULE_LICENSE("GPL");