1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <linux/time.h>
16 #include <sound/core.h>
17 #include <sound/dmaengine_pcm.h>
18 #include <sound/pcm_params.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
25 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
28 static const unsigned int fsl_sai_rates[] = {
29 8000, 11025, 12000, 16000, 22050,
30 24000, 32000, 44100, 48000, 64000,
31 88200, 96000, 176400, 192000
34 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
35 .count = ARRAY_SIZE(fsl_sai_rates),
36 .list = fsl_sai_rates,
39 static irqreturn_t fsl_sai_isr(int irq, void *devid)
41 struct fsl_sai *sai = (struct fsl_sai *)devid;
42 struct device *dev = &sai->pdev->dev;
43 u32 flags, xcsr, mask;
47 * Both IRQ status bits and IRQ mask bits are in the xCSR but
48 * different shifts. And we here create a mask only for those
49 * IRQs that we activated.
51 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
54 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
62 if (flags & FSL_SAI_CSR_WSF)
63 dev_dbg(dev, "isr: Start of Tx word detected\n");
65 if (flags & FSL_SAI_CSR_SEF)
66 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
68 if (flags & FSL_SAI_CSR_FEF) {
69 dev_dbg(dev, "isr: Transmit underrun detected\n");
70 /* FIFO reset for safety */
71 xcsr |= FSL_SAI_CSR_FR;
74 if (flags & FSL_SAI_CSR_FWF)
75 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
77 if (flags & FSL_SAI_CSR_FRF)
78 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
80 flags &= FSL_SAI_CSR_xF_W_MASK;
81 xcsr &= ~FSL_SAI_CSR_xF_MASK;
84 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
88 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
96 if (flags & FSL_SAI_CSR_WSF)
97 dev_dbg(dev, "isr: Start of Rx word detected\n");
99 if (flags & FSL_SAI_CSR_SEF)
100 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
102 if (flags & FSL_SAI_CSR_FEF) {
103 dev_dbg(dev, "isr: Receive overflow detected\n");
104 /* FIFO reset for safety */
105 xcsr |= FSL_SAI_CSR_FR;
108 if (flags & FSL_SAI_CSR_FWF)
109 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
111 if (flags & FSL_SAI_CSR_FRF)
112 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
114 flags &= FSL_SAI_CSR_xF_W_MASK;
115 xcsr &= ~FSL_SAI_CSR_xF_MASK;
118 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
127 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
128 u32 rx_mask, int slots, int slot_width)
130 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
133 sai->slot_width = slot_width;
138 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
139 int clk_id, unsigned int freq, int fsl_dir)
141 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
142 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
146 case FSL_SAI_CLK_BUS:
147 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
149 case FSL_SAI_CLK_MAST1:
150 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
152 case FSL_SAI_CLK_MAST2:
153 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
155 case FSL_SAI_CLK_MAST3:
156 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
162 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
163 FSL_SAI_CR2_MSEL_MASK, val_cr2);
168 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
169 int clk_id, unsigned int freq, int dir)
173 if (dir == SND_SOC_CLOCK_IN)
176 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
177 FSL_FMT_TRANSMITTER);
179 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
183 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
186 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
191 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
192 unsigned int fmt, int fsl_dir)
194 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
195 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
196 u32 val_cr2 = 0, val_cr4 = 0;
198 if (!sai->is_lsb_first)
199 val_cr4 |= FSL_SAI_CR4_MF;
202 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
203 case SND_SOC_DAIFMT_I2S:
205 * Frame low, 1clk before data, one word length for frame sync,
206 * frame sync starts one serial clock cycle earlier,
207 * that is, together with the last bit of the previous
210 val_cr2 |= FSL_SAI_CR2_BCP;
211 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
213 case SND_SOC_DAIFMT_LEFT_J:
215 * Frame high, one word length for frame sync,
216 * frame sync asserts with the first bit of the frame.
218 val_cr2 |= FSL_SAI_CR2_BCP;
220 case SND_SOC_DAIFMT_DSP_A:
222 * Frame high, 1clk before data, one bit for frame sync,
223 * frame sync starts one serial clock cycle earlier,
224 * that is, together with the last bit of the previous
227 val_cr2 |= FSL_SAI_CR2_BCP;
228 val_cr4 |= FSL_SAI_CR4_FSE;
229 sai->is_dsp_mode = true;
231 case SND_SOC_DAIFMT_DSP_B:
233 * Frame high, one bit for frame sync,
234 * frame sync asserts with the first bit of the frame.
236 val_cr2 |= FSL_SAI_CR2_BCP;
237 sai->is_dsp_mode = true;
239 case SND_SOC_DAIFMT_RIGHT_J:
245 /* DAI clock inversion */
246 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
247 case SND_SOC_DAIFMT_IB_IF:
248 /* Invert both clocks */
249 val_cr2 ^= FSL_SAI_CR2_BCP;
250 val_cr4 ^= FSL_SAI_CR4_FSP;
252 case SND_SOC_DAIFMT_IB_NF:
253 /* Invert bit clock */
254 val_cr2 ^= FSL_SAI_CR2_BCP;
256 case SND_SOC_DAIFMT_NB_IF:
257 /* Invert frame clock */
258 val_cr4 ^= FSL_SAI_CR4_FSP;
260 case SND_SOC_DAIFMT_NB_NF:
261 /* Nothing to do for both normal cases */
267 /* DAI clock master masks */
268 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
269 case SND_SOC_DAIFMT_CBS_CFS:
270 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
271 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
272 sai->is_slave_mode = false;
274 case SND_SOC_DAIFMT_CBM_CFM:
275 sai->is_slave_mode = true;
277 case SND_SOC_DAIFMT_CBS_CFM:
278 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
279 sai->is_slave_mode = false;
281 case SND_SOC_DAIFMT_CBM_CFS:
282 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
283 sai->is_slave_mode = true;
289 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
290 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
291 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
292 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
293 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
298 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
302 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
304 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
308 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
310 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
315 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
317 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
318 unsigned long clk_rate;
319 u32 savediv = 0, ratio, savesub = freq;
323 /* Don't apply to slave mode */
324 if (sai->is_slave_mode)
327 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
328 clk_rate = clk_get_rate(sai->mclk_clk[id]);
332 ratio = clk_rate / freq;
334 ret = clk_rate - ratio * freq;
337 * Drop the source that can not be
338 * divided into the required rate.
340 if (ret != 0 && clk_rate / ret < 1000)
344 "ratio %d for freq %dHz based on clock %ldHz\n",
345 ratio, freq, clk_rate);
347 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
354 sai->mclk_id[tx] = id;
363 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
364 tx ? 'T' : 'R', freq);
369 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
370 * set TCR2 register for playback.
371 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
373 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
375 * 4) For Tx and Rx are both Synchronous with another SAI, we just
378 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
379 (!tx && !sai->synchronous[RX])) {
380 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
381 FSL_SAI_CR2_MSEL_MASK,
382 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
383 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
384 FSL_SAI_CR2_DIV_MASK, savediv - 1);
385 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
386 (tx && !sai->synchronous[TX])) {
387 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
388 FSL_SAI_CR2_MSEL_MASK,
389 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
390 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
391 FSL_SAI_CR2_DIV_MASK, savediv - 1);
394 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
395 sai->mclk_id[tx], savediv, savesub);
400 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
401 struct snd_pcm_hw_params *params,
402 struct snd_soc_dai *cpu_dai)
404 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
405 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
406 unsigned int channels = params_channels(params);
407 u32 word_width = params_width(params);
408 u32 val_cr4 = 0, val_cr5 = 0;
409 u32 slots = (channels == 1) ? 2 : channels;
410 u32 slot_width = word_width;
417 slot_width = sai->slot_width;
419 if (!sai->is_slave_mode) {
420 ret = fsl_sai_set_bclk(cpu_dai, tx,
421 slots * slot_width * params_rate(params));
425 /* Do not enable the clock if it is already enabled */
426 if (!(sai->mclk_streams & BIT(substream->stream))) {
427 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
431 sai->mclk_streams |= BIT(substream->stream);
435 if (!sai->is_dsp_mode)
436 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
438 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
439 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
441 if (sai->is_lsb_first)
442 val_cr5 |= FSL_SAI_CR5_FBT(0);
444 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
446 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
449 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
450 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
451 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
455 if (!sai->is_slave_mode) {
456 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
457 regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
458 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
460 regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
461 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
462 FSL_SAI_CR5_FBT_MASK, val_cr5);
463 regmap_write(sai->regmap, FSL_SAI_TMR,
464 ~0UL - ((1 << channels) - 1));
465 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
466 regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
467 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
469 regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
470 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
471 FSL_SAI_CR5_FBT_MASK, val_cr5);
472 regmap_write(sai->regmap, FSL_SAI_RMR,
473 ~0UL - ((1 << channels) - 1));
477 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
478 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
480 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
481 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
482 FSL_SAI_CR5_FBT_MASK, val_cr5);
483 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
488 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
489 struct snd_soc_dai *cpu_dai)
491 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
492 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
494 if (!sai->is_slave_mode &&
495 sai->mclk_streams & BIT(substream->stream)) {
496 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
497 sai->mclk_streams &= ~BIT(substream->stream);
504 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
505 struct snd_soc_dai *cpu_dai)
507 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
508 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
509 u32 xcsr, count = 100;
512 * Asynchronous mode: Clear SYNC for both Tx and Rx.
513 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
514 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
516 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
517 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
518 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
519 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
522 * It is recommended that the transmitter is the last enabled
523 * and the first disabled.
526 case SNDRV_PCM_TRIGGER_START:
527 case SNDRV_PCM_TRIGGER_RESUME:
528 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
529 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
530 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
532 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
533 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
534 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
535 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
537 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
538 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
540 case SNDRV_PCM_TRIGGER_STOP:
541 case SNDRV_PCM_TRIGGER_SUSPEND:
542 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
543 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
544 FSL_SAI_CSR_FRDE, 0);
545 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
546 FSL_SAI_CSR_xIE_MASK, 0);
548 /* Check if the opposite FRDE is also disabled */
549 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
550 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
551 /* Disable both directions and reset their FIFOs */
552 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
553 FSL_SAI_CSR_TERE, 0);
554 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
555 FSL_SAI_CSR_TERE, 0);
557 /* TERE will remain set till the end of current frame */
560 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
561 } while (--count && xcsr & FSL_SAI_CSR_TERE);
563 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
564 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
565 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
566 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
569 * For sai master mode, after several open/close sai,
570 * there will be no frame clock, and can't recover
571 * anymore. Add software reset to fix this issue.
572 * This is a hardware bug, and will be fix in the
575 if (!sai->is_slave_mode) {
576 /* Software Reset for both Tx and Rx */
577 regmap_write(sai->regmap,
578 FSL_SAI_TCSR, FSL_SAI_CSR_SR);
579 regmap_write(sai->regmap,
580 FSL_SAI_RCSR, FSL_SAI_CSR_SR);
581 /* Clear SR bit to finish the reset */
582 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
583 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
594 static int fsl_sai_startup(struct snd_pcm_substream *substream,
595 struct snd_soc_dai *cpu_dai)
597 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
598 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
599 struct device *dev = &sai->pdev->dev;
602 ret = clk_prepare_enable(sai->bus_clk);
604 dev_err(dev, "failed to enable bus clock: %d\n", ret);
608 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
611 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
612 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
617 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
618 struct snd_soc_dai *cpu_dai)
620 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
621 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
623 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
625 clk_disable_unprepare(sai->bus_clk);
628 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
629 .set_sysclk = fsl_sai_set_dai_sysclk,
630 .set_fmt = fsl_sai_set_dai_fmt,
631 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
632 .hw_params = fsl_sai_hw_params,
633 .hw_free = fsl_sai_hw_free,
634 .trigger = fsl_sai_trigger,
635 .startup = fsl_sai_startup,
636 .shutdown = fsl_sai_shutdown,
639 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
641 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
643 /* Software Reset for both Tx and Rx */
644 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
645 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
646 /* Clear SR bit to finish the reset */
647 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
648 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
650 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
651 FSL_SAI_MAXBURST_TX * 2);
652 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
653 FSL_SAI_MAXBURST_RX - 1);
655 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
656 &sai->dma_params_rx);
658 snd_soc_dai_set_drvdata(cpu_dai, sai);
663 static struct snd_soc_dai_driver fsl_sai_dai = {
664 .probe = fsl_sai_dai_probe,
666 .stream_name = "CPU-Playback",
671 .rates = SNDRV_PCM_RATE_KNOT,
672 .formats = FSL_SAI_FORMATS,
675 .stream_name = "CPU-Capture",
680 .rates = SNDRV_PCM_RATE_KNOT,
681 .formats = FSL_SAI_FORMATS,
683 .ops = &fsl_sai_pcm_dai_ops,
686 static const struct snd_soc_component_driver fsl_component = {
690 static struct reg_default fsl_sai_reg_defaults[] = {
706 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
732 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
746 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
770 static const struct regmap_config fsl_sai_regmap_config = {
775 .max_register = FSL_SAI_RMR,
776 .reg_defaults = fsl_sai_reg_defaults,
777 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
778 .readable_reg = fsl_sai_readable_reg,
779 .volatile_reg = fsl_sai_volatile_reg,
780 .writeable_reg = fsl_sai_writeable_reg,
781 .cache_type = REGCACHE_FLAT,
784 static int fsl_sai_probe(struct platform_device *pdev)
786 struct device_node *np = pdev->dev.of_node;
789 struct resource *res;
795 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
801 if (of_device_is_compatible(np, "fsl,imx6sx-sai") ||
802 of_device_is_compatible(np, "fsl,imx6ul-sai"))
803 sai->sai_on_imx = true;
805 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 base = devm_ioremap_resource(&pdev->dev, res);
810 return PTR_ERR(base);
812 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
813 "bus", base, &fsl_sai_regmap_config);
815 /* Compatible with old DTB cases */
816 if (IS_ERR(sai->regmap))
817 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
818 "sai", base, &fsl_sai_regmap_config);
819 if (IS_ERR(sai->regmap)) {
820 dev_err(&pdev->dev, "regmap init failed\n");
821 return PTR_ERR(sai->regmap);
824 /* No error out for old DTB cases but only mark the clock NULL */
825 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
826 if (IS_ERR(sai->bus_clk)) {
827 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
828 PTR_ERR(sai->bus_clk));
832 sai->mclk_clk[0] = sai->bus_clk;
833 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
834 sprintf(tmp, "mclk%d", i);
835 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
836 if (IS_ERR(sai->mclk_clk[i])) {
837 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
838 i + 1, PTR_ERR(sai->mclk_clk[i]));
839 sai->mclk_clk[i] = NULL;
843 irq = platform_get_irq(pdev, 0);
845 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
849 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
851 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
855 /* Sync Tx with Rx as default by following old DT binding */
856 sai->synchronous[RX] = true;
857 sai->synchronous[TX] = false;
858 fsl_sai_dai.symmetric_rates = 1;
859 fsl_sai_dai.symmetric_channels = 1;
860 fsl_sai_dai.symmetric_samplebits = 1;
862 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
863 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
864 /* error out if both synchronous and asynchronous are present */
865 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
869 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
870 /* Sync Rx with Tx */
871 sai->synchronous[RX] = false;
872 sai->synchronous[TX] = true;
873 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
874 /* Discard all settings for asynchronous mode */
875 sai->synchronous[RX] = false;
876 sai->synchronous[TX] = false;
877 fsl_sai_dai.symmetric_rates = 0;
878 fsl_sai_dai.symmetric_channels = 0;
879 fsl_sai_dai.symmetric_samplebits = 0;
882 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
883 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
884 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
886 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
890 index = of_alias_get_id(np, "sai");
894 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
898 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
899 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
900 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
901 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
903 platform_set_drvdata(pdev, sai);
905 pm_runtime_enable(&pdev->dev);
907 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
913 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
915 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
918 static int fsl_sai_remove(struct platform_device *pdev)
920 pm_runtime_disable(&pdev->dev);
925 static const struct of_device_id fsl_sai_ids[] = {
926 { .compatible = "fsl,vf610-sai", },
927 { .compatible = "fsl,imx6sx-sai", },
928 { .compatible = "fsl,imx6ul-sai", },
931 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
934 static int fsl_sai_runtime_suspend(struct device *dev)
936 struct fsl_sai *sai = dev_get_drvdata(dev);
938 regcache_cache_only(sai->regmap, true);
939 regcache_mark_dirty(sai->regmap);
944 static int fsl_sai_runtime_resume(struct device *dev)
946 struct fsl_sai *sai = dev_get_drvdata(dev);
948 regcache_cache_only(sai->regmap, false);
949 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
950 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
951 usleep_range(1000, 2000);
952 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
953 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
954 return regcache_sync(sai->regmap);
956 #endif /* CONFIG_PM */
958 static const struct dev_pm_ops fsl_sai_pm_ops = {
959 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
960 fsl_sai_runtime_resume, NULL)
961 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
962 pm_runtime_force_resume)
965 static struct platform_driver fsl_sai_driver = {
966 .probe = fsl_sai_probe,
967 .remove = fsl_sai_remove,
970 .pm = &fsl_sai_pm_ops,
971 .of_match_table = fsl_sai_ids,
974 module_platform_driver(fsl_sai_driver);
976 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
977 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
978 MODULE_ALIAS("platform:fsl-sai");
979 MODULE_LICENSE("GPL");