1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/pm_qos.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/time.h>
19 #include <sound/core.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "fsl_utils.h"
29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
32 static const unsigned int fsl_sai_rates[] = {
33 8000, 11025, 12000, 16000, 22050,
34 24000, 32000, 44100, 48000, 64000,
35 88200, 96000, 176400, 192000, 352800,
36 384000, 705600, 768000, 1411200, 2822400,
39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
40 .count = ARRAY_SIZE(fsl_sai_rates),
41 .list = fsl_sai_rates,
45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
48 * or Receiver's for both streams. This function is used to check if clocks of
49 * the stream's are synced by the opposite stream.
52 * @dir: stream direction
54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
56 int adir = (dir == TX) ? RX : TX;
58 /* current dir in async mode while opposite dir in sync mode */
59 return !sai->synchronous[dir] && sai->synchronous[adir];
62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
64 struct pinctrl_state *state = NULL;
66 if (sai->is_pdm_mode) {
67 /* DSD512@44.1kHz, DSD512@48kHz */
69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
71 /* Get default DSD state */
72 if (IS_ERR_OR_NULL(state))
73 state = pinctrl_lookup_state(sai->pinctrl, "dsd");
75 /* 706k32b2c, 768k32b2c, etc */
77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
80 /* Get default state */
81 if (IS_ERR_OR_NULL(state))
82 state = pinctrl_lookup_state(sai->pinctrl, "default");
87 static irqreturn_t fsl_sai_isr(int irq, void *devid)
89 struct fsl_sai *sai = (struct fsl_sai *)devid;
90 unsigned int ofs = sai->soc_data->reg_offset;
91 struct device *dev = &sai->pdev->dev;
92 u32 flags, xcsr, mask;
93 irqreturn_t iret = IRQ_NONE;
96 * Both IRQ status bits and IRQ mask bits are in the xCSR but
97 * different shifts. And we here create a mask only for those
98 * IRQs that we activated.
100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
111 if (flags & FSL_SAI_CSR_WSF)
112 dev_dbg(dev, "isr: Start of Tx word detected\n");
114 if (flags & FSL_SAI_CSR_SEF)
115 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
117 if (flags & FSL_SAI_CSR_FEF)
118 dev_dbg(dev, "isr: Transmit underrun detected\n");
120 if (flags & FSL_SAI_CSR_FWF)
121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
123 if (flags & FSL_SAI_CSR_FRF)
124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
126 flags &= FSL_SAI_CSR_xF_W_MASK;
127 xcsr &= ~FSL_SAI_CSR_xF_MASK;
130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
142 if (flags & FSL_SAI_CSR_WSF)
143 dev_dbg(dev, "isr: Start of Rx word detected\n");
145 if (flags & FSL_SAI_CSR_SEF)
146 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
148 if (flags & FSL_SAI_CSR_FEF)
149 dev_dbg(dev, "isr: Receive overflow detected\n");
151 if (flags & FSL_SAI_CSR_FWF)
152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
154 if (flags & FSL_SAI_CSR_FRF)
155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
157 flags &= FSL_SAI_CSR_xF_W_MASK;
158 xcsr &= ~FSL_SAI_CSR_xF_MASK;
161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
168 u32 rx_mask, int slots, int slot_width)
170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
173 sai->slot_width = slot_width;
178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
183 sai->bclk_ratio = ratio;
188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
189 int clk_id, unsigned int freq, bool tx)
191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
192 unsigned int ofs = sai->soc_data->reg_offset;
196 case FSL_SAI_CLK_BUS:
197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
199 case FSL_SAI_CLK_MAST1:
200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
202 case FSL_SAI_CLK_MAST2:
203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
205 case FSL_SAI_CLK_MAST3:
206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
213 FSL_SAI_CR2_MSEL_MASK, val_cr2);
218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
224 sai->pll8k_clk, sai->pll11k_clk, freq);
226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
234 int clk_id, unsigned int freq, int dir)
236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
239 if (dir == SND_SOC_CLOCK_IN)
242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) {
243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
253 if (sai->mclk_streams == 0) {
254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
274 unsigned int fmt, bool tx)
276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
277 unsigned int ofs = sai->soc_data->reg_offset;
278 u32 val_cr2 = 0, val_cr4 = 0;
280 if (!sai->is_lsb_first)
281 val_cr4 |= FSL_SAI_CR4_MF;
283 sai->is_pdm_mode = false;
284 sai->is_dsp_mode = false;
286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
287 case SND_SOC_DAIFMT_I2S:
289 * Frame low, 1clk before data, one word length for frame sync,
290 * frame sync starts one serial clock cycle earlier,
291 * that is, together with the last bit of the previous
294 val_cr2 |= FSL_SAI_CR2_BCP;
295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
297 case SND_SOC_DAIFMT_LEFT_J:
299 * Frame high, one word length for frame sync,
300 * frame sync asserts with the first bit of the frame.
302 val_cr2 |= FSL_SAI_CR2_BCP;
304 case SND_SOC_DAIFMT_DSP_A:
306 * Frame high, 1clk before data, one bit for frame sync,
307 * frame sync starts one serial clock cycle earlier,
308 * that is, together with the last bit of the previous
311 val_cr2 |= FSL_SAI_CR2_BCP;
312 val_cr4 |= FSL_SAI_CR4_FSE;
313 sai->is_dsp_mode = true;
315 case SND_SOC_DAIFMT_DSP_B:
317 * Frame high, one bit for frame sync,
318 * frame sync asserts with the first bit of the frame.
320 val_cr2 |= FSL_SAI_CR2_BCP;
321 sai->is_dsp_mode = true;
323 case SND_SOC_DAIFMT_PDM:
324 val_cr2 |= FSL_SAI_CR2_BCP;
325 val_cr4 &= ~FSL_SAI_CR4_MF;
326 sai->is_pdm_mode = true;
328 case SND_SOC_DAIFMT_RIGHT_J:
334 /* DAI clock inversion */
335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
336 case SND_SOC_DAIFMT_IB_IF:
337 /* Invert both clocks */
338 val_cr2 ^= FSL_SAI_CR2_BCP;
339 val_cr4 ^= FSL_SAI_CR4_FSP;
341 case SND_SOC_DAIFMT_IB_NF:
342 /* Invert bit clock */
343 val_cr2 ^= FSL_SAI_CR2_BCP;
345 case SND_SOC_DAIFMT_NB_IF:
346 /* Invert frame clock */
347 val_cr4 ^= FSL_SAI_CR4_FSP;
349 case SND_SOC_DAIFMT_NB_NF:
350 /* Nothing to do for both normal cases */
356 /* DAI clock provider masks */
357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
358 case SND_SOC_DAIFMT_BP_FP:
359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
361 sai->is_consumer_mode = false;
363 case SND_SOC_DAIFMT_BC_FC:
364 sai->is_consumer_mode = true;
366 case SND_SOC_DAIFMT_BP_FC:
367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
368 sai->is_consumer_mode = false;
370 case SND_SOC_DAIFMT_BC_FP:
371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
372 sai->is_consumer_mode = true;
378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
387 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
404 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
407 unsigned int reg, ofs = sai->soc_data->reg_offset;
408 unsigned long clk_rate;
409 u32 savediv = 0, ratio, bestdiff = freq;
410 int adir = tx ? RX : TX;
411 int dir = tx ? TX : RX;
413 bool support_1_1_ratio = sai->verid.version >= 0x0301;
415 /* Don't apply to consumer mode */
416 if (sai->is_consumer_mode)
420 * There is no point in polling MCLK0 if it is identical to MCLK1.
421 * And given that MQS use case has to use MCLK1 though two clocks
422 * are the same, we simply skip MCLK0 and start to find from MCLK1.
424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
426 for (; id < FSL_SAI_MCLK_MAX; id++) {
429 clk_rate = clk_get_rate(sai->mclk_clk[id]);
433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
434 if (!ratio || ratio > 512)
436 if (ratio == 1 && !support_1_1_ratio)
438 if ((ratio & 1) && ratio > 1)
441 diff = abs((long)clk_rate - ratio * freq);
444 * Drop the source that can not be
445 * divided into the required rate.
447 if (diff != 0 && clk_rate / diff < 1000)
451 "ratio %d for freq %dHz based on clock %ldHz\n",
452 ratio, freq, clk_rate);
455 if (diff < bestdiff) {
457 sai->mclk_id[tx] = id;
466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
467 tx ? 'T' : 'R', freq);
471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
472 sai->mclk_id[tx], savediv, bestdiff);
475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
476 * set TCR2 register for playback.
477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
481 * 4) For Tx and Rx are both Synchronous with another SAI, we just
484 if (fsl_sai_dir_is_synced(sai, adir))
485 reg = FSL_SAI_xCR2(!tx, ofs);
486 else if (!sai->synchronous[dir])
487 reg = FSL_SAI_xCR2(tx, ofs);
491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
495 regmap_update_bits(sai->regmap, reg,
496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
498 if (fsl_sai_dir_is_synced(sai, adir))
499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
500 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
505 regmap_update_bits(sai->regmap, reg,
506 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
513 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
514 struct snd_pcm_hw_params *params,
515 struct snd_soc_dai *cpu_dai)
517 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
518 unsigned int ofs = sai->soc_data->reg_offset;
519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
520 unsigned int channels = params_channels(params);
521 struct snd_dmaengine_dai_dma_data *dma_params;
522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
523 u32 word_width = params_width(params);
524 int trce_mask = 0, dl_cfg_idx = 0;
525 int dl_cfg_cnt = sai->dl_cfg_cnt;
526 u32 dl_type = FSL_SAI_DL_I2S;
527 u32 val_cr4 = 0, val_cr5 = 0;
528 u32 slots = (channels == 1) ? 2 : channels;
529 u32 slot_width = word_width;
530 int adir = tx ? RX : TX;
536 slot_width = sai->slot_width;
540 else if (sai->bclk_ratio)
541 slots = sai->bclk_ratio / slot_width;
543 pins = DIV_ROUND_UP(channels, slots);
546 * PDM mode, channels are independent
547 * each channels are on one dataline/FIFO.
549 if (sai->is_pdm_mode) {
551 dl_type = FSL_SAI_DL_PDM;
554 for (i = 0; i < dl_cfg_cnt; i++) {
555 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
561 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
562 dev_err(cpu_dai->dev, "channel not supported\n");
566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
568 if (!IS_ERR_OR_NULL(sai->pinctrl)) {
569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
570 if (!IS_ERR_OR_NULL(sai->pins_state)) {
571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
579 if (!sai->is_consumer_mode) {
580 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
584 /* Do not enable the clock if it is already enabled */
585 if (!(sai->mclk_streams & BIT(substream->stream))) {
586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
590 sai->mclk_streams |= BIT(substream->stream);
594 if (!sai->is_dsp_mode && !sai->is_pdm_mode)
595 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
597 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
598 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
600 if (sai->is_lsb_first || sai->is_pdm_mode)
601 val_cr5 |= FSL_SAI_CR5_FBT(0);
603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
605 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
607 /* Set to output mode to avoid tri-stated data pins */
609 val_cr4 |= FSL_SAI_CR4_CHMOD;
612 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
613 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
614 * RCR5(TCR5) for playback(capture), or there will be sync error.
617 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) {
618 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
619 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
620 FSL_SAI_CR4_CHMOD_MASK,
622 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
623 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
624 FSL_SAI_CR5_FBT_MASK, val_cr5);
628 * Combine mode has limation:
629 * - Can't used for singel dataline/FIFO case except the FIFO0
630 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
631 * are successive and start from FIFO0
633 * So for common usage, all multi fifo case disable the combine mode.
635 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
636 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
637 FSL_SAI_CR4_FCOMB_MASK, 0);
639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
640 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
642 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
643 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
644 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
646 if (sai->is_multi_fifo_dma) {
647 sai->audio_config[tx].words_per_fifo = min(slots, channels);
649 sai->audio_config[tx].n_fifos_dst = pins;
650 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
652 sai->audio_config[tx].n_fifos_src = pins;
653 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
655 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
656 dma_params->peripheral_config = &sai->audio_config[tx];
657 dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
659 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
660 (dma_params->maxburst - 1);
661 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
662 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
666 /* Find a proper tcre setting */
667 for (i = 0; i < sai->soc_data->pins; i++) {
668 trce_mask = (1 << (i + 1)) - 1;
669 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
673 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
674 FSL_SAI_CR3_TRCE_MASK,
675 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
677 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
678 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
679 FSL_SAI_CR4_CHMOD_MASK,
681 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
682 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
683 FSL_SAI_CR5_FBT_MASK, val_cr5);
684 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
685 ~0UL - ((1 << min(channels, slots)) - 1));
690 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
691 struct snd_soc_dai *cpu_dai)
693 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
694 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
695 unsigned int ofs = sai->soc_data->reg_offset;
697 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
698 FSL_SAI_CR3_TRCE_MASK, 0);
700 if (!sai->is_consumer_mode &&
701 sai->mclk_streams & BIT(substream->stream)) {
702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
703 sai->mclk_streams &= ~BIT(substream->stream);
709 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
711 unsigned int ofs = sai->soc_data->reg_offset;
713 u32 xcsr, count = 100, mask;
715 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
716 mask = FSL_SAI_CSR_TERE;
718 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
720 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
723 /* TERE will remain set till the end of current frame */
726 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
727 } while (--count && xcsr & FSL_SAI_CSR_TERE);
729 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
730 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
733 * For sai master mode, after several open/close sai,
734 * there will be no frame clock, and can't recover
735 * anymore. Add software reset to fix this issue.
736 * This is a hardware bug, and will be fix in the
739 if (!sai->is_consumer_mode) {
741 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
742 /* Clear SR bit to finish the reset */
743 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
747 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
748 struct snd_soc_dai *cpu_dai)
750 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
751 unsigned int ofs = sai->soc_data->reg_offset;
753 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
754 int adir = tx ? RX : TX;
755 int dir = tx ? TX : RX;
759 * Asynchronous mode: Clear SYNC for both Tx and Rx.
760 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
761 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
763 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
764 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
765 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
766 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
769 * It is recommended that the transmitter is the last enabled
770 * and the first disabled.
773 case SNDRV_PCM_TRIGGER_START:
774 case SNDRV_PCM_TRIGGER_RESUME:
775 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
776 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
777 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
779 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
780 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
782 * Enable the opposite direction for synchronous mode
783 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
784 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
786 * RM recommends to enable RE after TE for case 1 and to enable
787 * TE after RE for case 2, but we here may not always guarantee
788 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
789 * TE after RE, which is against what RM recommends but should
790 * be safe to do, judging by years of testing results.
792 if (fsl_sai_dir_is_synced(sai, adir))
793 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
794 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
796 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
797 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
799 case SNDRV_PCM_TRIGGER_STOP:
800 case SNDRV_PCM_TRIGGER_SUSPEND:
801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
802 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
803 FSL_SAI_CSR_FRDE, 0);
804 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
805 FSL_SAI_CSR_xIE_MASK, 0);
807 /* Check if the opposite FRDE is also disabled */
808 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
811 * If opposite stream provides clocks for synchronous mode and
812 * it is inactive, disable it before disabling the current one
814 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
815 fsl_sai_config_disable(sai, adir);
818 * Disable current stream if either of:
819 * 1. current stream doesn't provide clocks for synchronous mode
820 * 2. current stream provides clocks for synchronous mode but no
821 * more stream is active.
823 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
824 fsl_sai_config_disable(sai, dir);
834 static int fsl_sai_startup(struct snd_pcm_substream *substream,
835 struct snd_soc_dai *cpu_dai)
837 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
838 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
842 * EDMA controller needs period size to be a multiple of
845 if (sai->soc_data->use_edma)
846 snd_pcm_hw_constraint_step(substream->runtime, 0,
847 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
848 tx ? sai->dma_params_tx.maxburst :
849 sai->dma_params_rx.maxburst);
851 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
852 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
857 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
859 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
860 unsigned int ofs = sai->soc_data->reg_offset;
862 /* Software Reset for both Tx and Rx */
863 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
864 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
865 /* Clear SR bit to finish the reset */
866 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
867 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
869 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
870 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
871 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
872 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
873 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
874 sai->dma_params_rx.maxburst - 1);
876 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
877 &sai->dma_params_rx);
882 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
883 .probe = fsl_sai_dai_probe,
884 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
885 .set_sysclk = fsl_sai_set_dai_sysclk,
886 .set_fmt = fsl_sai_set_dai_fmt,
887 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
888 .hw_params = fsl_sai_hw_params,
889 .hw_free = fsl_sai_hw_free,
890 .trigger = fsl_sai_trigger,
891 .startup = fsl_sai_startup,
894 static int fsl_sai_dai_resume(struct snd_soc_component *component)
896 struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
897 struct device *dev = &sai->pdev->dev;
900 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
901 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
903 dev_err(dev, "failed to set proper pins state: %d\n", ret);
911 static struct snd_soc_dai_driver fsl_sai_dai_template = {
913 .stream_name = "CPU-Playback",
918 .rates = SNDRV_PCM_RATE_KNOT,
919 .formats = FSL_SAI_FORMATS,
922 .stream_name = "CPU-Capture",
927 .rates = SNDRV_PCM_RATE_KNOT,
928 .formats = FSL_SAI_FORMATS,
930 .ops = &fsl_sai_pcm_dai_ops,
933 static const struct snd_soc_component_driver fsl_component = {
935 .resume = fsl_sai_dai_resume,
936 .legacy_dai_naming = 1,
939 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
940 {FSL_SAI_TCR1(0), 0},
941 {FSL_SAI_TCR2(0), 0},
942 {FSL_SAI_TCR3(0), 0},
943 {FSL_SAI_TCR4(0), 0},
944 {FSL_SAI_TCR5(0), 0},
954 {FSL_SAI_RCR1(0), 0},
955 {FSL_SAI_RCR2(0), 0},
956 {FSL_SAI_RCR3(0), 0},
957 {FSL_SAI_RCR4(0), 0},
958 {FSL_SAI_RCR5(0), 0},
962 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
963 {FSL_SAI_TCR1(8), 0},
964 {FSL_SAI_TCR2(8), 0},
965 {FSL_SAI_TCR3(8), 0},
966 {FSL_SAI_TCR4(8), 0},
967 {FSL_SAI_TCR5(8), 0},
977 {FSL_SAI_RCR1(8), 0},
978 {FSL_SAI_RCR2(8), 0},
979 {FSL_SAI_RCR3(8), 0},
980 {FSL_SAI_RCR4(8), 0},
981 {FSL_SAI_RCR5(8), 0},
987 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
989 struct fsl_sai *sai = dev_get_drvdata(dev);
990 unsigned int ofs = sai->soc_data->reg_offset;
992 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
995 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1043 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
1045 struct fsl_sai *sai = dev_get_drvdata(dev);
1046 unsigned int ofs = sai->soc_data->reg_offset;
1048 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
1051 /* Set VERID and PARAM be volatile for reading value in probe */
1052 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
1086 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
1088 struct fsl_sai *sai = dev_get_drvdata(dev);
1089 unsigned int ofs = sai->soc_data->reg_offset;
1091 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1094 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1118 static struct regmap_config fsl_sai_regmap_config = {
1124 .max_register = FSL_SAI_RMR,
1125 .reg_defaults = fsl_sai_reg_defaults_ofs0,
1126 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
1127 .readable_reg = fsl_sai_readable_reg,
1128 .volatile_reg = fsl_sai_volatile_reg,
1129 .writeable_reg = fsl_sai_writeable_reg,
1130 .cache_type = REGCACHE_FLAT,
1133 static int fsl_sai_check_version(struct device *dev)
1135 struct fsl_sai *sai = dev_get_drvdata(dev);
1136 unsigned char ofs = sai->soc_data->reg_offset;
1140 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
1143 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1147 dev_dbg(dev, "VERID: 0x%016X\n", val);
1149 sai->verid.version = val &
1150 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
1151 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1152 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1154 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1158 dev_dbg(dev, "PARAM: 0x%016X\n", val);
1160 /* Max slots per frame, power of 2 */
1161 sai->param.slot_num = 1 <<
1162 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
1164 /* Words per fifo, power of 2 */
1165 sai->param.fifo_depth = 1 <<
1166 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
1168 /* Number of datalines implemented */
1169 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1175 * Calculate the offset between first two datalines, don't
1176 * different offset in one case.
1178 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
1180 int fbidx, nbidx, offset;
1182 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1183 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
1184 offset = nbidx - fbidx - 1;
1186 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1190 * read the fsl,dataline property from dts file.
1191 * It has 3 value for each configuration, first one means the type:
1192 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
1193 * dataline mask for 'tx'. for example
1195 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
1197 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1198 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1201 static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
1203 struct platform_device *pdev = sai->pdev;
1204 struct device_node *np = pdev->dev.of_node;
1205 struct device *dev = &pdev->dev;
1206 int ret, elems, i, index, num_cfg;
1207 char *propname = "fsl,dataline";
1208 struct fsl_sai_dl_cfg *cfg;
1209 unsigned long dl_mask;
1210 unsigned int soc_dl;
1213 elems = of_property_count_u32_elems(np, propname);
1217 } else if (elems % 3) {
1218 dev_err(dev, "Number of elements must be divisible to 3.\n");
1222 num_cfg = elems / 3;
1223 /* Add one more for default value */
1224 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
1228 /* Consider default value "0 0xFF 0xFF" if property is missing */
1229 soc_dl = BIT(sai->soc_data->pins) - 1;
1230 cfg[0].type = FSL_SAI_DL_DEFAULT;
1231 cfg[0].pins[0] = sai->soc_data->pins;
1232 cfg[0].mask[0] = soc_dl;
1233 cfg[0].start_off[0] = 0;
1234 cfg[0].next_off[0] = 0;
1236 cfg[0].pins[1] = sai->soc_data->pins;
1237 cfg[0].mask[1] = soc_dl;
1238 cfg[0].start_off[1] = 0;
1239 cfg[0].next_off[1] = 0;
1240 for (i = 1, index = 0; i < num_cfg + 1; i++) {
1243 * 0 means default mode
1247 ret = of_property_read_u32_index(np, propname, index++, &type);
1251 ret = of_property_read_u32_index(np, propname, index++, &rx);
1255 ret = of_property_read_u32_index(np, propname, index++, &tx);
1259 if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
1260 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
1268 cfg[i].pins[0] = hweight8(rx);
1269 cfg[i].mask[0] = rx;
1271 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1272 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
1274 cfg[i].pins[1] = hweight8(tx);
1275 cfg[i].mask[1] = tx;
1277 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1278 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
1282 sai->dl_cfg_cnt = num_cfg + 1;
1286 static int fsl_sai_runtime_suspend(struct device *dev);
1287 static int fsl_sai_runtime_resume(struct device *dev);
1289 static int fsl_sai_probe(struct platform_device *pdev)
1291 struct device_node *np = pdev->dev.of_node;
1292 struct device *dev = &pdev->dev;
1293 struct fsl_sai *sai;
1301 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
1306 sai->soc_data = of_device_get_match_data(dev);
1308 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1310 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1312 return PTR_ERR(base);
1314 if (sai->soc_data->reg_offset == 8) {
1315 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1316 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1317 fsl_sai_regmap_config.num_reg_defaults =
1318 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1321 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1322 if (IS_ERR(sai->regmap)) {
1323 dev_err(dev, "regmap init failed\n");
1324 return PTR_ERR(sai->regmap);
1327 sai->bus_clk = devm_clk_get(dev, "bus");
1328 /* Compatible with old DTB cases */
1329 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1330 sai->bus_clk = devm_clk_get(dev, "sai");
1331 if (IS_ERR(sai->bus_clk)) {
1332 dev_err(dev, "failed to get bus clock: %ld\n",
1333 PTR_ERR(sai->bus_clk));
1335 return PTR_ERR(sai->bus_clk);
1338 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1339 sprintf(tmp, "mclk%d", i);
1340 sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1341 if (IS_ERR(sai->mclk_clk[i])) {
1342 dev_err(dev, "failed to get mclk%d clock: %ld\n",
1343 i, PTR_ERR(sai->mclk_clk[i]));
1344 sai->mclk_clk[i] = NULL;
1348 if (sai->soc_data->mclk0_is_mclk1)
1349 sai->mclk_clk[0] = sai->mclk_clk[1];
1351 sai->mclk_clk[0] = sai->bus_clk;
1353 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1356 /* Use Multi FIFO mode depending on the support from SDMA script */
1357 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1358 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1359 sai->is_multi_fifo_dma = true;
1361 /* read dataline mask for rx and tx*/
1362 ret = fsl_sai_read_dlcfg(sai);
1364 dev_err(dev, "failed to read dlcfg %d\n", ret);
1368 irq = platform_get_irq(pdev, 0);
1372 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
1375 dev_err(dev, "failed to claim irq %u\n", irq);
1379 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
1380 sizeof(fsl_sai_dai_template));
1382 /* Sync Tx with Rx as default by following old DT binding */
1383 sai->synchronous[RX] = true;
1384 sai->synchronous[TX] = false;
1385 sai->cpu_dai_drv.symmetric_rate = 1;
1386 sai->cpu_dai_drv.symmetric_channels = 1;
1387 sai->cpu_dai_drv.symmetric_sample_bits = 1;
1389 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1390 of_property_read_bool(np, "fsl,sai-asynchronous")) {
1391 /* error out if both synchronous and asynchronous are present */
1392 dev_err(dev, "invalid binding for synchronous mode\n");
1396 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1397 /* Sync Rx with Tx */
1398 sai->synchronous[RX] = false;
1399 sai->synchronous[TX] = true;
1400 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1401 /* Discard all settings for asynchronous mode */
1402 sai->synchronous[RX] = false;
1403 sai->synchronous[TX] = false;
1404 sai->cpu_dai_drv.symmetric_rate = 0;
1405 sai->cpu_dai_drv.symmetric_channels = 0;
1406 sai->cpu_dai_drv.symmetric_sample_bits = 0;
1409 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1411 if (sai->mclk_direction_output &&
1412 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1413 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1415 dev_err(dev, "cannot find iomuxc registers\n");
1416 return PTR_ERR(gpr);
1419 index = of_alias_get_id(np, "sai");
1423 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1427 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1428 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1429 sai->dma_params_rx.maxburst =
1430 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1431 sai->dma_params_tx.maxburst =
1432 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1434 sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1436 platform_set_drvdata(pdev, sai);
1437 pm_runtime_enable(dev);
1438 if (!pm_runtime_enabled(dev)) {
1439 ret = fsl_sai_runtime_resume(dev);
1441 goto err_pm_disable;
1444 ret = pm_runtime_resume_and_get(dev);
1446 goto err_pm_get_sync;
1448 /* Get sai version */
1449 ret = fsl_sai_check_version(dev);
1451 dev_warn(dev, "Error reading SAI version: %d\n", ret);
1453 /* Select MCLK direction */
1454 if (sai->mclk_direction_output &&
1455 sai->soc_data->max_register >= FSL_SAI_MCTL) {
1456 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1457 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1460 ret = pm_runtime_put_sync(dev);
1461 if (ret < 0 && ret != -ENOSYS)
1462 goto err_pm_get_sync;
1465 * Register platform component before registering cpu dai for there
1466 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1468 if (sai->soc_data->use_imx_pcm) {
1469 ret = imx_pcm_dma_init(pdev);
1471 dev_err_probe(dev, ret, "PCM DMA init failed\n");
1472 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
1473 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1474 goto err_pm_get_sync;
1477 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1479 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
1480 goto err_pm_get_sync;
1484 ret = devm_snd_soc_register_component(dev, &fsl_component,
1485 &sai->cpu_dai_drv, 1);
1487 goto err_pm_get_sync;
1492 if (!pm_runtime_status_suspended(dev))
1493 fsl_sai_runtime_suspend(dev);
1495 pm_runtime_disable(dev);
1500 static void fsl_sai_remove(struct platform_device *pdev)
1502 pm_runtime_disable(&pdev->dev);
1503 if (!pm_runtime_status_suspended(&pdev->dev))
1504 fsl_sai_runtime_suspend(&pdev->dev);
1507 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1508 .use_imx_pcm = false,
1513 .mclk0_is_mclk1 = false,
1515 .max_register = FSL_SAI_RMR,
1518 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1519 .use_imx_pcm = true,
1524 .mclk0_is_mclk1 = true,
1526 .max_register = FSL_SAI_RMR,
1529 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1530 .use_imx_pcm = true,
1535 .mclk0_is_mclk1 = false,
1536 .flags = PMQOS_CPU_LATENCY,
1537 .max_register = FSL_SAI_RMR,
1540 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1541 .use_imx_pcm = true,
1546 .mclk0_is_mclk1 = false,
1548 .max_register = FSL_SAI_RMR,
1551 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1552 .use_imx_pcm = true,
1557 .mclk0_is_mclk1 = false,
1559 .max_register = FSL_SAI_RMR,
1562 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
1563 .use_imx_pcm = true,
1567 .mclk0_is_mclk1 = false,
1570 .max_register = FSL_SAI_MCTL,
1573 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
1574 .use_imx_pcm = true,
1578 .mclk0_is_mclk1 = false,
1581 .max_register = FSL_SAI_MDIV,
1584 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
1585 .use_imx_pcm = true,
1589 .mclk0_is_mclk1 = false,
1592 .max_register = FSL_SAI_MDIV,
1593 .mclk_with_tere = true,
1596 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
1597 .use_imx_pcm = true,
1601 .mclk0_is_mclk1 = false,
1603 .flags = PMQOS_CPU_LATENCY,
1604 .max_register = FSL_SAI_RTCAP,
1607 static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
1608 .use_imx_pcm = true,
1612 .mclk0_is_mclk1 = false,
1615 .max_register = FSL_SAI_MCTL,
1616 .max_burst = {8, 8},
1619 static const struct of_device_id fsl_sai_ids[] = {
1620 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1621 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1622 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1623 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1624 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1625 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1626 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1627 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1628 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1629 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1630 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1633 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1635 static int fsl_sai_runtime_suspend(struct device *dev)
1637 struct fsl_sai *sai = dev_get_drvdata(dev);
1639 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1640 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1642 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1643 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1645 clk_disable_unprepare(sai->bus_clk);
1647 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1648 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1650 regcache_cache_only(sai->regmap, true);
1655 static int fsl_sai_runtime_resume(struct device *dev)
1657 struct fsl_sai *sai = dev_get_drvdata(dev);
1658 unsigned int ofs = sai->soc_data->reg_offset;
1661 ret = clk_prepare_enable(sai->bus_clk);
1663 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1667 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1668 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1670 goto disable_bus_clk;
1673 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1674 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1676 goto disable_tx_clk;
1679 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1680 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1682 regcache_cache_only(sai->regmap, false);
1683 regcache_mark_dirty(sai->regmap);
1684 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1685 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1686 usleep_range(1000, 2000);
1687 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1688 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1690 ret = regcache_sync(sai->regmap);
1692 goto disable_rx_clk;
1694 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1695 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1696 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
1701 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1704 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1705 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1707 clk_disable_unprepare(sai->bus_clk);
1712 static const struct dev_pm_ops fsl_sai_pm_ops = {
1713 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1714 fsl_sai_runtime_resume, NULL)
1715 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1716 pm_runtime_force_resume)
1719 static struct platform_driver fsl_sai_driver = {
1720 .probe = fsl_sai_probe,
1721 .remove_new = fsl_sai_remove,
1724 .pm = &fsl_sai_pm_ops,
1725 .of_match_table = fsl_sai_ids,
1728 module_platform_driver(fsl_sai_driver);
1730 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1731 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1732 MODULE_ALIAS("platform:fsl-sai");
1733 MODULE_LICENSE("GPL");