1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/pm_qos.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/time.h>
19 #include <sound/core.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "fsl_utils.h"
29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
32 static const unsigned int fsl_sai_rates[] = {
33 8000, 11025, 12000, 16000, 22050,
34 24000, 32000, 44100, 48000, 64000,
35 88200, 96000, 176400, 192000, 352800,
36 384000, 705600, 768000, 1411200, 2822400,
39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
40 .count = ARRAY_SIZE(fsl_sai_rates),
41 .list = fsl_sai_rates,
45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
48 * or Receiver's for both streams. This function is used to check if clocks of
49 * the stream's are synced by the opposite stream.
52 * @dir: stream direction
54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
56 int adir = (dir == TX) ? RX : TX;
58 /* current dir in async mode while opposite dir in sync mode */
59 return !sai->synchronous[dir] && sai->synchronous[adir];
62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
64 struct pinctrl_state *state = NULL;
66 if (sai->is_pdm_mode) {
67 /* DSD512@44.1kHz, DSD512@48kHz */
69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
71 /* Get default DSD state */
72 if (IS_ERR_OR_NULL(state))
73 state = pinctrl_lookup_state(sai->pinctrl, "dsd");
75 /* 706k32b2c, 768k32b2c, etc */
77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
80 /* Get default state */
81 if (IS_ERR_OR_NULL(state))
82 state = pinctrl_lookup_state(sai->pinctrl, "default");
87 static irqreturn_t fsl_sai_isr(int irq, void *devid)
89 struct fsl_sai *sai = (struct fsl_sai *)devid;
90 unsigned int ofs = sai->soc_data->reg_offset;
91 struct device *dev = &sai->pdev->dev;
92 u32 flags, xcsr, mask;
93 irqreturn_t iret = IRQ_NONE;
96 * Both IRQ status bits and IRQ mask bits are in the xCSR but
97 * different shifts. And we here create a mask only for those
98 * IRQs that we activated.
100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
111 if (flags & FSL_SAI_CSR_WSF)
112 dev_dbg(dev, "isr: Start of Tx word detected\n");
114 if (flags & FSL_SAI_CSR_SEF)
115 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
117 if (flags & FSL_SAI_CSR_FEF)
118 dev_dbg(dev, "isr: Transmit underrun detected\n");
120 if (flags & FSL_SAI_CSR_FWF)
121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
123 if (flags & FSL_SAI_CSR_FRF)
124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
126 flags &= FSL_SAI_CSR_xF_W_MASK;
127 xcsr &= ~FSL_SAI_CSR_xF_MASK;
130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
142 if (flags & FSL_SAI_CSR_WSF)
143 dev_dbg(dev, "isr: Start of Rx word detected\n");
145 if (flags & FSL_SAI_CSR_SEF)
146 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
148 if (flags & FSL_SAI_CSR_FEF)
149 dev_dbg(dev, "isr: Receive overflow detected\n");
151 if (flags & FSL_SAI_CSR_FWF)
152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
154 if (flags & FSL_SAI_CSR_FRF)
155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
157 flags &= FSL_SAI_CSR_xF_W_MASK;
158 xcsr &= ~FSL_SAI_CSR_xF_MASK;
161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
168 u32 rx_mask, int slots, int slot_width)
170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
173 sai->slot_width = slot_width;
178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
183 sai->bclk_ratio = ratio;
188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
189 int clk_id, unsigned int freq, bool tx)
191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
192 unsigned int ofs = sai->soc_data->reg_offset;
196 case FSL_SAI_CLK_BUS:
197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
199 case FSL_SAI_CLK_MAST1:
200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
202 case FSL_SAI_CLK_MAST2:
203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
205 case FSL_SAI_CLK_MAST3:
206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
213 FSL_SAI_CR2_MSEL_MASK, val_cr2);
218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
224 sai->pll8k_clk, sai->pll11k_clk, freq);
226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
234 int clk_id, unsigned int freq, int dir)
236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
239 if (dir == SND_SOC_CLOCK_IN)
242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) {
243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
253 if (sai->mclk_streams == 0) {
254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
274 unsigned int fmt, bool tx)
276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
277 unsigned int ofs = sai->soc_data->reg_offset;
278 u32 val_cr2 = 0, val_cr4 = 0;
280 if (!sai->is_lsb_first)
281 val_cr4 |= FSL_SAI_CR4_MF;
283 sai->is_pdm_mode = false;
284 sai->is_dsp_mode = false;
286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
287 case SND_SOC_DAIFMT_I2S:
289 * Frame low, 1clk before data, one word length for frame sync,
290 * frame sync starts one serial clock cycle earlier,
291 * that is, together with the last bit of the previous
294 val_cr2 |= FSL_SAI_CR2_BCP;
295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
297 case SND_SOC_DAIFMT_LEFT_J:
299 * Frame high, one word length for frame sync,
300 * frame sync asserts with the first bit of the frame.
302 val_cr2 |= FSL_SAI_CR2_BCP;
304 case SND_SOC_DAIFMT_DSP_A:
306 * Frame high, 1clk before data, one bit for frame sync,
307 * frame sync starts one serial clock cycle earlier,
308 * that is, together with the last bit of the previous
311 val_cr2 |= FSL_SAI_CR2_BCP;
312 val_cr4 |= FSL_SAI_CR4_FSE;
313 sai->is_dsp_mode = true;
315 case SND_SOC_DAIFMT_DSP_B:
317 * Frame high, one bit for frame sync,
318 * frame sync asserts with the first bit of the frame.
320 val_cr2 |= FSL_SAI_CR2_BCP;
321 sai->is_dsp_mode = true;
323 case SND_SOC_DAIFMT_PDM:
324 val_cr2 |= FSL_SAI_CR2_BCP;
325 val_cr4 &= ~FSL_SAI_CR4_MF;
326 sai->is_pdm_mode = true;
328 case SND_SOC_DAIFMT_RIGHT_J:
334 /* DAI clock inversion */
335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
336 case SND_SOC_DAIFMT_IB_IF:
337 /* Invert both clocks */
338 val_cr2 ^= FSL_SAI_CR2_BCP;
339 val_cr4 ^= FSL_SAI_CR4_FSP;
341 case SND_SOC_DAIFMT_IB_NF:
342 /* Invert bit clock */
343 val_cr2 ^= FSL_SAI_CR2_BCP;
345 case SND_SOC_DAIFMT_NB_IF:
346 /* Invert frame clock */
347 val_cr4 ^= FSL_SAI_CR4_FSP;
349 case SND_SOC_DAIFMT_NB_NF:
350 /* Nothing to do for both normal cases */
356 /* DAI clock provider masks */
357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
358 case SND_SOC_DAIFMT_BP_FP:
359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
361 sai->is_consumer_mode = false;
363 case SND_SOC_DAIFMT_BC_FC:
364 sai->is_consumer_mode = true;
366 case SND_SOC_DAIFMT_BP_FC:
367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
368 sai->is_consumer_mode = false;
370 case SND_SOC_DAIFMT_BC_FP:
371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
372 sai->is_consumer_mode = true;
378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
387 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
404 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
407 unsigned int reg, ofs = sai->soc_data->reg_offset;
408 unsigned long clk_rate;
409 u32 savediv = 0, ratio, bestdiff = freq;
410 int adir = tx ? RX : TX;
411 int dir = tx ? TX : RX;
413 bool support_1_1_ratio = sai->verid.version >= 0x0301;
415 /* Don't apply to consumer mode */
416 if (sai->is_consumer_mode)
420 * There is no point in polling MCLK0 if it is identical to MCLK1.
421 * And given that MQS use case has to use MCLK1 though two clocks
422 * are the same, we simply skip MCLK0 and start to find from MCLK1.
424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
426 for (; id < FSL_SAI_MCLK_MAX; id++) {
429 clk_rate = clk_get_rate(sai->mclk_clk[id]);
433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
434 if (!ratio || ratio > 512)
436 if (ratio == 1 && !support_1_1_ratio)
438 if ((ratio & 1) && ratio > 1)
441 diff = abs((long)clk_rate - ratio * freq);
444 * Drop the source that can not be
445 * divided into the required rate.
447 if (diff != 0 && clk_rate / diff < 1000)
451 "ratio %d for freq %dHz based on clock %ldHz\n",
452 ratio, freq, clk_rate);
455 if (diff < bestdiff) {
457 sai->mclk_id[tx] = id;
466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
467 tx ? 'T' : 'R', freq);
471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
472 sai->mclk_id[tx], savediv, bestdiff);
475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
476 * set TCR2 register for playback.
477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
481 * 4) For Tx and Rx are both Synchronous with another SAI, we just
484 if (fsl_sai_dir_is_synced(sai, adir))
485 reg = FSL_SAI_xCR2(!tx, ofs);
486 else if (!sai->synchronous[dir])
487 reg = FSL_SAI_xCR2(tx, ofs);
491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
495 regmap_update_bits(sai->regmap, reg,
496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
498 if (fsl_sai_dir_is_synced(sai, adir))
499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
500 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
505 regmap_update_bits(sai->regmap, reg,
506 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
513 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
514 struct snd_pcm_hw_params *params,
515 struct snd_soc_dai *cpu_dai)
517 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
518 unsigned int ofs = sai->soc_data->reg_offset;
519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
520 unsigned int channels = params_channels(params);
521 struct snd_dmaengine_dai_dma_data *dma_params;
522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
523 u32 word_width = params_width(params);
524 int trce_mask = 0, dl_cfg_idx = 0;
525 int dl_cfg_cnt = sai->dl_cfg_cnt;
526 u32 dl_type = FSL_SAI_DL_I2S;
527 u32 val_cr4 = 0, val_cr5 = 0;
528 u32 slots = (channels == 1) ? 2 : channels;
529 u32 slot_width = word_width;
530 int adir = tx ? RX : TX;
536 slot_width = sai->slot_width;
540 else if (sai->bclk_ratio)
541 slots = sai->bclk_ratio / slot_width;
543 pins = DIV_ROUND_UP(channels, slots);
546 * PDM mode, channels are independent
547 * each channels are on one dataline/FIFO.
549 if (sai->is_pdm_mode) {
551 dl_type = FSL_SAI_DL_PDM;
554 for (i = 0; i < dl_cfg_cnt; i++) {
555 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
561 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
562 dev_err(cpu_dai->dev, "channel not supported\n");
566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
568 if (!IS_ERR_OR_NULL(sai->pinctrl)) {
569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
570 if (!IS_ERR_OR_NULL(sai->pins_state)) {
571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
579 if (!sai->is_consumer_mode) {
580 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
584 /* Do not enable the clock if it is already enabled */
585 if (!(sai->mclk_streams & BIT(substream->stream))) {
586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
590 sai->mclk_streams |= BIT(substream->stream);
594 if (!sai->is_dsp_mode && !sai->is_pdm_mode)
595 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
597 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
598 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
600 if (sai->is_lsb_first || sai->is_pdm_mode)
601 val_cr5 |= FSL_SAI_CR5_FBT(0);
603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
605 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
607 /* Set to output mode to avoid tri-stated data pins */
609 val_cr4 |= FSL_SAI_CR4_CHMOD;
612 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
613 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
614 * RCR5(TCR5) for playback(capture), or there will be sync error.
617 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) {
618 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
619 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
620 FSL_SAI_CR4_CHMOD_MASK,
622 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
623 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
624 FSL_SAI_CR5_FBT_MASK, val_cr5);
628 * Combine mode has limation:
629 * - Can't used for singel dataline/FIFO case except the FIFO0
630 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
631 * are successive and start from FIFO0
633 * So for common usage, all multi fifo case disable the combine mode.
635 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
636 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
637 FSL_SAI_CR4_FCOMB_MASK, 0);
639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
640 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
642 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
643 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
644 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
646 if (sai->is_multi_fifo_dma) {
647 sai->audio_config[tx].words_per_fifo = min(slots, channels);
649 sai->audio_config[tx].n_fifos_dst = pins;
650 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
652 sai->audio_config[tx].n_fifos_src = pins;
653 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
655 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
656 dma_params->peripheral_config = &sai->audio_config[tx];
657 dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
659 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
660 (dma_params->maxburst - 1);
661 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
662 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
666 /* Find a proper tcre setting */
667 for (i = 0; i < sai->soc_data->pins; i++) {
668 trce_mask = (1 << (i + 1)) - 1;
669 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
673 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
674 FSL_SAI_CR3_TRCE_MASK,
675 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
678 * When the TERE and FSD_MSTR enabled before configuring the word width
679 * There will be no frame sync clock issue, because word width impact
680 * the generation of frame sync clock.
682 * TERE enabled earlier only for i.MX8MP case for the hardware limitation,
683 * We need to disable FSD_MSTR before configuring word width, then enable
684 * FSD_MSTR bit for this specific case.
686 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
687 !sai->is_consumer_mode)
688 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
689 FSL_SAI_CR4_FSD_MSTR, 0);
691 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
692 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
693 FSL_SAI_CR4_CHMOD_MASK,
695 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
696 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
697 FSL_SAI_CR5_FBT_MASK, val_cr5);
699 /* Enable FSD_MSTR after configuring word width */
700 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
701 !sai->is_consumer_mode)
702 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
703 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR);
705 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
706 ~0UL - ((1 << min(channels, slots)) - 1));
711 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
712 struct snd_soc_dai *cpu_dai)
714 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
715 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
716 unsigned int ofs = sai->soc_data->reg_offset;
718 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
719 FSL_SAI_CR3_TRCE_MASK, 0);
721 if (!sai->is_consumer_mode &&
722 sai->mclk_streams & BIT(substream->stream)) {
723 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
724 sai->mclk_streams &= ~BIT(substream->stream);
730 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
732 unsigned int ofs = sai->soc_data->reg_offset;
734 u32 xcsr, count = 100, mask;
736 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
737 mask = FSL_SAI_CSR_TERE;
739 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
741 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
744 /* TERE will remain set till the end of current frame */
747 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
748 } while (--count && xcsr & FSL_SAI_CSR_TERE);
750 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
751 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
754 * For sai master mode, after several open/close sai,
755 * there will be no frame clock, and can't recover
756 * anymore. Add software reset to fix this issue.
757 * This is a hardware bug, and will be fix in the
760 if (!sai->is_consumer_mode) {
762 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
763 /* Clear SR bit to finish the reset */
764 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
768 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
769 struct snd_soc_dai *cpu_dai)
771 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
772 unsigned int ofs = sai->soc_data->reg_offset;
774 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
775 int adir = tx ? RX : TX;
776 int dir = tx ? TX : RX;
780 * Asynchronous mode: Clear SYNC for both Tx and Rx.
781 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
782 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
784 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
785 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
786 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
787 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
790 * It is recommended that the transmitter is the last enabled
791 * and the first disabled.
794 case SNDRV_PCM_TRIGGER_START:
795 case SNDRV_PCM_TRIGGER_RESUME:
796 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
797 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
798 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
800 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
801 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
803 * Enable the opposite direction for synchronous mode
804 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
805 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
807 * RM recommends to enable RE after TE for case 1 and to enable
808 * TE after RE for case 2, but we here may not always guarantee
809 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
810 * TE after RE, which is against what RM recommends but should
811 * be safe to do, judging by years of testing results.
813 if (fsl_sai_dir_is_synced(sai, adir))
814 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
815 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
817 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
818 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
820 case SNDRV_PCM_TRIGGER_STOP:
821 case SNDRV_PCM_TRIGGER_SUSPEND:
822 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
823 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
824 FSL_SAI_CSR_FRDE, 0);
825 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
826 FSL_SAI_CSR_xIE_MASK, 0);
828 /* Check if the opposite FRDE is also disabled */
829 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
832 * If opposite stream provides clocks for synchronous mode and
833 * it is inactive, disable it before disabling the current one
835 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
836 fsl_sai_config_disable(sai, adir);
839 * Disable current stream if either of:
840 * 1. current stream doesn't provide clocks for synchronous mode
841 * 2. current stream provides clocks for synchronous mode but no
842 * more stream is active.
844 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
845 fsl_sai_config_disable(sai, dir);
855 static int fsl_sai_startup(struct snd_pcm_substream *substream,
856 struct snd_soc_dai *cpu_dai)
858 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
859 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
863 * EDMA controller needs period size to be a multiple of
866 if (sai->soc_data->use_edma)
867 snd_pcm_hw_constraint_step(substream->runtime, 0,
868 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
869 tx ? sai->dma_params_tx.maxburst :
870 sai->dma_params_rx.maxburst);
872 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
873 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
878 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
880 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
881 unsigned int ofs = sai->soc_data->reg_offset;
883 /* Software Reset for both Tx and Rx */
884 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
885 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
886 /* Clear SR bit to finish the reset */
887 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
888 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
890 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
891 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
892 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
893 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
894 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
895 sai->dma_params_rx.maxburst - 1);
897 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
898 &sai->dma_params_rx);
903 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
904 .probe = fsl_sai_dai_probe,
905 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
906 .set_sysclk = fsl_sai_set_dai_sysclk,
907 .set_fmt = fsl_sai_set_dai_fmt,
908 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
909 .hw_params = fsl_sai_hw_params,
910 .hw_free = fsl_sai_hw_free,
911 .trigger = fsl_sai_trigger,
912 .startup = fsl_sai_startup,
915 static int fsl_sai_dai_resume(struct snd_soc_component *component)
917 struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
918 struct device *dev = &sai->pdev->dev;
921 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
922 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
924 dev_err(dev, "failed to set proper pins state: %d\n", ret);
932 static struct snd_soc_dai_driver fsl_sai_dai_template = {
934 .stream_name = "CPU-Playback",
939 .rates = SNDRV_PCM_RATE_KNOT,
940 .formats = FSL_SAI_FORMATS,
943 .stream_name = "CPU-Capture",
948 .rates = SNDRV_PCM_RATE_KNOT,
949 .formats = FSL_SAI_FORMATS,
951 .ops = &fsl_sai_pcm_dai_ops,
954 static const struct snd_soc_component_driver fsl_component = {
956 .resume = fsl_sai_dai_resume,
957 .legacy_dai_naming = 1,
960 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
961 {FSL_SAI_TCR1(0), 0},
962 {FSL_SAI_TCR2(0), 0},
963 {FSL_SAI_TCR3(0), 0},
964 {FSL_SAI_TCR4(0), 0},
965 {FSL_SAI_TCR5(0), 0},
975 {FSL_SAI_RCR1(0), 0},
976 {FSL_SAI_RCR2(0), 0},
977 {FSL_SAI_RCR3(0), 0},
978 {FSL_SAI_RCR4(0), 0},
979 {FSL_SAI_RCR5(0), 0},
983 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
984 {FSL_SAI_TCR1(8), 0},
985 {FSL_SAI_TCR2(8), 0},
986 {FSL_SAI_TCR3(8), 0},
987 {FSL_SAI_TCR4(8), 0},
988 {FSL_SAI_TCR5(8), 0},
998 {FSL_SAI_RCR1(8), 0},
999 {FSL_SAI_RCR2(8), 0},
1000 {FSL_SAI_RCR3(8), 0},
1001 {FSL_SAI_RCR4(8), 0},
1002 {FSL_SAI_RCR5(8), 0},
1008 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
1010 struct fsl_sai *sai = dev_get_drvdata(dev);
1011 unsigned int ofs = sai->soc_data->reg_offset;
1013 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1016 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1064 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
1066 struct fsl_sai *sai = dev_get_drvdata(dev);
1067 unsigned int ofs = sai->soc_data->reg_offset;
1069 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
1072 /* Set VERID and PARAM be volatile for reading value in probe */
1073 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
1107 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
1109 struct fsl_sai *sai = dev_get_drvdata(dev);
1110 unsigned int ofs = sai->soc_data->reg_offset;
1112 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1115 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1139 static struct regmap_config fsl_sai_regmap_config = {
1145 .max_register = FSL_SAI_RMR,
1146 .reg_defaults = fsl_sai_reg_defaults_ofs0,
1147 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
1148 .readable_reg = fsl_sai_readable_reg,
1149 .volatile_reg = fsl_sai_volatile_reg,
1150 .writeable_reg = fsl_sai_writeable_reg,
1151 .cache_type = REGCACHE_FLAT,
1154 static int fsl_sai_check_version(struct device *dev)
1156 struct fsl_sai *sai = dev_get_drvdata(dev);
1157 unsigned char ofs = sai->soc_data->reg_offset;
1161 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
1164 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1168 dev_dbg(dev, "VERID: 0x%016X\n", val);
1170 sai->verid.version = val &
1171 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
1172 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1173 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1175 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1179 dev_dbg(dev, "PARAM: 0x%016X\n", val);
1181 /* Max slots per frame, power of 2 */
1182 sai->param.slot_num = 1 <<
1183 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
1185 /* Words per fifo, power of 2 */
1186 sai->param.fifo_depth = 1 <<
1187 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
1189 /* Number of datalines implemented */
1190 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1196 * Calculate the offset between first two datalines, don't
1197 * different offset in one case.
1199 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
1201 int fbidx, nbidx, offset;
1203 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1204 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
1205 offset = nbidx - fbidx - 1;
1207 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1211 * read the fsl,dataline property from dts file.
1212 * It has 3 value for each configuration, first one means the type:
1213 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
1214 * dataline mask for 'tx'. for example
1216 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
1218 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1219 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1222 static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
1224 struct platform_device *pdev = sai->pdev;
1225 struct device_node *np = pdev->dev.of_node;
1226 struct device *dev = &pdev->dev;
1227 int ret, elems, i, index, num_cfg;
1228 char *propname = "fsl,dataline";
1229 struct fsl_sai_dl_cfg *cfg;
1230 unsigned long dl_mask;
1231 unsigned int soc_dl;
1234 elems = of_property_count_u32_elems(np, propname);
1238 } else if (elems % 3) {
1239 dev_err(dev, "Number of elements must be divisible to 3.\n");
1243 num_cfg = elems / 3;
1244 /* Add one more for default value */
1245 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
1249 /* Consider default value "0 0xFF 0xFF" if property is missing */
1250 soc_dl = BIT(sai->soc_data->pins) - 1;
1251 cfg[0].type = FSL_SAI_DL_DEFAULT;
1252 cfg[0].pins[0] = sai->soc_data->pins;
1253 cfg[0].mask[0] = soc_dl;
1254 cfg[0].start_off[0] = 0;
1255 cfg[0].next_off[0] = 0;
1257 cfg[0].pins[1] = sai->soc_data->pins;
1258 cfg[0].mask[1] = soc_dl;
1259 cfg[0].start_off[1] = 0;
1260 cfg[0].next_off[1] = 0;
1261 for (i = 1, index = 0; i < num_cfg + 1; i++) {
1264 * 0 means default mode
1268 ret = of_property_read_u32_index(np, propname, index++, &type);
1272 ret = of_property_read_u32_index(np, propname, index++, &rx);
1276 ret = of_property_read_u32_index(np, propname, index++, &tx);
1280 if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
1281 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
1289 cfg[i].pins[0] = hweight8(rx);
1290 cfg[i].mask[0] = rx;
1292 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1293 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
1295 cfg[i].pins[1] = hweight8(tx);
1296 cfg[i].mask[1] = tx;
1298 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1299 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
1303 sai->dl_cfg_cnt = num_cfg + 1;
1307 static int fsl_sai_runtime_suspend(struct device *dev);
1308 static int fsl_sai_runtime_resume(struct device *dev);
1310 static int fsl_sai_probe(struct platform_device *pdev)
1312 struct device_node *np = pdev->dev.of_node;
1313 struct device *dev = &pdev->dev;
1314 struct fsl_sai *sai;
1322 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
1327 sai->soc_data = of_device_get_match_data(dev);
1329 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1331 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1333 return PTR_ERR(base);
1335 if (sai->soc_data->reg_offset == 8) {
1336 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1337 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1338 fsl_sai_regmap_config.num_reg_defaults =
1339 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1342 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1343 if (IS_ERR(sai->regmap)) {
1344 dev_err(dev, "regmap init failed\n");
1345 return PTR_ERR(sai->regmap);
1348 sai->bus_clk = devm_clk_get(dev, "bus");
1349 /* Compatible with old DTB cases */
1350 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1351 sai->bus_clk = devm_clk_get(dev, "sai");
1352 if (IS_ERR(sai->bus_clk)) {
1353 dev_err(dev, "failed to get bus clock: %ld\n",
1354 PTR_ERR(sai->bus_clk));
1356 return PTR_ERR(sai->bus_clk);
1359 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1360 sprintf(tmp, "mclk%d", i);
1361 sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1362 if (IS_ERR(sai->mclk_clk[i])) {
1363 dev_err(dev, "failed to get mclk%d clock: %ld\n",
1364 i, PTR_ERR(sai->mclk_clk[i]));
1365 sai->mclk_clk[i] = NULL;
1369 if (sai->soc_data->mclk0_is_mclk1)
1370 sai->mclk_clk[0] = sai->mclk_clk[1];
1372 sai->mclk_clk[0] = sai->bus_clk;
1374 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1377 /* Use Multi FIFO mode depending on the support from SDMA script */
1378 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1379 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1380 sai->is_multi_fifo_dma = true;
1382 /* read dataline mask for rx and tx*/
1383 ret = fsl_sai_read_dlcfg(sai);
1385 dev_err(dev, "failed to read dlcfg %d\n", ret);
1389 irq = platform_get_irq(pdev, 0);
1393 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
1396 dev_err(dev, "failed to claim irq %u\n", irq);
1400 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
1401 sizeof(fsl_sai_dai_template));
1403 /* Sync Tx with Rx as default by following old DT binding */
1404 sai->synchronous[RX] = true;
1405 sai->synchronous[TX] = false;
1406 sai->cpu_dai_drv.symmetric_rate = 1;
1407 sai->cpu_dai_drv.symmetric_channels = 1;
1408 sai->cpu_dai_drv.symmetric_sample_bits = 1;
1410 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1411 of_property_read_bool(np, "fsl,sai-asynchronous")) {
1412 /* error out if both synchronous and asynchronous are present */
1413 dev_err(dev, "invalid binding for synchronous mode\n");
1417 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1418 /* Sync Rx with Tx */
1419 sai->synchronous[RX] = false;
1420 sai->synchronous[TX] = true;
1421 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1422 /* Discard all settings for asynchronous mode */
1423 sai->synchronous[RX] = false;
1424 sai->synchronous[TX] = false;
1425 sai->cpu_dai_drv.symmetric_rate = 0;
1426 sai->cpu_dai_drv.symmetric_channels = 0;
1427 sai->cpu_dai_drv.symmetric_sample_bits = 0;
1430 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1432 if (sai->mclk_direction_output &&
1433 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1434 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1436 dev_err(dev, "cannot find iomuxc registers\n");
1437 return PTR_ERR(gpr);
1440 index = of_alias_get_id(np, "sai");
1444 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1448 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1449 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1450 sai->dma_params_rx.maxburst =
1451 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1452 sai->dma_params_tx.maxburst =
1453 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1455 sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1457 platform_set_drvdata(pdev, sai);
1458 pm_runtime_enable(dev);
1459 if (!pm_runtime_enabled(dev)) {
1460 ret = fsl_sai_runtime_resume(dev);
1462 goto err_pm_disable;
1465 ret = pm_runtime_resume_and_get(dev);
1467 goto err_pm_get_sync;
1469 /* Get sai version */
1470 ret = fsl_sai_check_version(dev);
1472 dev_warn(dev, "Error reading SAI version: %d\n", ret);
1474 /* Select MCLK direction */
1475 if (sai->mclk_direction_output &&
1476 sai->soc_data->max_register >= FSL_SAI_MCTL) {
1477 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1478 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1481 ret = pm_runtime_put_sync(dev);
1482 if (ret < 0 && ret != -ENOSYS)
1483 goto err_pm_get_sync;
1486 * Register platform component before registering cpu dai for there
1487 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1489 if (sai->soc_data->use_imx_pcm) {
1490 ret = imx_pcm_dma_init(pdev);
1492 dev_err_probe(dev, ret, "PCM DMA init failed\n");
1493 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
1494 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1495 goto err_pm_get_sync;
1498 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1500 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
1501 goto err_pm_get_sync;
1505 ret = devm_snd_soc_register_component(dev, &fsl_component,
1506 &sai->cpu_dai_drv, 1);
1508 goto err_pm_get_sync;
1513 if (!pm_runtime_status_suspended(dev))
1514 fsl_sai_runtime_suspend(dev);
1516 pm_runtime_disable(dev);
1521 static void fsl_sai_remove(struct platform_device *pdev)
1523 pm_runtime_disable(&pdev->dev);
1524 if (!pm_runtime_status_suspended(&pdev->dev))
1525 fsl_sai_runtime_suspend(&pdev->dev);
1528 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1529 .use_imx_pcm = false,
1534 .mclk0_is_mclk1 = false,
1536 .max_register = FSL_SAI_RMR,
1539 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1540 .use_imx_pcm = true,
1545 .mclk0_is_mclk1 = true,
1547 .max_register = FSL_SAI_RMR,
1550 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1551 .use_imx_pcm = true,
1556 .mclk0_is_mclk1 = false,
1557 .flags = PMQOS_CPU_LATENCY,
1558 .max_register = FSL_SAI_RMR,
1561 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1562 .use_imx_pcm = true,
1567 .mclk0_is_mclk1 = false,
1569 .max_register = FSL_SAI_RMR,
1572 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1573 .use_imx_pcm = true,
1578 .mclk0_is_mclk1 = false,
1580 .max_register = FSL_SAI_RMR,
1583 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
1584 .use_imx_pcm = true,
1588 .mclk0_is_mclk1 = false,
1591 .max_register = FSL_SAI_MCTL,
1594 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
1595 .use_imx_pcm = true,
1599 .mclk0_is_mclk1 = false,
1602 .max_register = FSL_SAI_MDIV,
1605 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
1606 .use_imx_pcm = true,
1610 .mclk0_is_mclk1 = false,
1613 .max_register = FSL_SAI_MDIV,
1614 .mclk_with_tere = true,
1617 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
1618 .use_imx_pcm = true,
1622 .mclk0_is_mclk1 = false,
1624 .flags = PMQOS_CPU_LATENCY,
1625 .max_register = FSL_SAI_RTCAP,
1628 static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
1629 .use_imx_pcm = true,
1633 .mclk0_is_mclk1 = false,
1636 .max_register = FSL_SAI_MCTL,
1637 .max_burst = {8, 8},
1640 static const struct of_device_id fsl_sai_ids[] = {
1641 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1642 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1643 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1644 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1645 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1646 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1647 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1648 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1649 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1650 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1651 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1654 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1656 static int fsl_sai_runtime_suspend(struct device *dev)
1658 struct fsl_sai *sai = dev_get_drvdata(dev);
1660 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1661 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1663 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1664 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1666 clk_disable_unprepare(sai->bus_clk);
1668 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1669 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1671 regcache_cache_only(sai->regmap, true);
1676 static int fsl_sai_runtime_resume(struct device *dev)
1678 struct fsl_sai *sai = dev_get_drvdata(dev);
1679 unsigned int ofs = sai->soc_data->reg_offset;
1682 ret = clk_prepare_enable(sai->bus_clk);
1684 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1688 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1689 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1691 goto disable_bus_clk;
1694 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1695 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1697 goto disable_tx_clk;
1700 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1701 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1703 regcache_cache_only(sai->regmap, false);
1704 regcache_mark_dirty(sai->regmap);
1705 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1706 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1707 usleep_range(1000, 2000);
1708 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1709 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1711 ret = regcache_sync(sai->regmap);
1713 goto disable_rx_clk;
1715 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1716 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1717 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
1722 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1723 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1725 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1726 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1728 clk_disable_unprepare(sai->bus_clk);
1733 static const struct dev_pm_ops fsl_sai_pm_ops = {
1734 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1735 fsl_sai_runtime_resume, NULL)
1736 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1737 pm_runtime_force_resume)
1740 static struct platform_driver fsl_sai_driver = {
1741 .probe = fsl_sai_probe,
1742 .remove_new = fsl_sai_remove,
1745 .pm = &fsl_sai_pm_ops,
1746 .of_match_table = fsl_sai_ids,
1749 module_platform_driver(fsl_sai_driver);
1751 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1752 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1753 MODULE_ALIAS("platform:fsl-sai");
1754 MODULE_LICENSE("GPL");