sound/soc/dwc/dwc-i2s.c

   1 /*
   2  * ALSA SoC Synopsys I2S Audio Layer
   3  *
   4  * sound/soc/dwc/designware_i2s.c
   5  *
   6  * Copyright (C) 2010 ST Microelectronics
   7  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/pm_runtime.h>
  22 #include <sound/designware_i2s.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/dmaengine_pcm.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30 #include "local.h"
  31
  32 #define CLOCK_BASE      0x13020000UL
  33
  34 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
  35 {
  36         writel(val, io_base + reg);
  37 }
  38
  39 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
  40 {
  41         return readl(io_base + reg);
  42 }
  43
  44 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
  45 {
  46         u32 i = 0;
  47
  48         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  49                 for (i = 0; i < 4; i++)
  50                         i2s_write_reg(dev->i2s_base, TER(i), 0);
  51         } else {
  52                 for (i = 0; i < 4; i++)
  53                         i2s_write_reg(dev->i2s_base, RER(i), 0);
  54         }
  55 }
  56
  57 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
  58 {
  59         u32 i = 0;
  60
  61         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  62                 for (i = 0; i < 4; i++)
  63                         i2s_read_reg(dev->i2s_base, TOR(i));
  64         } else {
  65                 for (i = 0; i < 4; i++)
  66                         i2s_read_reg(dev->i2s_base, ROR(i));
  67         }
  68 }
  69
  70 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
  71                                     int chan_nr)
  72 {
  73         u32 i, irq;
  74
  75         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  76                 for (i = 0; i <= ((chan_nr + 1) / 2); i++) {
  77                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  78                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
  79                 }
  80         } else {
  81                 for (i = 0; i <= ((chan_nr + 1) / 2); i++) {
  82                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  83                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
  84                 }
  85         }
  86 }
  87
  88 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
  89                                    int chan_nr)
  90 {
  91         u32 i, irq;
  92
  93         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  94                 for (i = 0; i < ((chan_nr + 1) / 2); i++) {
  95                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  96                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
  97                 }
  98         } else {
  99                 for (i = 0; i < ((chan_nr + 1) / 2); i++) {
 100                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 101                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
 102                 }
 103         }
 104 }
 105
 106 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
 107 {
 108         struct dw_i2s_dev *dev = dev_id;
 109         bool irq_valid = false;
 110         u32 isr[4];
 111         int i;
 112
 113         for (i = 0; i < 4; i++)
 114                 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
 115
 116         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
 117         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
 118
 119         for (i = 0; i < 4; i++) {
 120                 /*
 121                  * Check if TX fifo is empty. If empty fill FIFO with samples
 122                  * NOTE: Only two channels supported
 123                  */
 124                 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
 125                         dw_pcm_push_tx(dev);
 126                         irq_valid = true;
 127                 }
 128
 129                 /*
 130                  * Data available. Retrieve samples from FIFO
 131                  * NOTE: Only two channels supported
 132                  */
 133                 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
 134                         dw_pcm_pop_rx(dev);
 135                         irq_valid = true;
 136                 }
 137
 138                 /* Error Handling: TX */
 139                 if (isr[i] & ISR_TXFO) {
 140                         dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
 141                         irq_valid = true;
 142                 }
 143
 144                 /* Error Handling: TX */
 145                 if (isr[i] & ISR_RXFO) {
 146                         dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
 147                         irq_valid = true;
 148                 }
 149         }
 150
 151         if (irq_valid)
 152                 return IRQ_HANDLED;
 153         else
 154                 return IRQ_NONE;
 155 }
 156
 157 static void i2s_start(struct dw_i2s_dev *dev,
 158                       struct snd_pcm_substream *substream)
 159 {
 160         struct i2s_clk_config_data *config = &dev->config;
 161
 162         i2s_write_reg(dev->i2s_base, IER, 1);
 163         i2s_enable_irqs(dev, substream->stream, config->chan_nr);
 164
 165         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 166                 i2s_write_reg(dev->i2s_base, ITER, 1);
 167         else
 168                 i2s_write_reg(dev->i2s_base, IRER, 1);
 169
 170         i2s_write_reg(dev->i2s_base, CER, 1);
 171 }
 172
 173 static void i2s_stop(struct dw_i2s_dev *dev,
 174                 struct snd_pcm_substream *substream)
 175 {
 176
 177         i2s_clear_irqs(dev, substream->stream);
 178         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 179                 i2s_write_reg(dev->i2s_base, ITER, 0);
 180         else
 181                 i2s_write_reg(dev->i2s_base, IRER, 0);
 182
 183         i2s_disable_irqs(dev, substream->stream, 8);
 184
 185         if (!dev->active) {
 186                 i2s_write_reg(dev->i2s_base, CER, 0);
 187                 i2s_write_reg(dev->i2s_base, IER, 0);
 188         }
 189 }
 190
 191 static int dw_i2s_startup(struct snd_pcm_substream *substream,
 192                 struct snd_soc_dai *cpu_dai)
 193 {
 194         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 195 #ifndef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
 196         union dw_i2s_snd_dma_data *dma_data = NULL;
 197 #endif
 198
 199         if (!(dev->capability & DWC_I2S_RECORD) &&
 200                         (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
 201                 return -EINVAL;
 202
 203         if (!(dev->capability & DWC_I2S_PLAY) &&
 204                         (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
 205                 return -EINVAL;
 206
 207 #ifndef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
 208         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 209                 dma_data = &dev->play_dma_data;
 210         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 211                 dma_data = &dev->capture_dma_data;
 212
 213         snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
 214 #endif
 215         return 0;
 216 }
 217
 218 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
 219 {
 220         u32 ch_reg;
 221         struct i2s_clk_config_data *config = &dev->config;
 222
 223
 224         i2s_disable_channels(dev, stream);
 225         for (ch_reg = 0; ch_reg < ((config->chan_nr + 1) / 2); ch_reg++) {
 226                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 227                         i2s_write_reg(dev->i2s_base, TCR(ch_reg),
 228                                       dev->xfer_resolution);
 229                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
 230                                       dev->fifo_th - 1);
 231                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
 232                 } else {
 233                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
 234                                       dev->xfer_resolution);
 235                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
 236                                       dev->fifo_th - 1);
 237                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
 238                 }
 239
 240         }
 241 }
 242
 243 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 244                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 245 {
 246         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 247         struct i2s_clk_config_data *config = &dev->config;
 248         int ret;
 249         unsigned int txrx = substream->stream;
 250         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 251         struct snd_soc_dai_link *dai_link = rtd->dai_link;
 252
 253         dai_link->stop_dma_first = 1;
 254         config->chan_nr = params_channels(params);
 255         config->sample_rate = params_rate(params);
 256
 257         switch (params_format(params)) {
 258         case SNDRV_PCM_FORMAT_S16_LE:
 259                 if (config->sample_rate == 8000) {
 260                         dev_err(dev->dev, "I2S: unsupported 8000 rate with S16_LE, Stereo.\n");
 261                         return -EINVAL;
 262                 }
 263
 264                 if (txrx == SNDRV_PCM_STREAM_PLAYBACK)
 265                         dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 266                 else
 267                         dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 268                 config->data_width = 16;
 269                 dev->ccr = 0x00;
 270                 dev->xfer_resolution = 0x02;
 271                 break;
 272
 273         case SNDRV_PCM_FORMAT_S24_LE:
 274                 config->data_width = 24;
 275                 dev->ccr = 0x08;
 276                 dev->xfer_resolution = 0x04;
 277                 break;
 278
 279         case SNDRV_PCM_FORMAT_S32_LE:
 280                 if ((config->sample_rate == 16000) && (config->chan_nr == 1)) {
 281                         dev_err(dev->dev, "I2S: unsupported 16000 rate with S32_LE, Mono.\n");
 282                         return -EINVAL;
 283                 }
 284                 if (txrx == SNDRV_PCM_STREAM_PLAYBACK)
 285                         dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 286                 else
 287                         dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 288
 289                 config->data_width = 32;
 290                 dev->ccr = 0x10;
 291                 dev->xfer_resolution = 0x05;
 292                 break;
 293
 294         default:
 295                 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
 296                 return -EINVAL;
 297         }
 298         snd_soc_dai_set_drvdata(dai, dev);
 299
 300         switch (config->chan_nr) {
 301         case EIGHT_CHANNEL_SUPPORT:
 302         case SIX_CHANNEL_SUPPORT:
 303         case FOUR_CHANNEL_SUPPORT:
 304         case TWO_CHANNEL_SUPPORT:
 305         case ONE_CHANNEL_SUPPORT:
 306                 break;
 307         default:
 308                 dev_err(dev->dev, "channel not supported\n");
 309                 return -EINVAL;
 310         }
 311
 312         if (txrx == SNDRV_PCM_STREAM_PLAYBACK) {
 313                 ret = clk_prepare_enable(dev->clks_dac_bclk);
 314                 if (ret) {
 315                         dev_err(dev->dev, "%s: failed to enable clks_dac_bclk\n", __func__);
 316                         return ret;
 317                 }
 318
 319                 ret = clk_set_parent(dev->clks_bclk, dev->clks_dac_bclk);
 320                 if (ret) {
 321                         dev_err(dev->dev, "Can't set clock source for clks_bclk: %d\n", ret);
 322                         return ret;
 323                 }
 324
 325                 ret = clk_prepare_enable(dev->clks_dac_lrck);
 326                 if (ret) {
 327                         dev_err(dev->dev, "%s: failed to enable clks_dac_lrck\n", __func__);
 328                         return ret;
 329                 }
 330
 331                 ret = clk_set_parent(dev->clks_lrclk, dev->clks_dac_lrck);
 332                 if (ret) {
 333                         dev_err(dev->dev, "Can't set clock source for clks_lrclk: %d\n", ret);
 334                         return ret;
 335                 }
 336         } else if (txrx == SNDRV_PCM_STREAM_CAPTURE) {
 337                 ret = clk_prepare_enable(dev->clks[CLK_ADC_BCLK_EXT]);
 338                 if (ret) {
 339                         dev_err(dev->dev, "%s: failed to enable CLK_ADC_BCLK_EXT\n", __func__);
 340                         return ret;
 341                 }
 342
 343                 ret = clk_set_parent(dev->clks[CLK_ADC_RX_BCLK], dev->clks[CLK_ADC_BCLK_EXT]);
 344                 if (ret) {
 345                         dev_err(dev->dev, "Can't set clock source for CLK_ADC_RX_BCLK: %d\n", ret);
 346                         return ret;
 347                 }
 348
 349                 ret = clk_prepare_enable(dev->clks[CLK_ADC_LRCK_EXT]);
 350                 if (ret) {
 351                         dev_err(dev->dev, "%s: failed to enable CLK_ADC_LRCK_EXT\n", __func__);
 352                         return ret;
 353                 }
 354
 355                 ret = clk_set_parent(dev->clks[CLK_ADC_RX_LRCK], dev->clks[CLK_ADC_LRCK_EXT]);
 356                 if (ret) {
 357                         dev_err(dev->dev, "Can't set clock source for CLK_ADC_RX_LRCK: %d\n", ret);
 358                         return ret;
 359                 }
 360         }
 361
 362         dw_i2s_config(dev, substream->stream);
 363
 364         i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
 365
 366         if (dev->capability & DW_I2S_MASTER) {
 367                 if (dev->i2s_clk_cfg) {
 368                         ret = dev->i2s_clk_cfg(config);
 369                         if (ret < 0) {
 370                                 dev_err(dev->dev, "runtime audio clk config fail\n");
 371                                 return ret;
 372                         }
 373                 } else {
 374                         u32 bitclk = config->sample_rate *
 375                                         config->data_width * 2;
 376
 377                         ret = clk_set_rate(dev->clk, bitclk);
 378                         if (ret) {
 379                                 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
 380                                         ret);
 381                                 return ret;
 382                         }
 383                 }
 384         }
 385         return 0;
 386 }
 387
 388 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
 389                 struct snd_soc_dai *dai)
 390 {
 391 #ifndef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
 392         snd_soc_dai_set_dma_data(dai, substream, NULL);
 393 #endif
 394 }
 395
 396 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
 397                           struct snd_soc_dai *dai)
 398 {
 399         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 400
 401         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 402                 i2s_write_reg(dev->i2s_base, TXFFR, 1);
 403         else
 404                 i2s_write_reg(dev->i2s_base, RXFFR, 1);
 405
 406         return 0;
 407 }
 408
 409 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 410                 int cmd, struct snd_soc_dai *dai)
 411 {
 412         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 413         int ret = 0;
 414
 415         switch (cmd) {
 416         case SNDRV_PCM_TRIGGER_START:
 417         case SNDRV_PCM_TRIGGER_RESUME:
 418         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 419                 dev->active++;
 420                 i2s_start(dev, substream);
 421                 break;
 422
 423         case SNDRV_PCM_TRIGGER_STOP:
 424         case SNDRV_PCM_TRIGGER_SUSPEND:
 425         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 426                 dev->active--;
 427                 i2s_stop(dev, substream);
 428                 break;
 429         default:
 430                 ret = -EINVAL;
 431                 break;
 432         }
 433         return ret;
 434 }
 435
 436 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 437 {
 438         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 439         int ret = 0;
 440
 441         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 442         case SND_SOC_DAIFMT_CBM_CFM:
 443                 if (dev->capability & DW_I2S_SLAVE)
 444                         ret = 0;
 445                 else
 446                         ret = -EINVAL;
 447                 break;
 448         case SND_SOC_DAIFMT_CBS_CFS:
 449                 if (dev->capability & DW_I2S_MASTER)
 450                         ret = 0;
 451                 else
 452                         ret = -EINVAL;
 453                 break;
 454         case SND_SOC_DAIFMT_CBM_CFS:
 455         case SND_SOC_DAIFMT_CBS_CFM:
 456                 ret = -EINVAL;
 457                 break;
 458         default:
 459                 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
 460                 ret = -EINVAL;
 461                 break;
 462         }
 463         return ret;
 464 }
 465
 466 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
 467         .startup        = dw_i2s_startup,
 468         .shutdown       = dw_i2s_shutdown,
 469         .hw_params      = dw_i2s_hw_params,
 470         .prepare        = dw_i2s_prepare,
 471         .trigger        = dw_i2s_trigger,
 472         .set_fmt        = dw_i2s_set_fmt,
 473 };
 474
 475 #ifdef CONFIG_PM
 476 static int dw_i2s_runtime_suspend(struct device *dev)
 477 {
 478         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 479
 480         if (dw_dev->capability & DW_I2S_MASTER)
 481                 clk_disable(dw_dev->clk);
 482         return 0;
 483 }
 484
 485 static int dw_i2s_runtime_resume(struct device *dev)
 486 {
 487         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 488
 489         if (dw_dev->capability & DW_I2S_MASTER)
 490                 clk_enable(dw_dev->clk);
 491         return 0;
 492 }
 493
 494 static int dw_i2s_suspend(struct snd_soc_component *component)
 495 {
 496         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 497
 498         if (dev->capability & DW_I2S_MASTER)
 499                 clk_disable(dev->clk);
 500         return 0;
 501 }
 502
 503 static int dw_i2s_resume(struct snd_soc_component *component)
 504 {
 505         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 506         struct snd_soc_dai *dai;
 507         int stream;
 508
 509         if (dev->capability & DW_I2S_MASTER)
 510                 clk_enable(dev->clk);
 511
 512         for_each_component_dais(component, dai) {
 513                 for_each_pcm_streams(stream)
 514                         if (snd_soc_dai_stream_active(dai, stream))
 515                                 dw_i2s_config(dev, stream);
 516         }
 517
 518         return 0;
 519 }
 520
 521 #else
 522 #define dw_i2s_suspend  NULL
 523 #define dw_i2s_resume   NULL
 524 #endif
 525
 526 static const struct snd_soc_component_driver dw_i2s_component = {
 527         .name           = "dw-i2s",
 528         .suspend        = dw_i2s_suspend,
 529         .resume         = dw_i2s_resume,
 530 };
 531
 532 static int dw_i2srx_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 533 {
 534         int ret = 0;
 535
 536         static struct clk_bulk_data clks[] = {
 537                 { .id = "apb0" },
 538                 { .id = "3ch-apb" },
 539                 { .id = "audioroot" },
 540                 { .id = "mclk-inner" },
 541                 { .id = "bclk_mst" },
 542                 { .id = "3ch-lrck" },
 543                 { .id = "rx-bclk" },
 544                 { .id = "rx-lrck" },
 545                 { .id = "mclk" },
 546                 { .id = "bclk-ext" },
 547                 { .id = "lrck-ext" },
 548         };
 549
 550         ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
 551         if (ret) {
 552                 dev_err(&pdev->dev, "%s: failed to get audio_subsys clocks\n", __func__);
 553                 return ret;
 554         }
 555         dev->clks[CLK_ADC_APB0] = clks[0].clk;
 556         dev->clks[CLK_ADC_APB] = clks[1].clk;
 557         dev->clks[CLK_ADC_AUDROOT] = clks[2].clk;
 558         dev->clks[CLK_ADC_MCLK_INNER] = clks[3].clk;
 559         dev->clks[CLK_ADC_BCLK] = clks[4].clk;
 560         dev->clks[CLK_ADC_LRCLK] = clks[5].clk;
 561         dev->clks[CLK_ADC_RX_BCLK] = clks[6].clk;
 562         dev->clks[CLK_ADC_RX_LRCK] = clks[7].clk;
 563         dev->clks[CLK_ADC_MCLK] = clks[8].clk;
 564         dev->clks[CLK_ADC_BCLK_EXT] = clks[9].clk;
 565         dev->clks[CLK_ADC_LRCK_EXT] = clks[10].clk;
 566
 567         ret = clk_prepare_enable(dev->clks[CLK_ADC_APB0]);
 568         if (ret) {
 569                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_APB0\n", __func__);
 570                 goto disable_APB0_clk;
 571         }
 572
 573         ret = clk_prepare_enable(dev->clks[CLK_ADC_APB]);
 574         if (ret) {
 575                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_APB\n", __func__);
 576                 goto disable_APB_clk;
 577         }
 578
 579         ret = clk_prepare_enable(dev->clks[CLK_ADC_AUDROOT]);
 580         if (ret) {
 581                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_AUDROOT\n", __func__);
 582                 goto disable_audroot_clk;
 583         }
 584
 585         ret = clk_set_rate(dev->clks[CLK_ADC_AUDROOT], 204800000);
 586         if (ret) {
 587                 dev_err(&pdev->dev, "failed to set rate for CLK_ADC_MCLK \n");
 588                 goto disable_audroot_clk;
 589         }
 590
 591         ret = clk_prepare_enable(dev->clks[CLK_ADC_MCLK_INNER]);
 592         if (ret) {
 593                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_MCLK_INNER\n", __func__);
 594                 goto disable_inner_clk;
 595         }
 596
 597         ret = clk_set_rate(dev->clks[CLK_ADC_MCLK_INNER], 4096000);
 598         if (ret) {
 599                 dev_err(&pdev->dev, "failed to set rate for CLK_ADC_MCLK \n");
 600                 goto disable_inner_clk;
 601         }
 602
 603         ret = clk_prepare_enable(dev->clks[CLK_ADC_BCLK]);
 604         if (ret) {
 605                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_BCLK\n", __func__);
 606                 goto disable_bclk;
 607         }
 608
 609         ret = clk_prepare_enable(dev->clks[CLK_ADC_LRCLK]);
 610         if (ret) {
 611                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_LRCLK\n", __func__);
 612                 goto disable_lrclk;
 613         }
 614
 615         ret = clk_prepare_enable(dev->clks[CLK_ADC_RX_BCLK]);
 616         if (ret) {
 617                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_RX_BCLK\n", __func__);
 618                 goto disable_rx_bclk;
 619         }
 620
 621         ret = clk_prepare_enable(dev->clks[CLK_ADC_RX_LRCK]);
 622         if (ret) {
 623                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_RX_LRCK\n", __func__);
 624                 goto disable_rx_lrclk;
 625         }
 626         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_APB0] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_APB0]));
 627         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_APB] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_APB]));
 628         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_BCLK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_BCLK]));
 629         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_LRCLK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_LRCLK]));
 630         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_RX_BCLK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_RX_BCLK]));
 631         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_RX_LRCK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_RX_LRCK]));
 632
 633         dev->rstc_rx = devm_reset_control_array_get_exclusive(&pdev->dev);
 634         if (IS_ERR(dev->rstc_rx)) {
 635                 dev_err(&pdev->dev, "%s: failed to get rstc_rx reset control\n", __func__);
 636                 goto disable_rx_lrclk;
 637         }
 638
 639         ret = reset_control_assert(dev->rstc_rx);
 640         if (ret) {
 641                 dev_err(&pdev->dev, "%s: failed to reset control assert rstc_rx\n", __func__);
 642                 goto disable_rx_lrclk;
 643         }
 644         udelay(5);
 645         ret = reset_control_deassert(dev->rstc_rx);
 646         if (ret) {
 647                 dev_err(&pdev->dev, "%s: failed to reset control deassert rstc_rx\n", __func__);
 648                 goto disable_rx_lrclk;
 649         }
 650
 651         /*i2srx_3ch_adc_enable*/
 652         regmap_update_bits(dev->syscon_base, dev->syscon_offset_18,
 653                                         0x1 << 1, 0x1 << 1);
 654
 655         /*set i2sdin_sel*/
 656         regmap_update_bits(dev->syscon_base, dev->syscon_offset_34,
 657                 (0x1 << 10) | (0x1 << 14) | (0x1<<17), (0x0<<10) | (0x0<<14) | (0x0<<17));
 658
 659         return 0;
 660
 661 disable_rx_lrclk:
 662         clk_disable_unprepare(dev->clks[CLK_ADC_RX_LRCK]);
 663 disable_rx_bclk:
 664         clk_disable_unprepare(dev->clks[CLK_ADC_RX_BCLK]);
 665 disable_lrclk:
 666         clk_disable_unprepare(dev->clks[CLK_ADC_LRCLK]);
 667 disable_bclk:
 668         clk_disable_unprepare(dev->clks[CLK_ADC_BCLK]);
 669 disable_inner_clk:
 670         clk_disable_unprepare(dev->clks[CLK_ADC_MCLK_INNER]);
 671 disable_audroot_clk:
 672         clk_disable_unprepare(dev->clks[CLK_ADC_AUDROOT]);
 673 disable_APB_clk:
 674         clk_disable_unprepare(dev->clks[CLK_ADC_APB]);
 675 disable_APB0_clk:
 676         clk_disable_unprepare(dev->clks[CLK_ADC_APB0]);
 677
 678         return ret;
 679 }
 680
 681 static int dw_i2stx_4ch0_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 682 {
 683         static struct clk_bulk_data i2sclk[] = {
 684                 { .id = "inner" },              //clock-names in dts file
 685                 { .id = "bclk-mst" },
 686                 { .id = "lrck-mst" },
 687                 { .id = "mclk" },
 688                 { .id = "bclk0" },
 689                 { .id = "lrck0" },
 690         };
 691
 692         int ret = 0;
 693
 694         ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(i2sclk), i2sclk);
 695         if (ret) {
 696                 printk(KERN_INFO "%s: failed to get i2stx 4ch0 clocks\n", __func__);
 697                 return ret;
 698         }
 699
 700         dev->clks[CLK_DAC_INNER] = i2sclk[0].clk;
 701         dev->clks[CLK_DAC_BCLK_MST] = i2sclk[1].clk;
 702         dev->clks[CLK_DAC_LRCLK_MST] = i2sclk[2].clk;
 703         dev->clks[CLK_MCLK] = i2sclk[3].clk;
 704         dev->clks[CLK_DAC_BCLK0] = i2sclk[4].clk;
 705         dev->clks[CLK_DAC_LRCLK0] = i2sclk[5].clk;
 706
 707         ret = clk_prepare_enable(dev->clks[CLK_DAC_INNER]);
 708         if (ret) {
 709                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_INNER\n", __func__);
 710                 goto disable_inner_clk;
 711         }
 712
 713         ret = clk_prepare_enable(dev->clks[CLK_DAC_BCLK_MST]);
 714         if (ret) {
 715                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_BCLK_MST\n", __func__);
 716                 goto disable_bclk_mst;
 717         }
 718
 719         ret = clk_prepare_enable(dev->clks[CLK_DAC_LRCLK_MST]);
 720         if (ret) {
 721                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_LRCLK_MST\n", __func__);
 722                 goto disable_lrclk_mst;
 723         }
 724
 725         ret = clk_prepare_enable(dev->clks[CLK_MCLK]);
 726         if (ret) {
 727                 dev_err(&pdev->dev, "%s: failed to enable CLK_MCLK\n", __func__);
 728                 goto disable_mclk;
 729         }
 730
 731         ret = clk_prepare_enable(dev->clks[CLK_DAC_BCLK0]);
 732         if (ret) {
 733                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_BCLK0\n", __func__);
 734                 goto disable_bclk0;
 735         }
 736
 737         ret = clk_prepare_enable(dev->clks[CLK_DAC_LRCLK0]);
 738         if (ret) {
 739                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_LRCLK0\n", __func__);
 740                 goto disable_lrclk0;
 741         }
 742
 743         dev->rstc_ch0 = devm_reset_control_array_get_exclusive(&pdev->dev);
 744         if (IS_ERR(dev->rstc_ch0)) {
 745                 dev_err(&pdev->dev, "%s: failed to get rstc_ch0 reset control\n", __func__);
 746                 goto disable_lrclk0;
 747         }
 748
 749         ret = reset_control_deassert(dev->rstc_ch0);
 750         if (ret) {
 751                 dev_err(&pdev->dev, "%s: failed to reset control deassert rstc_ch0\n", __func__);
 752                 goto disable_lrclk0;
 753         }
 754
 755         return 0;
 756
 757 disable_lrclk0:
 758         clk_disable_unprepare(dev->clks[CLK_DAC_LRCLK0]);
 759 disable_bclk0:
 760         clk_disable_unprepare(dev->clks[CLK_DAC_BCLK0]);
 761 disable_mclk:
 762         clk_disable_unprepare(dev->clks[CLK_MCLK]);
 763 disable_lrclk_mst:
 764         clk_disable_unprepare(dev->clks[CLK_DAC_LRCLK_MST]);
 765 disable_bclk_mst:
 766         clk_disable_unprepare(dev->clks[CLK_DAC_BCLK_MST]);
 767 disable_inner_clk:
 768         clk_disable_unprepare(dev->clks[CLK_DAC_INNER]);
 769
 770         return ret;
 771 }
 772
 773 static int dw_i2stx_4ch1_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 774 {
 775         int ret = 0;
 776
 777         dev->clks_audroot = devm_clk_get(&pdev->dev, "audroot");
 778         if (IS_ERR(dev->clks_audroot))
 779                 return PTR_ERR(dev->clks_audroot);
 780
 781         dev->clks_inner = devm_clk_get(&pdev->dev, "mclk_inner");
 782         if (IS_ERR(dev->clks_inner))
 783                 return PTR_ERR(dev->clks_inner);
 784
 785         dev->clks_bclk_mst = devm_clk_get(&pdev->dev, "bclk_mst");
 786         if (IS_ERR(dev->clks_bclk_mst))
 787                 return PTR_ERR(dev->clks_bclk_mst);
 788
 789         dev->clks_lrclk_mst = devm_clk_get(&pdev->dev, "lrck_mst");
 790         if (IS_ERR(dev->clks_lrclk_mst))
 791                 return PTR_ERR(dev->clks_lrclk_mst);
 792
 793         dev->clks_mclk = devm_clk_get(&pdev->dev, "mclk");
 794         if (IS_ERR(dev->clks_mclk))
 795                 return PTR_ERR(dev->clks_mclk);
 796
 797         dev->clks_bclk = devm_clk_get(&pdev->dev, "4chbclk");
 798         if (IS_ERR(dev->clks_bclk))
 799                 return PTR_ERR(dev->clks_bclk);
 800
 801         dev->clks_lrclk = devm_clk_get(&pdev->dev, "4chlrck");
 802         if (IS_ERR(dev->clks_lrclk))
 803                 return PTR_ERR(dev->clks_lrclk);
 804
 805         dev->clks_mclk_out = devm_clk_get(&pdev->dev, "mclk_out");
 806         if (IS_ERR(dev->clks_mclk_out))
 807                 return PTR_ERR(dev->clks_mclk_out);
 808
 809         dev->clks_apb0 = devm_clk_get(&pdev->dev, "apb0");
 810         if (IS_ERR(dev->clks_apb0))
 811                 return PTR_ERR(dev->clks_apb0);
 812
 813         dev->clks_4ch_apb = devm_clk_get(&pdev->dev, "clk_apb");
 814         if (IS_ERR(dev->clks_4ch_apb))
 815                 return PTR_ERR(dev->clks_4ch_apb);
 816
 817         dev->clks_dac_bclk = devm_clk_get(&pdev->dev, "bclk_ext");
 818         if (IS_ERR(dev->clks_dac_bclk))
 819                 return PTR_ERR(dev->clks_dac_bclk);
 820
 821         dev->clks_dac_lrck = devm_clk_get(&pdev->dev, "lrck_ext");
 822         if (IS_ERR(dev->clks_dac_lrck))
 823                 return PTR_ERR(dev->clks_dac_lrck);
 824
 825         ret = clk_prepare_enable(dev->clks_audroot);
 826         if (ret) {
 827                 dev_err(&pdev->dev, "%s: failed to enable clks_audroot\n", __func__);
 828                 goto disable_audioroot_clk;
 829         }
 830         ret = clk_set_rate(dev->clks_audroot, 204800000);
 831         if (ret) {
 832                 dev_err(&pdev->dev, "failed to set rate for clks_audroot ret=%d\n", ret);
 833                 goto disable_audioroot_clk;
 834         }
 835
 836         ret = clk_prepare_enable(dev->clks_inner);
 837         if (ret) {
 838                 dev_err(&pdev->dev, "%s: failed to enable clks_inner\n", __func__);
 839                 goto disable_audinner_clk;
 840         }
 841
 842         ret = clk_set_rate(dev->clks_inner, 4096000);
 843         if (ret) {
 844                 dev_err(&pdev->dev, "failed to set rate for clks_inner ret=%d\n", ret);
 845                 goto disable_audinner_clk;
 846         }
 847
 848         ret = clk_prepare_enable(dev->clks_bclk_mst);
 849         if (ret) {
 850                 dev_err(&pdev->dev, "%s: failed to enable clks_bclk_mst\n", __func__);
 851                 goto disable_mst_bclk;
 852         }
 853
 854         ret = clk_set_rate(dev->clks_bclk_mst, 1024000);
 855         if (ret) {
 856                 dev_err(&pdev->dev, "failed to set rate for clks_bclk_mst ret=%d\n", ret);
 857                 goto disable_mst_bclk;
 858         }
 859
 860         ret = clk_prepare_enable(dev->clks_lrclk_mst);
 861         if (ret) {
 862                 dev_err(&pdev->dev, "%s: failed to enable clks_lrclk_mst\n", __func__);
 863                 goto disable_mst_lrclk;
 864         }
 865
 866         ret = clk_prepare_enable(dev->clks_mclk);
 867         if (ret) {
 868                 dev_err(&pdev->dev, "%s: failed to enable clks_mclk\n", __func__);
 869                 goto disable_mclk;
 870         }
 871
 872         ret = clk_prepare_enable(dev->clks_bclk);
 873         if (ret) {
 874                 dev_err(&pdev->dev, "%s: failed to enable clks_bclk\n", __func__);
 875                 goto disable_bclk;
 876         }
 877
 878         ret = clk_prepare_enable(dev->clks_lrclk);
 879         if (ret) {
 880                 dev_err(&pdev->dev, "%s: failed to enable clks_lrclk\n", __func__);
 881                 goto disable_lrclk;
 882         }
 883
 884         ret = clk_prepare_enable(dev->clks_mclk_out);
 885         if (ret) {
 886                 dev_err(&pdev->dev, "%s: failed to enable clks_mclk_out\n", __func__);
 887                 goto disable_mclk_out;
 888         }
 889
 890         ret = clk_prepare_enable(dev->clks_apb0);
 891         if (ret) {
 892                 dev_err(&pdev->dev, "%s: failed to enable clks_apb0\n", __func__);
 893                 goto disable_apb0;
 894         }
 895
 896         ret = clk_prepare_enable(dev->clks_4ch_apb);
 897         if (ret) {
 898                 dev_err(&pdev->dev, "%s: failed to enable clks_4ch_apb\n", __func__);
 899                 goto disable_4ch_apb;
 900         }
 901
 902
 903         dev_dbg(&pdev->dev, "dev->clks_inner = %lu \n", clk_get_rate(dev->clks_inner));
 904         dev_dbg(&pdev->dev, "dev->clks_bclk_mst = %lu \n", clk_get_rate(dev->clks_bclk_mst));
 905         dev_dbg(&pdev->dev, "dev->clks_lrclk_mst = %lu \n", clk_get_rate(dev->clks_lrclk_mst));
 906         dev_dbg(&pdev->dev, "dev->clks_mclk = %lu \n", clk_get_rate(dev->clks_mclk));
 907         dev_dbg(&pdev->dev, "dev->clks_bclk = %lu \n", clk_get_rate(dev->clks_bclk));
 908         dev_dbg(&pdev->dev, "dev->clks_lrclk = %lu \n", clk_get_rate(dev->clks_lrclk));
 909         dev_dbg(&pdev->dev, "dev->clks_mclk_out = %lu \n", clk_get_rate(dev->clks_mclk_out));
 910         dev_dbg(&pdev->dev, "dev->clks_apb0 = %lu \n", clk_get_rate(dev->clks_apb0));
 911         dev_dbg(&pdev->dev, "dev->clks_4ch_apb = %lu \n", clk_get_rate(dev->clks_4ch_apb));
 912
 913         dev->rstc_ch1 = devm_reset_control_array_get_exclusive(&pdev->dev);
 914         if (IS_ERR(dev->rstc_ch1)) {
 915                 dev_err(&pdev->dev, "%s: failed to get rstc_ch1 reset control\n", __func__);
 916                 goto disable_4ch_apb;
 917         }
 918
 919         ret = reset_control_assert(dev->rstc_ch1);
 920         if (ret) {
 921                 dev_err(&pdev->dev, "%s: failed to reset control assert rstc_ch1\n", __func__);
 922                 goto disable_4ch_apb;
 923         }
 924
 925         ret = reset_control_deassert(dev->rstc_ch1);
 926         if (ret) {
 927                 dev_err(&pdev->dev, "%s: failed to reset control deassert rstc_ch1\n", __func__);
 928                 goto disable_4ch_apb;
 929         }
 930
 931         return 0;
 932
 933 disable_4ch_apb:
 934         clk_disable_unprepare(dev->clks_4ch_apb);
 935 disable_apb0:
 936         clk_disable_unprepare(dev->clks_apb0);
 937 disable_mclk_out:
 938         clk_disable_unprepare(dev->clks_mclk_out);
 939 disable_lrclk:
 940         clk_disable_unprepare(dev->clks_lrclk);
 941 disable_bclk:
 942         clk_disable_unprepare(dev->clks_bclk);
 943 disable_mclk:
 944         clk_disable_unprepare(dev->clks_mclk);
 945 disable_mst_lrclk:
 946         clk_disable_unprepare(dev->clks_lrclk_mst);
 947 disable_mst_bclk:
 948         clk_disable_unprepare(dev->clks_bclk_mst);
 949 disable_audinner_clk:
 950         clk_disable_unprepare(dev->clks_inner);
 951 disable_audioroot_clk:
 952         clk_disable_unprepare(dev->clks_audroot);
 953
 954         return ret;
 955 }
 956
 957 /*
 958  * The following tables allow a direct lookup of various parameters
 959  * defined in the I2S block's configuration in terms of sound system
 960  * parameters.  Each table is sized to the number of entries possible
 961  * according to the number of configuration bits describing an I2S
 962  * block parameter.
 963  */
 964
 965 /* Maximum bit resolution of a channel - not uniformly spaced */
 966 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
 967         12, 16, 20, 24, 32, 0, 0, 0
 968 };
 969
 970 /* Width of (DMA) bus */
 971 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
 972         DMA_SLAVE_BUSWIDTH_1_BYTE,
 973         DMA_SLAVE_BUSWIDTH_2_BYTES,
 974         DMA_SLAVE_BUSWIDTH_4_BYTES,
 975         DMA_SLAVE_BUSWIDTH_UNDEFINED
 976 };
 977
 978 /* PCM format to support channel resolution */
 979 static const u32 formats[COMP_MAX_WORDSIZE] = {
 980         SNDRV_PCM_FMTBIT_S16_LE,
 981         SNDRV_PCM_FMTBIT_S16_LE,
 982         SNDRV_PCM_FMTBIT_S24_LE,
 983         SNDRV_PCM_FMTBIT_S24_LE,
 984         SNDRV_PCM_FMTBIT_S32_LE,
 985         0,
 986         0,
 987         0
 988 };
 989
 990 static int dw_configure_dai(struct dw_i2s_dev *dev,
 991                                    struct snd_soc_dai_driver *dw_i2s_dai,
 992                                    unsigned int rates)
 993 {
 994         /*
 995          * Read component parameter registers to extract
 996          * the I2S block's configuration.
 997          */
 998         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
 999         u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
1000         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
1001         u32 idx;
1002
1003         if (dev->capability & DWC_I2S_RECORD &&
1004                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
1005                 comp1 = comp1 & ~BIT(5);
1006
1007         if (dev->capability & DWC_I2S_PLAY &&
1008                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
1009                 comp1 = comp1 & ~BIT(6);
1010
1011         if (COMP1_TX_ENABLED(comp1)) {
1012                 dev_err(dev->dev, " designware: play supported\n");
1013                 idx = COMP1_TX_WORDSIZE_0(comp1);
1014                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
1015                         return -EINVAL;
1016                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
1017                         idx = 1;
1018                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
1019                 dw_i2s_dai->playback.channels_max =
1020                                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
1021                 dw_i2s_dai->playback.formats = formats[idx];
1022                 for (;idx > 0; idx--)
1023                         dw_i2s_dai->playback.formats |= formats[idx - 1];
1024
1025                 dw_i2s_dai->playback.rates = rates;
1026         }
1027
1028         if (COMP1_RX_ENABLED(comp1)) {
1029                 dev_err(dev->dev, "designware: record supported\n");
1030                 idx = COMP2_RX_WORDSIZE_0(comp2);
1031                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
1032                         return -EINVAL;
1033                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
1034                         idx = 1;
1035                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
1036                 dw_i2s_dai->capture.channels_max =
1037                                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
1038                 dw_i2s_dai->capture.formats = formats[idx];
1039                 for (;idx > 0; idx--)
1040                         dw_i2s_dai->capture.formats |= formats[idx - 1];
1041
1042                 dw_i2s_dai->capture.rates = rates;
1043         }
1044
1045         if (COMP1_MODE_EN(comp1)) {
1046                 dev_err(dev->dev, "designware: i2s master mode supported\n");
1047                 dev->capability |= DW_I2S_MASTER;
1048         } else {
1049                 dev_err(dev->dev, "designware: i2s slave mode supported\n");
1050                 dev->capability |= DW_I2S_SLAVE;
1051         }
1052
1053         dev->fifo_th = fifo_depth / 2;
1054         return 0;
1055 }
1056
1057 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
1058                                    struct snd_soc_dai_driver *dw_i2s_dai,
1059                                    struct resource *res,
1060                                    const struct i2s_platform_data *pdata)
1061 {
1062         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
1063         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
1064         int ret;
1065
1066         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
1067                 return -EINVAL;
1068
1069         ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
1070         if (ret < 0)
1071                 return ret;
1072
1073         if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
1074                 idx = 1;
1075         /* Set DMA slaves info */
1076         dev->play_dma_data.pd.data = pdata->play_dma_data;
1077         dev->capture_dma_data.pd.data = pdata->capture_dma_data;
1078         dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
1079         dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
1080         dev->play_dma_data.pd.max_burst = 16;
1081         dev->capture_dma_data.pd.max_burst = 16;
1082         dev->play_dma_data.pd.addr_width = bus_widths[idx];
1083         dev->capture_dma_data.pd.addr_width = bus_widths[idx];
1084         dev->play_dma_data.pd.filter = pdata->filter;
1085         dev->capture_dma_data.pd.filter = pdata->filter;
1086
1087         return 0;
1088 }
1089
1090 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
1091                                    struct snd_soc_dai_driver *dw_i2s_dai,
1092                                    struct resource *res)
1093 {
1094         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
1095         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
1096         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
1097         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
1098         u32 idx2;
1099         int ret;
1100
1101         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
1102                 return -EINVAL;
1103
1104         ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
1105         if (ret < 0)
1106                 return ret;
1107
1108         if (COMP1_TX_ENABLED(comp1)) {
1109                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
1110
1111                 dev->capability |= DWC_I2S_PLAY;
1112                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
1113                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
1114                 dev->play_dma_data.dt.fifo_size = fifo_depth *
1115                         (fifo_width[idx2]) >> 8;
1116                 dev->play_dma_data.dt.maxburst = 16;
1117         }
1118         if (COMP1_RX_ENABLED(comp1)) {
1119                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
1120
1121                 dev->capability |= DWC_I2S_RECORD;
1122                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
1123                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
1124                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
1125                         (fifo_width[idx2] >> 8);
1126                 dev->capture_dma_data.dt.maxburst = 16;
1127         }
1128
1129         return 0;
1130
1131 }
1132
1133 #ifdef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
1134 static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
1135 {
1136         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
1137
1138         snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
1139         return 0;
1140 }
1141 #endif
1142
1143 static int dw_i2s_probe(struct platform_device *pdev)
1144 {
1145         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
1146         struct device_node *np = pdev->dev.of_node;
1147         struct of_phandle_args args;
1148         struct dw_i2s_dev *dev;
1149         struct resource *res;
1150         int ret, irq;
1151         struct snd_soc_dai_driver *dw_i2s_dai;
1152         const char *clk_id;
1153
1154         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1155         if (!dev)
1156                 return -ENOMEM;
1157
1158         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
1159         if (!dw_i2s_dai)
1160                 return -ENOMEM;
1161
1162         dw_i2s_dai->ops = &dw_i2s_dai_ops;
1163 #ifdef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
1164         dw_i2s_dai->probe = dw_i2s_dai_probe;
1165 #endif
1166
1167         dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1168         if (IS_ERR(dev->i2s_base))
1169                 return PTR_ERR(dev->i2s_base);
1170
1171         dev->clk_base = ioremap(CLOCK_BASE, 0x300);
1172     if (IS_ERR(dev->clk_base)) {
1173         printk(KERN_INFO "%s: failed to alloc memory for clk_base\n", __func__);
1174         return PTR_ERR(dev->clk_base);
1175     }
1176
1177         dev->dev = &pdev->dev;
1178
1179         irq = platform_get_irq_optional(pdev, 0);
1180         if (irq >= 0) {
1181                 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
1182                                 pdev->name, dev);
1183                 if (ret < 0) {
1184                         dev_err(&pdev->dev, "failed to request irq\n");
1185                         return ret;
1186                 }
1187         }
1188
1189         if (of_device_is_compatible(np, "snps,designware-i2srx")) { //record
1190                 ret = of_parse_phandle_with_fixed_args(dev->dev->of_node,
1191                                                         "starfive,sys-syscon", 2, 0, &args);
1192                 if (ret) {
1193                         dev_err(dev->dev, "Failed to parse starfive,sys-syscon\n");
1194                         return -EINVAL;
1195                 }
1196                 dev->syscon_base = syscon_node_to_regmap(args.np);
1197                 of_node_put(args.np);
1198                 if (IS_ERR(dev->syscon_base))
1199                         return PTR_ERR(dev->syscon_base);
1200
1201                 dev->syscon_offset_18 = args.args[0];
1202                 dev->syscon_offset_34 = args.args[1];
1203                 ret = dw_i2srx_clk_init(pdev, dev);
1204                 if (ret < 0)
1205                         goto err_clk_disable;
1206         } else if (of_device_is_compatible(np, "snps,designware-i2stx-4ch0")) {   //playback
1207                 ret = dw_i2stx_4ch0_clk_init(pdev, dev);
1208                 if (ret < 0)
1209                         goto err_clk_disable;
1210         } else if (of_device_is_compatible(np, "snps,designware-i2stx-4ch1")) {   //playback
1211                 ret = dw_i2stx_4ch1_clk_init(pdev, dev);
1212                 if (ret < 0)
1213                         goto err_clk_disable;
1214         }
1215
1216         dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
1217         dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
1218         if (pdata) {
1219                 dev->capability = pdata->cap;
1220                 clk_id = NULL;
1221                 dev->quirks = pdata->quirks;
1222                 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
1223                         dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
1224                         dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
1225                 }
1226                 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
1227         } else {
1228                 clk_id = "bclk_mst";
1229                 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
1230         }
1231         if (ret < 0)
1232                 return ret;
1233
1234         if (dev->capability & DW_I2S_MASTER) {
1235                 if (pdata) {
1236                         dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
1237                         if (!dev->i2s_clk_cfg) {
1238                                 dev_err(&pdev->dev, "no clock configure method\n");
1239                                 return -ENODEV;
1240                         }
1241                 }
1242                 dev->clk = devm_clk_get(&pdev->dev, clk_id);
1243
1244                 if (IS_ERR(dev->clk))
1245                         return PTR_ERR(dev->clk);
1246
1247                 ret = clk_prepare_enable(dev->clk);
1248                 if (ret < 0)
1249                         return ret;
1250         }
1251
1252         dev_set_drvdata(&pdev->dev, dev);
1253         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
1254                                          dw_i2s_dai, 1);
1255         if (ret != 0) {
1256                 dev_err(&pdev->dev, "not able to register dai\n");
1257                 goto err_clk_disable;
1258         }
1259
1260         if (!pdata) {
1261                 if (irq >= 0) {
1262                         ret = dw_pcm_register(pdev);
1263                         dev->use_pio = true;
1264                 } else {
1265                         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
1266                                         0);
1267                         dev->use_pio = false;
1268                 }
1269
1270                 if (ret) {
1271                         dev_err(&pdev->dev, "could not register pcm: %d\n",
1272                                         ret);
1273                         goto err_clk_disable;
1274                 }
1275         }
1276
1277         pm_runtime_enable(&pdev->dev);
1278         clk_disable_unprepare(dev->clks_mclk_out);
1279         clk_disable_unprepare(dev->clks_bclk_mst);
1280         clk_disable_unprepare(dev->clks_lrclk_mst);
1281         return 0;
1282
1283 err_clk_disable:
1284         if (dev->capability & DW_I2S_MASTER)
1285                 clk_disable_unprepare(dev->clk);
1286         return ret;
1287 }
1288
1289 static int dw_i2s_remove(struct platform_device *pdev)
1290 {
1291         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
1292
1293         if (dev->capability & DW_I2S_MASTER)
1294                 clk_disable_unprepare(dev->clk);
1295
1296         pm_runtime_disable(&pdev->dev);
1297         return 0;
1298 }
1299
1300 #ifdef CONFIG_OF
1301 static const struct of_device_id dw_i2s_of_match[] = {
1302         { .compatible = "snps,designware-i2stx-4ch1",    },
1303         { .compatible = "snps,designware-i2srx",         },
1304         { .compatible = "snps,designware-i2stx-4ch0",    },
1305         {},
1306 };
1307
1308 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
1309 #endif
1310
1311 static const struct dev_pm_ops dwc_pm_ops = {
1312         SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
1313 };
1314
1315 static struct platform_driver dw_i2s_driver = {
1316         .probe          = dw_i2s_probe,
1317         .remove         = dw_i2s_remove,
1318         .driver         = {
1319                 .name   = "designware-i2s",
1320                 .of_match_table = of_match_ptr(dw_i2s_of_match),
1321                 .pm = &dwc_pm_ops,
1322         },
1323 };
1324
1325 static int __init dwci2s_driver_init(void)
1326 {
1327         return platform_driver_register(&dw_i2s_driver);
1328 }
1329
1330 static void dwci2s_driver_exit(void)
1331 {
1332         platform_driver_unregister(&dw_i2s_driver);
1333 }
1334
1335 late_initcall(dwci2s_driver_init);
1336 module_exit(dwci2s_driver_exit);
1337
1338
1339 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
1340 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
1341 MODULE_LICENSE("GPL");
1342 MODULE_ALIAS("platform:designware_i2s");