sound/soc/dwc/dwc-i2s.c

   1 /*
   2  * ALSA SoC Synopsys I2S Audio Layer
   3  *
   4  * sound/soc/dwc/designware_i2s.c
   5  *
   6  * Copyright (C) 2010 ST Microelectronics
   7  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/pm_runtime.h>
  22 #include <sound/designware_i2s.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/dmaengine_pcm.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30 #include "local.h"
  31
  32 #define CLOCK_BASE      0x13020000UL
  33
  34 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
  35 {
  36         writel(val, io_base + reg);
  37 }
  38
  39 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
  40 {
  41         return readl(io_base + reg);
  42 }
  43
  44 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
  45 {
  46         u32 i = 0;
  47
  48         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  49                 for (i = 0; i < 4; i++)
  50                         i2s_write_reg(dev->i2s_base, TER(i), 0);
  51         } else {
  52                 for (i = 0; i < 4; i++)
  53                         i2s_write_reg(dev->i2s_base, RER(i), 0);
  54         }
  55 }
  56
  57 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
  58 {
  59         u32 i = 0;
  60
  61         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  62                 for (i = 0; i < 4; i++)
  63                         i2s_read_reg(dev->i2s_base, TOR(i));
  64         } else {
  65                 for (i = 0; i < 4; i++)
  66                         i2s_read_reg(dev->i2s_base, ROR(i));
  67         }
  68 }
  69
  70 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
  71                                     int chan_nr)
  72 {
  73         u32 i, irq;
  74
  75         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  76                 for (i = 0; i <= ((chan_nr + 1) / 2); i++) {
  77                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  78                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
  79                 }
  80         } else {
  81                 for (i = 0; i <= ((chan_nr + 1) / 2); i++) {
  82                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  83                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
  84                 }
  85         }
  86 }
  87
  88 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
  89                                    int chan_nr)
  90 {
  91         u32 i, irq;
  92
  93         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  94                 for (i = 0; i < ((chan_nr + 1) / 2); i++) {
  95                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
  96                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
  97                 }
  98         } else {
  99                 for (i = 0; i < ((chan_nr + 1) / 2); i++) {
 100                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 101                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
 102                 }
 103         }
 104 }
 105
 106 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
 107 {
 108         struct dw_i2s_dev *dev = dev_id;
 109         bool irq_valid = false;
 110         u32 isr[4];
 111         int i;
 112
 113         for (i = 0; i < 4; i++)
 114                 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
 115
 116         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
 117         i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
 118
 119         for (i = 0; i < 4; i++) {
 120                 /*
 121                  * Check if TX fifo is empty. If empty fill FIFO with samples
 122                  * NOTE: Only two channels supported
 123                  */
 124                 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
 125                         dw_pcm_push_tx(dev);
 126                         irq_valid = true;
 127                 }
 128
 129                 /*
 130                  * Data available. Retrieve samples from FIFO
 131                  * NOTE: Only two channels supported
 132                  */
 133                 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
 134                         dw_pcm_pop_rx(dev);
 135                         irq_valid = true;
 136                 }
 137
 138                 /* Error Handling: TX */
 139                 if (isr[i] & ISR_TXFO) {
 140                         dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
 141                         irq_valid = true;
 142                 }
 143
 144                 /* Error Handling: TX */
 145                 if (isr[i] & ISR_RXFO) {
 146                         dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
 147                         irq_valid = true;
 148                 }
 149         }
 150
 151         if (irq_valid)
 152                 return IRQ_HANDLED;
 153         else
 154                 return IRQ_NONE;
 155 }
 156
 157 static void i2s_start(struct dw_i2s_dev *dev,
 158                       struct snd_pcm_substream *substream)
 159 {
 160         struct i2s_clk_config_data *config = &dev->config;
 161
 162         i2s_write_reg(dev->i2s_base, IER, 1);
 163         i2s_enable_irqs(dev, substream->stream, config->chan_nr);
 164
 165         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 166                 i2s_write_reg(dev->i2s_base, ITER, 1);
 167         else
 168                 i2s_write_reg(dev->i2s_base, IRER, 1);
 169
 170         i2s_write_reg(dev->i2s_base, CER, 1);
 171 }
 172
 173 static void i2s_stop(struct dw_i2s_dev *dev,
 174                 struct snd_pcm_substream *substream)
 175 {
 176
 177         i2s_clear_irqs(dev, substream->stream);
 178         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 179                 i2s_write_reg(dev->i2s_base, ITER, 0);
 180         else
 181                 i2s_write_reg(dev->i2s_base, IRER, 0);
 182
 183         i2s_disable_irqs(dev, substream->stream, 8);
 184
 185         if (!dev->active) {
 186                 i2s_write_reg(dev->i2s_base, CER, 0);
 187                 i2s_write_reg(dev->i2s_base, IER, 0);
 188         }
 189 }
 190
 191 static int dw_i2s_startup(struct snd_pcm_substream *substream,
 192                 struct snd_soc_dai *cpu_dai)
 193 {
 194         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 195 #ifndef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
 196         union dw_i2s_snd_dma_data *dma_data = NULL;
 197 #endif
 198
 199         if (!(dev->capability & DWC_I2S_RECORD) &&
 200                         (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
 201                 return -EINVAL;
 202
 203         if (!(dev->capability & DWC_I2S_PLAY) &&
 204                         (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
 205                 return -EINVAL;
 206
 207 #ifndef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
 208         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 209                 dma_data = &dev->play_dma_data;
 210         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 211                 dma_data = &dev->capture_dma_data;
 212
 213         snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
 214 #endif
 215         return 0;
 216 }
 217
 218 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
 219 {
 220         u32 ch_reg;
 221         struct i2s_clk_config_data *config = &dev->config;
 222
 223
 224         i2s_disable_channels(dev, stream);
 225         for (ch_reg = 0; ch_reg < ((config->chan_nr + 1) / 2); ch_reg++) {
 226                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 227                         i2s_write_reg(dev->i2s_base, TCR(ch_reg),
 228                                       dev->xfer_resolution);
 229                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
 230                                       dev->fifo_th - 1);
 231                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
 232                 } else {
 233                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
 234                                       dev->xfer_resolution);
 235                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
 236                                       dev->fifo_th - 1);
 237                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
 238                 }
 239
 240         }
 241 }
 242
 243 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 244                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 245 {
 246         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 247         struct i2s_clk_config_data *config = &dev->config;
 248         int ret;
 249         unsigned int txrx = substream->stream;
 250         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 251         struct snd_soc_dai_link *dai_link = rtd->dai_link;
 252
 253         dai_link->stop_dma_first = 1;
 254         config->chan_nr = params_channels(params);
 255         config->sample_rate = params_rate(params);
 256
 257         switch (params_format(params)) {
 258         case SNDRV_PCM_FORMAT_S16_LE:
 259                 if ((config->sample_rate == 8000) && (txrx == SNDRV_PCM_STREAM_PLAYBACK)) {
 260                         dev_err(dev->dev, "I2S: unsupported 8000 rate with S16_LE, Stereo.\n");
 261                         return -EINVAL;
 262                 }
 263
 264                 if (txrx == SNDRV_PCM_STREAM_PLAYBACK)
 265                         dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 266                 else
 267                         dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 268                 config->data_width = 16;
 269                 dev->ccr = 0x00;
 270                 dev->xfer_resolution = 0x02;
 271                 break;
 272
 273         case SNDRV_PCM_FORMAT_S24_LE:
 274                 config->data_width = 24;
 275                 dev->ccr = 0x08;
 276                 dev->xfer_resolution = 0x04;
 277                 break;
 278
 279         case SNDRV_PCM_FORMAT_S32_LE:
 280                 if ((config->sample_rate == 16000) && (config->chan_nr == 1) &&
 281                                 (txrx == SNDRV_PCM_STREAM_PLAYBACK)) {
 282                         dev_err(dev->dev, "I2S: unsupported 16000 rate with S32_LE, Mono.\n");
 283                         return -EINVAL;
 284                 }
 285                 if (txrx == SNDRV_PCM_STREAM_PLAYBACK)
 286                         dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 287                 else
 288                         dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 289
 290                 config->data_width = 32;
 291                 dev->ccr = 0x10;
 292                 dev->xfer_resolution = 0x05;
 293                 break;
 294
 295         default:
 296                 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
 297                 return -EINVAL;
 298         }
 299         snd_soc_dai_set_drvdata(dai, dev);
 300
 301         switch (config->chan_nr) {
 302         case EIGHT_CHANNEL_SUPPORT:
 303         case SIX_CHANNEL_SUPPORT:
 304         case FOUR_CHANNEL_SUPPORT:
 305         case TWO_CHANNEL_SUPPORT:
 306         case ONE_CHANNEL_SUPPORT:
 307                 break;
 308         default:
 309                 dev_err(dev->dev, "channel not supported\n");
 310                 return -EINVAL;
 311         }
 312
 313         if (txrx == SNDRV_PCM_STREAM_PLAYBACK) {
 314                 ret = clk_set_parent(dev->clks_bclk, dev->clks_dac_bclk);
 315                 if (ret) {
 316                         dev_err(dev->dev, "Can't set clock source for clks_bclk: %d\n", ret);
 317                         return ret;
 318                 }
 319
 320                 ret = clk_set_parent(dev->clks_lrclk, dev->clks_dac_lrck);
 321                 if (ret) {
 322                         dev_err(dev->dev, "Can't set clock source for clks_lrclk: %d\n", ret);
 323                         return ret;
 324                 }
 325         } else if (txrx == SNDRV_PCM_STREAM_CAPTURE) {
 326                 ret = clk_prepare_enable(dev->clks[CLK_ADC_BCLK_EXT]);
 327                 if (ret) {
 328                         dev_err(dev->dev, "%s: failed to enable CLK_ADC_BCLK_EXT\n", __func__);
 329                         return ret;
 330                 }
 331
 332                 ret = clk_set_parent(dev->clks[CLK_ADC_RX_BCLK], dev->clks[CLK_ADC_BCLK_EXT]);
 333                 if (ret) {
 334                         dev_err(dev->dev, "Can't set clock source for CLK_ADC_RX_BCLK: %d\n", ret);
 335                         return ret;
 336                 }
 337
 338                 ret = clk_prepare_enable(dev->clks[CLK_ADC_LRCK_EXT]);
 339                 if (ret) {
 340                         dev_err(dev->dev, "%s: failed to enable CLK_ADC_LRCK_EXT\n", __func__);
 341                         return ret;
 342                 }
 343
 344                 ret = clk_set_parent(dev->clks[CLK_ADC_RX_LRCK], dev->clks[CLK_ADC_LRCK_EXT]);
 345                 if (ret) {
 346                         dev_err(dev->dev, "Can't set clock source for CLK_ADC_RX_LRCK: %d\n", ret);
 347                         return ret;
 348                 }
 349         }
 350
 351         dw_i2s_config(dev, substream->stream);
 352
 353         i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
 354
 355         if (dev->capability & DW_I2S_MASTER) {
 356                 if (dev->i2s_clk_cfg) {
 357                         ret = dev->i2s_clk_cfg(config);
 358                         if (ret < 0) {
 359                                 dev_err(dev->dev, "runtime audio clk config fail\n");
 360                                 return ret;
 361                         }
 362                 } else {
 363                         u32 bitclk = config->sample_rate *
 364                                         config->data_width * 2;
 365
 366                         ret = clk_set_rate(dev->clk, bitclk);
 367                         if (ret) {
 368                                 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
 369                                         ret);
 370                                 return ret;
 371                         }
 372                 }
 373         }
 374         return 0;
 375 }
 376
 377 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
 378                 struct snd_soc_dai *dai)
 379 {
 380 #ifndef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
 381         snd_soc_dai_set_dma_data(dai, substream, NULL);
 382 #endif
 383 }
 384
 385 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
 386                           struct snd_soc_dai *dai)
 387 {
 388         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 389
 390         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 391                 i2s_write_reg(dev->i2s_base, TXFFR, 1);
 392         else
 393                 i2s_write_reg(dev->i2s_base, RXFFR, 1);
 394
 395         return 0;
 396 }
 397
 398 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 399                 int cmd, struct snd_soc_dai *dai)
 400 {
 401         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 402         int ret = 0;
 403
 404         switch (cmd) {
 405         case SNDRV_PCM_TRIGGER_START:
 406         case SNDRV_PCM_TRIGGER_RESUME:
 407         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 408                 dev->active++;
 409                 i2s_start(dev, substream);
 410                 break;
 411
 412         case SNDRV_PCM_TRIGGER_STOP:
 413         case SNDRV_PCM_TRIGGER_SUSPEND:
 414         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 415                 dev->active--;
 416                 i2s_stop(dev, substream);
 417                 break;
 418         default:
 419                 ret = -EINVAL;
 420                 break;
 421         }
 422         return ret;
 423 }
 424
 425 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 426 {
 427         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 428         int ret = 0;
 429
 430         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 431         case SND_SOC_DAIFMT_CBM_CFM:
 432                 if (dev->capability & DW_I2S_SLAVE)
 433                         ret = 0;
 434                 else
 435                         ret = -EINVAL;
 436                 break;
 437         case SND_SOC_DAIFMT_CBS_CFS:
 438                 if (dev->capability & DW_I2S_MASTER)
 439                         ret = 0;
 440                 else
 441                         ret = -EINVAL;
 442                 break;
 443         case SND_SOC_DAIFMT_CBM_CFS:
 444         case SND_SOC_DAIFMT_CBS_CFM:
 445                 ret = -EINVAL;
 446                 break;
 447         default:
 448                 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
 449                 ret = -EINVAL;
 450                 break;
 451         }
 452         return ret;
 453 }
 454
 455 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
 456         .startup        = dw_i2s_startup,
 457         .shutdown       = dw_i2s_shutdown,
 458         .hw_params      = dw_i2s_hw_params,
 459         .prepare        = dw_i2s_prepare,
 460         .trigger        = dw_i2s_trigger,
 461         .set_fmt        = dw_i2s_set_fmt,
 462 };
 463
 464 #ifdef CONFIG_PM
 465 static int dw_i2s_runtime_suspend(struct device *dev)
 466 {
 467         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 468
 469         if (dw_dev->capability & DW_I2S_MASTER)
 470                 clk_disable(dw_dev->clk);
 471         else {
 472                 clk_disable_unprepare(dw_dev->clks_bclk_mst);
 473                 clk_disable_unprepare(dw_dev->clks_mclk_out);
 474                 clk_disable_unprepare(dw_dev->clks_4ch_apb);
 475         }
 476         return 0;
 477 }
 478
 479 static int dw_i2s_runtime_resume(struct device *dev)
 480 {
 481         struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
 482         int ret;
 483
 484         if (dw_dev->capability & DW_I2S_MASTER)
 485                 clk_enable(dw_dev->clk);
 486         else {
 487                 ret = clk_prepare_enable(dw_dev->clks_4ch_apb);
 488                 if (ret) {
 489                         dev_err(dev, "failed to enable clks_4ch_apb\n");
 490                         goto failed_enable;
 491                 }
 492                 ret = clk_prepare_enable(dw_dev->clks_bclk_mst);
 493                 if (ret) {
 494                         dev_err(dev, "failed to enable clks_bclk_mst\n");
 495                         goto failed_enable;
 496                 }
 497                 ret = clk_prepare_enable(dw_dev->clks_mclk_out);
 498                 if (ret) {
 499                         dev_err(dev, "failed to enable clks_mclk_out\n");
 500                         goto failed_enable;
 501                 }
 502         }
 503         return 0;
 504
 505 failed_enable:
 506         return ret;
 507 }
 508
 509 static int dw_i2s_suspend(struct snd_soc_component *component)
 510 {
 511         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 512         int ret;
 513
 514         if (dev->capability & DW_I2S_MASTER)
 515                 clk_disable(dev->clk);
 516
 517         ret = pm_runtime_force_suspend(component->dev);
 518         if (ret)
 519                 return ret;
 520
 521         return 0;
 522 }
 523
 524 static int dw_i2s_resume(struct snd_soc_component *component)
 525 {
 526         struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
 527         struct snd_soc_dai *dai;
 528         int stream;
 529         int ret;
 530
 531         if (dev->capability & DW_I2S_MASTER)
 532                 clk_enable(dev->clk);
 533
 534         ret = pm_runtime_force_resume(component->dev);
 535         if (ret)
 536                 return ret;
 537
 538         for_each_component_dais(component, dai) {
 539                 for_each_pcm_streams(stream)
 540                         if (snd_soc_dai_stream_active(dai, stream))
 541                                 dw_i2s_config(dev, stream);
 542         }
 543
 544         return 0;
 545 }
 546
 547 #else
 548 #define dw_i2s_suspend  NULL
 549 #define dw_i2s_resume   NULL
 550 #endif
 551
 552 static const struct snd_soc_component_driver dw_i2s_component = {
 553         .name           = "dw-i2s",
 554         .suspend        = dw_i2s_suspend,
 555         .resume         = dw_i2s_resume,
 556 };
 557
 558 static int dw_i2srx_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 559 {
 560         int ret = 0;
 561
 562         static struct clk_bulk_data clks[] = {
 563                 { .id = "apb0" },
 564                 { .id = "3ch-apb" },
 565                 { .id = "audioroot" },
 566                 { .id = "mclk-inner" },
 567                 { .id = "bclk_mst" },
 568                 { .id = "3ch-lrck" },
 569                 { .id = "rx-bclk" },
 570                 { .id = "rx-lrck" },
 571                 { .id = "mclk" },
 572                 { .id = "bclk-ext" },
 573                 { .id = "lrck-ext" },
 574         };
 575
 576         ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
 577         if (ret) {
 578                 dev_err(&pdev->dev, "%s: failed to get audio_subsys clocks\n", __func__);
 579                 return ret;
 580         }
 581         dev->clks[CLK_ADC_APB0] = clks[0].clk;
 582         dev->clks[CLK_ADC_APB] = clks[1].clk;
 583         dev->clks[CLK_ADC_AUDROOT] = clks[2].clk;
 584         dev->clks[CLK_ADC_MCLK_INNER] = clks[3].clk;
 585         dev->clks[CLK_ADC_BCLK] = clks[4].clk;
 586         dev->clks[CLK_ADC_LRCLK] = clks[5].clk;
 587         dev->clks[CLK_ADC_RX_BCLK] = clks[6].clk;
 588         dev->clks[CLK_ADC_RX_LRCK] = clks[7].clk;
 589         dev->clks[CLK_ADC_MCLK] = clks[8].clk;
 590         dev->clks[CLK_ADC_BCLK_EXT] = clks[9].clk;
 591         dev->clks[CLK_ADC_LRCK_EXT] = clks[10].clk;
 592
 593         ret = clk_prepare_enable(dev->clks[CLK_ADC_APB0]);
 594         if (ret) {
 595                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_APB0\n", __func__);
 596                 goto disable_APB0_clk;
 597         }
 598
 599         ret = clk_prepare_enable(dev->clks[CLK_ADC_APB]);
 600         if (ret) {
 601                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_APB\n", __func__);
 602                 goto disable_APB_clk;
 603         }
 604
 605         ret = clk_prepare_enable(dev->clks[CLK_ADC_AUDROOT]);
 606         if (ret) {
 607                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_AUDROOT\n", __func__);
 608                 goto disable_audroot_clk;
 609         }
 610
 611         ret = clk_set_rate(dev->clks[CLK_ADC_AUDROOT], 204800000);
 612         if (ret) {
 613                 dev_err(&pdev->dev, "failed to set rate for CLK_ADC_MCLK \n");
 614                 goto disable_audroot_clk;
 615         }
 616
 617         ret = clk_prepare_enable(dev->clks[CLK_ADC_MCLK_INNER]);
 618         if (ret) {
 619                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_MCLK_INNER\n", __func__);
 620                 goto disable_inner_clk;
 621         }
 622
 623         ret = clk_set_rate(dev->clks[CLK_ADC_MCLK_INNER], 4096000);
 624         if (ret) {
 625                 dev_err(&pdev->dev, "failed to set rate for CLK_ADC_MCLK \n");
 626                 goto disable_inner_clk;
 627         }
 628
 629         ret = clk_prepare_enable(dev->clks[CLK_ADC_BCLK]);
 630         if (ret) {
 631                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_BCLK\n", __func__);
 632                 goto disable_bclk;
 633         }
 634
 635         ret = clk_prepare_enable(dev->clks[CLK_ADC_LRCLK]);
 636         if (ret) {
 637                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_LRCLK\n", __func__);
 638                 goto disable_lrclk;
 639         }
 640
 641         ret = clk_prepare_enable(dev->clks[CLK_ADC_RX_BCLK]);
 642         if (ret) {
 643                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_RX_BCLK\n", __func__);
 644                 goto disable_rx_bclk;
 645         }
 646
 647         ret = clk_prepare_enable(dev->clks[CLK_ADC_RX_LRCK]);
 648         if (ret) {
 649                 dev_err(&pdev->dev, "%s: failed to enable CLK_ADC_RX_LRCK\n", __func__);
 650                 goto disable_rx_lrclk;
 651         }
 652         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_APB0] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_APB0]));
 653         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_APB] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_APB]));
 654         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_BCLK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_BCLK]));
 655         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_LRCLK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_LRCLK]));
 656         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_RX_BCLK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_RX_BCLK]));
 657         dev_dbg(&pdev->dev, "dev->clks[CLK_ADC_RX_LRCK] = %lu \n", clk_get_rate(dev->clks[CLK_ADC_RX_LRCK]));
 658
 659         dev->rstc_rx = devm_reset_control_array_get_exclusive(&pdev->dev);
 660         if (IS_ERR(dev->rstc_rx)) {
 661                 dev_err(&pdev->dev, "%s: failed to get rstc_rx reset control\n", __func__);
 662                 goto disable_rx_lrclk;
 663         }
 664
 665         ret = reset_control_assert(dev->rstc_rx);
 666         if (ret) {
 667                 dev_err(&pdev->dev, "%s: failed to reset control assert rstc_rx\n", __func__);
 668                 goto disable_rx_lrclk;
 669         }
 670         udelay(5);
 671         ret = reset_control_deassert(dev->rstc_rx);
 672         if (ret) {
 673                 dev_err(&pdev->dev, "%s: failed to reset control deassert rstc_rx\n", __func__);
 674                 goto disable_rx_lrclk;
 675         }
 676
 677         /*i2srx_3ch_adc_enable*/
 678         regmap_update_bits(dev->syscon_base, dev->syscon_offset_18,
 679                                         0x1 << 1, 0x1 << 1);
 680
 681         /*set i2sdin_sel*/
 682         regmap_update_bits(dev->syscon_base, dev->syscon_offset_34,
 683                 (0x1 << 10) | (0x1 << 14) | (0x1<<17), (0x0<<10) | (0x0<<14) | (0x0<<17));
 684
 685         return 0;
 686
 687 disable_rx_lrclk:
 688         clk_disable_unprepare(dev->clks[CLK_ADC_RX_LRCK]);
 689 disable_rx_bclk:
 690         clk_disable_unprepare(dev->clks[CLK_ADC_RX_BCLK]);
 691 disable_lrclk:
 692         clk_disable_unprepare(dev->clks[CLK_ADC_LRCLK]);
 693 disable_bclk:
 694         clk_disable_unprepare(dev->clks[CLK_ADC_BCLK]);
 695 disable_inner_clk:
 696         clk_disable_unprepare(dev->clks[CLK_ADC_MCLK_INNER]);
 697 disable_audroot_clk:
 698         clk_disable_unprepare(dev->clks[CLK_ADC_AUDROOT]);
 699 disable_APB_clk:
 700         clk_disable_unprepare(dev->clks[CLK_ADC_APB]);
 701 disable_APB0_clk:
 702         clk_disable_unprepare(dev->clks[CLK_ADC_APB0]);
 703
 704         return ret;
 705 }
 706
 707 static int dw_i2stx_4ch0_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 708 {
 709         static struct clk_bulk_data i2sclk[] = {
 710                 { .id = "inner" },              //clock-names in dts file
 711                 { .id = "bclk-mst" },
 712                 { .id = "lrck-mst" },
 713                 { .id = "mclk" },
 714                 { .id = "bclk0" },
 715                 { .id = "lrck0" },
 716         };
 717
 718         int ret = 0;
 719
 720         ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(i2sclk), i2sclk);
 721         if (ret) {
 722                 printk(KERN_INFO "%s: failed to get i2stx 4ch0 clocks\n", __func__);
 723                 return ret;
 724         }
 725
 726         dev->clks[CLK_DAC_INNER] = i2sclk[0].clk;
 727         dev->clks[CLK_DAC_BCLK_MST] = i2sclk[1].clk;
 728         dev->clks[CLK_DAC_LRCLK_MST] = i2sclk[2].clk;
 729         dev->clks[CLK_MCLK] = i2sclk[3].clk;
 730         dev->clks[CLK_DAC_BCLK0] = i2sclk[4].clk;
 731         dev->clks[CLK_DAC_LRCLK0] = i2sclk[5].clk;
 732
 733         ret = clk_prepare_enable(dev->clks[CLK_DAC_INNER]);
 734         if (ret) {
 735                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_INNER\n", __func__);
 736                 goto disable_inner_clk;
 737         }
 738
 739         ret = clk_prepare_enable(dev->clks[CLK_DAC_BCLK_MST]);
 740         if (ret) {
 741                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_BCLK_MST\n", __func__);
 742                 goto disable_bclk_mst;
 743         }
 744
 745         ret = clk_prepare_enable(dev->clks[CLK_DAC_LRCLK_MST]);
 746         if (ret) {
 747                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_LRCLK_MST\n", __func__);
 748                 goto disable_lrclk_mst;
 749         }
 750
 751         ret = clk_prepare_enable(dev->clks[CLK_MCLK]);
 752         if (ret) {
 753                 dev_err(&pdev->dev, "%s: failed to enable CLK_MCLK\n", __func__);
 754                 goto disable_mclk;
 755         }
 756
 757         ret = clk_prepare_enable(dev->clks[CLK_DAC_BCLK0]);
 758         if (ret) {
 759                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_BCLK0\n", __func__);
 760                 goto disable_bclk0;
 761         }
 762
 763         ret = clk_prepare_enable(dev->clks[CLK_DAC_LRCLK0]);
 764         if (ret) {
 765                 dev_err(&pdev->dev, "%s: failed to enable CLK_DAC_LRCLK0\n", __func__);
 766                 goto disable_lrclk0;
 767         }
 768
 769         dev->rstc_ch0 = devm_reset_control_array_get_exclusive(&pdev->dev);
 770         if (IS_ERR(dev->rstc_ch0)) {
 771                 dev_err(&pdev->dev, "%s: failed to get rstc_ch0 reset control\n", __func__);
 772                 goto disable_lrclk0;
 773         }
 774
 775         ret = reset_control_deassert(dev->rstc_ch0);
 776         if (ret) {
 777                 dev_err(&pdev->dev, "%s: failed to reset control deassert rstc_ch0\n", __func__);
 778                 goto disable_lrclk0;
 779         }
 780
 781         return 0;
 782
 783 disable_lrclk0:
 784         clk_disable_unprepare(dev->clks[CLK_DAC_LRCLK0]);
 785 disable_bclk0:
 786         clk_disable_unprepare(dev->clks[CLK_DAC_BCLK0]);
 787 disable_mclk:
 788         clk_disable_unprepare(dev->clks[CLK_MCLK]);
 789 disable_lrclk_mst:
 790         clk_disable_unprepare(dev->clks[CLK_DAC_LRCLK_MST]);
 791 disable_bclk_mst:
 792         clk_disable_unprepare(dev->clks[CLK_DAC_BCLK_MST]);
 793 disable_inner_clk:
 794         clk_disable_unprepare(dev->clks[CLK_DAC_INNER]);
 795
 796         return ret;
 797 }
 798
 799 static int dw_i2stx_4ch1_clk_init(struct platform_device *pdev, struct dw_i2s_dev *dev)
 800 {
 801         int ret = 0;
 802
 803         dev->clks_audroot = devm_clk_get(&pdev->dev, "audroot");
 804         if (IS_ERR(dev->clks_audroot))
 805                 return PTR_ERR(dev->clks_audroot);
 806
 807         dev->clks_inner = devm_clk_get(&pdev->dev, "mclk_inner");
 808         if (IS_ERR(dev->clks_inner))
 809                 return PTR_ERR(dev->clks_inner);
 810
 811         dev->clks_bclk_mst = devm_clk_get(&pdev->dev, "bclk_mst");
 812         if (IS_ERR(dev->clks_bclk_mst))
 813                 return PTR_ERR(dev->clks_bclk_mst);
 814
 815         dev->clks_lrclk_mst = devm_clk_get(&pdev->dev, "lrck_mst");
 816         if (IS_ERR(dev->clks_lrclk_mst))
 817                 return PTR_ERR(dev->clks_lrclk_mst);
 818
 819         dev->clks_mclk = devm_clk_get(&pdev->dev, "mclk");
 820         if (IS_ERR(dev->clks_mclk))
 821                 return PTR_ERR(dev->clks_mclk);
 822
 823         dev->clks_bclk = devm_clk_get(&pdev->dev, "4chbclk");
 824         if (IS_ERR(dev->clks_bclk))
 825                 return PTR_ERR(dev->clks_bclk);
 826
 827         dev->clks_lrclk = devm_clk_get(&pdev->dev, "4chlrck");
 828         if (IS_ERR(dev->clks_lrclk))
 829                 return PTR_ERR(dev->clks_lrclk);
 830
 831         dev->clks_mclk_out = devm_clk_get(&pdev->dev, "mclk_out");
 832         if (IS_ERR(dev->clks_mclk_out))
 833                 return PTR_ERR(dev->clks_mclk_out);
 834
 835         dev->clks_apb0 = devm_clk_get(&pdev->dev, "apb0");
 836         if (IS_ERR(dev->clks_apb0))
 837                 return PTR_ERR(dev->clks_apb0);
 838
 839         dev->clks_4ch_apb = devm_clk_get(&pdev->dev, "clk_apb");
 840         if (IS_ERR(dev->clks_4ch_apb))
 841                 return PTR_ERR(dev->clks_4ch_apb);
 842
 843         dev->clks_dac_bclk = devm_clk_get(&pdev->dev, "bclk_ext");
 844         if (IS_ERR(dev->clks_dac_bclk))
 845                 return PTR_ERR(dev->clks_dac_bclk);
 846
 847         dev->clks_dac_lrck = devm_clk_get(&pdev->dev, "lrck_ext");
 848         if (IS_ERR(dev->clks_dac_lrck))
 849                 return PTR_ERR(dev->clks_dac_lrck);
 850
 851         ret = clk_set_rate(dev->clks_audroot, 204800000);
 852         if (ret) {
 853                 dev_err(&pdev->dev, "failed to set rate for clks_audroot ret=%d\n", ret);
 854                 goto disable_audioroot_clk;
 855         }
 856
 857         ret = clk_set_rate(dev->clks_inner, 4096000);
 858         if (ret) {
 859                 dev_err(&pdev->dev, "failed to set rate for clks_inner ret=%d\n", ret);
 860                 goto disable_audioroot_clk;
 861         }
 862
 863         ret = clk_prepare_enable(dev->clks_bclk_mst);
 864         if (ret) {
 865                 dev_err(&pdev->dev, "%s: failed to enable clks_bclk_mst\n", __func__);
 866                 goto disable_audioroot_clk;
 867         }
 868
 869         ret = clk_set_rate(dev->clks_bclk_mst, 1024000);
 870         if (ret) {
 871                 dev_err(&pdev->dev, "failed to set rate for clks_bclk_mst ret=%d\n", ret);
 872                 goto disable_mst_bclk;
 873         }
 874
 875         ret = clk_prepare_enable(dev->clks_mclk_out);
 876         if (ret) {
 877                 dev_err(&pdev->dev, "%s: failed to enable clks_mclk_out\n", __func__);
 878                 goto disable_mst_bclk;
 879         }
 880
 881         ret = clk_prepare_enable(dev->clks_4ch_apb);
 882         if (ret) {
 883                 dev_err(&pdev->dev, "%s: failed to enable clks_4ch_apb\n", __func__);
 884                 goto disable_4ch_apb;
 885         }
 886
 887         dev_dbg(&pdev->dev, "dev->clks_inner = %lu \n", clk_get_rate(dev->clks_inner));
 888         dev_dbg(&pdev->dev, "dev->clks_bclk_mst = %lu \n", clk_get_rate(dev->clks_bclk_mst));
 889         dev_dbg(&pdev->dev, "dev->clks_lrclk_mst = %lu \n", clk_get_rate(dev->clks_lrclk_mst));
 890         dev_dbg(&pdev->dev, "dev->clks_mclk = %lu \n", clk_get_rate(dev->clks_mclk));
 891         dev_dbg(&pdev->dev, "dev->clks_bclk = %lu \n", clk_get_rate(dev->clks_bclk));
 892         dev_dbg(&pdev->dev, "dev->clks_lrclk = %lu \n", clk_get_rate(dev->clks_lrclk));
 893         dev_dbg(&pdev->dev, "dev->clks_mclk_out = %lu \n", clk_get_rate(dev->clks_mclk_out));
 894         dev_dbg(&pdev->dev, "dev->clks_apb0 = %lu \n", clk_get_rate(dev->clks_apb0));
 895         dev_dbg(&pdev->dev, "dev->clks_4ch_apb = %lu \n", clk_get_rate(dev->clks_4ch_apb));
 896
 897         dev->rstc_ch1 = devm_reset_control_array_get_exclusive(&pdev->dev);
 898         if (IS_ERR(dev->rstc_ch1)) {
 899                 dev_err(&pdev->dev, "%s: failed to get rstc_ch1 reset control\n", __func__);
 900                 goto disable_rst;
 901         }
 902
 903         ret = reset_control_assert(dev->rstc_ch1);
 904         if (ret) {
 905                 dev_err(&pdev->dev, "%s: failed to reset control assert rstc_ch1\n", __func__);
 906                 goto disable_rst;
 907         }
 908
 909         ret = reset_control_deassert(dev->rstc_ch1);
 910         if (ret) {
 911                 dev_err(&pdev->dev, "%s: failed to reset control deassert rstc_ch1\n", __func__);
 912                 goto disable_rst;
 913         }
 914
 915         return 0;
 916
 917 disable_rst:
 918         clk_disable_unprepare(dev->clks_4ch_apb);
 919 disable_4ch_apb:
 920         clk_disable_unprepare(dev->clks_mclk_out);
 921 disable_mst_bclk:
 922         clk_disable_unprepare(dev->clks_bclk_mst);
 923 disable_audioroot_clk:
 924
 925         return ret;
 926 }
 927
 928 /*
 929  * The following tables allow a direct lookup of various parameters
 930  * defined in the I2S block's configuration in terms of sound system
 931  * parameters.  Each table is sized to the number of entries possible
 932  * according to the number of configuration bits describing an I2S
 933  * block parameter.
 934  */
 935
 936 /* Maximum bit resolution of a channel - not uniformly spaced */
 937 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
 938         12, 16, 20, 24, 32, 0, 0, 0
 939 };
 940
 941 /* Width of (DMA) bus */
 942 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
 943         DMA_SLAVE_BUSWIDTH_1_BYTE,
 944         DMA_SLAVE_BUSWIDTH_2_BYTES,
 945         DMA_SLAVE_BUSWIDTH_4_BYTES,
 946         DMA_SLAVE_BUSWIDTH_UNDEFINED
 947 };
 948
 949 /* PCM format to support channel resolution */
 950 static const u32 formats[COMP_MAX_WORDSIZE] = {
 951         SNDRV_PCM_FMTBIT_S16_LE,
 952         SNDRV_PCM_FMTBIT_S16_LE,
 953         SNDRV_PCM_FMTBIT_S24_LE,
 954         SNDRV_PCM_FMTBIT_S24_LE,
 955         SNDRV_PCM_FMTBIT_S32_LE,
 956         0,
 957         0,
 958         0
 959 };
 960
 961 static int dw_configure_dai(struct dw_i2s_dev *dev,
 962                                    struct snd_soc_dai_driver *dw_i2s_dai,
 963                                    unsigned int rates)
 964 {
 965         /*
 966          * Read component parameter registers to extract
 967          * the I2S block's configuration.
 968          */
 969         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
 970         u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
 971         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 972         u32 idx;
 973
 974         if (dev->capability & DWC_I2S_RECORD &&
 975                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
 976                 comp1 = comp1 & ~BIT(5);
 977
 978         if (dev->capability & DWC_I2S_PLAY &&
 979                         dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
 980                 comp1 = comp1 & ~BIT(6);
 981
 982         if (COMP1_TX_ENABLED(comp1)) {
 983                 dev_err(dev->dev, " designware: play supported\n");
 984                 idx = COMP1_TX_WORDSIZE_0(comp1);
 985                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 986                         return -EINVAL;
 987                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
 988                         idx = 1;
 989                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
 990                 dw_i2s_dai->playback.channels_max =
 991                                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
 992                 dw_i2s_dai->playback.formats = formats[idx];
 993                 for (;idx > 0; idx--)
 994                         dw_i2s_dai->playback.formats |= formats[idx - 1];
 995
 996                 dw_i2s_dai->playback.rates = rates;
 997         }
 998
 999         if (COMP1_RX_ENABLED(comp1)) {
1000                 dev_err(dev->dev, "designware: record supported\n");
1001                 idx = COMP2_RX_WORDSIZE_0(comp2);
1002                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
1003                         return -EINVAL;
1004                 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
1005                         idx = 1;
1006                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
1007                 dw_i2s_dai->capture.channels_max =
1008                                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
1009                 dw_i2s_dai->capture.formats = formats[idx];
1010                 for (;idx > 0; idx--)
1011                         dw_i2s_dai->capture.formats |= formats[idx - 1];
1012
1013                 dw_i2s_dai->capture.rates = rates;
1014         }
1015
1016         if (COMP1_MODE_EN(comp1)) {
1017                 dev_err(dev->dev, "designware: i2s master mode supported\n");
1018                 dev->capability |= DW_I2S_MASTER;
1019         } else {
1020                 dev_err(dev->dev, "designware: i2s slave mode supported\n");
1021                 dev->capability |= DW_I2S_SLAVE;
1022         }
1023
1024         dev->fifo_th = fifo_depth / 2;
1025         return 0;
1026 }
1027
1028 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
1029                                    struct snd_soc_dai_driver *dw_i2s_dai,
1030                                    struct resource *res,
1031                                    const struct i2s_platform_data *pdata)
1032 {
1033         u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
1034         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
1035         int ret;
1036
1037         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
1038                 return -EINVAL;
1039
1040         ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
1041         if (ret < 0)
1042                 return ret;
1043
1044         if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
1045                 idx = 1;
1046         /* Set DMA slaves info */
1047         dev->play_dma_data.pd.data = pdata->play_dma_data;
1048         dev->capture_dma_data.pd.data = pdata->capture_dma_data;
1049         dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
1050         dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
1051         dev->play_dma_data.pd.max_burst = 16;
1052         dev->capture_dma_data.pd.max_burst = 16;
1053         dev->play_dma_data.pd.addr_width = bus_widths[idx];
1054         dev->capture_dma_data.pd.addr_width = bus_widths[idx];
1055         dev->play_dma_data.pd.filter = pdata->filter;
1056         dev->capture_dma_data.pd.filter = pdata->filter;
1057
1058         return 0;
1059 }
1060
1061 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
1062                                    struct snd_soc_dai_driver *dw_i2s_dai,
1063                                    struct resource *res)
1064 {
1065         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
1066         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
1067         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
1068         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
1069         u32 idx2;
1070         int ret;
1071
1072         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
1073                 return -EINVAL;
1074
1075         ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
1076         if (ret < 0)
1077                 return ret;
1078
1079         if (COMP1_TX_ENABLED(comp1)) {
1080                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
1081
1082                 dev->capability |= DWC_I2S_PLAY;
1083                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
1084                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
1085                 dev->play_dma_data.dt.fifo_size = fifo_depth *
1086                         (fifo_width[idx2]) >> 8;
1087                 dev->play_dma_data.dt.maxburst = 16;
1088         }
1089         if (COMP1_RX_ENABLED(comp1)) {
1090                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
1091
1092                 dev->capability |= DWC_I2S_RECORD;
1093                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
1094                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
1095                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
1096                         (fifo_width[idx2] >> 8);
1097                 dev->capture_dma_data.dt.maxburst = 16;
1098         }
1099
1100         return 0;
1101
1102 }
1103
1104 #ifdef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
1105 static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
1106 {
1107         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
1108
1109         snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
1110         return 0;
1111 }
1112 #endif
1113
1114 static int dw_i2s_probe(struct platform_device *pdev)
1115 {
1116         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
1117         struct device_node *np = pdev->dev.of_node;
1118         struct of_phandle_args args;
1119         struct dw_i2s_dev *dev;
1120         struct resource *res;
1121         int ret, irq;
1122         struct snd_soc_dai_driver *dw_i2s_dai;
1123         const char *clk_id;
1124
1125         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1126         if (!dev)
1127                 return -ENOMEM;
1128
1129         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
1130         if (!dw_i2s_dai)
1131                 return -ENOMEM;
1132
1133         dw_i2s_dai->ops = &dw_i2s_dai_ops;
1134 #ifdef CONFIG_SND_DESIGNWARE_I2S_STARFIVE_JH7110
1135         dw_i2s_dai->probe = dw_i2s_dai_probe;
1136 #endif
1137
1138         dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1139         if (IS_ERR(dev->i2s_base))
1140                 return PTR_ERR(dev->i2s_base);
1141
1142         dev->clk_base = ioremap(CLOCK_BASE, 0x300);
1143     if (IS_ERR(dev->clk_base)) {
1144         printk(KERN_INFO "%s: failed to alloc memory for clk_base\n", __func__);
1145         return PTR_ERR(dev->clk_base);
1146     }
1147
1148         dev->dev = &pdev->dev;
1149
1150         irq = platform_get_irq_optional(pdev, 0);
1151         if (irq >= 0) {
1152                 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
1153                                 pdev->name, dev);
1154                 if (ret < 0) {
1155                         dev_err(&pdev->dev, "failed to request irq\n");
1156                         return ret;
1157                 }
1158         }
1159
1160         if (of_device_is_compatible(np, "starfive,jh7110-i2srx")) { //record
1161                 ret = of_parse_phandle_with_fixed_args(dev->dev->of_node,
1162                                                         "starfive,sys-syscon", 2, 0, &args);
1163                 if (ret) {
1164                         dev_err(dev->dev, "Failed to parse starfive,sys-syscon\n");
1165                         return -EINVAL;
1166                 }
1167                 dev->syscon_base = syscon_node_to_regmap(args.np);
1168                 of_node_put(args.np);
1169                 if (IS_ERR(dev->syscon_base))
1170                         return PTR_ERR(dev->syscon_base);
1171
1172                 dev->syscon_offset_18 = args.args[0];
1173                 dev->syscon_offset_34 = args.args[1];
1174                 ret = dw_i2srx_clk_init(pdev, dev);
1175                 if (ret < 0)
1176                         goto err_clk_disable;
1177         } else if (of_device_is_compatible(np, "snps,designware-i2stx-4ch0")) {   //playback
1178                 ret = dw_i2stx_4ch0_clk_init(pdev, dev);
1179                 if (ret < 0)
1180                         goto err_clk_disable;
1181         } else if (of_device_is_compatible(np, "starfive,jh7110-i2stx-4ch1")) {   //playback
1182                 ret = dw_i2stx_4ch1_clk_init(pdev, dev);
1183                 if (ret < 0)
1184                         goto err_clk_disable;
1185         }
1186
1187         dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
1188         dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
1189         if (pdata) {
1190                 dev->capability = pdata->cap;
1191                 clk_id = NULL;
1192                 dev->quirks = pdata->quirks;
1193                 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
1194                         dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
1195                         dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
1196                 }
1197                 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
1198         } else {
1199                 clk_id = "bclk_mst";
1200                 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
1201         }
1202         if (ret < 0)
1203                 return ret;
1204
1205         if (dev->capability & DW_I2S_MASTER) {
1206                 if (pdata) {
1207                         dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
1208                         if (!dev->i2s_clk_cfg) {
1209                                 dev_err(&pdev->dev, "no clock configure method\n");
1210                                 return -ENODEV;
1211                         }
1212                 }
1213                 dev->clk = devm_clk_get(&pdev->dev, clk_id);
1214
1215                 if (IS_ERR(dev->clk))
1216                         return PTR_ERR(dev->clk);
1217
1218                 ret = clk_prepare_enable(dev->clk);
1219                 if (ret < 0)
1220                         return ret;
1221         }
1222
1223         dev_set_drvdata(&pdev->dev, dev);
1224         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
1225                                          dw_i2s_dai, 1);
1226         if (ret != 0) {
1227                 dev_err(&pdev->dev, "not able to register dai\n");
1228                 goto err_clk_disable;
1229         }
1230
1231         if (!pdata) {
1232                 if (irq >= 0) {
1233                         ret = dw_pcm_register(pdev);
1234                         dev->use_pio = true;
1235                 } else {
1236                         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
1237                                         0);
1238                         dev->use_pio = false;
1239                 }
1240
1241                 if (ret) {
1242                         dev_err(&pdev->dev, "could not register pcm: %d\n",
1243                                         ret);
1244                         goto err_clk_disable;
1245                 }
1246         }
1247
1248         pm_runtime_enable(&pdev->dev);
1249
1250 #ifdef CONFIG_PM
1251         clk_disable_unprepare(dev->clks_mclk_out);
1252         clk_disable_unprepare(dev->clks_bclk_mst);
1253         clk_disable_unprepare(dev->clks_4ch_apb);
1254 #endif
1255
1256         return 0;
1257
1258 err_clk_disable:
1259         if (dev->capability & DW_I2S_MASTER)
1260                 clk_disable_unprepare(dev->clk);
1261         else{
1262                 clk_disable_unprepare(dev->clks_mclk_out);
1263                 clk_disable_unprepare(dev->clks_bclk_mst);
1264                 clk_disable_unprepare(dev->clks_4ch_apb);
1265         }
1266
1267         return ret;
1268 }
1269
1270 static int dw_i2s_remove(struct platform_device *pdev)
1271 {
1272         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
1273
1274         if (dev->capability & DW_I2S_MASTER)
1275                 clk_disable_unprepare(dev->clk);
1276
1277         pm_runtime_disable(&pdev->dev);
1278         return 0;
1279 }
1280
1281 #ifdef CONFIG_OF
1282 static const struct of_device_id dw_i2s_of_match[] = {
1283         { .compatible = "starfive,jh7110-i2stx-4ch1",    },
1284         { .compatible = "starfive,jh7110-i2srx",         },
1285         { .compatible = "snps,designware-i2stx-4ch0",    },
1286         {},
1287 };
1288
1289 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
1290 #endif
1291
1292 static const struct dev_pm_ops dwc_pm_ops = {
1293         SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
1294 };
1295
1296 static struct platform_driver dw_i2s_driver = {
1297         .probe          = dw_i2s_probe,
1298         .remove         = dw_i2s_remove,
1299         .driver         = {
1300                 .name   = "designware-i2s",
1301                 .of_match_table = of_match_ptr(dw_i2s_of_match),
1302                 .pm = &dwc_pm_ops,
1303         },
1304 };
1305
1306 static int __init dwci2s_driver_init(void)
1307 {
1308         return platform_driver_register(&dw_i2s_driver);
1309 }
1310
1311 static void dwci2s_driver_exit(void)
1312 {
1313         platform_driver_unregister(&dw_i2s_driver);
1314 }
1315
1316 late_initcall(dwci2s_driver_init);
1317 module_exit(dwci2s_driver_exit);
1318
1319
1320 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
1321 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
1322 MODULE_LICENSE("GPL");
1323 MODULE_ALIAS("platform:designware_i2s");