2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
38 struct davinci_audio_dev {
39 struct davinci_pcm_dma_params dma_params[2];
43 /* McASP specific data */
51 /* McASP FIFO related */
55 #ifdef CONFIG_PM_SLEEP
68 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
70 __raw_writel(__raw_readl(reg) | val, reg);
73 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
75 __raw_writel((__raw_readl(reg) & ~(val)), reg);
78 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
80 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
83 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
85 __raw_writel(val, reg);
88 static inline u32 mcasp_get_reg(void __iomem *reg)
90 return (unsigned int)__raw_readl(reg);
93 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
97 mcasp_set_bits(regs, val);
99 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
100 /* loop count is to avoid the lock-up */
101 for (i = 0; i < 1000; i++) {
102 if ((mcasp_get_reg(regs) & val) == val)
106 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
107 printk(KERN_ERR "GBLCTL write error\n");
110 static void mcasp_start_rx(struct davinci_audio_dev *dev)
112 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
113 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
114 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
115 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
117 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
118 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
119 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
121 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
122 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
125 static void mcasp_start_tx(struct davinci_audio_dev *dev)
130 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
131 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
132 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
133 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
135 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
136 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
137 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
138 for (i = 0; i < dev->num_serializer; i++) {
139 if (dev->serial_dir[i] == TX_MODE) {
145 /* wait for TX ready */
147 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
148 TXSTATE) && (cnt < 100000))
151 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
154 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
156 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
157 if (dev->txnumevt) { /* enable FIFO */
158 switch (dev->version) {
159 case MCASP_VERSION_3:
160 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
162 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
166 mcasp_clr_bits(dev->base +
167 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
168 mcasp_set_bits(dev->base +
169 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
174 if (dev->rxnumevt) { /* enable FIFO */
175 switch (dev->version) {
176 case MCASP_VERSION_3:
177 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
179 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
183 mcasp_clr_bits(dev->base +
184 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
185 mcasp_set_bits(dev->base +
186 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
193 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
195 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
196 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
199 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
201 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
202 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
205 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
207 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
208 if (dev->txnumevt) { /* disable FIFO */
209 switch (dev->version) {
210 case MCASP_VERSION_3:
211 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
215 mcasp_clr_bits(dev->base +
216 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
221 if (dev->rxnumevt) { /* disable FIFO */
222 switch (dev->version) {
223 case MCASP_VERSION_3:
224 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
229 mcasp_clr_bits(dev->base +
230 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
237 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
240 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
241 void __iomem *base = dev->base;
243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
244 case SND_SOC_DAIFMT_DSP_B:
245 case SND_SOC_DAIFMT_AC97:
246 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
247 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
250 /* configure a full-word SYNC pulse (LRCLK) */
251 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
252 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
254 /* make 1st data bit occur one ACLK cycle after the frame sync */
255 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
256 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
260 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
261 case SND_SOC_DAIFMT_CBS_CFS:
262 /* codec is clock and frame slave */
263 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
264 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
266 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
267 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
269 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
271 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
274 case SND_SOC_DAIFMT_CBM_CFS:
275 /* codec is clock master and frame slave */
276 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
277 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
279 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
280 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
282 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
284 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
287 case SND_SOC_DAIFMT_CBM_CFM:
288 /* codec is clock and frame master */
289 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
290 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
292 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
293 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
295 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
296 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
303 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
304 case SND_SOC_DAIFMT_IB_NF:
305 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
306 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
308 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
309 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
312 case SND_SOC_DAIFMT_NB_IF:
313 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
314 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
316 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
317 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
320 case SND_SOC_DAIFMT_IB_IF:
321 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
322 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
324 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
325 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
328 case SND_SOC_DAIFMT_NB_NF:
329 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
330 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
332 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
333 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
343 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
345 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
348 case 0: /* MCLK divider */
349 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
350 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
351 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
352 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
355 case 1: /* BCLK divider */
356 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
357 ACLKXDIV(div - 1), ACLKXDIV_MASK);
358 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
359 ACLKRDIV(div - 1), ACLKRDIV_MASK);
362 case 2: /* BCLK/LRCLK ratio */
363 dev->bclk_lrclk_ratio = div;
373 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
374 unsigned int freq, int dir)
376 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
378 if (dir == SND_SOC_CLOCK_OUT) {
379 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
380 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
381 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
383 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
384 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
385 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
391 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
395 u32 tx_rotate = (word_length / 4) & 0x7;
396 u32 rx_rotate = (32 - word_length) / 4;
397 u32 mask = (1ULL << word_length) - 1;
400 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
401 * callback, take it into account here. That allows us to for example
402 * send 32 bits per channel to the codec, while only 16 of them carry
404 * The clock ratio is given for a full period of data (for I2S format
405 * both left and right channels), so it has to be divided by number of
406 * tdm-slots (for I2S - divided by 2).
408 if (dev->bclk_lrclk_ratio)
409 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
411 /* mapping of the XSSZ bit-field as described in the datasheet */
412 fmt = (word_length >> 1) - 1;
414 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
415 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
416 RXSSZ(fmt), RXSSZ(0x0F));
417 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
418 TXSSZ(fmt), TXSSZ(0x0F));
419 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
420 TXROT(tx_rotate), TXROT(7));
421 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
422 RXROT(rx_rotate), RXROT(7));
423 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
427 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
432 static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
439 u8 slots = dev->tdm_slots;
440 u8 max_active_serializers = (channels + slots - 1) / slots;
441 /* Default configuration */
442 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
444 /* All PINS as McASP */
445 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
447 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
448 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
449 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
452 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
453 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
457 for (i = 0; i < dev->num_serializer; i++) {
458 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
460 if (dev->serial_dir[i] == TX_MODE &&
461 tx_ser < max_active_serializers) {
462 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
465 } else if (dev->serial_dir[i] == RX_MODE &&
466 rx_ser < max_active_serializers) {
467 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
471 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
472 SRMOD_INACTIVE, SRMOD_MASK);
476 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
481 if (ser < max_active_serializers) {
482 dev_warn(dev->dev, "stream has more channels (%d) than are "
483 "enabled in mcasp (%d)\n", channels, ser * slots);
487 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
488 if (dev->txnumevt * tx_ser > 64)
491 switch (dev->version) {
492 case MCASP_VERSION_3:
493 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
495 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
496 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
499 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
500 tx_ser, NUMDMA_MASK);
501 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
502 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
506 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
507 if (dev->rxnumevt * rx_ser > 64)
509 switch (dev->version) {
510 case MCASP_VERSION_3:
511 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
513 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
514 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
517 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
518 rx_ser, NUMDMA_MASK);
519 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
520 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
527 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
532 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
533 for (i = 0; i < active_slots; i++)
536 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
538 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
539 /* bit stream is MSB first with no delay */
541 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
542 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
544 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
545 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
546 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
548 printk(KERN_ERR "playback tdm slot %d not supported\n",
551 /* bit stream is MSB first with no delay */
553 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
554 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
556 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
557 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
558 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
560 printk(KERN_ERR "capture tdm slot %d not supported\n",
566 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
568 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
570 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
571 TXROT(6) | TXSSZ(15));
573 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
574 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
575 AFSXE | FSXMOD(0x180));
577 /* Set the TX tdm : for all the slots */
578 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
580 /* Set the TX clock controls : div = 1 and internal */
581 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
584 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
586 /* Only 44100 and 48000 are valid, both have the same setting */
587 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
590 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
593 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *cpu_dai)
597 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
598 struct davinci_pcm_dma_params *dma_params =
599 &dev->dma_params[substream->stream];
602 u8 slots = dev->tdm_slots;
603 u8 active_serializers;
605 struct snd_interval *pcm_channels = hw_param_interval(params,
606 SNDRV_PCM_HW_PARAM_CHANNELS);
607 channels = pcm_channels->min;
609 active_serializers = (channels + slots - 1) / slots;
611 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
613 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
614 fifo_level = dev->txnumevt * active_serializers;
616 fifo_level = dev->rxnumevt * active_serializers;
618 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
619 davinci_hw_dit_param(dev);
621 davinci_hw_param(dev, substream->stream);
623 switch (params_format(params)) {
624 case SNDRV_PCM_FORMAT_U8:
625 case SNDRV_PCM_FORMAT_S8:
626 dma_params->data_type = 1;
630 case SNDRV_PCM_FORMAT_U16_LE:
631 case SNDRV_PCM_FORMAT_S16_LE:
632 dma_params->data_type = 2;
636 case SNDRV_PCM_FORMAT_U24_3LE:
637 case SNDRV_PCM_FORMAT_S24_3LE:
638 dma_params->data_type = 3;
642 case SNDRV_PCM_FORMAT_U24_LE:
643 case SNDRV_PCM_FORMAT_S24_LE:
644 case SNDRV_PCM_FORMAT_U32_LE:
645 case SNDRV_PCM_FORMAT_S32_LE:
646 dma_params->data_type = 4;
651 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
655 if (dev->version == MCASP_VERSION_2 && !fifo_level)
656 dma_params->acnt = 4;
658 dma_params->acnt = dma_params->data_type;
660 dma_params->fifo_level = fifo_level;
661 davinci_config_channel_size(dev, word_length);
666 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
667 int cmd, struct snd_soc_dai *cpu_dai)
669 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
673 case SNDRV_PCM_TRIGGER_RESUME:
674 case SNDRV_PCM_TRIGGER_START:
675 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
676 ret = pm_runtime_get_sync(dev->dev);
677 if (IS_ERR_VALUE(ret))
678 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
679 davinci_mcasp_start(dev, substream->stream);
682 case SNDRV_PCM_TRIGGER_SUSPEND:
683 davinci_mcasp_stop(dev, substream->stream);
684 ret = pm_runtime_put_sync(dev->dev);
685 if (IS_ERR_VALUE(ret))
686 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
689 case SNDRV_PCM_TRIGGER_STOP:
690 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
691 davinci_mcasp_stop(dev, substream->stream);
701 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
702 struct snd_soc_dai *dai)
704 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
706 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
710 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
711 .startup = davinci_mcasp_startup,
712 .trigger = davinci_mcasp_trigger,
713 .hw_params = davinci_mcasp_hw_params,
714 .set_fmt = davinci_mcasp_set_dai_fmt,
715 .set_clkdiv = davinci_mcasp_set_clkdiv,
716 .set_sysclk = davinci_mcasp_set_sysclk,
719 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
721 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
722 SNDRV_PCM_FMTBIT_U8 | \
723 SNDRV_PCM_FMTBIT_S16_LE | \
724 SNDRV_PCM_FMTBIT_U16_LE | \
725 SNDRV_PCM_FMTBIT_S24_LE | \
726 SNDRV_PCM_FMTBIT_U24_LE | \
727 SNDRV_PCM_FMTBIT_S24_3LE | \
728 SNDRV_PCM_FMTBIT_U24_3LE | \
729 SNDRV_PCM_FMTBIT_S32_LE | \
730 SNDRV_PCM_FMTBIT_U32_LE)
732 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
734 .name = "davinci-mcasp.0",
737 .channels_max = 32 * 16,
738 .rates = DAVINCI_MCASP_RATES,
739 .formats = DAVINCI_MCASP_PCM_FMTS,
743 .channels_max = 32 * 16,
744 .rates = DAVINCI_MCASP_RATES,
745 .formats = DAVINCI_MCASP_PCM_FMTS,
747 .ops = &davinci_mcasp_dai_ops,
751 .name = "davinci-mcasp.1",
755 .rates = DAVINCI_MCASP_RATES,
756 .formats = DAVINCI_MCASP_PCM_FMTS,
758 .ops = &davinci_mcasp_dai_ops,
763 static const struct snd_soc_component_driver davinci_mcasp_component = {
764 .name = "davinci-mcasp",
767 /* Some HW specific values and defaults. The rest is filled in from DT. */
768 static struct snd_platform_data dm646x_mcasp_pdata = {
769 .tx_dma_offset = 0x400,
770 .rx_dma_offset = 0x400,
771 .asp_chan_q = EVENTQ_0,
772 .version = MCASP_VERSION_1,
775 static struct snd_platform_data da830_mcasp_pdata = {
776 .tx_dma_offset = 0x2000,
777 .rx_dma_offset = 0x2000,
778 .asp_chan_q = EVENTQ_0,
779 .version = MCASP_VERSION_2,
782 static struct snd_platform_data omap2_mcasp_pdata = {
785 .asp_chan_q = EVENTQ_0,
786 .version = MCASP_VERSION_3,
789 static const struct of_device_id mcasp_dt_ids[] = {
791 .compatible = "ti,dm646x-mcasp-audio",
792 .data = &dm646x_mcasp_pdata,
795 .compatible = "ti,da830-mcasp-audio",
796 .data = &da830_mcasp_pdata,
799 .compatible = "ti,am33xx-mcasp-audio",
800 .data = &omap2_mcasp_pdata,
804 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
806 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
807 struct platform_device *pdev)
809 struct device_node *np = pdev->dev.of_node;
810 struct snd_platform_data *pdata = NULL;
811 const struct of_device_id *match =
812 of_match_device(mcasp_dt_ids, &pdev->dev);
813 struct of_phandle_args dma_spec;
815 const u32 *of_serial_dir32;
819 if (pdev->dev.platform_data) {
820 pdata = pdev->dev.platform_data;
823 pdata = (struct snd_platform_data *) match->data;
825 /* control shouldn't reach here. something is wrong */
830 ret = of_property_read_u32(np, "op-mode", &val);
832 pdata->op_mode = val;
834 ret = of_property_read_u32(np, "tdm-slots", &val);
836 if (val < 2 || val > 32) {
838 "tdm-slots must be in rage [2-32]\n");
843 pdata->tdm_slots = val;
846 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
848 if (of_serial_dir32) {
849 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
850 (sizeof(*of_serial_dir) * val),
852 if (!of_serial_dir) {
857 for (i = 0; i < val; i++)
858 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
860 pdata->num_serializer = val;
861 pdata->serial_dir = of_serial_dir;
864 ret = of_property_match_string(np, "dma-names", "tx");
868 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
873 pdata->tx_dma_channel = dma_spec.args[0];
875 ret = of_property_match_string(np, "dma-names", "rx");
879 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
884 pdata->rx_dma_channel = dma_spec.args[0];
886 ret = of_property_read_u32(np, "tx-num-evt", &val);
888 pdata->txnumevt = val;
890 ret = of_property_read_u32(np, "rx-num-evt", &val);
892 pdata->rxnumevt = val;
894 ret = of_property_read_u32(np, "sram-size-playback", &val);
896 pdata->sram_size_playback = val;
898 ret = of_property_read_u32(np, "sram-size-capture", &val);
900 pdata->sram_size_capture = val;
906 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
913 static int davinci_mcasp_probe(struct platform_device *pdev)
915 struct davinci_pcm_dma_params *dma_data;
916 struct resource *mem, *ioarea, *res, *dat;
917 struct snd_platform_data *pdata;
918 struct davinci_audio_dev *dev;
921 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
922 dev_err(&pdev->dev, "No platform data supplied\n");
926 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
931 pdata = davinci_mcasp_set_pdata_from_of(pdev);
933 dev_err(&pdev->dev, "no platform data\n");
937 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
940 "\"mpu\" mem resource not found, using index 0\n");
941 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
943 dev_err(&pdev->dev, "no mem resource?\n");
948 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
949 resource_size(mem), pdev->name);
951 dev_err(&pdev->dev, "Audio region already claimed\n");
955 pm_runtime_enable(&pdev->dev);
957 ret = pm_runtime_get_sync(&pdev->dev);
958 if (IS_ERR_VALUE(ret)) {
959 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
963 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
965 dev_err(&pdev->dev, "ioremap failed\n");
967 goto err_release_clk;
970 dev->op_mode = pdata->op_mode;
971 dev->tdm_slots = pdata->tdm_slots;
972 dev->num_serializer = pdata->num_serializer;
973 dev->serial_dir = pdata->serial_dir;
974 dev->version = pdata->version;
975 dev->txnumevt = pdata->txnumevt;
976 dev->rxnumevt = pdata->rxnumevt;
977 dev->dev = &pdev->dev;
979 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
983 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
984 dma_data->asp_chan_q = pdata->asp_chan_q;
985 dma_data->ram_chan_q = pdata->ram_chan_q;
986 dma_data->sram_pool = pdata->sram_pool;
987 dma_data->sram_size = pdata->sram_size_playback;
988 dma_data->dma_addr = dat->start + pdata->tx_dma_offset;
990 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
992 dma_data->channel = res->start;
994 dma_data->channel = pdata->tx_dma_channel;
996 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
997 dma_data->asp_chan_q = pdata->asp_chan_q;
998 dma_data->ram_chan_q = pdata->ram_chan_q;
999 dma_data->sram_pool = pdata->sram_pool;
1000 dma_data->sram_size = pdata->sram_size_capture;
1001 dma_data->dma_addr = dat->start + pdata->rx_dma_offset;
1003 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1005 dma_data->channel = res->start;
1007 dma_data->channel = pdata->rx_dma_channel;
1009 dev_set_drvdata(&pdev->dev, dev);
1010 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1011 &davinci_mcasp_dai[pdata->op_mode], 1);
1014 goto err_release_clk;
1016 ret = davinci_soc_platform_register(&pdev->dev);
1018 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1019 goto err_unregister_component;
1024 err_unregister_component:
1025 snd_soc_unregister_component(&pdev->dev);
1027 pm_runtime_put_sync(&pdev->dev);
1028 pm_runtime_disable(&pdev->dev);
1032 static int davinci_mcasp_remove(struct platform_device *pdev)
1035 snd_soc_unregister_component(&pdev->dev);
1036 davinci_soc_platform_unregister(&pdev->dev);
1038 pm_runtime_put_sync(&pdev->dev);
1039 pm_runtime_disable(&pdev->dev);
1044 #ifdef CONFIG_PM_SLEEP
1045 static int davinci_mcasp_suspend(struct device *dev)
1047 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1048 void __iomem *base = a->base;
1050 a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
1051 a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
1052 a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
1053 a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
1054 a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
1055 a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
1056 a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
1061 static int davinci_mcasp_resume(struct device *dev)
1063 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1064 void __iomem *base = a->base;
1066 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl);
1067 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl);
1068 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt);
1069 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt);
1070 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl);
1071 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl);
1072 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir);
1078 SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1079 davinci_mcasp_suspend,
1080 davinci_mcasp_resume);
1082 static struct platform_driver davinci_mcasp_driver = {
1083 .probe = davinci_mcasp_probe,
1084 .remove = davinci_mcasp_remove,
1086 .name = "davinci-mcasp",
1087 .owner = THIS_MODULE,
1088 .pm = &davinci_mcasp_pm_ops,
1089 .of_match_table = mcasp_dt_ids,
1093 module_platform_driver(davinci_mcasp_driver);
1095 MODULE_AUTHOR("Steve Chen");
1096 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1097 MODULE_LICENSE("GPL");