2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
38 #define DAVINCI_MCASP_NUM_SERIALIZER 16
40 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
42 __raw_writel(__raw_readl(reg) | val, reg);
45 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
47 __raw_writel((__raw_readl(reg) & ~(val)), reg);
50 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
52 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
55 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
57 __raw_writel(val, reg);
60 static inline u32 mcasp_get_reg(void __iomem *reg)
62 return (unsigned int)__raw_readl(reg);
65 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
69 mcasp_set_bits(regs, val);
71 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
72 /* loop count is to avoid the lock-up */
73 for (i = 0; i < 1000; i++) {
74 if ((mcasp_get_reg(regs) & val) == val)
78 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
79 printk(KERN_ERR "GBLCTL write error\n");
82 static void mcasp_start_rx(struct davinci_audio_dev *dev)
84 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
85 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
86 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
87 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
89 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
90 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
91 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
93 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
94 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
97 static void mcasp_start_tx(struct davinci_audio_dev *dev)
102 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
103 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
104 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
105 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
107 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
108 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
109 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
110 for (i = 0; i < dev->num_serializer; i++) {
111 if (dev->serial_dir[i] == TX_MODE) {
117 /* wait for TX ready */
119 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
120 TXSTATE) && (cnt < 100000))
123 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
126 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
128 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
129 if (dev->txnumevt) { /* enable FIFO */
130 switch (dev->version) {
131 case MCASP_VERSION_3:
132 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
134 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
138 mcasp_clr_bits(dev->base +
139 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
140 mcasp_set_bits(dev->base +
141 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
146 if (dev->rxnumevt) { /* enable FIFO */
147 switch (dev->version) {
148 case MCASP_VERSION_3:
149 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
151 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
155 mcasp_clr_bits(dev->base +
156 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
157 mcasp_set_bits(dev->base +
158 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
165 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
167 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
168 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
171 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
173 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
174 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
177 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
179 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
180 if (dev->txnumevt) { /* disable FIFO */
181 switch (dev->version) {
182 case MCASP_VERSION_3:
183 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
187 mcasp_clr_bits(dev->base +
188 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
193 if (dev->rxnumevt) { /* disable FIFO */
194 switch (dev->version) {
195 case MCASP_VERSION_3:
196 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
201 mcasp_clr_bits(dev->base +
202 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
209 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
212 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
213 void __iomem *base = dev->base;
215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
216 case SND_SOC_DAIFMT_DSP_B:
217 case SND_SOC_DAIFMT_AC97:
218 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
219 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
222 /* configure a full-word SYNC pulse (LRCLK) */
223 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
224 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
226 /* make 1st data bit occur one ACLK cycle after the frame sync */
227 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
228 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
232 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
233 case SND_SOC_DAIFMT_CBS_CFS:
234 /* codec is clock and frame slave */
235 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
236 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
238 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
239 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
241 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
243 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
246 case SND_SOC_DAIFMT_CBM_CFS:
247 /* codec is clock master and frame slave */
248 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
249 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
251 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
252 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
254 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
256 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
259 case SND_SOC_DAIFMT_CBM_CFM:
260 /* codec is clock and frame master */
261 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
262 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
264 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
265 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
267 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
268 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
275 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
276 case SND_SOC_DAIFMT_IB_NF:
277 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
278 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
280 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
281 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
284 case SND_SOC_DAIFMT_NB_IF:
285 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
286 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
288 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
289 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
292 case SND_SOC_DAIFMT_IB_IF:
293 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
294 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
296 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
297 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
300 case SND_SOC_DAIFMT_NB_NF:
301 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
302 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
304 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
305 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
315 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
317 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
320 case 0: /* MCLK divider */
321 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
322 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
323 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
324 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
327 case 1: /* BCLK divider */
328 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
329 ACLKXDIV(div - 1), ACLKXDIV_MASK);
330 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
331 ACLKRDIV(div - 1), ACLKRDIV_MASK);
334 case 2: /* BCLK/LRCLK ratio */
335 dev->bclk_lrclk_ratio = div;
345 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
346 unsigned int freq, int dir)
348 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
350 if (dir == SND_SOC_CLOCK_OUT) {
351 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
352 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
353 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
355 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
356 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
357 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
363 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
367 u32 tx_rotate = (word_length / 4) & 0x7;
368 u32 rx_rotate = (32 - word_length) / 4;
369 u32 mask = (1ULL << word_length) - 1;
372 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
373 * callback, take it into account here. That allows us to for example
374 * send 32 bits per channel to the codec, while only 16 of them carry
376 * The clock ratio is given for a full period of data (for I2S format
377 * both left and right channels), so it has to be divided by number of
378 * tdm-slots (for I2S - divided by 2).
380 if (dev->bclk_lrclk_ratio)
381 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
383 /* mapping of the XSSZ bit-field as described in the datasheet */
384 fmt = (word_length >> 1) - 1;
386 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
387 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
388 RXSSZ(fmt), RXSSZ(0x0F));
389 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
390 TXSSZ(fmt), TXSSZ(0x0F));
391 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
392 TXROT(tx_rotate), TXROT(7));
393 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
394 RXROT(rx_rotate), RXROT(7));
395 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
399 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
404 static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
411 u8 slots = dev->tdm_slots;
412 u8 max_active_serializers = (channels + slots - 1) / slots;
413 /* Default configuration */
414 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
416 /* All PINS as McASP */
417 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
419 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
420 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
421 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
424 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
425 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
429 for (i = 0; i < dev->num_serializer; i++) {
430 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
432 if (dev->serial_dir[i] == TX_MODE &&
433 tx_ser < max_active_serializers) {
434 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
437 } else if (dev->serial_dir[i] == RX_MODE &&
438 rx_ser < max_active_serializers) {
439 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
443 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
444 SRMOD_INACTIVE, SRMOD_MASK);
448 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
453 if (ser < max_active_serializers) {
454 dev_warn(dev->dev, "stream has more channels (%d) than are "
455 "enabled in mcasp (%d)\n", channels, ser * slots);
459 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
460 if (dev->txnumevt * tx_ser > 64)
463 switch (dev->version) {
464 case MCASP_VERSION_3:
465 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
467 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
468 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
471 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
472 tx_ser, NUMDMA_MASK);
473 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
474 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
478 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
479 if (dev->rxnumevt * rx_ser > 64)
481 switch (dev->version) {
482 case MCASP_VERSION_3:
483 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
485 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
486 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
489 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
490 rx_ser, NUMDMA_MASK);
491 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
492 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
499 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
504 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
505 for (i = 0; i < active_slots; i++)
508 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
510 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
511 /* bit stream is MSB first with no delay */
513 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
514 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
516 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
517 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
518 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
520 printk(KERN_ERR "playback tdm slot %d not supported\n",
523 /* bit stream is MSB first with no delay */
525 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
526 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
528 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
529 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
530 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
532 printk(KERN_ERR "capture tdm slot %d not supported\n",
538 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
540 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
542 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
543 TXROT(6) | TXSSZ(15));
545 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
546 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
547 AFSXE | FSXMOD(0x180));
549 /* Set the TX tdm : for all the slots */
550 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
552 /* Set the TX clock controls : div = 1 and internal */
553 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
556 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
558 /* Only 44100 and 48000 are valid, both have the same setting */
559 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
562 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
565 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
566 struct snd_pcm_hw_params *params,
567 struct snd_soc_dai *cpu_dai)
569 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
570 struct davinci_pcm_dma_params *dma_params =
571 &dev->dma_params[substream->stream];
574 u8 slots = dev->tdm_slots;
575 u8 active_serializers;
577 struct snd_interval *pcm_channels = hw_param_interval(params,
578 SNDRV_PCM_HW_PARAM_CHANNELS);
579 channels = pcm_channels->min;
581 active_serializers = (channels + slots - 1) / slots;
583 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
585 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
586 fifo_level = dev->txnumevt * active_serializers;
588 fifo_level = dev->rxnumevt * active_serializers;
590 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
591 davinci_hw_dit_param(dev);
593 davinci_hw_param(dev, substream->stream);
595 switch (params_format(params)) {
596 case SNDRV_PCM_FORMAT_U8:
597 case SNDRV_PCM_FORMAT_S8:
598 dma_params->data_type = 1;
602 case SNDRV_PCM_FORMAT_U16_LE:
603 case SNDRV_PCM_FORMAT_S16_LE:
604 dma_params->data_type = 2;
608 case SNDRV_PCM_FORMAT_U24_3LE:
609 case SNDRV_PCM_FORMAT_S24_3LE:
610 dma_params->data_type = 3;
614 case SNDRV_PCM_FORMAT_U24_LE:
615 case SNDRV_PCM_FORMAT_S24_LE:
616 case SNDRV_PCM_FORMAT_U32_LE:
617 case SNDRV_PCM_FORMAT_S32_LE:
618 dma_params->data_type = 4;
623 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
627 if (dev->version == MCASP_VERSION_2 && !fifo_level)
628 dma_params->acnt = 4;
630 dma_params->acnt = dma_params->data_type;
632 dma_params->fifo_level = fifo_level;
633 davinci_config_channel_size(dev, word_length);
638 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
639 int cmd, struct snd_soc_dai *cpu_dai)
641 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
645 case SNDRV_PCM_TRIGGER_RESUME:
646 case SNDRV_PCM_TRIGGER_START:
647 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
648 ret = pm_runtime_get_sync(dev->dev);
649 if (IS_ERR_VALUE(ret))
650 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
651 davinci_mcasp_start(dev, substream->stream);
654 case SNDRV_PCM_TRIGGER_SUSPEND:
655 davinci_mcasp_stop(dev, substream->stream);
656 ret = pm_runtime_put_sync(dev->dev);
657 if (IS_ERR_VALUE(ret))
658 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
661 case SNDRV_PCM_TRIGGER_STOP:
662 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
663 davinci_mcasp_stop(dev, substream->stream);
673 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
674 struct snd_soc_dai *dai)
676 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
678 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
682 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
683 .startup = davinci_mcasp_startup,
684 .trigger = davinci_mcasp_trigger,
685 .hw_params = davinci_mcasp_hw_params,
686 .set_fmt = davinci_mcasp_set_dai_fmt,
687 .set_clkdiv = davinci_mcasp_set_clkdiv,
688 .set_sysclk = davinci_mcasp_set_sysclk,
691 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
693 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
694 SNDRV_PCM_FMTBIT_U8 | \
695 SNDRV_PCM_FMTBIT_S16_LE | \
696 SNDRV_PCM_FMTBIT_U16_LE | \
697 SNDRV_PCM_FMTBIT_S24_LE | \
698 SNDRV_PCM_FMTBIT_U24_LE | \
699 SNDRV_PCM_FMTBIT_S24_3LE | \
700 SNDRV_PCM_FMTBIT_U24_3LE | \
701 SNDRV_PCM_FMTBIT_S32_LE | \
702 SNDRV_PCM_FMTBIT_U32_LE)
704 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
706 .name = "davinci-mcasp.0",
709 .channels_max = 32 * 16,
710 .rates = DAVINCI_MCASP_RATES,
711 .formats = DAVINCI_MCASP_PCM_FMTS,
715 .channels_max = 32 * 16,
716 .rates = DAVINCI_MCASP_RATES,
717 .formats = DAVINCI_MCASP_PCM_FMTS,
719 .ops = &davinci_mcasp_dai_ops,
723 .name = "davinci-mcasp.1",
727 .rates = DAVINCI_MCASP_RATES,
728 .formats = DAVINCI_MCASP_PCM_FMTS,
730 .ops = &davinci_mcasp_dai_ops,
735 static const struct snd_soc_component_driver davinci_mcasp_component = {
736 .name = "davinci-mcasp",
739 /* Some HW specific values and defaults. The rest is filled in from DT. */
740 static struct snd_platform_data dm646x_mcasp_pdata = {
741 .tx_dma_offset = 0x400,
742 .rx_dma_offset = 0x400,
743 .asp_chan_q = EVENTQ_0,
744 .version = MCASP_VERSION_1,
747 static struct snd_platform_data da830_mcasp_pdata = {
748 .tx_dma_offset = 0x2000,
749 .rx_dma_offset = 0x2000,
750 .asp_chan_q = EVENTQ_0,
751 .version = MCASP_VERSION_2,
754 static struct snd_platform_data omap2_mcasp_pdata = {
757 .asp_chan_q = EVENTQ_0,
758 .version = MCASP_VERSION_3,
761 static const struct of_device_id mcasp_dt_ids[] = {
763 .compatible = "ti,dm646x-mcasp-audio",
764 .data = &dm646x_mcasp_pdata,
767 .compatible = "ti,da830-mcasp-audio",
768 .data = &da830_mcasp_pdata,
771 .compatible = "ti,am33xx-mcasp-audio",
772 .data = &omap2_mcasp_pdata,
776 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
778 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
779 struct platform_device *pdev)
781 struct device_node *np = pdev->dev.of_node;
782 struct snd_platform_data *pdata = NULL;
783 const struct of_device_id *match =
784 of_match_device(mcasp_dt_ids, &pdev->dev);
785 struct of_phandle_args dma_spec;
787 const u32 *of_serial_dir32;
791 if (pdev->dev.platform_data) {
792 pdata = pdev->dev.platform_data;
795 pdata = (struct snd_platform_data *) match->data;
797 /* control shouldn't reach here. something is wrong */
802 ret = of_property_read_u32(np, "op-mode", &val);
804 pdata->op_mode = val;
806 ret = of_property_read_u32(np, "tdm-slots", &val);
808 if (val < 2 || val > 32) {
810 "tdm-slots must be in rage [2-32]\n");
815 pdata->tdm_slots = val;
818 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
820 if (of_serial_dir32) {
821 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
822 (sizeof(*of_serial_dir) * val),
824 if (!of_serial_dir) {
829 for (i = 0; i < val; i++)
830 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
832 pdata->num_serializer = val;
833 pdata->serial_dir = of_serial_dir;
836 ret = of_property_match_string(np, "dma-names", "tx");
840 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
845 pdata->tx_dma_channel = dma_spec.args[0];
847 ret = of_property_match_string(np, "dma-names", "rx");
851 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
856 pdata->rx_dma_channel = dma_spec.args[0];
858 ret = of_property_read_u32(np, "tx-num-evt", &val);
860 pdata->txnumevt = val;
862 ret = of_property_read_u32(np, "rx-num-evt", &val);
864 pdata->rxnumevt = val;
866 ret = of_property_read_u32(np, "sram-size-playback", &val);
868 pdata->sram_size_playback = val;
870 ret = of_property_read_u32(np, "sram-size-capture", &val);
872 pdata->sram_size_capture = val;
878 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
885 static int davinci_mcasp_probe(struct platform_device *pdev)
887 struct davinci_pcm_dma_params *dma_data;
888 struct resource *mem, *ioarea, *res, *dat;
889 struct snd_platform_data *pdata;
890 struct davinci_audio_dev *dev;
893 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
894 dev_err(&pdev->dev, "No platform data supplied\n");
898 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
903 pdata = davinci_mcasp_set_pdata_from_of(pdev);
905 dev_err(&pdev->dev, "no platform data\n");
909 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
912 "\"mpu\" mem resource not found, using index 0\n");
913 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
915 dev_err(&pdev->dev, "no mem resource?\n");
920 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
921 resource_size(mem), pdev->name);
923 dev_err(&pdev->dev, "Audio region already claimed\n");
927 pm_runtime_enable(&pdev->dev);
929 ret = pm_runtime_get_sync(&pdev->dev);
930 if (IS_ERR_VALUE(ret)) {
931 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
935 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
937 dev_err(&pdev->dev, "ioremap failed\n");
939 goto err_release_clk;
942 dev->op_mode = pdata->op_mode;
943 dev->tdm_slots = pdata->tdm_slots;
944 dev->num_serializer = pdata->num_serializer;
945 dev->serial_dir = pdata->serial_dir;
946 dev->version = pdata->version;
947 dev->txnumevt = pdata->txnumevt;
948 dev->rxnumevt = pdata->rxnumevt;
949 dev->dev = &pdev->dev;
951 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
955 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
956 dma_data->asp_chan_q = pdata->asp_chan_q;
957 dma_data->ram_chan_q = pdata->ram_chan_q;
958 dma_data->sram_pool = pdata->sram_pool;
959 dma_data->sram_size = pdata->sram_size_playback;
960 dma_data->dma_addr = dat->start + pdata->tx_dma_offset;
962 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
964 dma_data->channel = res->start;
966 dma_data->channel = pdata->tx_dma_channel;
968 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
969 dma_data->asp_chan_q = pdata->asp_chan_q;
970 dma_data->ram_chan_q = pdata->ram_chan_q;
971 dma_data->sram_pool = pdata->sram_pool;
972 dma_data->sram_size = pdata->sram_size_capture;
973 dma_data->dma_addr = dat->start + pdata->rx_dma_offset;
975 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
977 dma_data->channel = res->start;
979 dma_data->channel = pdata->rx_dma_channel;
981 dev_set_drvdata(&pdev->dev, dev);
982 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
983 &davinci_mcasp_dai[pdata->op_mode], 1);
986 goto err_release_clk;
988 ret = davinci_soc_platform_register(&pdev->dev);
990 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
991 goto err_unregister_component;
996 err_unregister_component:
997 snd_soc_unregister_component(&pdev->dev);
999 pm_runtime_put_sync(&pdev->dev);
1000 pm_runtime_disable(&pdev->dev);
1004 static int davinci_mcasp_remove(struct platform_device *pdev)
1007 snd_soc_unregister_component(&pdev->dev);
1008 davinci_soc_platform_unregister(&pdev->dev);
1010 pm_runtime_put_sync(&pdev->dev);
1011 pm_runtime_disable(&pdev->dev);
1016 #ifdef CONFIG_PM_SLEEP
1017 static int davinci_mcasp_suspend(struct device *dev)
1019 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1020 void __iomem *base = a->base;
1022 a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
1023 a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
1024 a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
1025 a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
1026 a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
1027 a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
1028 a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
1033 static int davinci_mcasp_resume(struct device *dev)
1035 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1036 void __iomem *base = a->base;
1038 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl);
1039 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl);
1040 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt);
1041 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt);
1042 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl);
1043 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl);
1044 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir);
1050 SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1051 davinci_mcasp_suspend,
1052 davinci_mcasp_resume);
1054 static struct platform_driver davinci_mcasp_driver = {
1055 .probe = davinci_mcasp_probe,
1056 .remove = davinci_mcasp_remove,
1058 .name = "davinci-mcasp",
1059 .owner = THIS_MODULE,
1060 .pm = &davinci_mcasp_pm_ops,
1061 .of_match_table = mcasp_dt_ids,
1065 module_platform_driver(davinci_mcasp_driver);
1067 MODULE_AUTHOR("Steve Chen");
1068 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1069 MODULE_LICENSE("GPL");