sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/slab.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29
  30 #include <linux/mfd/wm8994/core.h>
  31 #include <linux/mfd/wm8994/registers.h>
  32 #include <linux/mfd/wm8994/pdata.h>
  33 #include <linux/mfd/wm8994/gpio.h>
  34
  35 #include "wm8994.h"
  36 #include "wm_hubs.h"
  37
  38 struct fll_config {
  39         int src;
  40         int in;
  41         int out;
  42 };
  43
  44 #define WM8994_NUM_DRC 3
  45 #define WM8994_NUM_EQ  3
  46
  47 static int wm8994_drc_base[] = {
  48         WM8994_AIF1_DRC1_1,
  49         WM8994_AIF1_DRC2_1,
  50         WM8994_AIF2_DRC_1,
  51 };
  52
  53 static int wm8994_retune_mobile_base[] = {
  54         WM8994_AIF1_DAC1_EQ_GAINS_1,
  55         WM8994_AIF1_DAC2_EQ_GAINS_1,
  56         WM8994_AIF2_EQ_GAINS_1,
  57 };
  58
  59 #define WM8994_REG_CACHE_SIZE  0x621
  60
  61 struct wm8994_micdet {
  62         struct snd_soc_jack *jack;
  63         int det;
  64         int shrt;
  65 };
  66
  67 /* codec private data */
  68 struct wm8994_priv {
  69         struct wm_hubs_data hubs;
  70         enum snd_soc_control_type control_type;
  71         void *control_data;
  72         struct snd_soc_codec *codec;
  73         u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
  74         int sysclk[2];
  75         int sysclk_rate[2];
  76         int mclk[2];
  77         int aifclk[2];
  78         struct fll_config fll[2], fll_suspend[2];
  79
  80         int dac_rates[2];
  81         int lrclk_shared[2];
  82
  83         int mbc_ena[3];
  84
  85         /* Platform dependant DRC configuration */
  86         const char **drc_texts;
  87         int drc_cfg[WM8994_NUM_DRC];
  88         struct soc_enum drc_enum;
  89
  90         /* Platform dependant ReTune mobile configuration */
  91         int num_retune_mobile_texts;
  92         const char **retune_mobile_texts;
  93         int retune_mobile_cfg[WM8994_NUM_EQ];
  94         struct soc_enum retune_mobile_enum;
  95
  96         struct wm8994_micdet micdet[2];
  97
  98         int revision;
  99         struct wm8994_pdata *pdata;
 100 };
 101
 102 static int wm8994_readable(unsigned int reg)
 103 {
 104         switch (reg) {
 105         case WM8994_GPIO_1:
 106         case WM8994_GPIO_2:
 107         case WM8994_GPIO_3:
 108         case WM8994_GPIO_4:
 109         case WM8994_GPIO_5:
 110         case WM8994_GPIO_6:
 111         case WM8994_GPIO_7:
 112         case WM8994_GPIO_8:
 113         case WM8994_GPIO_9:
 114         case WM8994_GPIO_10:
 115         case WM8994_GPIO_11:
 116         case WM8994_INTERRUPT_STATUS_1:
 117         case WM8994_INTERRUPT_STATUS_2:
 118         case WM8994_INTERRUPT_RAW_STATUS_2:
 119                 return 1;
 120         default:
 121                 break;
 122         }
 123
 124         if (reg >= WM8994_CACHE_SIZE)
 125                 return 0;
 126         return wm8994_access_masks[reg].readable != 0;
 127 }
 128
 129 static int wm8994_volatile(unsigned int reg)
 130 {
 131         if (reg >= WM8994_REG_CACHE_SIZE)
 132                 return 1;
 133
 134         switch (reg) {
 135         case WM8994_SOFTWARE_RESET:
 136         case WM8994_CHIP_REVISION:
 137         case WM8994_DC_SERVO_1:
 138         case WM8994_DC_SERVO_READBACK:
 139         case WM8994_RATE_STATUS:
 140         case WM8994_LDO_1:
 141         case WM8994_LDO_2:
 142         case WM8958_DSP2_EXECCONTROL:
 143                 return 1;
 144         default:
 145                 return 0;
 146         }
 147 }
 148
 149 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 150         unsigned int value)
 151 {
 152         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 153
 154         BUG_ON(reg > WM8994_MAX_REGISTER);
 155
 156         if (!wm8994_volatile(reg))
 157                 wm8994->reg_cache[reg] = value;
 158
 159         return wm8994_reg_write(codec->control_data, reg, value);
 160 }
 161
 162 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 163                                 unsigned int reg)
 164 {
 165         u16 *reg_cache = codec->reg_cache;
 166
 167         BUG_ON(reg > WM8994_MAX_REGISTER);
 168
 169         if (wm8994_volatile(reg))
 170                 return wm8994_reg_read(codec->control_data, reg);
 171         else
 172                 return reg_cache[reg];
 173 }
 174
 175 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 176 {
 177         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 178         int rate;
 179         int reg1 = 0;
 180         int offset;
 181
 182         if (aif)
 183                 offset = 4;
 184         else
 185                 offset = 0;
 186
 187         switch (wm8994->sysclk[aif]) {
 188         case WM8994_SYSCLK_MCLK1:
 189                 rate = wm8994->mclk[0];
 190                 break;
 191
 192         case WM8994_SYSCLK_MCLK2:
 193                 reg1 |= 0x8;
 194                 rate = wm8994->mclk[1];
 195                 break;
 196
 197         case WM8994_SYSCLK_FLL1:
 198                 reg1 |= 0x10;
 199                 rate = wm8994->fll[0].out;
 200                 break;
 201
 202         case WM8994_SYSCLK_FLL2:
 203                 reg1 |= 0x18;
 204                 rate = wm8994->fll[1].out;
 205                 break;
 206
 207         default:
 208                 return -EINVAL;
 209         }
 210
 211         if (rate >= 13500000) {
 212                 rate /= 2;
 213                 reg1 |= WM8994_AIF1CLK_DIV;
 214
 215                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 216                         aif + 1, rate);
 217         }
 218
 219         if (rate && rate < 3000000)
 220                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 221                          aif + 1, rate);
 222
 223         wm8994->aifclk[aif] = rate;
 224
 225         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 226                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 227                             reg1);
 228
 229         return 0;
 230 }
 231
 232 static int configure_clock(struct snd_soc_codec *codec)
 233 {
 234         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 235         int old, new;
 236
 237         /* Bring up the AIF clocks first */
 238         configure_aif_clock(codec, 0);
 239         configure_aif_clock(codec, 1);
 240
 241         /* Then switch CLK_SYS over to the higher of them; a change
 242          * can only happen as a result of a clocking change which can
 243          * only be made outside of DAPM so we can safely redo the
 244          * clocking.
 245          */
 246
 247         /* If they're equal it doesn't matter which is used */
 248         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 249                 return 0;
 250
 251         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 252                 new = WM8994_SYSCLK_SRC;
 253         else
 254                 new = 0;
 255
 256         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 257
 258         /* If there's no change then we're done. */
 259         if (old == new)
 260                 return 0;
 261
 262         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 263
 264         snd_soc_dapm_sync(&codec->dapm);
 265
 266         return 0;
 267 }
 268
 269 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 270                          struct snd_soc_dapm_widget *sink)
 271 {
 272         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 273         const char *clk;
 274
 275         /* Check what we're currently using for CLK_SYS */
 276         if (reg & WM8994_SYSCLK_SRC)
 277                 clk = "AIF2CLK";
 278         else
 279                 clk = "AIF1CLK";
 280
 281         return strcmp(source->name, clk) == 0;
 282 }
 283
 284 static const char *sidetone_hpf_text[] = {
 285         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 286 };
 287
 288 static const struct soc_enum sidetone_hpf =
 289         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 290
 291 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 292 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 293 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 294 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 295 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 296
 297 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 298 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 299         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 300         .put = wm8994_put_drc_sw, \
 301         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 302
 303 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 304                              struct snd_ctl_elem_value *ucontrol)
 305 {
 306         struct soc_mixer_control *mc =
 307                 (struct soc_mixer_control *)kcontrol->private_value;
 308         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 309         int mask, ret;
 310
 311         /* Can't enable both ADC and DAC paths simultaneously */
 312         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 313                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 314                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 315         else
 316                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 317
 318         ret = snd_soc_read(codec, mc->reg);
 319         if (ret < 0)
 320                 return ret;
 321         if (ret & mask)
 322                 return -EINVAL;
 323
 324         return snd_soc_put_volsw(kcontrol, ucontrol);
 325 }
 326
 327 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 328 {
 329         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 330         struct wm8994_pdata *pdata = wm8994->pdata;
 331         int base = wm8994_drc_base[drc];
 332         int cfg = wm8994->drc_cfg[drc];
 333         int save, i;
 334
 335         /* Save any enables; the configuration should clear them. */
 336         save = snd_soc_read(codec, base);
 337         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 338                 WM8994_AIF1ADC1R_DRC_ENA;
 339
 340         for (i = 0; i < WM8994_DRC_REGS; i++)
 341                 snd_soc_update_bits(codec, base + i, 0xffff,
 342                                     pdata->drc_cfgs[cfg].regs[i]);
 343
 344         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 345                              WM8994_AIF1ADC1L_DRC_ENA |
 346                              WM8994_AIF1ADC1R_DRC_ENA, save);
 347 }
 348
 349 /* Icky as hell but saves code duplication */
 350 static int wm8994_get_drc(const char *name)
 351 {
 352         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 353                 return 0;
 354         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 355                 return 1;
 356         if (strcmp(name, "AIF2DRC Mode") == 0)
 357                 return 2;
 358         return -EINVAL;
 359 }
 360
 361 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 362                                struct snd_ctl_elem_value *ucontrol)
 363 {
 364         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 365         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 366         struct wm8994_pdata *pdata = wm8994->pdata;
 367         int drc = wm8994_get_drc(kcontrol->id.name);
 368         int value = ucontrol->value.integer.value[0];
 369
 370         if (drc < 0)
 371                 return drc;
 372
 373         if (value >= pdata->num_drc_cfgs)
 374                 return -EINVAL;
 375
 376         wm8994->drc_cfg[drc] = value;
 377
 378         wm8994_set_drc(codec, drc);
 379
 380         return 0;
 381 }
 382
 383 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 384                                struct snd_ctl_elem_value *ucontrol)
 385 {
 386         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 387         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 388         int drc = wm8994_get_drc(kcontrol->id.name);
 389
 390         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 391
 392         return 0;
 393 }
 394
 395 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 396 {
 397         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 398         struct wm8994_pdata *pdata = wm8994->pdata;
 399         int base = wm8994_retune_mobile_base[block];
 400         int iface, best, best_val, save, i, cfg;
 401
 402         if (!pdata || !wm8994->num_retune_mobile_texts)
 403                 return;
 404
 405         switch (block) {
 406         case 0:
 407         case 1:
 408                 iface = 0;
 409                 break;
 410         case 2:
 411                 iface = 1;
 412                 break;
 413         default:
 414                 return;
 415         }
 416
 417         /* Find the version of the currently selected configuration
 418          * with the nearest sample rate. */
 419         cfg = wm8994->retune_mobile_cfg[block];
 420         best = 0;
 421         best_val = INT_MAX;
 422         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 423                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 424                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 425                     abs(pdata->retune_mobile_cfgs[i].rate
 426                         - wm8994->dac_rates[iface]) < best_val) {
 427                         best = i;
 428                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 429                                        - wm8994->dac_rates[iface]);
 430                 }
 431         }
 432
 433         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 434                 block,
 435                 pdata->retune_mobile_cfgs[best].name,
 436                 pdata->retune_mobile_cfgs[best].rate,
 437                 wm8994->dac_rates[iface]);
 438
 439         /* The EQ will be disabled while reconfiguring it, remember the
 440          * current configuration.
 441          */
 442         save = snd_soc_read(codec, base);
 443         save &= WM8994_AIF1DAC1_EQ_ENA;
 444
 445         for (i = 0; i < WM8994_EQ_REGS; i++)
 446                 snd_soc_update_bits(codec, base + i, 0xffff,
 447                                 pdata->retune_mobile_cfgs[best].regs[i]);
 448
 449         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 450 }
 451
 452 /* Icky as hell but saves code duplication */
 453 static int wm8994_get_retune_mobile_block(const char *name)
 454 {
 455         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 456                 return 0;
 457         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 458                 return 1;
 459         if (strcmp(name, "AIF2 EQ Mode") == 0)
 460                 return 2;
 461         return -EINVAL;
 462 }
 463
 464 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 465                                          struct snd_ctl_elem_value *ucontrol)
 466 {
 467         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 468         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 469         struct wm8994_pdata *pdata = wm8994->pdata;
 470         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 471         int value = ucontrol->value.integer.value[0];
 472
 473         if (block < 0)
 474                 return block;
 475
 476         if (value >= pdata->num_retune_mobile_cfgs)
 477                 return -EINVAL;
 478
 479         wm8994->retune_mobile_cfg[block] = value;
 480
 481         wm8994_set_retune_mobile(codec, block);
 482
 483         return 0;
 484 }
 485
 486 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 487                                          struct snd_ctl_elem_value *ucontrol)
 488 {
 489         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 490         struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
 491         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 492
 493         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 494
 495         return 0;
 496 }
 497
 498 static const char *aif_chan_src_text[] = {
 499         "Left", "Right"
 500 };
 501
 502 static const struct soc_enum aif1adcl_src =
 503         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 504
 505 static const struct soc_enum aif1adcr_src =
 506         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 507
 508 static const struct soc_enum aif2adcl_src =
 509         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 510
 511 static const struct soc_enum aif2adcr_src =
 512         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 513
 514 static const struct soc_enum aif1dacl_src =
 515         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 516
 517 static const struct soc_enum aif1dacr_src =
 518         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 519
 520 static const struct soc_enum aif2dacl_src =
 521         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 522
 523 static const struct soc_enum aif2dacr_src =
 524         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 525
 526 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
 527 {
 528         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 529         int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
 530         int ena, reg, aif;
 531
 532         switch (mbc) {
 533         case 0:
 534                 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
 535                 aif = 0;
 536                 break;
 537         case 1:
 538                 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
 539                 aif = 0;
 540                 break;
 541         case 2:
 542                 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
 543                 aif = 1;
 544                 break;
 545         default:
 546                 BUG();
 547                 return;
 548         }
 549
 550         /* We can only enable the MBC if the AIF is enabled and we
 551          * want it to be enabled. */
 552         ena = pwr_reg && wm8994->mbc_ena[mbc];
 553
 554         reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
 555
 556         dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
 557                 mbc, start, pwr_reg, reg);
 558
 559         if (start && ena) {
 560                 /* If the DSP is already running then noop */
 561                 if (reg & WM8958_DSP2_ENA)
 562                         return;
 563
 564                 /* Switch the clock over to the appropriate AIF */
 565                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 566                                     WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
 567                                     aif << WM8958_DSP2CLK_SRC_SHIFT |
 568                                     WM8958_DSP2CLK_ENA);
 569
 570                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 571                                     WM8958_DSP2_ENA, WM8958_DSP2_ENA);
 572
 573                 /* TODO: Apply any user specified MBC settings */
 574
 575                 /* Run the DSP */
 576                 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
 577                               WM8958_DSP2_RUNR);
 578
 579                 /* And we're off! */
 580                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 581                                     WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
 582                                     mbc << WM8958_MBC_SEL_SHIFT |
 583                                     WM8958_MBC_ENA);
 584         } else {
 585                 /* If the DSP is already stopped then noop */
 586                 if (!(reg & WM8958_DSP2_ENA))
 587                         return;
 588
 589                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 590                                     WM8958_MBC_ENA, 0);
 591                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 592                                     WM8958_DSP2_ENA, 0);
 593                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 594                                     WM8958_DSP2CLK_ENA, 0);
 595         }
 596 }
 597
 598 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
 599                     struct snd_kcontrol *kcontrol, int event)
 600 {
 601         struct snd_soc_codec *codec = w->codec;
 602         int mbc;
 603
 604         switch (w->shift) {
 605         case 13:
 606         case 12:
 607                 mbc = 2;
 608                 break;
 609         case 11:
 610         case 10:
 611                 mbc = 1;
 612                 break;
 613         case 9:
 614         case 8:
 615                 mbc = 0;
 616                 break;
 617         default:
 618                 BUG();
 619                 return -EINVAL;
 620         }
 621
 622         switch (event) {
 623         case SND_SOC_DAPM_POST_PMU:
 624                 wm8958_mbc_apply(codec, mbc, 1);
 625                 break;
 626         case SND_SOC_DAPM_POST_PMD:
 627                 wm8958_mbc_apply(codec, mbc, 0);
 628                 break;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
 635                            struct snd_ctl_elem_info *uinfo)
 636 {
 637         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 638         uinfo->count = 1;
 639         uinfo->value.integer.min = 0;
 640         uinfo->value.integer.max = 1;
 641         return 0;
 642 }
 643
 644 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
 645                           struct snd_ctl_elem_value *ucontrol)
 646 {
 647         int mbc = kcontrol->private_value;
 648         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 649         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 650
 651         ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
 652
 653         return 0;
 654 }
 655
 656 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
 657                           struct snd_ctl_elem_value *ucontrol)
 658 {
 659         int mbc = kcontrol->private_value;
 660         int i;
 661         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 662         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 663
 664         if (ucontrol->value.integer.value[0] > 1)
 665                 return -EINVAL;
 666
 667         for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
 668                 if (mbc != i && wm8994->mbc_ena[i]) {
 669                         dev_dbg(codec->dev, "MBC %d active already\n", mbc);
 670                         return -EBUSY;
 671                 }
 672         }
 673
 674         wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
 675
 676         wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
 677
 678         return 0;
 679 }
 680
 681 #define WM8958_MBC_SWITCH(xname, xval) {\
 682         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 683         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 684         .info = wm8958_mbc_info, \
 685         .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
 686         .private_value = xval }
 687
 688 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 689 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 690                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 691                  1, 119, 0, digital_tlv),
 692 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 693                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 694                  1, 119, 0, digital_tlv),
 695 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 696                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 697                  1, 119, 0, digital_tlv),
 698
 699 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 700 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 701 SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
 702 SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
 703
 704 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 705 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 706 SOC_ENUM("AIF2DACL Source", aif1dacl_src),
 707 SOC_ENUM("AIF2DACR Source", aif1dacr_src),
 708
 709 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 710                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 711 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 712                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 713 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 714                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 715
 716 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 717 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 718
 719 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 720 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 721 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 722
 723 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 724 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 725 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 726
 727 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 728 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 729 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 730
 731 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 732 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 733 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 734
 735 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 736                5, 12, 0, st_tlv),
 737 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 738                0, 12, 0, st_tlv),
 739 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 740                5, 12, 0, st_tlv),
 741 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 742                0, 12, 0, st_tlv),
 743 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 744 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 745
 746 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 747                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 748 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 749              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 750
 751 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 752                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 753 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 754              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 755
 756 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 757                6, 1, 1, wm_hubs_spkmix_tlv),
 758 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 759                2, 1, 1, wm_hubs_spkmix_tlv),
 760
 761 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 762                6, 1, 1, wm_hubs_spkmix_tlv),
 763 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 764                2, 1, 1, wm_hubs_spkmix_tlv),
 765
 766 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 767                10, 15, 0, wm8994_3d_tlv),
 768 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 769            8, 1, 0),
 770 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 771                10, 15, 0, wm8994_3d_tlv),
 772 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 773            8, 1, 0),
 774 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 775                10, 15, 0, wm8994_3d_tlv),
 776 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 777            8, 1, 0),
 778 };
 779
 780 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 781 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 782                eq_tlv),
 783 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 784                eq_tlv),
 785 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 786                eq_tlv),
 787 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 788                eq_tlv),
 789 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 790                eq_tlv),
 791
 792 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 793                eq_tlv),
 794 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 795                eq_tlv),
 796 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 797                eq_tlv),
 798 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 799                eq_tlv),
 800 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 801                eq_tlv),
 802
 803 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 804                eq_tlv),
 805 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 806                eq_tlv),
 807 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 808                eq_tlv),
 809 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 810                eq_tlv),
 811 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 812                eq_tlv),
 813 };
 814
 815 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 816 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 817 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
 818 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
 819 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
 820 };
 821
 822 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 823                          struct snd_kcontrol *kcontrol, int event)
 824 {
 825         struct snd_soc_codec *codec = w->codec;
 826
 827         switch (event) {
 828         case SND_SOC_DAPM_PRE_PMU:
 829                 return configure_clock(codec);
 830
 831         case SND_SOC_DAPM_POST_PMD:
 832                 configure_clock(codec);
 833                 break;
 834         }
 835
 836         return 0;
 837 }
 838
 839 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 840 {
 841         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 842         int enable = 1;
 843         int source = 0;  /* GCC flow analysis can't track enable */
 844         int reg, reg_r;
 845
 846         /* Only support direct DAC->headphone paths */
 847         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 848         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 849                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 850                 enable = 0;
 851         }
 852
 853         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 854         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 855                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 856                 enable = 0;
 857         }
 858
 859         /* We also need the same setting for L/R and only one path */
 860         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 861         switch (reg) {
 862         case WM8994_AIF2DACL_TO_DAC1L:
 863                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 864                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 865                 break;
 866         case WM8994_AIF1DAC2L_TO_DAC1L:
 867                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 868                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 869                 break;
 870         case WM8994_AIF1DAC1L_TO_DAC1L:
 871                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 872                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 873                 break;
 874         default:
 875                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 876                 enable = 0;
 877                 break;
 878         }
 879
 880         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 881         if (reg_r != reg) {
 882                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 883                 enable = 0;
 884         }
 885
 886         if (enable) {
 887                 dev_dbg(codec->dev, "Class W enabled\n");
 888                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 889                                     WM8994_CP_DYN_PWR |
 890                                     WM8994_CP_DYN_SRC_SEL_MASK,
 891                                     source | WM8994_CP_DYN_PWR);
 892                 wm8994->hubs.class_w = true;
 893
 894         } else {
 895                 dev_dbg(codec->dev, "Class W disabled\n");
 896                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 897                                     WM8994_CP_DYN_PWR, 0);
 898                 wm8994->hubs.class_w = false;
 899         }
 900 }
 901
 902 static const char *hp_mux_text[] = {
 903         "Mixer",
 904         "DAC",
 905 };
 906
 907 #define WM8994_HP_ENUM(xname, xenum) \
 908 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 909         .info = snd_soc_info_enum_double, \
 910         .get = snd_soc_dapm_get_enum_double, \
 911         .put = wm8994_put_hp_enum, \
 912         .private_value = (unsigned long)&xenum }
 913
 914 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 915                               struct snd_ctl_elem_value *ucontrol)
 916 {
 917         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
 918         struct snd_soc_codec *codec = w->codec;
 919         int ret;
 920
 921         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 922
 923         wm8994_update_class_w(codec);
 924
 925         return ret;
 926 }
 927
 928 static const struct soc_enum hpl_enum =
 929         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 930
 931 static const struct snd_kcontrol_new hpl_mux =
 932         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
 933
 934 static const struct soc_enum hpr_enum =
 935         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
 936
 937 static const struct snd_kcontrol_new hpr_mux =
 938         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
 939
 940 static const char *adc_mux_text[] = {
 941         "ADC",
 942         "DMIC",
 943 };
 944
 945 static const struct soc_enum adc_enum =
 946         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
 947
 948 static const struct snd_kcontrol_new adcl_mux =
 949         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
 950
 951 static const struct snd_kcontrol_new adcr_mux =
 952         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
 953
 954 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 955 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
 956 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
 957 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
 958 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
 959 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
 960 };
 961
 962 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 963 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
 964 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
 965 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
 966 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
 967 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
 968 };
 969
 970 /* Debugging; dump chip status after DAPM transitions */
 971 static int post_ev(struct snd_soc_dapm_widget *w,
 972             struct snd_kcontrol *kcontrol, int event)
 973 {
 974         struct snd_soc_codec *codec = w->codec;
 975         dev_dbg(codec->dev, "SRC status: %x\n",
 976                 snd_soc_read(codec,
 977                              WM8994_RATE_STATUS));
 978         return 0;
 979 }
 980
 981 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
 982 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 983                 1, 1, 0),
 984 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 985                 0, 1, 0),
 986 };
 987
 988 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
 989 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 990                 1, 1, 0),
 991 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 992                 0, 1, 0),
 993 };
 994
 995 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
 996 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 997                 1, 1, 0),
 998 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 999                 0, 1, 0),
1000 };
1001
1002 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1003 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1004                 1, 1, 0),
1005 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1006                 0, 1, 0),
1007 };
1008
1009 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1010 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1011                 5, 1, 0),
1012 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1013                 4, 1, 0),
1014 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1015                 2, 1, 0),
1016 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1017                 1, 1, 0),
1018 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1019                 0, 1, 0),
1020 };
1021
1022 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1023 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1024                 5, 1, 0),
1025 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1026                 4, 1, 0),
1027 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1028                 2, 1, 0),
1029 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1030                 1, 1, 0),
1031 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1032                 0, 1, 0),
1033 };
1034
1035 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1036 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1037         .info = snd_soc_info_volsw, \
1038         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1039         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1040
1041 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1042                               struct snd_ctl_elem_value *ucontrol)
1043 {
1044         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1045         struct snd_soc_codec *codec = w->codec;
1046         int ret;
1047
1048         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1049
1050         wm8994_update_class_w(codec);
1051
1052         return ret;
1053 }
1054
1055 static const struct snd_kcontrol_new dac1l_mix[] = {
1056 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1057                       5, 1, 0),
1058 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1059                       4, 1, 0),
1060 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1061                       2, 1, 0),
1062 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1063                       1, 1, 0),
1064 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1065                       0, 1, 0),
1066 };
1067
1068 static const struct snd_kcontrol_new dac1r_mix[] = {
1069 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1070                       5, 1, 0),
1071 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1072                       4, 1, 0),
1073 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1074                       2, 1, 0),
1075 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1076                       1, 1, 0),
1077 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1078                       0, 1, 0),
1079 };
1080
1081 static const char *sidetone_text[] = {
1082         "ADC/DMIC1", "DMIC2",
1083 };
1084
1085 static const struct soc_enum sidetone1_enum =
1086         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1087
1088 static const struct snd_kcontrol_new sidetone1_mux =
1089         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1090
1091 static const struct soc_enum sidetone2_enum =
1092         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1093
1094 static const struct snd_kcontrol_new sidetone2_mux =
1095         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1096
1097 static const char *aif1dac_text[] = {
1098         "AIF1DACDAT", "AIF3DACDAT",
1099 };
1100
1101 static const struct soc_enum aif1dac_enum =
1102         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1103
1104 static const struct snd_kcontrol_new aif1dac_mux =
1105         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1106
1107 static const char *aif2dac_text[] = {
1108         "AIF2DACDAT", "AIF3DACDAT",
1109 };
1110
1111 static const struct soc_enum aif2dac_enum =
1112         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1113
1114 static const struct snd_kcontrol_new aif2dac_mux =
1115         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1116
1117 static const char *aif2adc_text[] = {
1118         "AIF2ADCDAT", "AIF3DACDAT",
1119 };
1120
1121 static const struct soc_enum aif2adc_enum =
1122         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1123
1124 static const struct snd_kcontrol_new aif2adc_mux =
1125         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1126
1127 static const char *aif3adc_text[] = {
1128         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1129 };
1130
1131 static const struct soc_enum wm8994_aif3adc_enum =
1132         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1133
1134 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1135         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1136
1137 static const struct soc_enum wm8958_aif3adc_enum =
1138         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1139
1140 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1141         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1142
1143 static const char *mono_pcm_out_text[] = {
1144         "None", "AIF2ADCL", "AIF2ADCR",
1145 };
1146
1147 static const struct soc_enum mono_pcm_out_enum =
1148         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1149
1150 static const struct snd_kcontrol_new mono_pcm_out_mux =
1151         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1152
1153 static const char *aif2dac_src_text[] = {
1154         "AIF2", "AIF3",
1155 };
1156
1157 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1158 static const struct soc_enum aif2dacl_src_enum =
1159         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1160
1161 static const struct snd_kcontrol_new aif2dacl_src_mux =
1162         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1163
1164 static const struct soc_enum aif2dacr_src_enum =
1165         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1166
1167 static const struct snd_kcontrol_new aif2dacr_src_mux =
1168         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1169
1170 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1171 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1172 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1173 SND_SOC_DAPM_INPUT("Clock"),
1174
1175 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1176                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1177
1178 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1179 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1180 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1181
1182 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1183 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1184
1185 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
1186                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1187 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
1188                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1189 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1190                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1191                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1192 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1193                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1194                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1195
1196 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
1197                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1198 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
1199                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1200 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1201                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1202                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1203 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1204                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1205                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1206
1207 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1208                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1209 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1210                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1211
1212 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1213                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1214 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1215                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1216
1217 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1218                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1219 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1220                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1221
1222 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1223 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1224
1225 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1226                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1227 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1228                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1229
1230 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1231                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1232 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1233                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1234 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1235                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1236                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1237 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1238                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1239                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1240
1241 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1242 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1243 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1244
1245 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1246 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1247 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1248
1249 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1250 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1251
1252 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1253
1254 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1255 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1256 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1257 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1258
1259 /* Power is done with the muxes since the ADC power also controls the
1260  * downsampling chain, the chip will automatically manage the analogue
1261  * specific portions.
1262  */
1263 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1264 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1265
1266 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1267 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1268
1269 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1270 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1271 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1272 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1273
1274 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1275 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1276
1277 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1278                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1279 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1280                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1281
1282 SND_SOC_DAPM_POST("Debug log", post_ev),
1283 };
1284
1285 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1286 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1287 };
1288
1289 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1290 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1291 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1292 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1293 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1294 };
1295
1296 static const struct snd_soc_dapm_route intercon[] = {
1297         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1298         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1299
1300         { "DSP1CLK", NULL, "CLK_SYS" },
1301         { "DSP2CLK", NULL, "CLK_SYS" },
1302         { "DSPINTCLK", NULL, "CLK_SYS" },
1303
1304         { "AIF1ADC1L", NULL, "AIF1CLK" },
1305         { "AIF1ADC1L", NULL, "DSP1CLK" },
1306         { "AIF1ADC1R", NULL, "AIF1CLK" },
1307         { "AIF1ADC1R", NULL, "DSP1CLK" },
1308         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1309
1310         { "AIF1DAC1L", NULL, "AIF1CLK" },
1311         { "AIF1DAC1L", NULL, "DSP1CLK" },
1312         { "AIF1DAC1R", NULL, "AIF1CLK" },
1313         { "AIF1DAC1R", NULL, "DSP1CLK" },
1314         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1315
1316         { "AIF1ADC2L", NULL, "AIF1CLK" },
1317         { "AIF1ADC2L", NULL, "DSP1CLK" },
1318         { "AIF1ADC2R", NULL, "AIF1CLK" },
1319         { "AIF1ADC2R", NULL, "DSP1CLK" },
1320         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1321
1322         { "AIF1DAC2L", NULL, "AIF1CLK" },
1323         { "AIF1DAC2L", NULL, "DSP1CLK" },
1324         { "AIF1DAC2R", NULL, "AIF1CLK" },
1325         { "AIF1DAC2R", NULL, "DSP1CLK" },
1326         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1327
1328         { "AIF2ADCL", NULL, "AIF2CLK" },
1329         { "AIF2ADCL", NULL, "DSP2CLK" },
1330         { "AIF2ADCR", NULL, "AIF2CLK" },
1331         { "AIF2ADCR", NULL, "DSP2CLK" },
1332         { "AIF2ADCR", NULL, "DSPINTCLK" },
1333
1334         { "AIF2DACL", NULL, "AIF2CLK" },
1335         { "AIF2DACL", NULL, "DSP2CLK" },
1336         { "AIF2DACR", NULL, "AIF2CLK" },
1337         { "AIF2DACR", NULL, "DSP2CLK" },
1338         { "AIF2DACR", NULL, "DSPINTCLK" },
1339
1340         { "DMIC1L", NULL, "DMIC1DAT" },
1341         { "DMIC1L", NULL, "CLK_SYS" },
1342         { "DMIC1R", NULL, "DMIC1DAT" },
1343         { "DMIC1R", NULL, "CLK_SYS" },
1344         { "DMIC2L", NULL, "DMIC2DAT" },
1345         { "DMIC2L", NULL, "CLK_SYS" },
1346         { "DMIC2R", NULL, "DMIC2DAT" },
1347         { "DMIC2R", NULL, "CLK_SYS" },
1348
1349         { "ADCL", NULL, "AIF1CLK" },
1350         { "ADCL", NULL, "DSP1CLK" },
1351         { "ADCL", NULL, "DSPINTCLK" },
1352
1353         { "ADCR", NULL, "AIF1CLK" },
1354         { "ADCR", NULL, "DSP1CLK" },
1355         { "ADCR", NULL, "DSPINTCLK" },
1356
1357         { "ADCL Mux", "ADC", "ADCL" },
1358         { "ADCL Mux", "DMIC", "DMIC1L" },
1359         { "ADCR Mux", "ADC", "ADCR" },
1360         { "ADCR Mux", "DMIC", "DMIC1R" },
1361
1362         { "DAC1L", NULL, "AIF1CLK" },
1363         { "DAC1L", NULL, "DSP1CLK" },
1364         { "DAC1L", NULL, "DSPINTCLK" },
1365
1366         { "DAC1R", NULL, "AIF1CLK" },
1367         { "DAC1R", NULL, "DSP1CLK" },
1368         { "DAC1R", NULL, "DSPINTCLK" },
1369
1370         { "DAC2L", NULL, "AIF2CLK" },
1371         { "DAC2L", NULL, "DSP2CLK" },
1372         { "DAC2L", NULL, "DSPINTCLK" },
1373
1374         { "DAC2R", NULL, "AIF2DACR" },
1375         { "DAC2R", NULL, "AIF2CLK" },
1376         { "DAC2R", NULL, "DSP2CLK" },
1377         { "DAC2R", NULL, "DSPINTCLK" },
1378
1379         { "TOCLK", NULL, "CLK_SYS" },
1380
1381         /* AIF1 outputs */
1382         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1383         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1384         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1385
1386         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1387         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1388         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1389
1390         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1391         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1392         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1393
1394         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1395         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1396         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1397
1398         /* Pin level routing for AIF3 */
1399         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1400         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1401         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1402         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1403
1404         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1405         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1406         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1407         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1408         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1409         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1410         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1411
1412         /* DAC1 inputs */
1413         { "DAC1L", NULL, "DAC1L Mixer" },
1414         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1415         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1416         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1417         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1418         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1419
1420         { "DAC1R", NULL, "DAC1R Mixer" },
1421         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1422         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1423         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1424         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1425         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1426
1427         /* DAC2/AIF2 outputs  */
1428         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1429         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1430         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1431         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1432         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1433         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1434         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1435
1436         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1437         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1438         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1439         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1440         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1441         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1442         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1443
1444         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1445
1446         /* AIF3 output */
1447         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1448         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1449         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1450         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1451         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1452         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1453         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1454         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1455
1456         /* Sidetone */
1457         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1458         { "Left Sidetone", "DMIC2", "DMIC2L" },
1459         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1460         { "Right Sidetone", "DMIC2", "DMIC2R" },
1461
1462         /* Output stages */
1463         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1464         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1465
1466         { "SPKL", "DAC1 Switch", "DAC1L" },
1467         { "SPKL", "DAC2 Switch", "DAC2L" },
1468
1469         { "SPKR", "DAC1 Switch", "DAC1R" },
1470         { "SPKR", "DAC2 Switch", "DAC2R" },
1471
1472         { "Left Headphone Mux", "DAC", "DAC1L" },
1473         { "Right Headphone Mux", "DAC", "DAC1R" },
1474 };
1475
1476 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1477         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1478         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1479 };
1480
1481 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1482         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1483         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1484
1485         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1486         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1487         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1488         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1489
1490         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1491         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1492
1493         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1494 };
1495
1496 /* The size in bits of the FLL divide multiplied by 10
1497  * to allow rounding later */
1498 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1499
1500 struct fll_div {
1501         u16 outdiv;
1502         u16 n;
1503         u16 k;
1504         u16 clk_ref_div;
1505         u16 fll_fratio;
1506 };
1507
1508 static int wm8994_get_fll_config(struct fll_div *fll,
1509                                  int freq_in, int freq_out)
1510 {
1511         u64 Kpart;
1512         unsigned int K, Ndiv, Nmod;
1513
1514         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1515
1516         /* Scale the input frequency down to <= 13.5MHz */
1517         fll->clk_ref_div = 0;
1518         while (freq_in > 13500000) {
1519                 fll->clk_ref_div++;
1520                 freq_in /= 2;
1521
1522                 if (fll->clk_ref_div > 3)
1523                         return -EINVAL;
1524         }
1525         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1526
1527         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1528         fll->outdiv = 3;
1529         while (freq_out * (fll->outdiv + 1) < 90000000) {
1530                 fll->outdiv++;
1531                 if (fll->outdiv > 63)
1532                         return -EINVAL;
1533         }
1534         freq_out *= fll->outdiv + 1;
1535         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1536
1537         if (freq_in > 1000000) {
1538                 fll->fll_fratio = 0;
1539         } else if (freq_in > 256000) {
1540                 fll->fll_fratio = 1;
1541                 freq_in *= 2;
1542         } else if (freq_in > 128000) {
1543                 fll->fll_fratio = 2;
1544                 freq_in *= 4;
1545         } else if (freq_in > 64000) {
1546                 fll->fll_fratio = 3;
1547                 freq_in *= 8;
1548         } else {
1549                 fll->fll_fratio = 4;
1550                 freq_in *= 16;
1551         }
1552         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1553
1554         /* Now, calculate N.K */
1555         Ndiv = freq_out / freq_in;
1556
1557         fll->n = Ndiv;
1558         Nmod = freq_out % freq_in;
1559         pr_debug("Nmod=%d\n", Nmod);
1560
1561         /* Calculate fractional part - scale up so we can round. */
1562         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1563
1564         do_div(Kpart, freq_in);
1565
1566         K = Kpart & 0xFFFFFFFF;
1567
1568         if ((K % 10) >= 5)
1569                 K += 5;
1570
1571         /* Move down to proper range now rounding is done */
1572         fll->k = K / 10;
1573
1574         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1575
1576         return 0;
1577 }
1578
1579 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1580                           unsigned int freq_in, unsigned int freq_out)
1581 {
1582         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1583         int reg_offset, ret;
1584         struct fll_div fll;
1585         u16 reg, aif1, aif2;
1586
1587         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1588                 & WM8994_AIF1CLK_ENA;
1589
1590         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1591                 & WM8994_AIF2CLK_ENA;
1592
1593         switch (id) {
1594         case WM8994_FLL1:
1595                 reg_offset = 0;
1596                 id = 0;
1597                 break;
1598         case WM8994_FLL2:
1599                 reg_offset = 0x20;
1600                 id = 1;
1601                 break;
1602         default:
1603                 return -EINVAL;
1604         }
1605
1606         switch (src) {
1607         case 0:
1608                 /* Allow no source specification when stopping */
1609                 if (freq_out)
1610                         return -EINVAL;
1611                 break;
1612         case WM8994_FLL_SRC_MCLK1:
1613         case WM8994_FLL_SRC_MCLK2:
1614         case WM8994_FLL_SRC_LRCLK:
1615         case WM8994_FLL_SRC_BCLK:
1616                 break;
1617         default:
1618                 return -EINVAL;
1619         }
1620
1621         /* Are we changing anything? */
1622         if (wm8994->fll[id].src == src &&
1623             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1624                 return 0;
1625
1626         /* If we're stopping the FLL redo the old config - no
1627          * registers will actually be written but we avoid GCC flow
1628          * analysis bugs spewing warnings.
1629          */
1630         if (freq_out)
1631                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1632         else
1633                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1634                                             wm8994->fll[id].out);
1635         if (ret < 0)
1636                 return ret;
1637
1638         /* Gate the AIF clocks while we reclock */
1639         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1640                             WM8994_AIF1CLK_ENA, 0);
1641         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1642                             WM8994_AIF2CLK_ENA, 0);
1643
1644         /* We always need to disable the FLL while reconfiguring */
1645         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1646                             WM8994_FLL1_ENA, 0);
1647
1648         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1649                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1650         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1651                             WM8994_FLL1_OUTDIV_MASK |
1652                             WM8994_FLL1_FRATIO_MASK, reg);
1653
1654         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1655
1656         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1657                             WM8994_FLL1_N_MASK,
1658                                     fll.n << WM8994_FLL1_N_SHIFT);
1659
1660         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1661                             WM8994_FLL1_REFCLK_DIV_MASK |
1662                             WM8994_FLL1_REFCLK_SRC_MASK,
1663                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1664                             (src - 1));
1665
1666         /* Enable (with fractional mode if required) */
1667         if (freq_out) {
1668                 if (fll.k)
1669                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1670                 else
1671                         reg = WM8994_FLL1_ENA;
1672                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1673                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1674                                     reg);
1675         }
1676
1677         wm8994->fll[id].in = freq_in;
1678         wm8994->fll[id].out = freq_out;
1679         wm8994->fll[id].src = src;
1680
1681         /* Enable any gated AIF clocks */
1682         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1683                             WM8994_AIF1CLK_ENA, aif1);
1684         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1685                             WM8994_AIF2CLK_ENA, aif2);
1686
1687         configure_clock(codec);
1688
1689         return 0;
1690 }
1691
1692
1693 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1694
1695 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1696                           unsigned int freq_in, unsigned int freq_out)
1697 {
1698         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1699 }
1700
1701 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1702                 int clk_id, unsigned int freq, int dir)
1703 {
1704         struct snd_soc_codec *codec = dai->codec;
1705         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1706         int i;
1707
1708         switch (dai->id) {
1709         case 1:
1710         case 2:
1711                 break;
1712
1713         default:
1714                 /* AIF3 shares clocking with AIF1/2 */
1715                 return -EINVAL;
1716         }
1717
1718         switch (clk_id) {
1719         case WM8994_SYSCLK_MCLK1:
1720                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1721                 wm8994->mclk[0] = freq;
1722                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1723                         dai->id, freq);
1724                 break;
1725
1726         case WM8994_SYSCLK_MCLK2:
1727                 /* TODO: Set GPIO AF */
1728                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1729                 wm8994->mclk[1] = freq;
1730                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1731                         dai->id, freq);
1732                 break;
1733
1734         case WM8994_SYSCLK_FLL1:
1735                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1736                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1737                 break;
1738
1739         case WM8994_SYSCLK_FLL2:
1740                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1741                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1742                 break;
1743
1744         case WM8994_SYSCLK_OPCLK:
1745                 /* Special case - a division (times 10) is given and
1746                  * no effect on main clocking.
1747                  */
1748                 if (freq) {
1749                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1750                                 if (opclk_divs[i] == freq)
1751                                         break;
1752                         if (i == ARRAY_SIZE(opclk_divs))
1753                                 return -EINVAL;
1754                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1755                                             WM8994_OPCLK_DIV_MASK, i);
1756                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1757                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1758                 } else {
1759                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1760                                             WM8994_OPCLK_ENA, 0);
1761                 }
1762
1763         default:
1764                 return -EINVAL;
1765         }
1766
1767         configure_clock(codec);
1768
1769         return 0;
1770 }
1771
1772 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1773                                  enum snd_soc_bias_level level)
1774 {
1775         struct wm8994 *control = codec->control_data;
1776         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1777
1778         switch (level) {
1779         case SND_SOC_BIAS_ON:
1780                 break;
1781
1782         case SND_SOC_BIAS_PREPARE:
1783                 /* VMID=2x40k */
1784                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1785                                     WM8994_VMID_SEL_MASK, 0x2);
1786                 break;
1787
1788         case SND_SOC_BIAS_STANDBY:
1789                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1790                         /* Tweak DC servo and DSP configuration for
1791                          * improved performance. */
1792                         if (control->type == WM8994 && wm8994->revision < 4) {
1793                                 /* Tweak DC servo and DSP configuration for
1794                                  * improved performance. */
1795                                 snd_soc_write(codec, 0x102, 0x3);
1796                                 snd_soc_write(codec, 0x56, 0x3);
1797                                 snd_soc_write(codec, 0x817, 0);
1798                                 snd_soc_write(codec, 0x102, 0);
1799                         }
1800
1801                         /* Discharge LINEOUT1 & 2 */
1802                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1803                                             WM8994_LINEOUT1_DISCH |
1804                                             WM8994_LINEOUT2_DISCH,
1805                                             WM8994_LINEOUT1_DISCH |
1806                                             WM8994_LINEOUT2_DISCH);
1807
1808                         /* Startup bias, VMID ramp & buffer */
1809                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1810                                             WM8994_STARTUP_BIAS_ENA |
1811                                             WM8994_VMID_BUF_ENA |
1812                                             WM8994_VMID_RAMP_MASK,
1813                                             WM8994_STARTUP_BIAS_ENA |
1814                                             WM8994_VMID_BUF_ENA |
1815                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1816
1817                         /* Main bias enable, VMID=2x40k */
1818                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1819                                             WM8994_BIAS_ENA |
1820                                             WM8994_VMID_SEL_MASK,
1821                                             WM8994_BIAS_ENA | 0x2);
1822
1823                         msleep(20);
1824                 }
1825
1826                 /* VMID=2x500k */
1827                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1828                                     WM8994_VMID_SEL_MASK, 0x4);
1829
1830                 break;
1831
1832         case SND_SOC_BIAS_OFF:
1833                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1834                         /* Switch over to startup biases */
1835                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1836                                             WM8994_BIAS_SRC |
1837                                             WM8994_STARTUP_BIAS_ENA |
1838                                             WM8994_VMID_BUF_ENA |
1839                                             WM8994_VMID_RAMP_MASK,
1840                                             WM8994_BIAS_SRC |
1841                                             WM8994_STARTUP_BIAS_ENA |
1842                                             WM8994_VMID_BUF_ENA |
1843                                             (1 << WM8994_VMID_RAMP_SHIFT));
1844
1845                         /* Disable main biases */
1846                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1847                                             WM8994_BIAS_ENA |
1848                                             WM8994_VMID_SEL_MASK, 0);
1849
1850                         /* Discharge line */
1851                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1852                                             WM8994_LINEOUT1_DISCH |
1853                                             WM8994_LINEOUT2_DISCH,
1854                                             WM8994_LINEOUT1_DISCH |
1855                                             WM8994_LINEOUT2_DISCH);
1856
1857                         msleep(5);
1858
1859                         /* Switch off startup biases */
1860                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1861                                             WM8994_BIAS_SRC |
1862                                             WM8994_STARTUP_BIAS_ENA |
1863                                             WM8994_VMID_BUF_ENA |
1864                                             WM8994_VMID_RAMP_MASK, 0);
1865                 }
1866                 break;
1867         }
1868         codec->dapm.bias_level = level;
1869         return 0;
1870 }
1871
1872 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1873 {
1874         struct snd_soc_codec *codec = dai->codec;
1875         struct wm8994 *control = codec->control_data;
1876         int ms_reg;
1877         int aif1_reg;
1878         int ms = 0;
1879         int aif1 = 0;
1880
1881         switch (dai->id) {
1882         case 1:
1883                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1884                 aif1_reg = WM8994_AIF1_CONTROL_1;
1885                 break;
1886         case 2:
1887                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1888                 aif1_reg = WM8994_AIF2_CONTROL_1;
1889                 break;
1890         default:
1891                 return -EINVAL;
1892         }
1893
1894         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1895         case SND_SOC_DAIFMT_CBS_CFS:
1896                 break;
1897         case SND_SOC_DAIFMT_CBM_CFM:
1898                 ms = WM8994_AIF1_MSTR;
1899                 break;
1900         default:
1901                 return -EINVAL;
1902         }
1903
1904         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1905         case SND_SOC_DAIFMT_DSP_B:
1906                 aif1 |= WM8994_AIF1_LRCLK_INV;
1907         case SND_SOC_DAIFMT_DSP_A:
1908                 aif1 |= 0x18;
1909                 break;
1910         case SND_SOC_DAIFMT_I2S:
1911                 aif1 |= 0x10;
1912                 break;
1913         case SND_SOC_DAIFMT_RIGHT_J:
1914                 break;
1915         case SND_SOC_DAIFMT_LEFT_J:
1916                 aif1 |= 0x8;
1917                 break;
1918         default:
1919                 return -EINVAL;
1920         }
1921
1922         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1923         case SND_SOC_DAIFMT_DSP_A:
1924         case SND_SOC_DAIFMT_DSP_B:
1925                 /* frame inversion not valid for DSP modes */
1926                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1927                 case SND_SOC_DAIFMT_NB_NF:
1928                         break;
1929                 case SND_SOC_DAIFMT_IB_NF:
1930                         aif1 |= WM8994_AIF1_BCLK_INV;
1931                         break;
1932                 default:
1933                         return -EINVAL;
1934                 }
1935                 break;
1936
1937         case SND_SOC_DAIFMT_I2S:
1938         case SND_SOC_DAIFMT_RIGHT_J:
1939         case SND_SOC_DAIFMT_LEFT_J:
1940                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1941                 case SND_SOC_DAIFMT_NB_NF:
1942                         break;
1943                 case SND_SOC_DAIFMT_IB_IF:
1944                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
1945                         break;
1946                 case SND_SOC_DAIFMT_IB_NF:
1947                         aif1 |= WM8994_AIF1_BCLK_INV;
1948                         break;
1949                 case SND_SOC_DAIFMT_NB_IF:
1950                         aif1 |= WM8994_AIF1_LRCLK_INV;
1951                         break;
1952                 default:
1953                         return -EINVAL;
1954                 }
1955                 break;
1956         default:
1957                 return -EINVAL;
1958         }
1959
1960         /* The AIF2 format configuration needs to be mirrored to AIF3
1961          * on WM8958 if it's in use so just do it all the time. */
1962         if (control->type == WM8958 && dai->id == 2)
1963                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
1964                                     WM8994_AIF1_LRCLK_INV |
1965                                     WM8958_AIF3_FMT_MASK, aif1);
1966
1967         snd_soc_update_bits(codec, aif1_reg,
1968                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
1969                             WM8994_AIF1_FMT_MASK,
1970                             aif1);
1971         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
1972                             ms);
1973
1974         return 0;
1975 }
1976
1977 static struct {
1978         int val, rate;
1979 } srs[] = {
1980         { 0,   8000 },
1981         { 1,  11025 },
1982         { 2,  12000 },
1983         { 3,  16000 },
1984         { 4,  22050 },
1985         { 5,  24000 },
1986         { 6,  32000 },
1987         { 7,  44100 },
1988         { 8,  48000 },
1989         { 9,  88200 },
1990         { 10, 96000 },
1991 };
1992
1993 static int fs_ratios[] = {
1994         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
1995 };
1996
1997 static int bclk_divs[] = {
1998         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
1999         640, 880, 960, 1280, 1760, 1920
2000 };
2001
2002 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2003                             struct snd_pcm_hw_params *params,
2004                             struct snd_soc_dai *dai)
2005 {
2006         struct snd_soc_codec *codec = dai->codec;
2007         struct wm8994 *control = codec->control_data;
2008         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2009         int aif1_reg;
2010         int bclk_reg;
2011         int lrclk_reg;
2012         int rate_reg;
2013         int aif1 = 0;
2014         int bclk = 0;
2015         int lrclk = 0;
2016         int rate_val = 0;
2017         int id = dai->id - 1;
2018
2019         int i, cur_val, best_val, bclk_rate, best;
2020
2021         switch (dai->id) {
2022         case 1:
2023                 aif1_reg = WM8994_AIF1_CONTROL_1;
2024                 bclk_reg = WM8994_AIF1_BCLK;
2025                 rate_reg = WM8994_AIF1_RATE;
2026                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2027                     wm8994->lrclk_shared[0]) {
2028                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2029                 } else {
2030                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2031                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2032                 }
2033                 break;
2034         case 2:
2035                 aif1_reg = WM8994_AIF2_CONTROL_1;
2036                 bclk_reg = WM8994_AIF2_BCLK;
2037                 rate_reg = WM8994_AIF2_RATE;
2038                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2039                     wm8994->lrclk_shared[1]) {
2040                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2041                 } else {
2042                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2043                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2044                 }
2045                 break;
2046         case 3:
2047                 switch (control->type) {
2048                 case WM8958:
2049                         aif1_reg = WM8958_AIF3_CONTROL_1;
2050                         break;
2051                 default:
2052                         return 0;
2053                 }
2054         default:
2055                 return -EINVAL;
2056         }
2057
2058         bclk_rate = params_rate(params) * 2;
2059         switch (params_format(params)) {
2060         case SNDRV_PCM_FORMAT_S16_LE:
2061                 bclk_rate *= 16;
2062                 break;
2063         case SNDRV_PCM_FORMAT_S20_3LE:
2064                 bclk_rate *= 20;
2065                 aif1 |= 0x20;
2066                 break;
2067         case SNDRV_PCM_FORMAT_S24_LE:
2068                 bclk_rate *= 24;
2069                 aif1 |= 0x40;
2070                 break;
2071         case SNDRV_PCM_FORMAT_S32_LE:
2072                 bclk_rate *= 32;
2073                 aif1 |= 0x60;
2074                 break;
2075         default:
2076                 return -EINVAL;
2077         }
2078
2079         /* Try to find an appropriate sample rate; look for an exact match. */
2080         for (i = 0; i < ARRAY_SIZE(srs); i++)
2081                 if (srs[i].rate == params_rate(params))
2082                         break;
2083         if (i == ARRAY_SIZE(srs))
2084                 return -EINVAL;
2085         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2086
2087         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2088         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2089                 dai->id, wm8994->aifclk[id], bclk_rate);
2090
2091         if (wm8994->aifclk[id] == 0) {
2092                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2093                 return -EINVAL;
2094         }
2095
2096         /* AIFCLK/fs ratio; look for a close match in either direction */
2097         best = 0;
2098         best_val = abs((fs_ratios[0] * params_rate(params))
2099                        - wm8994->aifclk[id]);
2100         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2101                 cur_val = abs((fs_ratios[i] * params_rate(params))
2102                               - wm8994->aifclk[id]);
2103                 if (cur_val >= best_val)
2104                         continue;
2105                 best = i;
2106                 best_val = cur_val;
2107         }
2108         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2109                 dai->id, fs_ratios[best]);
2110         rate_val |= best;
2111
2112         /* We may not get quite the right frequency if using
2113          * approximate clocks so look for the closest match that is
2114          * higher than the target (we need to ensure that there enough
2115          * BCLKs to clock out the samples).
2116          */
2117         best = 0;
2118         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2119                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2120                 if (cur_val < 0) /* BCLK table is sorted */
2121                         break;
2122                 best = i;
2123         }
2124         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2125         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2126                 bclk_divs[best], bclk_rate);
2127         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2128
2129         lrclk = bclk_rate / params_rate(params);
2130         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2131                 lrclk, bclk_rate / lrclk);
2132
2133         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2134         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2135         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2136                             lrclk);
2137         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2138                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2139
2140         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2141                 switch (dai->id) {
2142                 case 1:
2143                         wm8994->dac_rates[0] = params_rate(params);
2144                         wm8994_set_retune_mobile(codec, 0);
2145                         wm8994_set_retune_mobile(codec, 1);
2146                         break;
2147                 case 2:
2148                         wm8994->dac_rates[1] = params_rate(params);
2149                         wm8994_set_retune_mobile(codec, 2);
2150                         break;
2151                 }
2152         }
2153
2154         return 0;
2155 }
2156
2157 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2158                                  struct snd_pcm_hw_params *params,
2159                                  struct snd_soc_dai *dai)
2160 {
2161         struct snd_soc_codec *codec = dai->codec;
2162         struct wm8994 *control = codec->control_data;
2163         int aif1_reg;
2164         int aif1 = 0;
2165
2166         switch (dai->id) {
2167         case 3:
2168                 switch (control->type) {
2169                 case WM8958:
2170                         aif1_reg = WM8958_AIF3_CONTROL_1;
2171                         break;
2172                 default:
2173                         return 0;
2174                 }
2175         default:
2176                 return 0;
2177         }
2178
2179         switch (params_format(params)) {
2180         case SNDRV_PCM_FORMAT_S16_LE:
2181                 break;
2182         case SNDRV_PCM_FORMAT_S20_3LE:
2183                 aif1 |= 0x20;
2184                 break;
2185         case SNDRV_PCM_FORMAT_S24_LE:
2186                 aif1 |= 0x40;
2187                 break;
2188         case SNDRV_PCM_FORMAT_S32_LE:
2189                 aif1 |= 0x60;
2190                 break;
2191         default:
2192                 return -EINVAL;
2193         }
2194
2195         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2196 }
2197
2198 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2199 {
2200         struct snd_soc_codec *codec = codec_dai->codec;
2201         int mute_reg;
2202         int reg;
2203
2204         switch (codec_dai->id) {
2205         case 1:
2206                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2207                 break;
2208         case 2:
2209                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2210                 break;
2211         default:
2212                 return -EINVAL;
2213         }
2214
2215         if (mute)
2216                 reg = WM8994_AIF1DAC1_MUTE;
2217         else
2218                 reg = 0;
2219
2220         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2221
2222         return 0;
2223 }
2224
2225 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2226 {
2227         struct snd_soc_codec *codec = codec_dai->codec;
2228         int reg, val, mask;
2229
2230         switch (codec_dai->id) {
2231         case 1:
2232                 reg = WM8994_AIF1_MASTER_SLAVE;
2233                 mask = WM8994_AIF1_TRI;
2234                 break;
2235         case 2:
2236                 reg = WM8994_AIF2_MASTER_SLAVE;
2237                 mask = WM8994_AIF2_TRI;
2238                 break;
2239         case 3:
2240                 reg = WM8994_POWER_MANAGEMENT_6;
2241                 mask = WM8994_AIF3_TRI;
2242                 break;
2243         default:
2244                 return -EINVAL;
2245         }
2246
2247         if (tristate)
2248                 val = mask;
2249         else
2250                 val = 0;
2251
2252         return snd_soc_update_bits(codec, reg, mask, reg);
2253 }
2254
2255 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2256
2257 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2258                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2259
2260 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2261         .set_sysclk     = wm8994_set_dai_sysclk,
2262         .set_fmt        = wm8994_set_dai_fmt,
2263         .hw_params      = wm8994_hw_params,
2264         .digital_mute   = wm8994_aif_mute,
2265         .set_pll        = wm8994_set_fll,
2266         .set_tristate   = wm8994_set_tristate,
2267 };
2268
2269 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2270         .set_sysclk     = wm8994_set_dai_sysclk,
2271         .set_fmt        = wm8994_set_dai_fmt,
2272         .hw_params      = wm8994_hw_params,
2273         .digital_mute   = wm8994_aif_mute,
2274         .set_pll        = wm8994_set_fll,
2275         .set_tristate   = wm8994_set_tristate,
2276 };
2277
2278 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2279         .hw_params      = wm8994_aif3_hw_params,
2280         .set_tristate   = wm8994_set_tristate,
2281 };
2282
2283 static struct snd_soc_dai_driver wm8994_dai[] = {
2284         {
2285                 .name = "wm8994-aif1",
2286                 .id = 1,
2287                 .playback = {
2288                         .stream_name = "AIF1 Playback",
2289                         .channels_min = 2,
2290                         .channels_max = 2,
2291                         .rates = WM8994_RATES,
2292                         .formats = WM8994_FORMATS,
2293                 },
2294                 .capture = {
2295                         .stream_name = "AIF1 Capture",
2296                         .channels_min = 2,
2297                         .channels_max = 2,
2298                         .rates = WM8994_RATES,
2299                         .formats = WM8994_FORMATS,
2300                  },
2301                 .ops = &wm8994_aif1_dai_ops,
2302         },
2303         {
2304                 .name = "wm8994-aif2",
2305                 .id = 2,
2306                 .playback = {
2307                         .stream_name = "AIF2 Playback",
2308                         .channels_min = 2,
2309                         .channels_max = 2,
2310                         .rates = WM8994_RATES,
2311                         .formats = WM8994_FORMATS,
2312                 },
2313                 .capture = {
2314                         .stream_name = "AIF2 Capture",
2315                         .channels_min = 2,
2316                         .channels_max = 2,
2317                         .rates = WM8994_RATES,
2318                         .formats = WM8994_FORMATS,
2319                 },
2320                 .ops = &wm8994_aif2_dai_ops,
2321         },
2322         {
2323                 .name = "wm8994-aif3",
2324                 .id = 3,
2325                 .playback = {
2326                         .stream_name = "AIF3 Playback",
2327                         .channels_min = 2,
2328                         .channels_max = 2,
2329                         .rates = WM8994_RATES,
2330                         .formats = WM8994_FORMATS,
2331                 },
2332                 .capture = {
2333                         .stream_name = "AIF3 Capture",
2334                         .channels_min = 2,
2335                         .channels_max = 2,
2336                         .rates = WM8994_RATES,
2337                         .formats = WM8994_FORMATS,
2338                 },
2339                 .ops = &wm8994_aif3_dai_ops,
2340         }
2341 };
2342
2343 #ifdef CONFIG_PM
2344 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2345 {
2346         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2347         int i, ret;
2348
2349         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2350                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2351                        sizeof(struct fll_config));
2352                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2353                 if (ret < 0)
2354                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2355                                  i + 1, ret);
2356         }
2357
2358         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2359
2360         return 0;
2361 }
2362
2363 static int wm8994_resume(struct snd_soc_codec *codec)
2364 {
2365         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2366         u16 *reg_cache = codec->reg_cache;
2367         int i, ret;
2368
2369         /* Restore the registers */
2370         for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
2371                 switch (i) {
2372                 case WM8994_LDO_1:
2373                 case WM8994_LDO_2:
2374                 case WM8994_SOFTWARE_RESET:
2375                         /* Handled by other MFD drivers */
2376                         continue;
2377                 default:
2378                         break;
2379                 }
2380
2381                 if (!wm8994_access_masks[i].writable)
2382                         continue;
2383
2384                 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
2385         }
2386
2387         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2388
2389         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2390                 if (!wm8994->fll_suspend[i].out)
2391                         continue;
2392
2393                 ret = _wm8994_set_fll(codec, i + 1,
2394                                      wm8994->fll_suspend[i].src,
2395                                      wm8994->fll_suspend[i].in,
2396                                      wm8994->fll_suspend[i].out);
2397                 if (ret < 0)
2398                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2399                                  i + 1, ret);
2400         }
2401
2402         return 0;
2403 }
2404 #else
2405 #define wm8994_suspend NULL
2406 #define wm8994_resume NULL
2407 #endif
2408
2409 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2410 {
2411         struct snd_soc_codec *codec = wm8994->codec;
2412         struct wm8994_pdata *pdata = wm8994->pdata;
2413         struct snd_kcontrol_new controls[] = {
2414                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2415                              wm8994->retune_mobile_enum,
2416                              wm8994_get_retune_mobile_enum,
2417                              wm8994_put_retune_mobile_enum),
2418                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2419                              wm8994->retune_mobile_enum,
2420                              wm8994_get_retune_mobile_enum,
2421                              wm8994_put_retune_mobile_enum),
2422                 SOC_ENUM_EXT("AIF2 EQ Mode",
2423                              wm8994->retune_mobile_enum,
2424                              wm8994_get_retune_mobile_enum,
2425                              wm8994_put_retune_mobile_enum),
2426         };
2427         int ret, i, j;
2428         const char **t;
2429
2430         /* We need an array of texts for the enum API but the number
2431          * of texts is likely to be less than the number of
2432          * configurations due to the sample rate dependency of the
2433          * configurations. */
2434         wm8994->num_retune_mobile_texts = 0;
2435         wm8994->retune_mobile_texts = NULL;
2436         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2437                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2438                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2439                                    wm8994->retune_mobile_texts[j]) == 0)
2440                                 break;
2441                 }
2442
2443                 if (j != wm8994->num_retune_mobile_texts)
2444                         continue;
2445
2446                 /* Expand the array... */
2447                 t = krealloc(wm8994->retune_mobile_texts,
2448                              sizeof(char *) *
2449                              (wm8994->num_retune_mobile_texts + 1),
2450                              GFP_KERNEL);
2451                 if (t == NULL)
2452                         continue;
2453
2454                 /* ...store the new entry... */
2455                 t[wm8994->num_retune_mobile_texts] =
2456                         pdata->retune_mobile_cfgs[i].name;
2457
2458                 /* ...and remember the new version. */
2459                 wm8994->num_retune_mobile_texts++;
2460                 wm8994->retune_mobile_texts = t;
2461         }
2462
2463         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2464                 wm8994->num_retune_mobile_texts);
2465
2466         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2467         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2468
2469         ret = snd_soc_add_controls(wm8994->codec, controls,
2470                                    ARRAY_SIZE(controls));
2471         if (ret != 0)
2472                 dev_err(wm8994->codec->dev,
2473                         "Failed to add ReTune Mobile controls: %d\n", ret);
2474 }
2475
2476 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2477 {
2478         struct snd_soc_codec *codec = wm8994->codec;
2479         struct wm8994_pdata *pdata = wm8994->pdata;
2480         int ret, i;
2481
2482         if (!pdata)
2483                 return;
2484
2485         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2486                                       pdata->lineout2_diff,
2487                                       pdata->lineout1fb,
2488                                       pdata->lineout2fb,
2489                                       pdata->jd_scthr,
2490                                       pdata->jd_thr,
2491                                       pdata->micbias1_lvl,
2492                                       pdata->micbias2_lvl);
2493
2494         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2495
2496         if (pdata->num_drc_cfgs) {
2497                 struct snd_kcontrol_new controls[] = {
2498                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2499                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2500                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2501                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2502                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2503                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2504                 };
2505
2506                 /* We need an array of texts for the enum API */
2507                 wm8994->drc_texts = kmalloc(sizeof(char *)
2508                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2509                 if (!wm8994->drc_texts) {
2510                         dev_err(wm8994->codec->dev,
2511                                 "Failed to allocate %d DRC config texts\n",
2512                                 pdata->num_drc_cfgs);
2513                         return;
2514                 }
2515
2516                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2517                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2518
2519                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2520                 wm8994->drc_enum.texts = wm8994->drc_texts;
2521
2522                 ret = snd_soc_add_controls(wm8994->codec, controls,
2523                                            ARRAY_SIZE(controls));
2524                 if (ret != 0)
2525                         dev_err(wm8994->codec->dev,
2526                                 "Failed to add DRC mode controls: %d\n", ret);
2527
2528                 for (i = 0; i < WM8994_NUM_DRC; i++)
2529                         wm8994_set_drc(codec, i);
2530         }
2531
2532         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2533                 pdata->num_retune_mobile_cfgs);
2534
2535         if (pdata->num_retune_mobile_cfgs)
2536                 wm8994_handle_retune_mobile_pdata(wm8994);
2537         else
2538                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2539                                      ARRAY_SIZE(wm8994_eq_controls));
2540 }
2541
2542 /**
2543  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2544  *
2545  * @codec:   WM8994 codec
2546  * @jack:    jack to report detection events on
2547  * @micbias: microphone bias to detect on
2548  * @det:     value to report for presence detection
2549  * @shrt:    value to report for short detection
2550  *
2551  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2552  * being used to bring out signals to the processor then only platform
2553  * data configuration is needed for WM8994 and processor GPIOs should
2554  * be configured using snd_soc_jack_add_gpios() instead.
2555  *
2556  * Configuration of detection levels is available via the micbias1_lvl
2557  * and micbias2_lvl platform data members.
2558  */
2559 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2560                       int micbias, int det, int shrt)
2561 {
2562         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2563         struct wm8994_micdet *micdet;
2564         struct wm8994 *control = codec->control_data;
2565         int reg;
2566
2567         if (control->type != WM8994)
2568                 return -EINVAL;
2569
2570         switch (micbias) {
2571         case 1:
2572                 micdet = &wm8994->micdet[0];
2573                 break;
2574         case 2:
2575                 micdet = &wm8994->micdet[1];
2576                 break;
2577         default:
2578                 return -EINVAL;
2579         }
2580
2581         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2582                 micbias, det, shrt);
2583
2584         /* Store the configuration */
2585         micdet->jack = jack;
2586         micdet->det = det;
2587         micdet->shrt = shrt;
2588
2589         /* If either of the jacks is set up then enable detection */
2590         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2591                 reg = WM8994_MICD_ENA;
2592         else
2593                 reg = 0;
2594
2595         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2596
2597         return 0;
2598 }
2599 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2600
2601 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2602 {
2603         struct wm8994_priv *priv = data;
2604         struct snd_soc_codec *codec = priv->codec;
2605         int reg;
2606         int report;
2607
2608         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2609         if (reg < 0) {
2610                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2611                         reg);
2612                 return IRQ_HANDLED;
2613         }
2614
2615         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2616
2617         report = 0;
2618         if (reg & WM8994_MIC1_DET_STS)
2619                 report |= priv->micdet[0].det;
2620         if (reg & WM8994_MIC1_SHRT_STS)
2621                 report |= priv->micdet[0].shrt;
2622         snd_soc_jack_report(priv->micdet[0].jack, report,
2623                             priv->micdet[0].det | priv->micdet[0].shrt);
2624
2625         report = 0;
2626         if (reg & WM8994_MIC2_DET_STS)
2627                 report |= priv->micdet[1].det;
2628         if (reg & WM8994_MIC2_SHRT_STS)
2629                 report |= priv->micdet[1].shrt;
2630         snd_soc_jack_report(priv->micdet[1].jack, report,
2631                             priv->micdet[1].det | priv->micdet[1].shrt);
2632
2633         return IRQ_HANDLED;
2634 }
2635
2636 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2637 {
2638         struct wm8994 *control;
2639         struct wm8994_priv *wm8994;
2640         struct snd_soc_dapm_context *dapm = &codec->dapm;
2641         int ret, i;
2642
2643         codec->control_data = dev_get_drvdata(codec->dev->parent);
2644         control = codec->control_data;
2645
2646         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2647         if (wm8994 == NULL)
2648                 return -ENOMEM;
2649         snd_soc_codec_set_drvdata(codec, wm8994);
2650
2651         codec->reg_cache = &wm8994->reg_cache;
2652
2653         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2654         wm8994->codec = codec;
2655
2656         /* Fill the cache with physical values we inherited; don't reset */
2657         ret = wm8994_bulk_read(codec->control_data, 0,
2658                                ARRAY_SIZE(wm8994->reg_cache) - 1,
2659                                codec->reg_cache);
2660         if (ret < 0) {
2661                 dev_err(codec->dev, "Failed to fill register cache: %d\n",
2662                         ret);
2663                 goto err;
2664         }
2665
2666         /* Clear the cached values for unreadable/volatile registers to
2667          * avoid potential confusion.
2668          */
2669         for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
2670                 if (wm8994_volatile(i) || !wm8994_readable(i))
2671                         wm8994->reg_cache[i] = 0;
2672
2673         /* Set revision-specific configuration */
2674         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2675         switch (control->type) {
2676         case WM8994:
2677                 switch (wm8994->revision) {
2678                 case 2:
2679                 case 3:
2680                         wm8994->hubs.dcs_codes = -5;
2681                         wm8994->hubs.hp_startup_mode = 1;
2682                         wm8994->hubs.dcs_readback_mode = 1;
2683                         break;
2684                 default:
2685                         wm8994->hubs.dcs_readback_mode = 1;
2686                         break;
2687                 }
2688
2689         case WM8958:
2690                 wm8994->hubs.dcs_readback_mode = 1;
2691                 break;
2692
2693         default:
2694                 break;
2695         }
2696
2697         switch (control->type) {
2698         case WM8994:
2699                 ret = wm8994_request_irq(codec->control_data,
2700                                          WM8994_IRQ_MIC1_DET,
2701                                          wm8994_mic_irq, "Mic 1 detect",
2702                                          wm8994);
2703                 if (ret != 0)
2704                         dev_warn(codec->dev,
2705                                  "Failed to request Mic1 detect IRQ: %d\n",
2706                                  ret);
2707
2708                 ret = wm8994_request_irq(codec->control_data,
2709                                          WM8994_IRQ_MIC1_SHRT,
2710                                          wm8994_mic_irq, "Mic 1 short",
2711                                          wm8994);
2712                 if (ret != 0)
2713                         dev_warn(codec->dev,
2714                                  "Failed to request Mic1 short IRQ: %d\n",
2715                                  ret);
2716
2717                 ret = wm8994_request_irq(codec->control_data,
2718                                          WM8994_IRQ_MIC2_DET,
2719                                          wm8994_mic_irq, "Mic 2 detect",
2720                                          wm8994);
2721                 if (ret != 0)
2722                         dev_warn(codec->dev,
2723                                  "Failed to request Mic2 detect IRQ: %d\n",
2724                                  ret);
2725
2726                 ret = wm8994_request_irq(codec->control_data,
2727                                          WM8994_IRQ_MIC2_SHRT,
2728                                          wm8994_mic_irq, "Mic 2 short",
2729                                          wm8994);
2730                 if (ret != 0)
2731                         dev_warn(codec->dev,
2732                                  "Failed to request Mic2 short IRQ: %d\n",
2733                                  ret);
2734                 break;
2735         }
2736
2737         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
2738          * configured on init - if a system wants to do this dynamically
2739          * at runtime we can deal with that then.
2740          */
2741         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2742         if (ret < 0) {
2743                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
2744                 goto err_irq;
2745         }
2746         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2747                 wm8994->lrclk_shared[0] = 1;
2748                 wm8994_dai[0].symmetric_rates = 1;
2749         } else {
2750                 wm8994->lrclk_shared[0] = 0;
2751         }
2752
2753         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2754         if (ret < 0) {
2755                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
2756                 goto err_irq;
2757         }
2758         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2759                 wm8994->lrclk_shared[1] = 1;
2760                 wm8994_dai[1].symmetric_rates = 1;
2761         } else {
2762                 wm8994->lrclk_shared[1] = 0;
2763         }
2764
2765         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2766
2767         /* Latch volume updates (right only; we always do left then right). */
2768         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
2769                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
2770         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
2771                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
2772         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
2773                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
2774         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
2775                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
2776         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
2777                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
2778         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
2779                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
2780         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
2781                             WM8994_DAC1_VU, WM8994_DAC1_VU);
2782         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
2783                             WM8994_DAC2_VU, WM8994_DAC2_VU);
2784
2785         /* Set the low bit of the 3D stereo depth so TLV matches */
2786         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
2787                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
2788                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
2789         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
2790                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
2791                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
2792         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
2793                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
2794                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
2795
2796         /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2797          * behaviour on idle TDM clock cycles. */
2798         snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
2799                             WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
2800
2801         wm8994_update_class_w(codec);
2802
2803         wm8994_handle_pdata(wm8994);
2804
2805         wm_hubs_add_analogue_controls(codec);
2806         snd_soc_add_controls(codec, wm8994_snd_controls,
2807                              ARRAY_SIZE(wm8994_snd_controls));
2808         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
2809                                   ARRAY_SIZE(wm8994_dapm_widgets));
2810
2811         switch (control->type) {
2812         case WM8994:
2813                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
2814                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
2815                 break;
2816         case WM8958:
2817                 snd_soc_add_controls(codec, wm8958_snd_controls,
2818                                      ARRAY_SIZE(wm8958_snd_controls));
2819                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
2820                                           ARRAY_SIZE(wm8958_dapm_widgets));
2821                 break;
2822         }
2823
2824
2825         wm_hubs_add_analogue_routes(codec, 0, 0);
2826         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
2827
2828         switch (control->type) {
2829         case WM8994:
2830                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
2831                                         ARRAY_SIZE(wm8994_intercon));
2832                 break;
2833         case WM8958:
2834                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
2835                                         ARRAY_SIZE(wm8958_intercon));
2836                 break;
2837         }
2838
2839         return 0;
2840
2841 err_irq:
2842         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2843         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2844         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2845         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
2846 err:
2847         kfree(wm8994);
2848         return ret;
2849 }
2850
2851 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
2852 {
2853         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2854         struct wm8994 *control = codec->control_data;
2855
2856         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2857
2858         switch (control->type) {
2859         case WM8994:
2860                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
2861                                 wm8994);
2862                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
2863                                 wm8994);
2864                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
2865                                 wm8994);
2866                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
2867                                 wm8994);
2868                 break;
2869         }
2870         kfree(wm8994->retune_mobile_texts);
2871         kfree(wm8994->drc_texts);
2872         kfree(wm8994);
2873
2874         return 0;
2875 }
2876
2877 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
2878         .probe =        wm8994_codec_probe,
2879         .remove =       wm8994_codec_remove,
2880         .suspend =      wm8994_suspend,
2881         .resume =       wm8994_resume,
2882         .read = wm8994_read,
2883         .write = wm8994_write,
2884         .readable_register = wm8994_readable,
2885         .volatile_register = wm8994_volatile,
2886         .set_bias_level = wm8994_set_bias_level,
2887 };
2888
2889 static int __devinit wm8994_probe(struct platform_device *pdev)
2890 {
2891         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
2892                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
2893 }
2894
2895 static int __devexit wm8994_remove(struct platform_device *pdev)
2896 {
2897         snd_soc_unregister_codec(&pdev->dev);
2898         return 0;
2899 }
2900
2901 static struct platform_driver wm8994_codec_driver = {
2902         .driver = {
2903                    .name = "wm8994-codec",
2904                    .owner = THIS_MODULE,
2905                    },
2906         .probe = wm8994_probe,
2907         .remove = __devexit_p(wm8994_remove),
2908 };
2909
2910 static __init int wm8994_init(void)
2911 {
2912         return platform_driver_register(&wm8994_codec_driver);
2913 }
2914 module_init(wm8994_init);
2915
2916 static __exit void wm8994_exit(void)
2917 {
2918         platform_driver_unregister(&wm8994_codec_driver);
2919 }
2920 module_exit(wm8994_exit);
2921
2922
2923 MODULE_DESCRIPTION("ASoC WM8994 driver");
2924 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2925 MODULE_LICENSE("GPL");
2926 MODULE_ALIAS("platform:wm8994-codec");