sound/soc/codecs/wm8962.c

   1 /*
   2  * wm8962.c  --  WM8962 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010-2 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/input.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/slab.h>
  27 #include <linux/workqueue.h>
  28 #include <sound/core.h>
  29 #include <sound/jack.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/soc.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <sound/wm8962.h>
  36 #include <trace/events/asoc.h>
  37
  38 #include "wm8962.h"
  39
  40 #define WM8962_NUM_SUPPLIES 8
  41 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  42         "DCVDD",
  43         "DBVDD",
  44         "AVDD",
  45         "CPVDD",
  46         "MICVDD",
  47         "PLLVDD",
  48         "SPKVDD1",
  49         "SPKVDD2",
  50 };
  51
  52 /* codec private data */
  53 struct wm8962_priv {
  54         struct wm8962_pdata pdata;
  55         struct regmap *regmap;
  56         struct snd_soc_codec *codec;
  57
  58         int sysclk;
  59         int sysclk_rate;
  60
  61         int bclk;  /* Desired BCLK */
  62         int lrclk;
  63
  64         struct completion fll_lock;
  65         int fll_src;
  66         int fll_fref;
  67         int fll_fout;
  68
  69         u16 dsp2_ena;
  70
  71         struct delayed_work mic_work;
  72         struct snd_soc_jack *jack;
  73
  74         struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  75         struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  76
  77 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  78         struct input_dev *beep;
  79         struct work_struct beep_work;
  80         int beep_rate;
  81 #endif
  82
  83 #ifdef CONFIG_GPIOLIB
  84         struct gpio_chip gpio_chip;
  85 #endif
  86
  87         int irq;
  88 };
  89
  90 /* We can't use the same notifier block for more than one supply and
  91  * there's no way I can see to get from a callback to the caller
  92  * except container_of().
  93  */
  94 #define WM8962_REGULATOR_EVENT(n) \
  95 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  96                                     unsigned long event, void *data)    \
  97 { \
  98         struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  99                                                   disable_nb[n]); \
 100         if (event & REGULATOR_EVENT_DISABLE) { \
 101                 regcache_mark_dirty(wm8962->regmap);    \
 102         } \
 103         return 0; \
 104 }
 105
 106 WM8962_REGULATOR_EVENT(0)
 107 WM8962_REGULATOR_EVENT(1)
 108 WM8962_REGULATOR_EVENT(2)
 109 WM8962_REGULATOR_EVENT(3)
 110 WM8962_REGULATOR_EVENT(4)
 111 WM8962_REGULATOR_EVENT(5)
 112 WM8962_REGULATOR_EVENT(6)
 113 WM8962_REGULATOR_EVENT(7)
 114
 115 static struct reg_default wm8962_reg[] = {
 116         { 0, 0x009F },   /* R0     - Left Input volume */
 117         { 1, 0x049F },   /* R1     - Right Input volume */
 118         { 2, 0x0000 },   /* R2     - HPOUTL volume */
 119         { 3, 0x0000 },   /* R3     - HPOUTR volume */
 120
 121         { 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
 122         { 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
 123         { 7, 0x000A },   /* R7     - Audio Interface 0 */
 124
 125         { 9, 0x0300 },   /* R9     - Audio Interface 1 */
 126         { 10, 0x00C0 },  /* R10    - Left DAC volume */
 127         { 11, 0x00C0 },  /* R11    - Right DAC volume */
 128
 129         { 14, 0x0040 },   /* R14    - Audio Interface 2 */
 130         { 15, 0x6243 },   /* R15    - Software Reset */
 131
 132         { 17, 0x007B },   /* R17    - ALC1 */
 133
 134         { 19, 0x1C32 },   /* R19    - ALC3 */
 135         { 20, 0x3200 },   /* R20    - Noise Gate */
 136         { 21, 0x00C0 },   /* R21    - Left ADC volume */
 137         { 22, 0x00C0 },   /* R22    - Right ADC volume */
 138         { 23, 0x0160 },   /* R23    - Additional control(1) */
 139         { 24, 0x0000 },   /* R24    - Additional control(2) */
 140         { 25, 0x0000 },   /* R25    - Pwr Mgmt (1) */
 141         { 26, 0x0000 },   /* R26    - Pwr Mgmt (2) */
 142         { 27, 0x0010 },   /* R27    - Additional Control (3) */
 143         { 28, 0x0000 },   /* R28    - Anti-pop */
 144
 145         { 30, 0x005E },   /* R30    - Clocking 3 */
 146         { 31, 0x0000 },   /* R31    - Input mixer control (1) */
 147         { 32, 0x0145 },   /* R32    - Left input mixer volume */
 148         { 33, 0x0145 },   /* R33    - Right input mixer volume */
 149         { 34, 0x0009 },   /* R34    - Input mixer control (2) */
 150         { 35, 0x0003 },   /* R35    - Input bias control */
 151         { 37, 0x0008 },   /* R37    - Left input PGA control */
 152         { 38, 0x0008 },   /* R38    - Right input PGA control */
 153
 154         { 40, 0x0000 },   /* R40    - SPKOUTL volume */
 155         { 41, 0x0000 },   /* R41    - SPKOUTR volume */
 156
 157         { 51, 0x0003 },   /* R51    - Class D Control 2 */
 158
 159         { 56, 0x0506 },   /* R56    - Clocking 4 */
 160         { 57, 0x0000 },   /* R57    - DAC DSP Mixing (1) */
 161         { 58, 0x0000 },   /* R58    - DAC DSP Mixing (2) */
 162
 163         { 60, 0x0300 },   /* R60    - DC Servo 0 */
 164         { 61, 0x0300 },   /* R61    - DC Servo 1 */
 165
 166         { 64, 0x0810 },   /* R64    - DC Servo 4 */
 167
 168         { 68, 0x001B },   /* R68    - Analogue PGA Bias */
 169         { 69, 0x0000 },   /* R69    - Analogue HP 0 */
 170
 171         { 71, 0x01FB },   /* R71    - Analogue HP 2 */
 172         { 72, 0x0000 },   /* R72    - Charge Pump 1 */
 173
 174         { 82, 0x0004 },   /* R82    - Charge Pump B */
 175
 176         { 87, 0x0000 },   /* R87    - Write Sequencer Control 1 */
 177
 178         { 90, 0x0000 },   /* R90    - Write Sequencer Control 2 */
 179
 180         { 93, 0x0000 },   /* R93    - Write Sequencer Control 3 */
 181         { 94, 0x0000 },   /* R94    - Control Interface */
 182
 183         { 99, 0x0000 },   /* R99    - Mixer Enables */
 184         { 100, 0x0000 },   /* R100   - Headphone Mixer (1) */
 185         { 101, 0x0000 },   /* R101   - Headphone Mixer (2) */
 186         { 102, 0x013F },   /* R102   - Headphone Mixer (3) */
 187         { 103, 0x013F },   /* R103   - Headphone Mixer (4) */
 188
 189         { 105, 0x0000 },   /* R105   - Speaker Mixer (1) */
 190         { 106, 0x0000 },   /* R106   - Speaker Mixer (2) */
 191         { 107, 0x013F },   /* R107   - Speaker Mixer (3) */
 192         { 108, 0x013F },   /* R108   - Speaker Mixer (4) */
 193         { 109, 0x0003 },   /* R109   - Speaker Mixer (5) */
 194         { 110, 0x0002 },   /* R110   - Beep Generator (1) */
 195
 196         { 115, 0x0006 },   /* R115   - Oscillator Trim (3) */
 197         { 116, 0x0026 },   /* R116   - Oscillator Trim (4) */
 198
 199         { 119, 0x0000 },   /* R119   - Oscillator Trim (7) */
 200
 201         { 124, 0x0011 },   /* R124   - Analogue Clocking1 */
 202         { 125, 0x004B },   /* R125   - Analogue Clocking2 */
 203         { 126, 0x000D },   /* R126   - Analogue Clocking3 */
 204         { 127, 0x0000 },   /* R127   - PLL Software Reset */
 205
 206         { 131, 0x0000 },   /* R131   - PLL 4 */
 207
 208         { 136, 0x0067 },   /* R136   - PLL 9 */
 209         { 137, 0x001C },   /* R137   - PLL 10 */
 210         { 138, 0x0071 },   /* R138   - PLL 11 */
 211         { 139, 0x00C7 },   /* R139   - PLL 12 */
 212         { 140, 0x0067 },   /* R140   - PLL 13 */
 213         { 141, 0x0048 },   /* R141   - PLL 14 */
 214         { 142, 0x0022 },   /* R142   - PLL 15 */
 215         { 143, 0x0097 },   /* R143   - PLL 16 */
 216
 217         { 155, 0x000C },   /* R155   - FLL Control (1) */
 218         { 156, 0x0039 },   /* R156   - FLL Control (2) */
 219         { 157, 0x0180 },   /* R157   - FLL Control (3) */
 220
 221         { 159, 0x0032 },   /* R159   - FLL Control (5) */
 222         { 160, 0x0018 },   /* R160   - FLL Control (6) */
 223         { 161, 0x007D },   /* R161   - FLL Control (7) */
 224         { 162, 0x0008 },   /* R162   - FLL Control (8) */
 225
 226         { 252, 0x0005 },   /* R252   - General test 1 */
 227
 228         { 256, 0x0000 },   /* R256   - DF1 */
 229         { 257, 0x0000 },   /* R257   - DF2 */
 230         { 258, 0x0000 },   /* R258   - DF3 */
 231         { 259, 0x0000 },   /* R259   - DF4 */
 232         { 260, 0x0000 },   /* R260   - DF5 */
 233         { 261, 0x0000 },   /* R261   - DF6 */
 234         { 262, 0x0000 },   /* R262   - DF7 */
 235
 236         { 264, 0x0000 },   /* R264   - LHPF1 */
 237         { 265, 0x0000 },   /* R265   - LHPF2 */
 238
 239         { 268, 0x0000 },   /* R268   - THREED1 */
 240         { 269, 0x0000 },   /* R269   - THREED2 */
 241         { 270, 0x0000 },   /* R270   - THREED3 */
 242         { 271, 0x0000 },   /* R271   - THREED4 */
 243
 244         { 276, 0x000C },   /* R276   - DRC 1 */
 245         { 277, 0x0925 },   /* R277   - DRC 2 */
 246         { 278, 0x0000 },   /* R278   - DRC 3 */
 247         { 279, 0x0000 },   /* R279   - DRC 4 */
 248         { 280, 0x0000 },   /* R280   - DRC 5 */
 249
 250         { 285, 0x0000 },   /* R285   - Tloopback */
 251
 252         { 335, 0x0004 },   /* R335   - EQ1 */
 253         { 336, 0x6318 },   /* R336   - EQ2 */
 254         { 337, 0x6300 },   /* R337   - EQ3 */
 255         { 338, 0x0FCA },   /* R338   - EQ4 */
 256         { 339, 0x0400 },   /* R339   - EQ5 */
 257         { 340, 0x00D8 },   /* R340   - EQ6 */
 258         { 341, 0x1EB5 },   /* R341   - EQ7 */
 259         { 342, 0xF145 },   /* R342   - EQ8 */
 260         { 343, 0x0B75 },   /* R343   - EQ9 */
 261         { 344, 0x01C5 },   /* R344   - EQ10 */
 262         { 345, 0x1C58 },   /* R345   - EQ11 */
 263         { 346, 0xF373 },   /* R346   - EQ12 */
 264         { 347, 0x0A54 },   /* R347   - EQ13 */
 265         { 348, 0x0558 },   /* R348   - EQ14 */
 266         { 349, 0x168E },   /* R349   - EQ15 */
 267         { 350, 0xF829 },   /* R350   - EQ16 */
 268         { 351, 0x07AD },   /* R351   - EQ17 */
 269         { 352, 0x1103 },   /* R352   - EQ18 */
 270         { 353, 0x0564 },   /* R353   - EQ19 */
 271         { 354, 0x0559 },   /* R354   - EQ20 */
 272         { 355, 0x4000 },   /* R355   - EQ21 */
 273         { 356, 0x6318 },   /* R356   - EQ22 */
 274         { 357, 0x6300 },   /* R357   - EQ23 */
 275         { 358, 0x0FCA },   /* R358   - EQ24 */
 276         { 359, 0x0400 },   /* R359   - EQ25 */
 277         { 360, 0x00D8 },   /* R360   - EQ26 */
 278         { 361, 0x1EB5 },   /* R361   - EQ27 */
 279         { 362, 0xF145 },   /* R362   - EQ28 */
 280         { 363, 0x0B75 },   /* R363   - EQ29 */
 281         { 364, 0x01C5 },   /* R364   - EQ30 */
 282         { 365, 0x1C58 },   /* R365   - EQ31 */
 283         { 366, 0xF373 },   /* R366   - EQ32 */
 284         { 367, 0x0A54 },   /* R367   - EQ33 */
 285         { 368, 0x0558 },   /* R368   - EQ34 */
 286         { 369, 0x168E },   /* R369   - EQ35 */
 287         { 370, 0xF829 },   /* R370   - EQ36 */
 288         { 371, 0x07AD },   /* R371   - EQ37 */
 289         { 372, 0x1103 },   /* R372   - EQ38 */
 290         { 373, 0x0564 },   /* R373   - EQ39 */
 291         { 374, 0x0559 },   /* R374   - EQ40 */
 292         { 375, 0x4000 },   /* R375   - EQ41 */
 293
 294         { 513, 0x0000 },   /* R513   - GPIO 2 */
 295         { 514, 0x0000 },   /* R514   - GPIO 3 */
 296
 297         { 516, 0x8100 },   /* R516   - GPIO 5 */
 298         { 517, 0x8100 },   /* R517   - GPIO 6 */
 299
 300         { 568, 0x0030 },   /* R568   - Interrupt Status 1 Mask */
 301         { 569, 0xFFED },   /* R569   - Interrupt Status 2 Mask */
 302
 303         { 576, 0x0000 },   /* R576   - Interrupt Control */
 304
 305         { 584, 0x002D },   /* R584   - IRQ Debounce */
 306
 307         { 586, 0x0000 },   /* R586   -  MICINT Source Pol */
 308
 309         { 768, 0x1C00 },   /* R768   - DSP2 Power Management */
 310
 311         { 8192, 0x0000 },   /* R8192  - DSP2 Instruction RAM 0 */
 312
 313         { 9216, 0x0030 },   /* R9216  - DSP2 Address RAM 2 */
 314         { 9217, 0x0000 },   /* R9217  - DSP2 Address RAM 1 */
 315         { 9218, 0x0000 },   /* R9218  - DSP2 Address RAM 0 */
 316
 317         { 12288, 0x0000 },   /* R12288 - DSP2 Data1 RAM 1 */
 318         { 12289, 0x0000 },   /* R12289 - DSP2 Data1 RAM 0 */
 319
 320         { 13312, 0x0000 },   /* R13312 - DSP2 Data2 RAM 1 */
 321         { 13313, 0x0000 },   /* R13313 - DSP2 Data2 RAM 0 */
 322
 323         { 14336, 0x0000 },   /* R14336 - DSP2 Data3 RAM 1 */
 324         { 14337, 0x0000 },   /* R14337 - DSP2 Data3 RAM 0 */
 325
 326         { 15360, 0x000A },   /* R15360 - DSP2 Coeff RAM 0 */
 327
 328         { 16384, 0x0000 },   /* R16384 - RETUNEADC_SHARED_COEFF_1 */
 329         { 16385, 0x0000 },   /* R16385 - RETUNEADC_SHARED_COEFF_0 */
 330         { 16386, 0x0000 },   /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
 331         { 16387, 0x0000 },   /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
 332         { 16388, 0x0000 },   /* R16388 - SOUNDSTAGE_ENABLES_1 */
 333         { 16389, 0x0000 },   /* R16389 - SOUNDSTAGE_ENABLES_0 */
 334
 335         { 16896, 0x0002 },   /* R16896 - HDBASS_AI_1 */
 336         { 16897, 0xBD12 },   /* R16897 - HDBASS_AI_0 */
 337         { 16898, 0x007C },   /* R16898 - HDBASS_AR_1 */
 338         { 16899, 0x586C },   /* R16899 - HDBASS_AR_0 */
 339         { 16900, 0x0053 },   /* R16900 - HDBASS_B_1 */
 340         { 16901, 0x8121 },   /* R16901 - HDBASS_B_0 */
 341         { 16902, 0x003F },   /* R16902 - HDBASS_K_1 */
 342         { 16903, 0x8BD8 },   /* R16903 - HDBASS_K_0 */
 343         { 16904, 0x0032 },   /* R16904 - HDBASS_N1_1 */
 344         { 16905, 0xF52D },   /* R16905 - HDBASS_N1_0 */
 345         { 16906, 0x0065 },   /* R16906 - HDBASS_N2_1 */
 346         { 16907, 0xAC8C },   /* R16907 - HDBASS_N2_0 */
 347         { 16908, 0x006B },   /* R16908 - HDBASS_N3_1 */
 348         { 16909, 0xE087 },   /* R16909 - HDBASS_N3_0 */
 349         { 16910, 0x0072 },   /* R16910 - HDBASS_N4_1 */
 350         { 16911, 0x1483 },   /* R16911 - HDBASS_N4_0 */
 351         { 16912, 0x0072 },   /* R16912 - HDBASS_N5_1 */
 352         { 16913, 0x1483 },   /* R16913 - HDBASS_N5_0 */
 353         { 16914, 0x0043 },   /* R16914 - HDBASS_X1_1 */
 354         { 16915, 0x3525 },   /* R16915 - HDBASS_X1_0 */
 355         { 16916, 0x0006 },   /* R16916 - HDBASS_X2_1 */
 356         { 16917, 0x6A4A },   /* R16917 - HDBASS_X2_0 */
 357         { 16918, 0x0043 },   /* R16918 - HDBASS_X3_1 */
 358         { 16919, 0x6079 },   /* R16919 - HDBASS_X3_0 */
 359         { 16920, 0x0008 },   /* R16920 - HDBASS_ATK_1 */
 360         { 16921, 0x0000 },   /* R16921 - HDBASS_ATK_0 */
 361         { 16922, 0x0001 },   /* R16922 - HDBASS_DCY_1 */
 362         { 16923, 0x0000 },   /* R16923 - HDBASS_DCY_0 */
 363         { 16924, 0x0059 },   /* R16924 - HDBASS_PG_1 */
 364         { 16925, 0x999A },   /* R16925 - HDBASS_PG_0 */
 365
 366         { 17048, 0x0083 },   /* R17408 - HPF_C_1 */
 367         { 17049, 0x98AD },   /* R17409 - HPF_C_0 */
 368
 369         { 17920, 0x007F },   /* R17920 - ADCL_RETUNE_C1_1 */
 370         { 17921, 0xFFFF },   /* R17921 - ADCL_RETUNE_C1_0 */
 371         { 17922, 0x0000 },   /* R17922 - ADCL_RETUNE_C2_1 */
 372         { 17923, 0x0000 },   /* R17923 - ADCL_RETUNE_C2_0 */
 373         { 17924, 0x0000 },   /* R17924 - ADCL_RETUNE_C3_1 */
 374         { 17925, 0x0000 },   /* R17925 - ADCL_RETUNE_C3_0 */
 375         { 17926, 0x0000 },   /* R17926 - ADCL_RETUNE_C4_1 */
 376         { 17927, 0x0000 },   /* R17927 - ADCL_RETUNE_C4_0 */
 377         { 17928, 0x0000 },   /* R17928 - ADCL_RETUNE_C5_1 */
 378         { 17929, 0x0000 },   /* R17929 - ADCL_RETUNE_C5_0 */
 379         { 17930, 0x0000 },   /* R17930 - ADCL_RETUNE_C6_1 */
 380         { 17931, 0x0000 },   /* R17931 - ADCL_RETUNE_C6_0 */
 381         { 17932, 0x0000 },   /* R17932 - ADCL_RETUNE_C7_1 */
 382         { 17933, 0x0000 },   /* R17933 - ADCL_RETUNE_C7_0 */
 383         { 17934, 0x0000 },   /* R17934 - ADCL_RETUNE_C8_1 */
 384         { 17935, 0x0000 },   /* R17935 - ADCL_RETUNE_C8_0 */
 385         { 17936, 0x0000 },   /* R17936 - ADCL_RETUNE_C9_1 */
 386         { 17937, 0x0000 },   /* R17937 - ADCL_RETUNE_C9_0 */
 387         { 17938, 0x0000 },   /* R17938 - ADCL_RETUNE_C10_1 */
 388         { 17939, 0x0000 },   /* R17939 - ADCL_RETUNE_C10_0 */
 389         { 17940, 0x0000 },   /* R17940 - ADCL_RETUNE_C11_1 */
 390         { 17941, 0x0000 },   /* R17941 - ADCL_RETUNE_C11_0 */
 391         { 17942, 0x0000 },   /* R17942 - ADCL_RETUNE_C12_1 */
 392         { 17943, 0x0000 },   /* R17943 - ADCL_RETUNE_C12_0 */
 393         { 17944, 0x0000 },   /* R17944 - ADCL_RETUNE_C13_1 */
 394         { 17945, 0x0000 },   /* R17945 - ADCL_RETUNE_C13_0 */
 395         { 17946, 0x0000 },   /* R17946 - ADCL_RETUNE_C14_1 */
 396         { 17947, 0x0000 },   /* R17947 - ADCL_RETUNE_C14_0 */
 397         { 17948, 0x0000 },   /* R17948 - ADCL_RETUNE_C15_1 */
 398         { 17949, 0x0000 },   /* R17949 - ADCL_RETUNE_C15_0 */
 399         { 17950, 0x0000 },   /* R17950 - ADCL_RETUNE_C16_1 */
 400         { 17951, 0x0000 },   /* R17951 - ADCL_RETUNE_C16_0 */
 401         { 17952, 0x0000 },   /* R17952 - ADCL_RETUNE_C17_1 */
 402         { 17953, 0x0000 },   /* R17953 - ADCL_RETUNE_C17_0 */
 403         { 17954, 0x0000 },   /* R17954 - ADCL_RETUNE_C18_1 */
 404         { 17955, 0x0000 },   /* R17955 - ADCL_RETUNE_C18_0 */
 405         { 17956, 0x0000 },   /* R17956 - ADCL_RETUNE_C19_1 */
 406         { 17957, 0x0000 },   /* R17957 - ADCL_RETUNE_C19_0 */
 407         { 17958, 0x0000 },   /* R17958 - ADCL_RETUNE_C20_1 */
 408         { 17959, 0x0000 },   /* R17959 - ADCL_RETUNE_C20_0 */
 409         { 17960, 0x0000 },   /* R17960 - ADCL_RETUNE_C21_1 */
 410         { 17961, 0x0000 },   /* R17961 - ADCL_RETUNE_C21_0 */
 411         { 17962, 0x0000 },   /* R17962 - ADCL_RETUNE_C22_1 */
 412         { 17963, 0x0000 },   /* R17963 - ADCL_RETUNE_C22_0 */
 413         { 17964, 0x0000 },   /* R17964 - ADCL_RETUNE_C23_1 */
 414         { 17965, 0x0000 },   /* R17965 - ADCL_RETUNE_C23_0 */
 415         { 17966, 0x0000 },   /* R17966 - ADCL_RETUNE_C24_1 */
 416         { 17967, 0x0000 },   /* R17967 - ADCL_RETUNE_C24_0 */
 417         { 17968, 0x0000 },   /* R17968 - ADCL_RETUNE_C25_1 */
 418         { 17969, 0x0000 },   /* R17969 - ADCL_RETUNE_C25_0 */
 419         { 17970, 0x0000 },   /* R17970 - ADCL_RETUNE_C26_1 */
 420         { 17971, 0x0000 },   /* R17971 - ADCL_RETUNE_C26_0 */
 421         { 17972, 0x0000 },   /* R17972 - ADCL_RETUNE_C27_1 */
 422         { 17973, 0x0000 },   /* R17973 - ADCL_RETUNE_C27_0 */
 423         { 17974, 0x0000 },   /* R17974 - ADCL_RETUNE_C28_1 */
 424         { 17975, 0x0000 },   /* R17975 - ADCL_RETUNE_C28_0 */
 425         { 17976, 0x0000 },   /* R17976 - ADCL_RETUNE_C29_1 */
 426         { 17977, 0x0000 },   /* R17977 - ADCL_RETUNE_C29_0 */
 427         { 17978, 0x0000 },   /* R17978 - ADCL_RETUNE_C30_1 */
 428         { 17979, 0x0000 },   /* R17979 - ADCL_RETUNE_C30_0 */
 429         { 17980, 0x0000 },   /* R17980 - ADCL_RETUNE_C31_1 */
 430         { 17981, 0x0000 },   /* R17981 - ADCL_RETUNE_C31_0 */
 431         { 17982, 0x0000 },   /* R17982 - ADCL_RETUNE_C32_1 */
 432         { 17983, 0x0000 },   /* R17983 - ADCL_RETUNE_C32_0 */
 433
 434         { 18432, 0x0020 },   /* R18432 - RETUNEADC_PG2_1 */
 435         { 18433, 0x0000 },   /* R18433 - RETUNEADC_PG2_0 */
 436         { 18434, 0x0040 },   /* R18434 - RETUNEADC_PG_1 */
 437         { 18435, 0x0000 },   /* R18435 - RETUNEADC_PG_0 */
 438
 439         { 18944, 0x007F },   /* R18944 - ADCR_RETUNE_C1_1 */
 440         { 18945, 0xFFFF },   /* R18945 - ADCR_RETUNE_C1_0 */
 441         { 18946, 0x0000 },   /* R18946 - ADCR_RETUNE_C2_1 */
 442         { 18947, 0x0000 },   /* R18947 - ADCR_RETUNE_C2_0 */
 443         { 18948, 0x0000 },   /* R18948 - ADCR_RETUNE_C3_1 */
 444         { 18949, 0x0000 },   /* R18949 - ADCR_RETUNE_C3_0 */
 445         { 18950, 0x0000 },   /* R18950 - ADCR_RETUNE_C4_1 */
 446         { 18951, 0x0000 },   /* R18951 - ADCR_RETUNE_C4_0 */
 447         { 18952, 0x0000 },   /* R18952 - ADCR_RETUNE_C5_1 */
 448         { 18953, 0x0000 },   /* R18953 - ADCR_RETUNE_C5_0 */
 449         { 18954, 0x0000 },   /* R18954 - ADCR_RETUNE_C6_1 */
 450         { 18955, 0x0000 },   /* R18955 - ADCR_RETUNE_C6_0 */
 451         { 18956, 0x0000 },   /* R18956 - ADCR_RETUNE_C7_1 */
 452         { 18957, 0x0000 },   /* R18957 - ADCR_RETUNE_C7_0 */
 453         { 18958, 0x0000 },   /* R18958 - ADCR_RETUNE_C8_1 */
 454         { 18959, 0x0000 },   /* R18959 - ADCR_RETUNE_C8_0 */
 455         { 18960, 0x0000 },   /* R18960 - ADCR_RETUNE_C9_1 */
 456         { 18961, 0x0000 },   /* R18961 - ADCR_RETUNE_C9_0 */
 457         { 18962, 0x0000 },   /* R18962 - ADCR_RETUNE_C10_1 */
 458         { 18963, 0x0000 },   /* R18963 - ADCR_RETUNE_C10_0 */
 459         { 18964, 0x0000 },   /* R18964 - ADCR_RETUNE_C11_1 */
 460         { 18965, 0x0000 },   /* R18965 - ADCR_RETUNE_C11_0 */
 461         { 18966, 0x0000 },   /* R18966 - ADCR_RETUNE_C12_1 */
 462         { 18967, 0x0000 },   /* R18967 - ADCR_RETUNE_C12_0 */
 463         { 18968, 0x0000 },   /* R18968 - ADCR_RETUNE_C13_1 */
 464         { 18969, 0x0000 },   /* R18969 - ADCR_RETUNE_C13_0 */
 465         { 18970, 0x0000 },   /* R18970 - ADCR_RETUNE_C14_1 */
 466         { 18971, 0x0000 },   /* R18971 - ADCR_RETUNE_C14_0 */
 467         { 18972, 0x0000 },   /* R18972 - ADCR_RETUNE_C15_1 */
 468         { 18973, 0x0000 },   /* R18973 - ADCR_RETUNE_C15_0 */
 469         { 18974, 0x0000 },   /* R18974 - ADCR_RETUNE_C16_1 */
 470         { 18975, 0x0000 },   /* R18975 - ADCR_RETUNE_C16_0 */
 471         { 18976, 0x0000 },   /* R18976 - ADCR_RETUNE_C17_1 */
 472         { 18977, 0x0000 },   /* R18977 - ADCR_RETUNE_C17_0 */
 473         { 18978, 0x0000 },   /* R18978 - ADCR_RETUNE_C18_1 */
 474         { 18979, 0x0000 },   /* R18979 - ADCR_RETUNE_C18_0 */
 475         { 18980, 0x0000 },   /* R18980 - ADCR_RETUNE_C19_1 */
 476         { 18981, 0x0000 },   /* R18981 - ADCR_RETUNE_C19_0 */
 477         { 18982, 0x0000 },   /* R18982 - ADCR_RETUNE_C20_1 */
 478         { 18983, 0x0000 },   /* R18983 - ADCR_RETUNE_C20_0 */
 479         { 18984, 0x0000 },   /* R18984 - ADCR_RETUNE_C21_1 */
 480         { 18985, 0x0000 },   /* R18985 - ADCR_RETUNE_C21_0 */
 481         { 18986, 0x0000 },   /* R18986 - ADCR_RETUNE_C22_1 */
 482         { 18987, 0x0000 },   /* R18987 - ADCR_RETUNE_C22_0 */
 483         { 18988, 0x0000 },   /* R18988 - ADCR_RETUNE_C23_1 */
 484         { 18989, 0x0000 },   /* R18989 - ADCR_RETUNE_C23_0 */
 485         { 18990, 0x0000 },   /* R18990 - ADCR_RETUNE_C24_1 */
 486         { 18991, 0x0000 },   /* R18991 - ADCR_RETUNE_C24_0 */
 487         { 18992, 0x0000 },   /* R18992 - ADCR_RETUNE_C25_1 */
 488         { 18993, 0x0000 },   /* R18993 - ADCR_RETUNE_C25_0 */
 489         { 18994, 0x0000 },   /* R18994 - ADCR_RETUNE_C26_1 */
 490         { 18995, 0x0000 },   /* R18995 - ADCR_RETUNE_C26_0 */
 491         { 18996, 0x0000 },   /* R18996 - ADCR_RETUNE_C27_1 */
 492         { 18997, 0x0000 },   /* R18997 - ADCR_RETUNE_C27_0 */
 493         { 18998, 0x0000 },   /* R18998 - ADCR_RETUNE_C28_1 */
 494         { 18999, 0x0000 },   /* R18999 - ADCR_RETUNE_C28_0 */
 495         { 19000, 0x0000 },   /* R19000 - ADCR_RETUNE_C29_1 */
 496         { 19001, 0x0000 },   /* R19001 - ADCR_RETUNE_C29_0 */
 497         { 19002, 0x0000 },   /* R19002 - ADCR_RETUNE_C30_1 */
 498         { 19003, 0x0000 },   /* R19003 - ADCR_RETUNE_C30_0 */
 499         { 19004, 0x0000 },   /* R19004 - ADCR_RETUNE_C31_1 */
 500         { 19005, 0x0000 },   /* R19005 - ADCR_RETUNE_C31_0 */
 501         { 19006, 0x0000 },   /* R19006 - ADCR_RETUNE_C32_1 */
 502         { 19007, 0x0000 },   /* R19007 - ADCR_RETUNE_C32_0 */
 503
 504         { 19456, 0x007F },   /* R19456 - DACL_RETUNE_C1_1 */
 505         { 19457, 0xFFFF },   /* R19457 - DACL_RETUNE_C1_0 */
 506         { 19458, 0x0000 },   /* R19458 - DACL_RETUNE_C2_1 */
 507         { 19459, 0x0000 },   /* R19459 - DACL_RETUNE_C2_0 */
 508         { 19460, 0x0000 },   /* R19460 - DACL_RETUNE_C3_1 */
 509         { 19461, 0x0000 },   /* R19461 - DACL_RETUNE_C3_0 */
 510         { 19462, 0x0000 },   /* R19462 - DACL_RETUNE_C4_1 */
 511         { 19463, 0x0000 },   /* R19463 - DACL_RETUNE_C4_0 */
 512         { 19464, 0x0000 },   /* R19464 - DACL_RETUNE_C5_1 */
 513         { 19465, 0x0000 },   /* R19465 - DACL_RETUNE_C5_0 */
 514         { 19466, 0x0000 },   /* R19466 - DACL_RETUNE_C6_1 */
 515         { 19467, 0x0000 },   /* R19467 - DACL_RETUNE_C6_0 */
 516         { 19468, 0x0000 },   /* R19468 - DACL_RETUNE_C7_1 */
 517         { 19469, 0x0000 },   /* R19469 - DACL_RETUNE_C7_0 */
 518         { 19470, 0x0000 },   /* R19470 - DACL_RETUNE_C8_1 */
 519         { 19471, 0x0000 },   /* R19471 - DACL_RETUNE_C8_0 */
 520         { 19472, 0x0000 },   /* R19472 - DACL_RETUNE_C9_1 */
 521         { 19473, 0x0000 },   /* R19473 - DACL_RETUNE_C9_0 */
 522         { 19474, 0x0000 },   /* R19474 - DACL_RETUNE_C10_1 */
 523         { 19475, 0x0000 },   /* R19475 - DACL_RETUNE_C10_0 */
 524         { 19476, 0x0000 },   /* R19476 - DACL_RETUNE_C11_1 */
 525         { 19477, 0x0000 },   /* R19477 - DACL_RETUNE_C11_0 */
 526         { 19478, 0x0000 },   /* R19478 - DACL_RETUNE_C12_1 */
 527         { 19479, 0x0000 },   /* R19479 - DACL_RETUNE_C12_0 */
 528         { 19480, 0x0000 },   /* R19480 - DACL_RETUNE_C13_1 */
 529         { 19481, 0x0000 },   /* R19481 - DACL_RETUNE_C13_0 */
 530         { 19482, 0x0000 },   /* R19482 - DACL_RETUNE_C14_1 */
 531         { 19483, 0x0000 },   /* R19483 - DACL_RETUNE_C14_0 */
 532         { 19484, 0x0000 },   /* R19484 - DACL_RETUNE_C15_1 */
 533         { 19485, 0x0000 },   /* R19485 - DACL_RETUNE_C15_0 */
 534         { 19486, 0x0000 },   /* R19486 - DACL_RETUNE_C16_1 */
 535         { 19487, 0x0000 },   /* R19487 - DACL_RETUNE_C16_0 */
 536         { 19488, 0x0000 },   /* R19488 - DACL_RETUNE_C17_1 */
 537         { 19489, 0x0000 },   /* R19489 - DACL_RETUNE_C17_0 */
 538         { 19490, 0x0000 },   /* R19490 - DACL_RETUNE_C18_1 */
 539         { 19491, 0x0000 },   /* R19491 - DACL_RETUNE_C18_0 */
 540         { 19492, 0x0000 },   /* R19492 - DACL_RETUNE_C19_1 */
 541         { 19493, 0x0000 },   /* R19493 - DACL_RETUNE_C19_0 */
 542         { 19494, 0x0000 },   /* R19494 - DACL_RETUNE_C20_1 */
 543         { 19495, 0x0000 },   /* R19495 - DACL_RETUNE_C20_0 */
 544         { 19496, 0x0000 },   /* R19496 - DACL_RETUNE_C21_1 */
 545         { 19497, 0x0000 },   /* R19497 - DACL_RETUNE_C21_0 */
 546         { 19498, 0x0000 },   /* R19498 - DACL_RETUNE_C22_1 */
 547         { 19499, 0x0000 },   /* R19499 - DACL_RETUNE_C22_0 */
 548         { 19500, 0x0000 },   /* R19500 - DACL_RETUNE_C23_1 */
 549         { 19501, 0x0000 },   /* R19501 - DACL_RETUNE_C23_0 */
 550         { 19502, 0x0000 },   /* R19502 - DACL_RETUNE_C24_1 */
 551         { 19503, 0x0000 },   /* R19503 - DACL_RETUNE_C24_0 */
 552         { 19504, 0x0000 },   /* R19504 - DACL_RETUNE_C25_1 */
 553         { 19505, 0x0000 },   /* R19505 - DACL_RETUNE_C25_0 */
 554         { 19506, 0x0000 },   /* R19506 - DACL_RETUNE_C26_1 */
 555         { 19507, 0x0000 },   /* R19507 - DACL_RETUNE_C26_0 */
 556         { 19508, 0x0000 },   /* R19508 - DACL_RETUNE_C27_1 */
 557         { 19509, 0x0000 },   /* R19509 - DACL_RETUNE_C27_0 */
 558         { 19510, 0x0000 },   /* R19510 - DACL_RETUNE_C28_1 */
 559         { 19511, 0x0000 },   /* R19511 - DACL_RETUNE_C28_0 */
 560         { 19512, 0x0000 },   /* R19512 - DACL_RETUNE_C29_1 */
 561         { 19513, 0x0000 },   /* R19513 - DACL_RETUNE_C29_0 */
 562         { 19514, 0x0000 },   /* R19514 - DACL_RETUNE_C30_1 */
 563         { 19515, 0x0000 },   /* R19515 - DACL_RETUNE_C30_0 */
 564         { 19516, 0x0000 },   /* R19516 - DACL_RETUNE_C31_1 */
 565         { 19517, 0x0000 },   /* R19517 - DACL_RETUNE_C31_0 */
 566         { 19518, 0x0000 },   /* R19518 - DACL_RETUNE_C32_1 */
 567         { 19519, 0x0000 },   /* R19519 - DACL_RETUNE_C32_0 */
 568
 569         { 19968, 0x0020 },   /* R19968 - RETUNEDAC_PG2_1 */
 570         { 19969, 0x0000 },   /* R19969 - RETUNEDAC_PG2_0 */
 571         { 19970, 0x0040 },   /* R19970 - RETUNEDAC_PG_1 */
 572         { 19971, 0x0000 },   /* R19971 - RETUNEDAC_PG_0 */
 573
 574         { 20480, 0x007F },   /* R20480 - DACR_RETUNE_C1_1 */
 575         { 20481, 0xFFFF },   /* R20481 - DACR_RETUNE_C1_0 */
 576         { 20482, 0x0000 },   /* R20482 - DACR_RETUNE_C2_1 */
 577         { 20483, 0x0000 },   /* R20483 - DACR_RETUNE_C2_0 */
 578         { 20484, 0x0000 },   /* R20484 - DACR_RETUNE_C3_1 */
 579         { 20485, 0x0000 },   /* R20485 - DACR_RETUNE_C3_0 */
 580         { 20486, 0x0000 },   /* R20486 - DACR_RETUNE_C4_1 */
 581         { 20487, 0x0000 },   /* R20487 - DACR_RETUNE_C4_0 */
 582         { 20488, 0x0000 },   /* R20488 - DACR_RETUNE_C5_1 */
 583         { 20489, 0x0000 },   /* R20489 - DACR_RETUNE_C5_0 */
 584         { 20490, 0x0000 },   /* R20490 - DACR_RETUNE_C6_1 */
 585         { 20491, 0x0000 },   /* R20491 - DACR_RETUNE_C6_0 */
 586         { 20492, 0x0000 },   /* R20492 - DACR_RETUNE_C7_1 */
 587         { 20493, 0x0000 },   /* R20493 - DACR_RETUNE_C7_0 */
 588         { 20494, 0x0000 },   /* R20494 - DACR_RETUNE_C8_1 */
 589         { 20495, 0x0000 },   /* R20495 - DACR_RETUNE_C8_0 */
 590         { 20496, 0x0000 },   /* R20496 - DACR_RETUNE_C9_1 */
 591         { 20497, 0x0000 },   /* R20497 - DACR_RETUNE_C9_0 */
 592         { 20498, 0x0000 },   /* R20498 - DACR_RETUNE_C10_1 */
 593         { 20499, 0x0000 },   /* R20499 - DACR_RETUNE_C10_0 */
 594         { 20500, 0x0000 },   /* R20500 - DACR_RETUNE_C11_1 */
 595         { 20501, 0x0000 },   /* R20501 - DACR_RETUNE_C11_0 */
 596         { 20502, 0x0000 },   /* R20502 - DACR_RETUNE_C12_1 */
 597         { 20503, 0x0000 },   /* R20503 - DACR_RETUNE_C12_0 */
 598         { 20504, 0x0000 },   /* R20504 - DACR_RETUNE_C13_1 */
 599         { 20505, 0x0000 },   /* R20505 - DACR_RETUNE_C13_0 */
 600         { 20506, 0x0000 },   /* R20506 - DACR_RETUNE_C14_1 */
 601         { 20507, 0x0000 },   /* R20507 - DACR_RETUNE_C14_0 */
 602         { 20508, 0x0000 },   /* R20508 - DACR_RETUNE_C15_1 */
 603         { 20509, 0x0000 },   /* R20509 - DACR_RETUNE_C15_0 */
 604         { 20510, 0x0000 },   /* R20510 - DACR_RETUNE_C16_1 */
 605         { 20511, 0x0000 },   /* R20511 - DACR_RETUNE_C16_0 */
 606         { 20512, 0x0000 },   /* R20512 - DACR_RETUNE_C17_1 */
 607         { 20513, 0x0000 },   /* R20513 - DACR_RETUNE_C17_0 */
 608         { 20514, 0x0000 },   /* R20514 - DACR_RETUNE_C18_1 */
 609         { 20515, 0x0000 },   /* R20515 - DACR_RETUNE_C18_0 */
 610         { 20516, 0x0000 },   /* R20516 - DACR_RETUNE_C19_1 */
 611         { 20517, 0x0000 },   /* R20517 - DACR_RETUNE_C19_0 */
 612         { 20518, 0x0000 },   /* R20518 - DACR_RETUNE_C20_1 */
 613         { 20519, 0x0000 },   /* R20519 - DACR_RETUNE_C20_0 */
 614         { 20520, 0x0000 },   /* R20520 - DACR_RETUNE_C21_1 */
 615         { 20521, 0x0000 },   /* R20521 - DACR_RETUNE_C21_0 */
 616         { 20522, 0x0000 },   /* R20522 - DACR_RETUNE_C22_1 */
 617         { 20523, 0x0000 },   /* R20523 - DACR_RETUNE_C22_0 */
 618         { 20524, 0x0000 },   /* R20524 - DACR_RETUNE_C23_1 */
 619         { 20525, 0x0000 },   /* R20525 - DACR_RETUNE_C23_0 */
 620         { 20526, 0x0000 },   /* R20526 - DACR_RETUNE_C24_1 */
 621         { 20527, 0x0000 },   /* R20527 - DACR_RETUNE_C24_0 */
 622         { 20528, 0x0000 },   /* R20528 - DACR_RETUNE_C25_1 */
 623         { 20529, 0x0000 },   /* R20529 - DACR_RETUNE_C25_0 */
 624         { 20530, 0x0000 },   /* R20530 - DACR_RETUNE_C26_1 */
 625         { 20531, 0x0000 },   /* R20531 - DACR_RETUNE_C26_0 */
 626         { 20532, 0x0000 },   /* R20532 - DACR_RETUNE_C27_1 */
 627         { 20533, 0x0000 },   /* R20533 - DACR_RETUNE_C27_0 */
 628         { 20534, 0x0000 },   /* R20534 - DACR_RETUNE_C28_1 */
 629         { 20535, 0x0000 },   /* R20535 - DACR_RETUNE_C28_0 */
 630         { 20536, 0x0000 },   /* R20536 - DACR_RETUNE_C29_1 */
 631         { 20537, 0x0000 },   /* R20537 - DACR_RETUNE_C29_0 */
 632         { 20538, 0x0000 },   /* R20538 - DACR_RETUNE_C30_1 */
 633         { 20539, 0x0000 },   /* R20539 - DACR_RETUNE_C30_0 */
 634         { 20540, 0x0000 },   /* R20540 - DACR_RETUNE_C31_1 */
 635         { 20541, 0x0000 },   /* R20541 - DACR_RETUNE_C31_0 */
 636         { 20542, 0x0000 },   /* R20542 - DACR_RETUNE_C32_1 */
 637         { 20543, 0x0000 },   /* R20543 - DACR_RETUNE_C32_0 */
 638
 639         { 20992, 0x008C },   /* R20992 - VSS_XHD2_1 */
 640         { 20993, 0x0200 },   /* R20993 - VSS_XHD2_0 */
 641         { 20994, 0x0035 },   /* R20994 - VSS_XHD3_1 */
 642         { 20995, 0x0700 },   /* R20995 - VSS_XHD3_0 */
 643         { 20996, 0x003A },   /* R20996 - VSS_XHN1_1 */
 644         { 20997, 0x4100 },   /* R20997 - VSS_XHN1_0 */
 645         { 20998, 0x008B },   /* R20998 - VSS_XHN2_1 */
 646         { 20999, 0x7D00 },   /* R20999 - VSS_XHN2_0 */
 647         { 21000, 0x003A },   /* R21000 - VSS_XHN3_1 */
 648         { 21001, 0x4100 },   /* R21001 - VSS_XHN3_0 */
 649         { 21002, 0x008C },   /* R21002 - VSS_XLA_1 */
 650         { 21003, 0xFEE8 },   /* R21003 - VSS_XLA_0 */
 651         { 21004, 0x0078 },   /* R21004 - VSS_XLB_1 */
 652         { 21005, 0x0000 },   /* R21005 - VSS_XLB_0 */
 653         { 21006, 0x003F },   /* R21006 - VSS_XLG_1 */
 654         { 21007, 0xB260 },   /* R21007 - VSS_XLG_0 */
 655         { 21008, 0x002D },   /* R21008 - VSS_PG2_1 */
 656         { 21009, 0x1818 },   /* R21009 - VSS_PG2_0 */
 657         { 21010, 0x0020 },   /* R21010 - VSS_PG_1 */
 658         { 21011, 0x0000 },   /* R21011 - VSS_PG_0 */
 659         { 21012, 0x00F1 },   /* R21012 - VSS_XTD1_1 */
 660         { 21013, 0x8340 },   /* R21013 - VSS_XTD1_0 */
 661         { 21014, 0x00FB },   /* R21014 - VSS_XTD2_1 */
 662         { 21015, 0x8300 },   /* R21015 - VSS_XTD2_0 */
 663         { 21016, 0x00EE },   /* R21016 - VSS_XTD3_1 */
 664         { 21017, 0xAEC0 },   /* R21017 - VSS_XTD3_0 */
 665         { 21018, 0x00FB },   /* R21018 - VSS_XTD4_1 */
 666         { 21019, 0xAC40 },   /* R21019 - VSS_XTD4_0 */
 667         { 21020, 0x00F1 },   /* R21020 - VSS_XTD5_1 */
 668         { 21021, 0x7F80 },   /* R21021 - VSS_XTD5_0 */
 669         { 21022, 0x00F4 },   /* R21022 - VSS_XTD6_1 */
 670         { 21023, 0x3B40 },   /* R21023 - VSS_XTD6_0 */
 671         { 21024, 0x00F5 },   /* R21024 - VSS_XTD7_1 */
 672         { 21025, 0xFB00 },   /* R21025 - VSS_XTD7_0 */
 673         { 21026, 0x00EA },   /* R21026 - VSS_XTD8_1 */
 674         { 21027, 0x10C0 },   /* R21027 - VSS_XTD8_0 */
 675         { 21028, 0x00FC },   /* R21028 - VSS_XTD9_1 */
 676         { 21029, 0xC580 },   /* R21029 - VSS_XTD9_0 */
 677         { 21030, 0x00E2 },   /* R21030 - VSS_XTD10_1 */
 678         { 21031, 0x75C0 },   /* R21031 - VSS_XTD10_0 */
 679         { 21032, 0x0004 },   /* R21032 - VSS_XTD11_1 */
 680         { 21033, 0xB480 },   /* R21033 - VSS_XTD11_0 */
 681         { 21034, 0x00D4 },   /* R21034 - VSS_XTD12_1 */
 682         { 21035, 0xF980 },   /* R21035 - VSS_XTD12_0 */
 683         { 21036, 0x0004 },   /* R21036 - VSS_XTD13_1 */
 684         { 21037, 0x9140 },   /* R21037 - VSS_XTD13_0 */
 685         { 21038, 0x00D8 },   /* R21038 - VSS_XTD14_1 */
 686         { 21039, 0xA480 },   /* R21039 - VSS_XTD14_0 */
 687         { 21040, 0x0002 },   /* R21040 - VSS_XTD15_1 */
 688         { 21041, 0x3DC0 },   /* R21041 - VSS_XTD15_0 */
 689         { 21042, 0x00CF },   /* R21042 - VSS_XTD16_1 */
 690         { 21043, 0x7A80 },   /* R21043 - VSS_XTD16_0 */
 691         { 21044, 0x00DC },   /* R21044 - VSS_XTD17_1 */
 692         { 21045, 0x0600 },   /* R21045 - VSS_XTD17_0 */
 693         { 21046, 0x00F2 },   /* R21046 - VSS_XTD18_1 */
 694         { 21047, 0xDAC0 },   /* R21047 - VSS_XTD18_0 */
 695         { 21048, 0x00BA },   /* R21048 - VSS_XTD19_1 */
 696         { 21049, 0xF340 },   /* R21049 - VSS_XTD19_0 */
 697         { 21050, 0x000A },   /* R21050 - VSS_XTD20_1 */
 698         { 21051, 0x7940 },   /* R21051 - VSS_XTD20_0 */
 699         { 21052, 0x001C },   /* R21052 - VSS_XTD21_1 */
 700         { 21053, 0x0680 },   /* R21053 - VSS_XTD21_0 */
 701         { 21054, 0x00FD },   /* R21054 - VSS_XTD22_1 */
 702         { 21055, 0x2D00 },   /* R21055 - VSS_XTD22_0 */
 703         { 21056, 0x001C },   /* R21056 - VSS_XTD23_1 */
 704         { 21057, 0xE840 },   /* R21057 - VSS_XTD23_0 */
 705         { 21058, 0x000D },   /* R21058 - VSS_XTD24_1 */
 706         { 21059, 0xDC40 },   /* R21059 - VSS_XTD24_0 */
 707         { 21060, 0x00FC },   /* R21060 - VSS_XTD25_1 */
 708         { 21061, 0x9D00 },   /* R21061 - VSS_XTD25_0 */
 709         { 21062, 0x0009 },   /* R21062 - VSS_XTD26_1 */
 710         { 21063, 0x5580 },   /* R21063 - VSS_XTD26_0 */
 711         { 21064, 0x00FE },   /* R21064 - VSS_XTD27_1 */
 712         { 21065, 0x7E80 },   /* R21065 - VSS_XTD27_0 */
 713         { 21066, 0x000E },   /* R21066 - VSS_XTD28_1 */
 714         { 21067, 0xAB40 },   /* R21067 - VSS_XTD28_0 */
 715         { 21068, 0x00F9 },   /* R21068 - VSS_XTD29_1 */
 716         { 21069, 0x9880 },   /* R21069 - VSS_XTD29_0 */
 717         { 21070, 0x0009 },   /* R21070 - VSS_XTD30_1 */
 718         { 21071, 0x87C0 },   /* R21071 - VSS_XTD30_0 */
 719         { 21072, 0x00FD },   /* R21072 - VSS_XTD31_1 */
 720         { 21073, 0x2C40 },   /* R21073 - VSS_XTD31_0 */
 721         { 21074, 0x0009 },   /* R21074 - VSS_XTD32_1 */
 722         { 21075, 0x4800 },   /* R21075 - VSS_XTD32_0 */
 723         { 21076, 0x0003 },   /* R21076 - VSS_XTS1_1 */
 724         { 21077, 0x5F40 },   /* R21077 - VSS_XTS1_0 */
 725         { 21078, 0x0000 },   /* R21078 - VSS_XTS2_1 */
 726         { 21079, 0x8700 },   /* R21079 - VSS_XTS2_0 */
 727         { 21080, 0x00FA },   /* R21080 - VSS_XTS3_1 */
 728         { 21081, 0xE4C0 },   /* R21081 - VSS_XTS3_0 */
 729         { 21082, 0x0000 },   /* R21082 - VSS_XTS4_1 */
 730         { 21083, 0x0B40 },   /* R21083 - VSS_XTS4_0 */
 731         { 21084, 0x0004 },   /* R21084 - VSS_XTS5_1 */
 732         { 21085, 0xE180 },   /* R21085 - VSS_XTS5_0 */
 733         { 21086, 0x0001 },   /* R21086 - VSS_XTS6_1 */
 734         { 21087, 0x1F40 },   /* R21087 - VSS_XTS6_0 */
 735         { 21088, 0x00F8 },   /* R21088 - VSS_XTS7_1 */
 736         { 21089, 0xB000 },   /* R21089 - VSS_XTS7_0 */
 737         { 21090, 0x00FB },   /* R21090 - VSS_XTS8_1 */
 738         { 21091, 0xCBC0 },   /* R21091 - VSS_XTS8_0 */
 739         { 21092, 0x0004 },   /* R21092 - VSS_XTS9_1 */
 740         { 21093, 0xF380 },   /* R21093 - VSS_XTS9_0 */
 741         { 21094, 0x0007 },   /* R21094 - VSS_XTS10_1 */
 742         { 21095, 0xDF40 },   /* R21095 - VSS_XTS10_0 */
 743         { 21096, 0x00FF },   /* R21096 - VSS_XTS11_1 */
 744         { 21097, 0x0700 },   /* R21097 - VSS_XTS11_0 */
 745         { 21098, 0x00EF },   /* R21098 - VSS_XTS12_1 */
 746         { 21099, 0xD700 },   /* R21099 - VSS_XTS12_0 */
 747         { 21100, 0x00FB },   /* R21100 - VSS_XTS13_1 */
 748         { 21101, 0xAF40 },   /* R21101 - VSS_XTS13_0 */
 749         { 21102, 0x0010 },   /* R21102 - VSS_XTS14_1 */
 750         { 21103, 0x8A80 },   /* R21103 - VSS_XTS14_0 */
 751         { 21104, 0x0011 },   /* R21104 - VSS_XTS15_1 */
 752         { 21105, 0x07C0 },   /* R21105 - VSS_XTS15_0 */
 753         { 21106, 0x00E0 },   /* R21106 - VSS_XTS16_1 */
 754         { 21107, 0x0800 },   /* R21107 - VSS_XTS16_0 */
 755         { 21108, 0x00D2 },   /* R21108 - VSS_XTS17_1 */
 756         { 21109, 0x7600 },   /* R21109 - VSS_XTS17_0 */
 757         { 21110, 0x0020 },   /* R21110 - VSS_XTS18_1 */
 758         { 21111, 0xCF40 },   /* R21111 - VSS_XTS18_0 */
 759         { 21112, 0x0030 },   /* R21112 - VSS_XTS19_1 */
 760         { 21113, 0x2340 },   /* R21113 - VSS_XTS19_0 */
 761         { 21114, 0x00FD },   /* R21114 - VSS_XTS20_1 */
 762         { 21115, 0x69C0 },   /* R21115 - VSS_XTS20_0 */
 763         { 21116, 0x0028 },   /* R21116 - VSS_XTS21_1 */
 764         { 21117, 0x3500 },   /* R21117 - VSS_XTS21_0 */
 765         { 21118, 0x0006 },   /* R21118 - VSS_XTS22_1 */
 766         { 21119, 0x3300 },   /* R21119 - VSS_XTS22_0 */
 767         { 21120, 0x00D9 },   /* R21120 - VSS_XTS23_1 */
 768         { 21121, 0xF6C0 },   /* R21121 - VSS_XTS23_0 */
 769         { 21122, 0x00F3 },   /* R21122 - VSS_XTS24_1 */
 770         { 21123, 0x3340 },   /* R21123 - VSS_XTS24_0 */
 771         { 21124, 0x000F },   /* R21124 - VSS_XTS25_1 */
 772         { 21125, 0x4200 },   /* R21125 - VSS_XTS25_0 */
 773         { 21126, 0x0004 },   /* R21126 - VSS_XTS26_1 */
 774         { 21127, 0x0C80 },   /* R21127 - VSS_XTS26_0 */
 775         { 21128, 0x00FB },   /* R21128 - VSS_XTS27_1 */
 776         { 21129, 0x3F80 },   /* R21129 - VSS_XTS27_0 */
 777         { 21130, 0x00F7 },   /* R21130 - VSS_XTS28_1 */
 778         { 21131, 0x57C0 },   /* R21131 - VSS_XTS28_0 */
 779         { 21132, 0x0003 },   /* R21132 - VSS_XTS29_1 */
 780         { 21133, 0x5400 },   /* R21133 - VSS_XTS29_0 */
 781         { 21134, 0x0000 },   /* R21134 - VSS_XTS30_1 */
 782         { 21135, 0xC6C0 },   /* R21135 - VSS_XTS30_0 */
 783         { 21136, 0x0003 },   /* R21136 - VSS_XTS31_1 */
 784         { 21137, 0x12C0 },   /* R21137 - VSS_XTS31_0 */
 785         { 21138, 0x00FD },   /* R21138 - VSS_XTS32_1 */
 786         { 21139, 0x8580 },   /* R21139 - VSS_XTS32_0 */
 787 };
 788
 789 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
 790 {
 791         switch (reg) {
 792         case WM8962_CLOCKING1:
 793         case WM8962_CLOCKING2:
 794         case WM8962_SOFTWARE_RESET:
 795         case WM8962_ALC2:
 796         case WM8962_THERMAL_SHUTDOWN_STATUS:
 797         case WM8962_ADDITIONAL_CONTROL_4:
 798         case WM8962_CLASS_D_CONTROL_1:
 799         case WM8962_DC_SERVO_6:
 800         case WM8962_INTERRUPT_STATUS_1:
 801         case WM8962_INTERRUPT_STATUS_2:
 802         case WM8962_DSP2_EXECCONTROL:
 803                 return true;
 804         default:
 805                 return false;
 806         }
 807 }
 808
 809 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
 810 {
 811         switch (reg) {
 812         case WM8962_LEFT_INPUT_VOLUME:
 813         case WM8962_RIGHT_INPUT_VOLUME:
 814         case WM8962_HPOUTL_VOLUME:
 815         case WM8962_HPOUTR_VOLUME:
 816         case WM8962_CLOCKING1:
 817         case WM8962_ADC_DAC_CONTROL_1:
 818         case WM8962_ADC_DAC_CONTROL_2:
 819         case WM8962_AUDIO_INTERFACE_0:
 820         case WM8962_CLOCKING2:
 821         case WM8962_AUDIO_INTERFACE_1:
 822         case WM8962_LEFT_DAC_VOLUME:
 823         case WM8962_RIGHT_DAC_VOLUME:
 824         case WM8962_AUDIO_INTERFACE_2:
 825         case WM8962_SOFTWARE_RESET:
 826         case WM8962_ALC1:
 827         case WM8962_ALC2:
 828         case WM8962_ALC3:
 829         case WM8962_NOISE_GATE:
 830         case WM8962_LEFT_ADC_VOLUME:
 831         case WM8962_RIGHT_ADC_VOLUME:
 832         case WM8962_ADDITIONAL_CONTROL_1:
 833         case WM8962_ADDITIONAL_CONTROL_2:
 834         case WM8962_PWR_MGMT_1:
 835         case WM8962_PWR_MGMT_2:
 836         case WM8962_ADDITIONAL_CONTROL_3:
 837         case WM8962_ANTI_POP:
 838         case WM8962_CLOCKING_3:
 839         case WM8962_INPUT_MIXER_CONTROL_1:
 840         case WM8962_LEFT_INPUT_MIXER_VOLUME:
 841         case WM8962_RIGHT_INPUT_MIXER_VOLUME:
 842         case WM8962_INPUT_MIXER_CONTROL_2:
 843         case WM8962_INPUT_BIAS_CONTROL:
 844         case WM8962_LEFT_INPUT_PGA_CONTROL:
 845         case WM8962_RIGHT_INPUT_PGA_CONTROL:
 846         case WM8962_SPKOUTL_VOLUME:
 847         case WM8962_SPKOUTR_VOLUME:
 848         case WM8962_THERMAL_SHUTDOWN_STATUS:
 849         case WM8962_ADDITIONAL_CONTROL_4:
 850         case WM8962_CLASS_D_CONTROL_1:
 851         case WM8962_CLASS_D_CONTROL_2:
 852         case WM8962_CLOCKING_4:
 853         case WM8962_DAC_DSP_MIXING_1:
 854         case WM8962_DAC_DSP_MIXING_2:
 855         case WM8962_DC_SERVO_0:
 856         case WM8962_DC_SERVO_1:
 857         case WM8962_DC_SERVO_4:
 858         case WM8962_DC_SERVO_6:
 859         case WM8962_ANALOGUE_PGA_BIAS:
 860         case WM8962_ANALOGUE_HP_0:
 861         case WM8962_ANALOGUE_HP_2:
 862         case WM8962_CHARGE_PUMP_1:
 863         case WM8962_CHARGE_PUMP_B:
 864         case WM8962_WRITE_SEQUENCER_CONTROL_1:
 865         case WM8962_WRITE_SEQUENCER_CONTROL_2:
 866         case WM8962_WRITE_SEQUENCER_CONTROL_3:
 867         case WM8962_CONTROL_INTERFACE:
 868         case WM8962_MIXER_ENABLES:
 869         case WM8962_HEADPHONE_MIXER_1:
 870         case WM8962_HEADPHONE_MIXER_2:
 871         case WM8962_HEADPHONE_MIXER_3:
 872         case WM8962_HEADPHONE_MIXER_4:
 873         case WM8962_SPEAKER_MIXER_1:
 874         case WM8962_SPEAKER_MIXER_2:
 875         case WM8962_SPEAKER_MIXER_3:
 876         case WM8962_SPEAKER_MIXER_4:
 877         case WM8962_SPEAKER_MIXER_5:
 878         case WM8962_BEEP_GENERATOR_1:
 879         case WM8962_OSCILLATOR_TRIM_3:
 880         case WM8962_OSCILLATOR_TRIM_4:
 881         case WM8962_OSCILLATOR_TRIM_7:
 882         case WM8962_ANALOGUE_CLOCKING1:
 883         case WM8962_ANALOGUE_CLOCKING2:
 884         case WM8962_ANALOGUE_CLOCKING3:
 885         case WM8962_PLL_SOFTWARE_RESET:
 886         case WM8962_PLL2:
 887         case WM8962_PLL_4:
 888         case WM8962_PLL_9:
 889         case WM8962_PLL_10:
 890         case WM8962_PLL_11:
 891         case WM8962_PLL_12:
 892         case WM8962_PLL_13:
 893         case WM8962_PLL_14:
 894         case WM8962_PLL_15:
 895         case WM8962_PLL_16:
 896         case WM8962_FLL_CONTROL_1:
 897         case WM8962_FLL_CONTROL_2:
 898         case WM8962_FLL_CONTROL_3:
 899         case WM8962_FLL_CONTROL_5:
 900         case WM8962_FLL_CONTROL_6:
 901         case WM8962_FLL_CONTROL_7:
 902         case WM8962_FLL_CONTROL_8:
 903         case WM8962_GENERAL_TEST_1:
 904         case WM8962_DF1:
 905         case WM8962_DF2:
 906         case WM8962_DF3:
 907         case WM8962_DF4:
 908         case WM8962_DF5:
 909         case WM8962_DF6:
 910         case WM8962_DF7:
 911         case WM8962_LHPF1:
 912         case WM8962_LHPF2:
 913         case WM8962_THREED1:
 914         case WM8962_THREED2:
 915         case WM8962_THREED3:
 916         case WM8962_THREED4:
 917         case WM8962_DRC_1:
 918         case WM8962_DRC_2:
 919         case WM8962_DRC_3:
 920         case WM8962_DRC_4:
 921         case WM8962_DRC_5:
 922         case WM8962_TLOOPBACK:
 923         case WM8962_EQ1:
 924         case WM8962_EQ2:
 925         case WM8962_EQ3:
 926         case WM8962_EQ4:
 927         case WM8962_EQ5:
 928         case WM8962_EQ6:
 929         case WM8962_EQ7:
 930         case WM8962_EQ8:
 931         case WM8962_EQ9:
 932         case WM8962_EQ10:
 933         case WM8962_EQ11:
 934         case WM8962_EQ12:
 935         case WM8962_EQ13:
 936         case WM8962_EQ14:
 937         case WM8962_EQ15:
 938         case WM8962_EQ16:
 939         case WM8962_EQ17:
 940         case WM8962_EQ18:
 941         case WM8962_EQ19:
 942         case WM8962_EQ20:
 943         case WM8962_EQ21:
 944         case WM8962_EQ22:
 945         case WM8962_EQ23:
 946         case WM8962_EQ24:
 947         case WM8962_EQ25:
 948         case WM8962_EQ26:
 949         case WM8962_EQ27:
 950         case WM8962_EQ28:
 951         case WM8962_EQ29:
 952         case WM8962_EQ30:
 953         case WM8962_EQ31:
 954         case WM8962_EQ32:
 955         case WM8962_EQ33:
 956         case WM8962_EQ34:
 957         case WM8962_EQ35:
 958         case WM8962_EQ36:
 959         case WM8962_EQ37:
 960         case WM8962_EQ38:
 961         case WM8962_EQ39:
 962         case WM8962_EQ40:
 963         case WM8962_EQ41:
 964         case WM8962_GPIO_BASE:
 965         case WM8962_GPIO_2:
 966         case WM8962_GPIO_3:
 967         case WM8962_GPIO_5:
 968         case WM8962_GPIO_6:
 969         case WM8962_INTERRUPT_STATUS_1:
 970         case WM8962_INTERRUPT_STATUS_2:
 971         case WM8962_INTERRUPT_STATUS_1_MASK:
 972         case WM8962_INTERRUPT_STATUS_2_MASK:
 973         case WM8962_INTERRUPT_CONTROL:
 974         case WM8962_IRQ_DEBOUNCE:
 975         case WM8962_MICINT_SOURCE_POL:
 976         case WM8962_DSP2_POWER_MANAGEMENT:
 977         case WM8962_DSP2_EXECCONTROL:
 978         case WM8962_DSP2_INSTRUCTION_RAM_0:
 979         case WM8962_DSP2_ADDRESS_RAM_2:
 980         case WM8962_DSP2_ADDRESS_RAM_1:
 981         case WM8962_DSP2_ADDRESS_RAM_0:
 982         case WM8962_DSP2_DATA1_RAM_1:
 983         case WM8962_DSP2_DATA1_RAM_0:
 984         case WM8962_DSP2_DATA2_RAM_1:
 985         case WM8962_DSP2_DATA2_RAM_0:
 986         case WM8962_DSP2_DATA3_RAM_1:
 987         case WM8962_DSP2_DATA3_RAM_0:
 988         case WM8962_DSP2_COEFF_RAM_0:
 989         case WM8962_RETUNEADC_SHARED_COEFF_1:
 990         case WM8962_RETUNEADC_SHARED_COEFF_0:
 991         case WM8962_RETUNEDAC_SHARED_COEFF_1:
 992         case WM8962_RETUNEDAC_SHARED_COEFF_0:
 993         case WM8962_SOUNDSTAGE_ENABLES_1:
 994         case WM8962_SOUNDSTAGE_ENABLES_0:
 995         case WM8962_HDBASS_AI_1:
 996         case WM8962_HDBASS_AI_0:
 997         case WM8962_HDBASS_AR_1:
 998         case WM8962_HDBASS_AR_0:
 999         case WM8962_HDBASS_B_1:
1000         case WM8962_HDBASS_B_0:
1001         case WM8962_HDBASS_K_1:
1002         case WM8962_HDBASS_K_0:
1003         case WM8962_HDBASS_N1_1:
1004         case WM8962_HDBASS_N1_0:
1005         case WM8962_HDBASS_N2_1:
1006         case WM8962_HDBASS_N2_0:
1007         case WM8962_HDBASS_N3_1:
1008         case WM8962_HDBASS_N3_0:
1009         case WM8962_HDBASS_N4_1:
1010         case WM8962_HDBASS_N4_0:
1011         case WM8962_HDBASS_N5_1:
1012         case WM8962_HDBASS_N5_0:
1013         case WM8962_HDBASS_X1_1:
1014         case WM8962_HDBASS_X1_0:
1015         case WM8962_HDBASS_X2_1:
1016         case WM8962_HDBASS_X2_0:
1017         case WM8962_HDBASS_X3_1:
1018         case WM8962_HDBASS_X3_0:
1019         case WM8962_HDBASS_ATK_1:
1020         case WM8962_HDBASS_ATK_0:
1021         case WM8962_HDBASS_DCY_1:
1022         case WM8962_HDBASS_DCY_0:
1023         case WM8962_HDBASS_PG_1:
1024         case WM8962_HDBASS_PG_0:
1025         case WM8962_HPF_C_1:
1026         case WM8962_HPF_C_0:
1027         case WM8962_ADCL_RETUNE_C1_1:
1028         case WM8962_ADCL_RETUNE_C1_0:
1029         case WM8962_ADCL_RETUNE_C2_1:
1030         case WM8962_ADCL_RETUNE_C2_0:
1031         case WM8962_ADCL_RETUNE_C3_1:
1032         case WM8962_ADCL_RETUNE_C3_0:
1033         case WM8962_ADCL_RETUNE_C4_1:
1034         case WM8962_ADCL_RETUNE_C4_0:
1035         case WM8962_ADCL_RETUNE_C5_1:
1036         case WM8962_ADCL_RETUNE_C5_0:
1037         case WM8962_ADCL_RETUNE_C6_1:
1038         case WM8962_ADCL_RETUNE_C6_0:
1039         case WM8962_ADCL_RETUNE_C7_1:
1040         case WM8962_ADCL_RETUNE_C7_0:
1041         case WM8962_ADCL_RETUNE_C8_1:
1042         case WM8962_ADCL_RETUNE_C8_0:
1043         case WM8962_ADCL_RETUNE_C9_1:
1044         case WM8962_ADCL_RETUNE_C9_0:
1045         case WM8962_ADCL_RETUNE_C10_1:
1046         case WM8962_ADCL_RETUNE_C10_0:
1047         case WM8962_ADCL_RETUNE_C11_1:
1048         case WM8962_ADCL_RETUNE_C11_0:
1049         case WM8962_ADCL_RETUNE_C12_1:
1050         case WM8962_ADCL_RETUNE_C12_0:
1051         case WM8962_ADCL_RETUNE_C13_1:
1052         case WM8962_ADCL_RETUNE_C13_0:
1053         case WM8962_ADCL_RETUNE_C14_1:
1054         case WM8962_ADCL_RETUNE_C14_0:
1055         case WM8962_ADCL_RETUNE_C15_1:
1056         case WM8962_ADCL_RETUNE_C15_0:
1057         case WM8962_ADCL_RETUNE_C16_1:
1058         case WM8962_ADCL_RETUNE_C16_0:
1059         case WM8962_ADCL_RETUNE_C17_1:
1060         case WM8962_ADCL_RETUNE_C17_0:
1061         case WM8962_ADCL_RETUNE_C18_1:
1062         case WM8962_ADCL_RETUNE_C18_0:
1063         case WM8962_ADCL_RETUNE_C19_1:
1064         case WM8962_ADCL_RETUNE_C19_0:
1065         case WM8962_ADCL_RETUNE_C20_1:
1066         case WM8962_ADCL_RETUNE_C20_0:
1067         case WM8962_ADCL_RETUNE_C21_1:
1068         case WM8962_ADCL_RETUNE_C21_0:
1069         case WM8962_ADCL_RETUNE_C22_1:
1070         case WM8962_ADCL_RETUNE_C22_0:
1071         case WM8962_ADCL_RETUNE_C23_1:
1072         case WM8962_ADCL_RETUNE_C23_0:
1073         case WM8962_ADCL_RETUNE_C24_1:
1074         case WM8962_ADCL_RETUNE_C24_0:
1075         case WM8962_ADCL_RETUNE_C25_1:
1076         case WM8962_ADCL_RETUNE_C25_0:
1077         case WM8962_ADCL_RETUNE_C26_1:
1078         case WM8962_ADCL_RETUNE_C26_0:
1079         case WM8962_ADCL_RETUNE_C27_1:
1080         case WM8962_ADCL_RETUNE_C27_0:
1081         case WM8962_ADCL_RETUNE_C28_1:
1082         case WM8962_ADCL_RETUNE_C28_0:
1083         case WM8962_ADCL_RETUNE_C29_1:
1084         case WM8962_ADCL_RETUNE_C29_0:
1085         case WM8962_ADCL_RETUNE_C30_1:
1086         case WM8962_ADCL_RETUNE_C30_0:
1087         case WM8962_ADCL_RETUNE_C31_1:
1088         case WM8962_ADCL_RETUNE_C31_0:
1089         case WM8962_ADCL_RETUNE_C32_1:
1090         case WM8962_ADCL_RETUNE_C32_0:
1091         case WM8962_RETUNEADC_PG2_1:
1092         case WM8962_RETUNEADC_PG2_0:
1093         case WM8962_RETUNEADC_PG_1:
1094         case WM8962_RETUNEADC_PG_0:
1095         case WM8962_ADCR_RETUNE_C1_1:
1096         case WM8962_ADCR_RETUNE_C1_0:
1097         case WM8962_ADCR_RETUNE_C2_1:
1098         case WM8962_ADCR_RETUNE_C2_0:
1099         case WM8962_ADCR_RETUNE_C3_1:
1100         case WM8962_ADCR_RETUNE_C3_0:
1101         case WM8962_ADCR_RETUNE_C4_1:
1102         case WM8962_ADCR_RETUNE_C4_0:
1103         case WM8962_ADCR_RETUNE_C5_1:
1104         case WM8962_ADCR_RETUNE_C5_0:
1105         case WM8962_ADCR_RETUNE_C6_1:
1106         case WM8962_ADCR_RETUNE_C6_0:
1107         case WM8962_ADCR_RETUNE_C7_1:
1108         case WM8962_ADCR_RETUNE_C7_0:
1109         case WM8962_ADCR_RETUNE_C8_1:
1110         case WM8962_ADCR_RETUNE_C8_0:
1111         case WM8962_ADCR_RETUNE_C9_1:
1112         case WM8962_ADCR_RETUNE_C9_0:
1113         case WM8962_ADCR_RETUNE_C10_1:
1114         case WM8962_ADCR_RETUNE_C10_0:
1115         case WM8962_ADCR_RETUNE_C11_1:
1116         case WM8962_ADCR_RETUNE_C11_0:
1117         case WM8962_ADCR_RETUNE_C12_1:
1118         case WM8962_ADCR_RETUNE_C12_0:
1119         case WM8962_ADCR_RETUNE_C13_1:
1120         case WM8962_ADCR_RETUNE_C13_0:
1121         case WM8962_ADCR_RETUNE_C14_1:
1122         case WM8962_ADCR_RETUNE_C14_0:
1123         case WM8962_ADCR_RETUNE_C15_1:
1124         case WM8962_ADCR_RETUNE_C15_0:
1125         case WM8962_ADCR_RETUNE_C16_1:
1126         case WM8962_ADCR_RETUNE_C16_0:
1127         case WM8962_ADCR_RETUNE_C17_1:
1128         case WM8962_ADCR_RETUNE_C17_0:
1129         case WM8962_ADCR_RETUNE_C18_1:
1130         case WM8962_ADCR_RETUNE_C18_0:
1131         case WM8962_ADCR_RETUNE_C19_1:
1132         case WM8962_ADCR_RETUNE_C19_0:
1133         case WM8962_ADCR_RETUNE_C20_1:
1134         case WM8962_ADCR_RETUNE_C20_0:
1135         case WM8962_ADCR_RETUNE_C21_1:
1136         case WM8962_ADCR_RETUNE_C21_0:
1137         case WM8962_ADCR_RETUNE_C22_1:
1138         case WM8962_ADCR_RETUNE_C22_0:
1139         case WM8962_ADCR_RETUNE_C23_1:
1140         case WM8962_ADCR_RETUNE_C23_0:
1141         case WM8962_ADCR_RETUNE_C24_1:
1142         case WM8962_ADCR_RETUNE_C24_0:
1143         case WM8962_ADCR_RETUNE_C25_1:
1144         case WM8962_ADCR_RETUNE_C25_0:
1145         case WM8962_ADCR_RETUNE_C26_1:
1146         case WM8962_ADCR_RETUNE_C26_0:
1147         case WM8962_ADCR_RETUNE_C27_1:
1148         case WM8962_ADCR_RETUNE_C27_0:
1149         case WM8962_ADCR_RETUNE_C28_1:
1150         case WM8962_ADCR_RETUNE_C28_0:
1151         case WM8962_ADCR_RETUNE_C29_1:
1152         case WM8962_ADCR_RETUNE_C29_0:
1153         case WM8962_ADCR_RETUNE_C30_1:
1154         case WM8962_ADCR_RETUNE_C30_0:
1155         case WM8962_ADCR_RETUNE_C31_1:
1156         case WM8962_ADCR_RETUNE_C31_0:
1157         case WM8962_ADCR_RETUNE_C32_1:
1158         case WM8962_ADCR_RETUNE_C32_0:
1159         case WM8962_DACL_RETUNE_C1_1:
1160         case WM8962_DACL_RETUNE_C1_0:
1161         case WM8962_DACL_RETUNE_C2_1:
1162         case WM8962_DACL_RETUNE_C2_0:
1163         case WM8962_DACL_RETUNE_C3_1:
1164         case WM8962_DACL_RETUNE_C3_0:
1165         case WM8962_DACL_RETUNE_C4_1:
1166         case WM8962_DACL_RETUNE_C4_0:
1167         case WM8962_DACL_RETUNE_C5_1:
1168         case WM8962_DACL_RETUNE_C5_0:
1169         case WM8962_DACL_RETUNE_C6_1:
1170         case WM8962_DACL_RETUNE_C6_0:
1171         case WM8962_DACL_RETUNE_C7_1:
1172         case WM8962_DACL_RETUNE_C7_0:
1173         case WM8962_DACL_RETUNE_C8_1:
1174         case WM8962_DACL_RETUNE_C8_0:
1175         case WM8962_DACL_RETUNE_C9_1:
1176         case WM8962_DACL_RETUNE_C9_0:
1177         case WM8962_DACL_RETUNE_C10_1:
1178         case WM8962_DACL_RETUNE_C10_0:
1179         case WM8962_DACL_RETUNE_C11_1:
1180         case WM8962_DACL_RETUNE_C11_0:
1181         case WM8962_DACL_RETUNE_C12_1:
1182         case WM8962_DACL_RETUNE_C12_0:
1183         case WM8962_DACL_RETUNE_C13_1:
1184         case WM8962_DACL_RETUNE_C13_0:
1185         case WM8962_DACL_RETUNE_C14_1:
1186         case WM8962_DACL_RETUNE_C14_0:
1187         case WM8962_DACL_RETUNE_C15_1:
1188         case WM8962_DACL_RETUNE_C15_0:
1189         case WM8962_DACL_RETUNE_C16_1:
1190         case WM8962_DACL_RETUNE_C16_0:
1191         case WM8962_DACL_RETUNE_C17_1:
1192         case WM8962_DACL_RETUNE_C17_0:
1193         case WM8962_DACL_RETUNE_C18_1:
1194         case WM8962_DACL_RETUNE_C18_0:
1195         case WM8962_DACL_RETUNE_C19_1:
1196         case WM8962_DACL_RETUNE_C19_0:
1197         case WM8962_DACL_RETUNE_C20_1:
1198         case WM8962_DACL_RETUNE_C20_0:
1199         case WM8962_DACL_RETUNE_C21_1:
1200         case WM8962_DACL_RETUNE_C21_0:
1201         case WM8962_DACL_RETUNE_C22_1:
1202         case WM8962_DACL_RETUNE_C22_0:
1203         case WM8962_DACL_RETUNE_C23_1:
1204         case WM8962_DACL_RETUNE_C23_0:
1205         case WM8962_DACL_RETUNE_C24_1:
1206         case WM8962_DACL_RETUNE_C24_0:
1207         case WM8962_DACL_RETUNE_C25_1:
1208         case WM8962_DACL_RETUNE_C25_0:
1209         case WM8962_DACL_RETUNE_C26_1:
1210         case WM8962_DACL_RETUNE_C26_0:
1211         case WM8962_DACL_RETUNE_C27_1:
1212         case WM8962_DACL_RETUNE_C27_0:
1213         case WM8962_DACL_RETUNE_C28_1:
1214         case WM8962_DACL_RETUNE_C28_0:
1215         case WM8962_DACL_RETUNE_C29_1:
1216         case WM8962_DACL_RETUNE_C29_0:
1217         case WM8962_DACL_RETUNE_C30_1:
1218         case WM8962_DACL_RETUNE_C30_0:
1219         case WM8962_DACL_RETUNE_C31_1:
1220         case WM8962_DACL_RETUNE_C31_0:
1221         case WM8962_DACL_RETUNE_C32_1:
1222         case WM8962_DACL_RETUNE_C32_0:
1223         case WM8962_RETUNEDAC_PG2_1:
1224         case WM8962_RETUNEDAC_PG2_0:
1225         case WM8962_RETUNEDAC_PG_1:
1226         case WM8962_RETUNEDAC_PG_0:
1227         case WM8962_DACR_RETUNE_C1_1:
1228         case WM8962_DACR_RETUNE_C1_0:
1229         case WM8962_DACR_RETUNE_C2_1:
1230         case WM8962_DACR_RETUNE_C2_0:
1231         case WM8962_DACR_RETUNE_C3_1:
1232         case WM8962_DACR_RETUNE_C3_0:
1233         case WM8962_DACR_RETUNE_C4_1:
1234         case WM8962_DACR_RETUNE_C4_0:
1235         case WM8962_DACR_RETUNE_C5_1:
1236         case WM8962_DACR_RETUNE_C5_0:
1237         case WM8962_DACR_RETUNE_C6_1:
1238         case WM8962_DACR_RETUNE_C6_0:
1239         case WM8962_DACR_RETUNE_C7_1:
1240         case WM8962_DACR_RETUNE_C7_0:
1241         case WM8962_DACR_RETUNE_C8_1:
1242         case WM8962_DACR_RETUNE_C8_0:
1243         case WM8962_DACR_RETUNE_C9_1:
1244         case WM8962_DACR_RETUNE_C9_0:
1245         case WM8962_DACR_RETUNE_C10_1:
1246         case WM8962_DACR_RETUNE_C10_0:
1247         case WM8962_DACR_RETUNE_C11_1:
1248         case WM8962_DACR_RETUNE_C11_0:
1249         case WM8962_DACR_RETUNE_C12_1:
1250         case WM8962_DACR_RETUNE_C12_0:
1251         case WM8962_DACR_RETUNE_C13_1:
1252         case WM8962_DACR_RETUNE_C13_0:
1253         case WM8962_DACR_RETUNE_C14_1:
1254         case WM8962_DACR_RETUNE_C14_0:
1255         case WM8962_DACR_RETUNE_C15_1:
1256         case WM8962_DACR_RETUNE_C15_0:
1257         case WM8962_DACR_RETUNE_C16_1:
1258         case WM8962_DACR_RETUNE_C16_0:
1259         case WM8962_DACR_RETUNE_C17_1:
1260         case WM8962_DACR_RETUNE_C17_0:
1261         case WM8962_DACR_RETUNE_C18_1:
1262         case WM8962_DACR_RETUNE_C18_0:
1263         case WM8962_DACR_RETUNE_C19_1:
1264         case WM8962_DACR_RETUNE_C19_0:
1265         case WM8962_DACR_RETUNE_C20_1:
1266         case WM8962_DACR_RETUNE_C20_0:
1267         case WM8962_DACR_RETUNE_C21_1:
1268         case WM8962_DACR_RETUNE_C21_0:
1269         case WM8962_DACR_RETUNE_C22_1:
1270         case WM8962_DACR_RETUNE_C22_0:
1271         case WM8962_DACR_RETUNE_C23_1:
1272         case WM8962_DACR_RETUNE_C23_0:
1273         case WM8962_DACR_RETUNE_C24_1:
1274         case WM8962_DACR_RETUNE_C24_0:
1275         case WM8962_DACR_RETUNE_C25_1:
1276         case WM8962_DACR_RETUNE_C25_0:
1277         case WM8962_DACR_RETUNE_C26_1:
1278         case WM8962_DACR_RETUNE_C26_0:
1279         case WM8962_DACR_RETUNE_C27_1:
1280         case WM8962_DACR_RETUNE_C27_0:
1281         case WM8962_DACR_RETUNE_C28_1:
1282         case WM8962_DACR_RETUNE_C28_0:
1283         case WM8962_DACR_RETUNE_C29_1:
1284         case WM8962_DACR_RETUNE_C29_0:
1285         case WM8962_DACR_RETUNE_C30_1:
1286         case WM8962_DACR_RETUNE_C30_0:
1287         case WM8962_DACR_RETUNE_C31_1:
1288         case WM8962_DACR_RETUNE_C31_0:
1289         case WM8962_DACR_RETUNE_C32_1:
1290         case WM8962_DACR_RETUNE_C32_0:
1291         case WM8962_VSS_XHD2_1:
1292         case WM8962_VSS_XHD2_0:
1293         case WM8962_VSS_XHD3_1:
1294         case WM8962_VSS_XHD3_0:
1295         case WM8962_VSS_XHN1_1:
1296         case WM8962_VSS_XHN1_0:
1297         case WM8962_VSS_XHN2_1:
1298         case WM8962_VSS_XHN2_0:
1299         case WM8962_VSS_XHN3_1:
1300         case WM8962_VSS_XHN3_0:
1301         case WM8962_VSS_XLA_1:
1302         case WM8962_VSS_XLA_0:
1303         case WM8962_VSS_XLB_1:
1304         case WM8962_VSS_XLB_0:
1305         case WM8962_VSS_XLG_1:
1306         case WM8962_VSS_XLG_0:
1307         case WM8962_VSS_PG2_1:
1308         case WM8962_VSS_PG2_0:
1309         case WM8962_VSS_PG_1:
1310         case WM8962_VSS_PG_0:
1311         case WM8962_VSS_XTD1_1:
1312         case WM8962_VSS_XTD1_0:
1313         case WM8962_VSS_XTD2_1:
1314         case WM8962_VSS_XTD2_0:
1315         case WM8962_VSS_XTD3_1:
1316         case WM8962_VSS_XTD3_0:
1317         case WM8962_VSS_XTD4_1:
1318         case WM8962_VSS_XTD4_0:
1319         case WM8962_VSS_XTD5_1:
1320         case WM8962_VSS_XTD5_0:
1321         case WM8962_VSS_XTD6_1:
1322         case WM8962_VSS_XTD6_0:
1323         case WM8962_VSS_XTD7_1:
1324         case WM8962_VSS_XTD7_0:
1325         case WM8962_VSS_XTD8_1:
1326         case WM8962_VSS_XTD8_0:
1327         case WM8962_VSS_XTD9_1:
1328         case WM8962_VSS_XTD9_0:
1329         case WM8962_VSS_XTD10_1:
1330         case WM8962_VSS_XTD10_0:
1331         case WM8962_VSS_XTD11_1:
1332         case WM8962_VSS_XTD11_0:
1333         case WM8962_VSS_XTD12_1:
1334         case WM8962_VSS_XTD12_0:
1335         case WM8962_VSS_XTD13_1:
1336         case WM8962_VSS_XTD13_0:
1337         case WM8962_VSS_XTD14_1:
1338         case WM8962_VSS_XTD14_0:
1339         case WM8962_VSS_XTD15_1:
1340         case WM8962_VSS_XTD15_0:
1341         case WM8962_VSS_XTD16_1:
1342         case WM8962_VSS_XTD16_0:
1343         case WM8962_VSS_XTD17_1:
1344         case WM8962_VSS_XTD17_0:
1345         case WM8962_VSS_XTD18_1:
1346         case WM8962_VSS_XTD18_0:
1347         case WM8962_VSS_XTD19_1:
1348         case WM8962_VSS_XTD19_0:
1349         case WM8962_VSS_XTD20_1:
1350         case WM8962_VSS_XTD20_0:
1351         case WM8962_VSS_XTD21_1:
1352         case WM8962_VSS_XTD21_0:
1353         case WM8962_VSS_XTD22_1:
1354         case WM8962_VSS_XTD22_0:
1355         case WM8962_VSS_XTD23_1:
1356         case WM8962_VSS_XTD23_0:
1357         case WM8962_VSS_XTD24_1:
1358         case WM8962_VSS_XTD24_0:
1359         case WM8962_VSS_XTD25_1:
1360         case WM8962_VSS_XTD25_0:
1361         case WM8962_VSS_XTD26_1:
1362         case WM8962_VSS_XTD26_0:
1363         case WM8962_VSS_XTD27_1:
1364         case WM8962_VSS_XTD27_0:
1365         case WM8962_VSS_XTD28_1:
1366         case WM8962_VSS_XTD28_0:
1367         case WM8962_VSS_XTD29_1:
1368         case WM8962_VSS_XTD29_0:
1369         case WM8962_VSS_XTD30_1:
1370         case WM8962_VSS_XTD30_0:
1371         case WM8962_VSS_XTD31_1:
1372         case WM8962_VSS_XTD31_0:
1373         case WM8962_VSS_XTD32_1:
1374         case WM8962_VSS_XTD32_0:
1375         case WM8962_VSS_XTS1_1:
1376         case WM8962_VSS_XTS1_0:
1377         case WM8962_VSS_XTS2_1:
1378         case WM8962_VSS_XTS2_0:
1379         case WM8962_VSS_XTS3_1:
1380         case WM8962_VSS_XTS3_0:
1381         case WM8962_VSS_XTS4_1:
1382         case WM8962_VSS_XTS4_0:
1383         case WM8962_VSS_XTS5_1:
1384         case WM8962_VSS_XTS5_0:
1385         case WM8962_VSS_XTS6_1:
1386         case WM8962_VSS_XTS6_0:
1387         case WM8962_VSS_XTS7_1:
1388         case WM8962_VSS_XTS7_0:
1389         case WM8962_VSS_XTS8_1:
1390         case WM8962_VSS_XTS8_0:
1391         case WM8962_VSS_XTS9_1:
1392         case WM8962_VSS_XTS9_0:
1393         case WM8962_VSS_XTS10_1:
1394         case WM8962_VSS_XTS10_0:
1395         case WM8962_VSS_XTS11_1:
1396         case WM8962_VSS_XTS11_0:
1397         case WM8962_VSS_XTS12_1:
1398         case WM8962_VSS_XTS12_0:
1399         case WM8962_VSS_XTS13_1:
1400         case WM8962_VSS_XTS13_0:
1401         case WM8962_VSS_XTS14_1:
1402         case WM8962_VSS_XTS14_0:
1403         case WM8962_VSS_XTS15_1:
1404         case WM8962_VSS_XTS15_0:
1405         case WM8962_VSS_XTS16_1:
1406         case WM8962_VSS_XTS16_0:
1407         case WM8962_VSS_XTS17_1:
1408         case WM8962_VSS_XTS17_0:
1409         case WM8962_VSS_XTS18_1:
1410         case WM8962_VSS_XTS18_0:
1411         case WM8962_VSS_XTS19_1:
1412         case WM8962_VSS_XTS19_0:
1413         case WM8962_VSS_XTS20_1:
1414         case WM8962_VSS_XTS20_0:
1415         case WM8962_VSS_XTS21_1:
1416         case WM8962_VSS_XTS21_0:
1417         case WM8962_VSS_XTS22_1:
1418         case WM8962_VSS_XTS22_0:
1419         case WM8962_VSS_XTS23_1:
1420         case WM8962_VSS_XTS23_0:
1421         case WM8962_VSS_XTS24_1:
1422         case WM8962_VSS_XTS24_0:
1423         case WM8962_VSS_XTS25_1:
1424         case WM8962_VSS_XTS25_0:
1425         case WM8962_VSS_XTS26_1:
1426         case WM8962_VSS_XTS26_0:
1427         case WM8962_VSS_XTS27_1:
1428         case WM8962_VSS_XTS27_0:
1429         case WM8962_VSS_XTS28_1:
1430         case WM8962_VSS_XTS28_0:
1431         case WM8962_VSS_XTS29_1:
1432         case WM8962_VSS_XTS29_0:
1433         case WM8962_VSS_XTS30_1:
1434         case WM8962_VSS_XTS30_0:
1435         case WM8962_VSS_XTS31_1:
1436         case WM8962_VSS_XTS31_0:
1437         case WM8962_VSS_XTS32_1:
1438         case WM8962_VSS_XTS32_0:
1439                 return true;
1440         default:
1441                 return false;
1442         }
1443 }
1444
1445 static int wm8962_reset(struct wm8962_priv *wm8962)
1446 {
1447         int ret;
1448
1449         ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1450         if (ret != 0)
1451                 return ret;
1452
1453         return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1454 }
1455
1456 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1457 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1458 static const unsigned int mixinpga_tlv[] = {
1459         TLV_DB_RANGE_HEAD(5),
1460         0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1461         2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1462         3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1463         5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1464         6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1465 };
1466 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1467 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1468 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1469 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1470 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1471 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1472 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1473 static const unsigned int classd_tlv[] = {
1474         TLV_DB_RANGE_HEAD(2),
1475         0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1476         7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1477 };
1478 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1479
1480 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1481 {
1482         return regcache_sync_region(codec->control_data,
1483                                     WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1484 }
1485
1486 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1487 {
1488         u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1489         u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1490         u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1491
1492         /* Mute the ADCs and DACs */
1493         snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1494         snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1495         snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1496                             WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1497
1498         snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1499
1500         /* Restore the ADCs and DACs */
1501         snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1502         snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1503         snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1504                             WM8962_DAC_MUTE, dac);
1505
1506         return 0;
1507 }
1508
1509 static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1510 {
1511         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1512
1513         wm8962_dsp2_write_config(codec);
1514
1515         snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1516
1517         wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1518
1519         return 0;
1520 }
1521
1522 static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1523 {
1524         wm8962_dsp2_set_enable(codec, 0);
1525
1526         snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1527
1528         return 0;
1529 }
1530
1531 #define WM8962_DSP2_ENABLE(xname, xshift) \
1532 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1533         .info = wm8962_dsp2_ena_info, \
1534         .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1535         .private_value = xshift }
1536
1537 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1538                                 struct snd_ctl_elem_info *uinfo)
1539 {
1540         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1541
1542         uinfo->count = 1;
1543         uinfo->value.integer.min = 0;
1544         uinfo->value.integer.max = 1;
1545
1546         return 0;
1547 }
1548
1549 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1550                                struct snd_ctl_elem_value *ucontrol)
1551 {
1552         int shift = kcontrol->private_value;
1553         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1554         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1555
1556         ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1557
1558         return 0;
1559 }
1560
1561 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1562                                struct snd_ctl_elem_value *ucontrol)
1563 {
1564         int shift = kcontrol->private_value;
1565         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1566         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1567         int old = wm8962->dsp2_ena;
1568         int ret = 0;
1569         int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1570                 WM8962_DSP2_ENA;
1571
1572         mutex_lock(&codec->mutex);
1573
1574         if (ucontrol->value.integer.value[0])
1575                 wm8962->dsp2_ena |= 1 << shift;
1576         else
1577                 wm8962->dsp2_ena &= ~(1 << shift);
1578
1579         if (wm8962->dsp2_ena == old)
1580                 goto out;
1581
1582         ret = 1;
1583
1584         if (dsp2_running) {
1585                 if (wm8962->dsp2_ena)
1586                         wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1587                 else
1588                         wm8962_dsp2_stop(codec);
1589         }
1590
1591 out:
1592         mutex_unlock(&codec->mutex);
1593
1594         return ret;
1595 }
1596
1597 /* The VU bits for the headphones are in a different register to the mute
1598  * bits and only take effect on the PGA if it is actually powered.
1599  */
1600 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1601                             struct snd_ctl_elem_value *ucontrol)
1602 {
1603         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1604         int ret;
1605
1606         /* Apply the update (if any) */
1607         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1608         if (ret == 0)
1609                 return 0;
1610
1611         /* If the left PGA is enabled hit that VU bit... */
1612         ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1613         if (ret & WM8962_HPOUTL_PGA_ENA) {
1614                 snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1615                               snd_soc_read(codec, WM8962_HPOUTL_VOLUME));
1616                 return 1;
1617         }
1618
1619         /* ...otherwise the right.  The VU is stereo. */
1620         if (ret & WM8962_HPOUTR_PGA_ENA)
1621                 snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1622                               snd_soc_read(codec, WM8962_HPOUTR_VOLUME));
1623
1624         return 1;
1625 }
1626
1627 /* The VU bits for the speakers are in a different register to the mute
1628  * bits and only take effect on the PGA if it is actually powered.
1629  */
1630 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1631                             struct snd_ctl_elem_value *ucontrol)
1632 {
1633         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1634         int ret;
1635
1636         /* Apply the update (if any) */
1637         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1638         if (ret == 0)
1639                 return 0;
1640
1641         /* If the left PGA is enabled hit that VU bit... */
1642         ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1643         if (ret & WM8962_SPKOUTL_PGA_ENA) {
1644                 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1645                               snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1646                 return 1;
1647         }
1648
1649         /* ...otherwise the right.  The VU is stereo. */
1650         if (ret & WM8962_SPKOUTR_PGA_ENA)
1651                 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1652                               snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1653
1654         return 1;
1655 }
1656
1657 static const char *cap_hpf_mode_text[] = {
1658         "Hi-fi", "Application"
1659 };
1660
1661 static const struct soc_enum cap_hpf_mode =
1662         SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1663
1664
1665 static const char *cap_lhpf_mode_text[] = {
1666         "LPF", "HPF"
1667 };
1668
1669 static const struct soc_enum cap_lhpf_mode =
1670         SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1671
1672 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1673 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1674
1675 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1676                mixin_tlv),
1677 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1678                mixinpga_tlv),
1679 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1680                mixin_tlv),
1681
1682 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1683                mixin_tlv),
1684 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1685                mixinpga_tlv),
1686 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1687                mixin_tlv),
1688
1689 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1690                  WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1691 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1692                  WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1693 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1694              WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1695 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1696              WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1697 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1698 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1699 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1700 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1701 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1702
1703 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1704                  WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1705
1706 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1707                  WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1708 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1709 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1710 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1711
1712 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1713            5, 1, 0),
1714
1715 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1716
1717 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1718                  WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1719 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1720                snd_soc_get_volsw, wm8962_put_hp_sw),
1721 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1722              7, 1, 0),
1723 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1724                hp_tlv),
1725
1726 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1727              WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1728
1729 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1730                3, 7, 0, bypass_tlv),
1731 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1732                0, 7, 0, bypass_tlv),
1733 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1734                7, 1, 1, inmix_tlv),
1735 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1736                6, 1, 1, inmix_tlv),
1737
1738 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1739                3, 7, 0, bypass_tlv),
1740 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1741                0, 7, 0, bypass_tlv),
1742 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1743                7, 1, 1, inmix_tlv),
1744 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1745                6, 1, 1, inmix_tlv),
1746
1747 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1748                classd_tlv),
1749
1750 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1751 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1752                  WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1753 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1754                  WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1755 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1756                  WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1757 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1758                  WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1759 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1760                  WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1761 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1762 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1763
1764
1765 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1766 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1767
1768 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1769 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1770
1771 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1772 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1773
1774 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1775 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1776 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1777 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1778 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1779 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1780 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1781
1782 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1783                 WM8962_ALCR_ENA_SHIFT, 1, 0),
1784 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1785                 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1786 };
1787
1788 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1789 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1790 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1791                snd_soc_get_volsw, wm8962_put_spk_sw),
1792 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1793
1794 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1795 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1796                3, 7, 0, bypass_tlv),
1797 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1798                0, 7, 0, bypass_tlv),
1799 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1800                7, 1, 1, inmix_tlv),
1801 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1802                6, 1, 1, inmix_tlv),
1803 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1804                7, 1, 0, inmix_tlv),
1805 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1806                6, 1, 0, inmix_tlv),
1807 };
1808
1809 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1810 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1811                  WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1812 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1813                snd_soc_get_volsw, wm8962_put_spk_sw),
1814 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1815              7, 1, 0),
1816
1817 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1818              WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1819
1820 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1821                3, 7, 0, bypass_tlv),
1822 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1823                0, 7, 0, bypass_tlv),
1824 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1825                7, 1, 1, inmix_tlv),
1826 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1827                6, 1, 1, inmix_tlv),
1828 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1829                7, 1, 0, inmix_tlv),
1830 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1831                6, 1, 0, inmix_tlv),
1832
1833 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1834                3, 7, 0, bypass_tlv),
1835 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1836                0, 7, 0, bypass_tlv),
1837 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1838                7, 1, 1, inmix_tlv),
1839 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1840                6, 1, 1, inmix_tlv),
1841 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1842                5, 1, 0, inmix_tlv),
1843 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1844                4, 1, 0, inmix_tlv),
1845 };
1846
1847 static int cp_event(struct snd_soc_dapm_widget *w,
1848                     struct snd_kcontrol *kcontrol, int event)
1849 {
1850         switch (event) {
1851         case SND_SOC_DAPM_POST_PMU:
1852                 msleep(5);
1853                 break;
1854
1855         default:
1856                 WARN(1, "Invalid event %d\n", event);
1857                 return -EINVAL;
1858         }
1859
1860         return 0;
1861 }
1862
1863 static int hp_event(struct snd_soc_dapm_widget *w,
1864                     struct snd_kcontrol *kcontrol, int event)
1865 {
1866         struct snd_soc_codec *codec = w->codec;
1867         int timeout;
1868         int reg;
1869         int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1870                         WM8962_DCS_STARTUP_DONE_HP1R);
1871
1872         switch (event) {
1873         case SND_SOC_DAPM_POST_PMU:
1874                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1875                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1876                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1877                 udelay(20);
1878
1879                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1880                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1881                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1882
1883                 /* Start the DC servo */
1884                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1885                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1886                                     WM8962_HP1L_DCS_STARTUP |
1887                                     WM8962_HP1R_DCS_STARTUP,
1888                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1889                                     WM8962_HP1L_DCS_STARTUP |
1890                                     WM8962_HP1R_DCS_STARTUP);
1891
1892                 /* Wait for it to complete, should be well under 100ms */
1893                 timeout = 0;
1894                 do {
1895                         msleep(1);
1896                         reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1897                         if (reg < 0) {
1898                                 dev_err(codec->dev,
1899                                         "Failed to read DCS status: %d\n",
1900                                         reg);
1901                                 continue;
1902                         }
1903                         dev_dbg(codec->dev, "DCS status: %x\n", reg);
1904                 } while (++timeout < 200 && (reg & expected) != expected);
1905
1906                 if ((reg & expected) != expected)
1907                         dev_err(codec->dev, "DC servo timed out\n");
1908                 else
1909                         dev_dbg(codec->dev, "DC servo complete after %dms\n",
1910                                 timeout);
1911
1912                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1913                                     WM8962_HP1L_ENA_OUTP |
1914                                     WM8962_HP1R_ENA_OUTP,
1915                                     WM8962_HP1L_ENA_OUTP |
1916                                     WM8962_HP1R_ENA_OUTP);
1917                 udelay(20);
1918
1919                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1920                                     WM8962_HP1L_RMV_SHORT |
1921                                     WM8962_HP1R_RMV_SHORT,
1922                                     WM8962_HP1L_RMV_SHORT |
1923                                     WM8962_HP1R_RMV_SHORT);
1924                 break;
1925
1926         case SND_SOC_DAPM_PRE_PMD:
1927                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1928                                     WM8962_HP1L_RMV_SHORT |
1929                                     WM8962_HP1R_RMV_SHORT, 0);
1930
1931                 udelay(20);
1932
1933                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1934                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1935                                     WM8962_HP1L_DCS_STARTUP |
1936                                     WM8962_HP1R_DCS_STARTUP,
1937                                     0);
1938
1939                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1940                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1941                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1942                                     WM8962_HP1L_ENA_OUTP |
1943                                     WM8962_HP1R_ENA_OUTP, 0);
1944
1945                 break;
1946
1947         default:
1948                 WARN(1, "Invalid event %d\n", event);
1949                 return -EINVAL;
1950
1951         }
1952
1953         return 0;
1954 }
1955
1956 /* VU bits for the output PGAs only take effect while the PGA is powered */
1957 static int out_pga_event(struct snd_soc_dapm_widget *w,
1958                          struct snd_kcontrol *kcontrol, int event)
1959 {
1960         struct snd_soc_codec *codec = w->codec;
1961         int reg;
1962
1963         switch (w->shift) {
1964         case WM8962_HPOUTR_PGA_ENA_SHIFT:
1965                 reg = WM8962_HPOUTR_VOLUME;
1966                 break;
1967         case WM8962_HPOUTL_PGA_ENA_SHIFT:
1968                 reg = WM8962_HPOUTL_VOLUME;
1969                 break;
1970         case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1971                 reg = WM8962_SPKOUTR_VOLUME;
1972                 break;
1973         case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1974                 reg = WM8962_SPKOUTL_VOLUME;
1975                 break;
1976         default:
1977                 WARN(1, "Invalid shift %d\n", w->shift);
1978                 return -EINVAL;
1979         }
1980
1981         switch (event) {
1982         case SND_SOC_DAPM_POST_PMU:
1983                 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1984         default:
1985                 WARN(1, "Invalid event %d\n", event);
1986                 return -EINVAL;
1987         }
1988 }
1989
1990 static int dsp2_event(struct snd_soc_dapm_widget *w,
1991                       struct snd_kcontrol *kcontrol, int event)
1992 {
1993         struct snd_soc_codec *codec = w->codec;
1994         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1995
1996         switch (event) {
1997         case SND_SOC_DAPM_POST_PMU:
1998                 if (wm8962->dsp2_ena)
1999                         wm8962_dsp2_start(codec);
2000                 break;
2001
2002         case SND_SOC_DAPM_PRE_PMD:
2003                 if (wm8962->dsp2_ena)
2004                         wm8962_dsp2_stop(codec);
2005                 break;
2006
2007         default:
2008                 WARN(1, "Invalid event %d\n", event);
2009                 return -EINVAL;
2010         }
2011
2012         return 0;
2013 }
2014
2015 static const char *st_text[] = { "None", "Left", "Right" };
2016
2017 static const struct soc_enum str_enum =
2018         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2019
2020 static const struct snd_kcontrol_new str_mux =
2021         SOC_DAPM_ENUM("Right Sidetone", str_enum);
2022
2023 static const struct soc_enum stl_enum =
2024         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2025
2026 static const struct snd_kcontrol_new stl_mux =
2027         SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2028
2029 static const char *outmux_text[] = { "DAC", "Mixer" };
2030
2031 static const struct soc_enum spkoutr_enum =
2032         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2033
2034 static const struct snd_kcontrol_new spkoutr_mux =
2035         SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2036
2037 static const struct soc_enum spkoutl_enum =
2038         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2039
2040 static const struct snd_kcontrol_new spkoutl_mux =
2041         SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2042
2043 static const struct soc_enum hpoutr_enum =
2044         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2045
2046 static const struct snd_kcontrol_new hpoutr_mux =
2047         SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2048
2049 static const struct soc_enum hpoutl_enum =
2050         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2051
2052 static const struct snd_kcontrol_new hpoutl_mux =
2053         SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2054
2055 static const struct snd_kcontrol_new inpgal[] = {
2056 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2057 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2058 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2059 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2060 };
2061
2062 static const struct snd_kcontrol_new inpgar[] = {
2063 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2064 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2065 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2066 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2067 };
2068
2069 static const struct snd_kcontrol_new mixinl[] = {
2070 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2071 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2072 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2073 };
2074
2075 static const struct snd_kcontrol_new mixinr[] = {
2076 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2077 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2078 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2079 };
2080
2081 static const struct snd_kcontrol_new hpmixl[] = {
2082 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2083 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2084 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2085 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2086 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2087 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2088 };
2089
2090 static const struct snd_kcontrol_new hpmixr[] = {
2091 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2092 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2093 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2094 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2095 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2096 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2097 };
2098
2099 static const struct snd_kcontrol_new spkmixl[] = {
2100 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2101 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2102 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2103 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2104 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2105 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2106 };
2107
2108 static const struct snd_kcontrol_new spkmixr[] = {
2109 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2110 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2111 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2112 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2113 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2114 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2115 };
2116
2117 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2118 SND_SOC_DAPM_INPUT("IN1L"),
2119 SND_SOC_DAPM_INPUT("IN1R"),
2120 SND_SOC_DAPM_INPUT("IN2L"),
2121 SND_SOC_DAPM_INPUT("IN2R"),
2122 SND_SOC_DAPM_INPUT("IN3L"),
2123 SND_SOC_DAPM_INPUT("IN3R"),
2124 SND_SOC_DAPM_INPUT("IN4L"),
2125 SND_SOC_DAPM_INPUT("IN4R"),
2126 SND_SOC_DAPM_SIGGEN("Beep"),
2127 SND_SOC_DAPM_INPUT("DMICDAT"),
2128
2129 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2130
2131 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2132 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2133 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2134                     SND_SOC_DAPM_POST_PMU),
2135 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2136 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2137                       WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2138                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2139 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2140 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2141
2142 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2143                    inpgal, ARRAY_SIZE(inpgal)),
2144 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2145                    inpgar, ARRAY_SIZE(inpgar)),
2146 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2147                    mixinl, ARRAY_SIZE(mixinl)),
2148 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2149                    mixinr, ARRAY_SIZE(mixinr)),
2150
2151 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2152
2153 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2154 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2155
2156 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2157 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2158
2159 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2160 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2161
2162 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2163 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2164
2165 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2166                    hpmixl, ARRAY_SIZE(hpmixl)),
2167 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2168                    hpmixr, ARRAY_SIZE(hpmixr)),
2169
2170 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2171                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2172 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2173                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2174
2175 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2176                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2177
2178 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2179 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2180 };
2181
2182 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2183 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2184                    spkmixl, ARRAY_SIZE(spkmixl)),
2185 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2186                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2187 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2188 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2189 };
2190
2191 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2192 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2193                    spkmixl, ARRAY_SIZE(spkmixl)),
2194 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2195                    spkmixr, ARRAY_SIZE(spkmixr)),
2196
2197 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2198                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2199 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2200                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2201
2202 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2203 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2204
2205 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2206 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2207 };
2208
2209 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2210         { "INPGAL", "IN1L Switch", "IN1L" },
2211         { "INPGAL", "IN2L Switch", "IN2L" },
2212         { "INPGAL", "IN3L Switch", "IN3L" },
2213         { "INPGAL", "IN4L Switch", "IN4L" },
2214
2215         { "INPGAR", "IN1R Switch", "IN1R" },
2216         { "INPGAR", "IN2R Switch", "IN2R" },
2217         { "INPGAR", "IN3R Switch", "IN3R" },
2218         { "INPGAR", "IN4R Switch", "IN4R" },
2219
2220         { "MIXINL", "IN2L Switch", "IN2L" },
2221         { "MIXINL", "IN3L Switch", "IN3L" },
2222         { "MIXINL", "PGA Switch", "INPGAL" },
2223
2224         { "MIXINR", "IN2R Switch", "IN2R" },
2225         { "MIXINR", "IN3R Switch", "IN3R" },
2226         { "MIXINR", "PGA Switch", "INPGAR" },
2227
2228         { "MICBIAS", NULL, "SYSCLK" },
2229
2230         { "DMIC_ENA", NULL, "DMICDAT" },
2231
2232         { "ADCL", NULL, "SYSCLK" },
2233         { "ADCL", NULL, "TOCLK" },
2234         { "ADCL", NULL, "MIXINL" },
2235         { "ADCL", NULL, "DMIC_ENA" },
2236         { "ADCL", NULL, "DSP2" },
2237
2238         { "ADCR", NULL, "SYSCLK" },
2239         { "ADCR", NULL, "TOCLK" },
2240         { "ADCR", NULL, "MIXINR" },
2241         { "ADCR", NULL, "DMIC_ENA" },
2242         { "ADCR", NULL, "DSP2" },
2243
2244         { "STL", "Left", "ADCL" },
2245         { "STL", "Right", "ADCR" },
2246         { "STL", NULL, "Class G" },
2247
2248         { "STR", "Left", "ADCL" },
2249         { "STR", "Right", "ADCR" },
2250         { "STR", NULL, "Class G" },
2251
2252         { "DACL", NULL, "SYSCLK" },
2253         { "DACL", NULL, "TOCLK" },
2254         { "DACL", NULL, "Beep" },
2255         { "DACL", NULL, "STL" },
2256         { "DACL", NULL, "DSP2" },
2257
2258         { "DACR", NULL, "SYSCLK" },
2259         { "DACR", NULL, "TOCLK" },
2260         { "DACR", NULL, "Beep" },
2261         { "DACR", NULL, "STR" },
2262         { "DACR", NULL, "DSP2" },
2263
2264         { "HPMIXL", "IN4L Switch", "IN4L" },
2265         { "HPMIXL", "IN4R Switch", "IN4R" },
2266         { "HPMIXL", "DACL Switch", "DACL" },
2267         { "HPMIXL", "DACR Switch", "DACR" },
2268         { "HPMIXL", "MIXINL Switch", "MIXINL" },
2269         { "HPMIXL", "MIXINR Switch", "MIXINR" },
2270
2271         { "HPMIXR", "IN4L Switch", "IN4L" },
2272         { "HPMIXR", "IN4R Switch", "IN4R" },
2273         { "HPMIXR", "DACL Switch", "DACL" },
2274         { "HPMIXR", "DACR Switch", "DACR" },
2275         { "HPMIXR", "MIXINL Switch", "MIXINL" },
2276         { "HPMIXR", "MIXINR Switch", "MIXINR" },
2277
2278         { "Left Bypass", NULL, "HPMIXL" },
2279         { "Left Bypass", NULL, "Class G" },
2280
2281         { "Right Bypass", NULL, "HPMIXR" },
2282         { "Right Bypass", NULL, "Class G" },
2283
2284         { "HPOUTL PGA", "Mixer", "Left Bypass" },
2285         { "HPOUTL PGA", "DAC", "DACL" },
2286
2287         { "HPOUTR PGA", "Mixer", "Right Bypass" },
2288         { "HPOUTR PGA", "DAC", "DACR" },
2289
2290         { "HPOUT", NULL, "HPOUTL PGA" },
2291         { "HPOUT", NULL, "HPOUTR PGA" },
2292         { "HPOUT", NULL, "Charge Pump" },
2293         { "HPOUT", NULL, "SYSCLK" },
2294         { "HPOUT", NULL, "TOCLK" },
2295
2296         { "HPOUTL", NULL, "HPOUT" },
2297         { "HPOUTR", NULL, "HPOUT" },
2298
2299         { "HPOUTL", NULL, "TEMP_HP" },
2300         { "HPOUTR", NULL, "TEMP_HP" },
2301 };
2302
2303 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2304         { "Speaker Mixer", "IN4L Switch", "IN4L" },
2305         { "Speaker Mixer", "IN4R Switch", "IN4R" },
2306         { "Speaker Mixer", "DACL Switch", "DACL" },
2307         { "Speaker Mixer", "DACR Switch", "DACR" },
2308         { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2309         { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2310
2311         { "Speaker PGA", "Mixer", "Speaker Mixer" },
2312         { "Speaker PGA", "DAC", "DACL" },
2313
2314         { "Speaker Output", NULL, "Speaker PGA" },
2315         { "Speaker Output", NULL, "SYSCLK" },
2316         { "Speaker Output", NULL, "TOCLK" },
2317         { "Speaker Output", NULL, "TEMP_SPK" },
2318
2319         { "SPKOUT", NULL, "Speaker Output" },
2320 };
2321
2322 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2323         { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2324         { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2325         { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2326         { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2327         { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2328         { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2329
2330         { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2331         { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2332         { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2333         { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2334         { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2335         { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2336
2337         { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2338         { "SPKOUTL PGA", "DAC", "DACL" },
2339
2340         { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2341         { "SPKOUTR PGA", "DAC", "DACR" },
2342
2343         { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2344         { "SPKOUTL Output", NULL, "SYSCLK" },
2345         { "SPKOUTL Output", NULL, "TOCLK" },
2346         { "SPKOUTL Output", NULL, "TEMP_SPK" },
2347
2348         { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2349         { "SPKOUTR Output", NULL, "SYSCLK" },
2350         { "SPKOUTR Output", NULL, "TOCLK" },
2351         { "SPKOUTR Output", NULL, "TEMP_SPK" },
2352
2353         { "SPKOUTL", NULL, "SPKOUTL Output" },
2354         { "SPKOUTR", NULL, "SPKOUTR Output" },
2355 };
2356
2357 static int wm8962_add_widgets(struct snd_soc_codec *codec)
2358 {
2359         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2360         struct wm8962_pdata *pdata = &wm8962->pdata;
2361         struct snd_soc_dapm_context *dapm = &codec->dapm;
2362
2363         snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2364                              ARRAY_SIZE(wm8962_snd_controls));
2365         if (pdata->spk_mono)
2366                 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2367                                      ARRAY_SIZE(wm8962_spk_mono_controls));
2368         else
2369                 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2370                                      ARRAY_SIZE(wm8962_spk_stereo_controls));
2371
2372
2373         snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2374                                   ARRAY_SIZE(wm8962_dapm_widgets));
2375         if (pdata->spk_mono)
2376                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2377                                           ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2378         else
2379                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2380                                           ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2381
2382         snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2383                                 ARRAY_SIZE(wm8962_intercon));
2384         if (pdata->spk_mono)
2385                 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2386                                         ARRAY_SIZE(wm8962_spk_mono_intercon));
2387         else
2388                 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2389                                         ARRAY_SIZE(wm8962_spk_stereo_intercon));
2390
2391
2392         snd_soc_dapm_disable_pin(dapm, "Beep");
2393
2394         return 0;
2395 }
2396
2397 /* -1 for reserved values */
2398 static const int bclk_divs[] = {
2399         1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2400 };
2401
2402 static const int sysclk_rates[] = {
2403         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2404 };
2405
2406 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2407 {
2408         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2409         int dspclk, i;
2410         int clocking2 = 0;
2411         int clocking4 = 0;
2412         int aif2 = 0;
2413
2414         if (!wm8962->sysclk_rate) {
2415                 dev_dbg(codec->dev, "No SYSCLK configured\n");
2416                 return;
2417         }
2418
2419         if (!wm8962->bclk || !wm8962->lrclk) {
2420                 dev_dbg(codec->dev, "No audio clocks configured\n");
2421                 return;
2422         }
2423
2424         for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2425                 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2426                         clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2427                         break;
2428                 }
2429         }
2430
2431         if (i == ARRAY_SIZE(sysclk_rates)) {
2432                 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2433                         wm8962->sysclk_rate / wm8962->lrclk);
2434                 return;
2435         }
2436
2437         dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2438
2439         snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2440                             WM8962_SYSCLK_RATE_MASK, clocking4);
2441
2442         /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2443          * So we here provisionally enable it and then disable it afterward
2444          * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2445          */
2446         if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2447                 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2448                                 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2449
2450         dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2451
2452         if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2453                 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2454                                 WM8962_SYSCLK_ENA_MASK, 0);
2455
2456         if (dspclk < 0) {
2457                 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2458                 return;
2459         }
2460
2461         dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2462         switch (dspclk) {
2463         case 0:
2464                 dspclk = wm8962->sysclk_rate;
2465                 break;
2466         case 1:
2467                 dspclk = wm8962->sysclk_rate / 2;
2468                 break;
2469         case 2:
2470                 dspclk = wm8962->sysclk_rate / 4;
2471                 break;
2472         default:
2473                 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2474                 dspclk = wm8962->sysclk;
2475         }
2476
2477         dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2478
2479         /* We're expecting an exact match */
2480         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2481                 if (bclk_divs[i] < 0)
2482                         continue;
2483
2484                 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2485                         dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2486                                 bclk_divs[i], wm8962->bclk);
2487                         clocking2 |= i;
2488                         break;
2489                 }
2490         }
2491         if (i == ARRAY_SIZE(bclk_divs)) {
2492                 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2493                         dspclk / wm8962->bclk);
2494                 return;
2495         }
2496
2497         aif2 |= wm8962->bclk / wm8962->lrclk;
2498         dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2499                 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2500
2501         snd_soc_update_bits(codec, WM8962_CLOCKING2,
2502                             WM8962_BCLK_DIV_MASK, clocking2);
2503         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2504                             WM8962_AIF_RATE_MASK, aif2);
2505 }
2506
2507 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2508                                  enum snd_soc_bias_level level)
2509 {
2510         if (level == codec->dapm.bias_level)
2511                 return 0;
2512
2513         switch (level) {
2514         case SND_SOC_BIAS_ON:
2515                 break;
2516
2517         case SND_SOC_BIAS_PREPARE:
2518                 /* VMID 2*50k */
2519                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2520                                     WM8962_VMID_SEL_MASK, 0x80);
2521
2522                 wm8962_configure_bclk(codec);
2523                 break;
2524
2525         case SND_SOC_BIAS_STANDBY:
2526                 /* VMID 2*250k */
2527                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2528                                     WM8962_VMID_SEL_MASK, 0x100);
2529
2530                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2531                         msleep(100);
2532                 break;
2533
2534         case SND_SOC_BIAS_OFF:
2535                 break;
2536         }
2537
2538         codec->dapm.bias_level = level;
2539         return 0;
2540 }
2541
2542 static const struct {
2543         int rate;
2544         int reg;
2545 } sr_vals[] = {
2546         { 48000, 0 },
2547         { 44100, 0 },
2548         { 32000, 1 },
2549         { 22050, 2 },
2550         { 24000, 2 },
2551         { 16000, 3 },
2552         { 11025, 4 },
2553         { 12000, 4 },
2554         { 8000,  5 },
2555         { 88200, 6 },
2556         { 96000, 6 },
2557 };
2558
2559 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2560                             struct snd_pcm_hw_params *params,
2561                             struct snd_soc_dai *dai)
2562 {
2563         struct snd_soc_codec *codec = dai->codec;
2564         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2565         int i;
2566         int aif0 = 0;
2567         int adctl3 = 0;
2568
2569         wm8962->bclk = snd_soc_params_to_bclk(params);
2570         if (params_channels(params) == 1)
2571                 wm8962->bclk *= 2;
2572
2573         wm8962->lrclk = params_rate(params);
2574
2575         for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2576                 if (sr_vals[i].rate == wm8962->lrclk) {
2577                         adctl3 |= sr_vals[i].reg;
2578                         break;
2579                 }
2580         }
2581         if (i == ARRAY_SIZE(sr_vals)) {
2582                 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2583                 return -EINVAL;
2584         }
2585
2586         if (wm8962->lrclk % 8000 == 0)
2587                 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2588
2589         switch (params_format(params)) {
2590         case SNDRV_PCM_FORMAT_S16_LE:
2591                 break;
2592         case SNDRV_PCM_FORMAT_S20_3LE:
2593                 aif0 |= 0x4;
2594                 break;
2595         case SNDRV_PCM_FORMAT_S24_LE:
2596                 aif0 |= 0x8;
2597                 break;
2598         case SNDRV_PCM_FORMAT_S32_LE:
2599                 aif0 |= 0xc;
2600                 break;
2601         default:
2602                 return -EINVAL;
2603         }
2604
2605         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2606                             WM8962_WL_MASK, aif0);
2607         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2608                             WM8962_SAMPLE_RATE_INT_MODE |
2609                             WM8962_SAMPLE_RATE_MASK, adctl3);
2610
2611         dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2612                 wm8962->bclk, wm8962->lrclk);
2613
2614         if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2615                 wm8962_configure_bclk(codec);
2616
2617         return 0;
2618 }
2619
2620 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2621                                  unsigned int freq, int dir)
2622 {
2623         struct snd_soc_codec *codec = dai->codec;
2624         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2625         int src;
2626
2627         switch (clk_id) {
2628         case WM8962_SYSCLK_MCLK:
2629                 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2630                 src = 0;
2631                 break;
2632         case WM8962_SYSCLK_FLL:
2633                 wm8962->sysclk = WM8962_SYSCLK_FLL;
2634                 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2635                 break;
2636         default:
2637                 return -EINVAL;
2638         }
2639
2640         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2641                             src);
2642
2643         wm8962->sysclk_rate = freq;
2644
2645         return 0;
2646 }
2647
2648 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2649 {
2650         struct snd_soc_codec *codec = dai->codec;
2651         int aif0 = 0;
2652
2653         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2654         case SND_SOC_DAIFMT_DSP_B:
2655                 aif0 |= WM8962_LRCLK_INV | 3;
2656         case SND_SOC_DAIFMT_DSP_A:
2657                 aif0 |= 3;
2658
2659                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2660                 case SND_SOC_DAIFMT_NB_NF:
2661                 case SND_SOC_DAIFMT_IB_NF:
2662                         break;
2663                 default:
2664                         return -EINVAL;
2665                 }
2666                 break;
2667
2668         case SND_SOC_DAIFMT_RIGHT_J:
2669                 break;
2670         case SND_SOC_DAIFMT_LEFT_J:
2671                 aif0 |= 1;
2672                 break;
2673         case SND_SOC_DAIFMT_I2S:
2674                 aif0 |= 2;
2675                 break;
2676         default:
2677                 return -EINVAL;
2678         }
2679
2680         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2681         case SND_SOC_DAIFMT_NB_NF:
2682                 break;
2683         case SND_SOC_DAIFMT_IB_NF:
2684                 aif0 |= WM8962_BCLK_INV;
2685                 break;
2686         case SND_SOC_DAIFMT_NB_IF:
2687                 aif0 |= WM8962_LRCLK_INV;
2688                 break;
2689         case SND_SOC_DAIFMT_IB_IF:
2690                 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2691                 break;
2692         default:
2693                 return -EINVAL;
2694         }
2695
2696         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2697         case SND_SOC_DAIFMT_CBM_CFM:
2698                 aif0 |= WM8962_MSTR;
2699                 break;
2700         case SND_SOC_DAIFMT_CBS_CFS:
2701                 break;
2702         default:
2703                 return -EINVAL;
2704         }
2705
2706         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2707                             WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2708                             WM8962_LRCLK_INV, aif0);
2709
2710         return 0;
2711 }
2712
2713 struct _fll_div {
2714         u16 fll_fratio;
2715         u16 fll_outdiv;
2716         u16 fll_refclk_div;
2717         u16 n;
2718         u16 theta;
2719         u16 lambda;
2720 };
2721
2722 /* The size in bits of the FLL divide multiplied by 10
2723  * to allow rounding later */
2724 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2725
2726 static struct {
2727         unsigned int min;
2728         unsigned int max;
2729         u16 fll_fratio;
2730         int ratio;
2731 } fll_fratios[] = {
2732         {       0,    64000, 4, 16 },
2733         {   64000,   128000, 3,  8 },
2734         {  128000,   256000, 2,  4 },
2735         {  256000,  1000000, 1,  2 },
2736         { 1000000, 13500000, 0,  1 },
2737 };
2738
2739 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2740                        unsigned int Fout)
2741 {
2742         unsigned int target;
2743         unsigned int div;
2744         unsigned int fratio, gcd_fll;
2745         int i;
2746
2747         /* Fref must be <=13.5MHz */
2748         div = 1;
2749         fll_div->fll_refclk_div = 0;
2750         while ((Fref / div) > 13500000) {
2751                 div *= 2;
2752                 fll_div->fll_refclk_div++;
2753
2754                 if (div > 4) {
2755                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2756                                Fref);
2757                         return -EINVAL;
2758                 }
2759         }
2760
2761         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2762
2763         /* Apply the division for our remaining calculations */
2764         Fref /= div;
2765
2766         /* Fvco should be 90-100MHz; don't check the upper bound */
2767         div = 2;
2768         while (Fout * div < 90000000) {
2769                 div++;
2770                 if (div > 64) {
2771                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2772                                Fout);
2773                         return -EINVAL;
2774                 }
2775         }
2776         target = Fout * div;
2777         fll_div->fll_outdiv = div - 1;
2778
2779         pr_debug("FLL Fvco=%dHz\n", target);
2780
2781         /* Find an appropriate FLL_FRATIO and factor it out of the target */
2782         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2783                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2784                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2785                         fratio = fll_fratios[i].ratio;
2786                         break;
2787                 }
2788         }
2789         if (i == ARRAY_SIZE(fll_fratios)) {
2790                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2791                 return -EINVAL;
2792         }
2793
2794         fll_div->n = target / (fratio * Fref);
2795
2796         if (target % Fref == 0) {
2797                 fll_div->theta = 0;
2798                 fll_div->lambda = 0;
2799         } else {
2800                 gcd_fll = gcd(target, fratio * Fref);
2801
2802                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2803                         / gcd_fll;
2804                 fll_div->lambda = (fratio * Fref) / gcd_fll;
2805         }
2806
2807         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2808                  fll_div->n, fll_div->theta, fll_div->lambda);
2809         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2810                  fll_div->fll_fratio, fll_div->fll_outdiv,
2811                  fll_div->fll_refclk_div);
2812
2813         return 0;
2814 }
2815
2816 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2817                           unsigned int Fref, unsigned int Fout)
2818 {
2819         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2820         struct _fll_div fll_div;
2821         unsigned long timeout;
2822         int ret;
2823         int fll1 = 0;
2824
2825         /* Any change? */
2826         if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2827             Fout == wm8962->fll_fout)
2828                 return 0;
2829
2830         if (Fout == 0) {
2831                 dev_dbg(codec->dev, "FLL disabled\n");
2832
2833                 wm8962->fll_fref = 0;
2834                 wm8962->fll_fout = 0;
2835
2836                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2837                                     WM8962_FLL_ENA, 0);
2838
2839                 pm_runtime_put(codec->dev);
2840
2841                 return 0;
2842         }
2843
2844         ret = fll_factors(&fll_div, Fref, Fout);
2845         if (ret != 0)
2846                 return ret;
2847
2848         /* Parameters good, disable so we can reprogram */
2849         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2850
2851         switch (fll_id) {
2852         case WM8962_FLL_MCLK:
2853         case WM8962_FLL_BCLK:
2854         case WM8962_FLL_OSC:
2855                 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2856                 break;
2857         case WM8962_FLL_INT:
2858                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2859                                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2860                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2861                                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2862                 break;
2863         default:
2864                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2865                 return -EINVAL;
2866         }
2867
2868         if (fll_div.theta || fll_div.lambda)
2869                 fll1 |= WM8962_FLL_FRAC;
2870
2871         /* Stop the FLL while we reconfigure */
2872         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2873
2874         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2875                             WM8962_FLL_OUTDIV_MASK |
2876                             WM8962_FLL_REFCLK_DIV_MASK,
2877                             (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2878                             (fll_div.fll_refclk_div));
2879
2880         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2881                             WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2882
2883         snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2884         snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2885         snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2886
2887         try_wait_for_completion(&wm8962->fll_lock);
2888
2889         pm_runtime_get_sync(codec->dev);
2890
2891         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2892                             WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2893                             WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2894
2895         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2896
2897         ret = 0;
2898
2899         /* This should be a massive overestimate but go even
2900          * higher if we'll error out
2901          */
2902         if (wm8962->irq)
2903                 timeout = msecs_to_jiffies(5);
2904         else
2905                 timeout = msecs_to_jiffies(1);
2906
2907         timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2908                                               timeout);
2909
2910         if (timeout == 0 && wm8962->irq) {
2911                 dev_err(codec->dev, "FLL lock timed out");
2912                 ret = -ETIMEDOUT;
2913         }
2914
2915         wm8962->fll_fref = Fref;
2916         wm8962->fll_fout = Fout;
2917         wm8962->fll_src = source;
2918
2919         return ret;
2920 }
2921
2922 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2923 {
2924         struct snd_soc_codec *codec = dai->codec;
2925         int val;
2926
2927         if (mute)
2928                 val = WM8962_DAC_MUTE;
2929         else
2930                 val = 0;
2931
2932         return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2933                                    WM8962_DAC_MUTE, val);
2934 }
2935
2936 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2937
2938 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2939                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2940
2941 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2942         .hw_params = wm8962_hw_params,
2943         .set_sysclk = wm8962_set_dai_sysclk,
2944         .set_fmt = wm8962_set_dai_fmt,
2945         .digital_mute = wm8962_mute,
2946 };
2947
2948 static struct snd_soc_dai_driver wm8962_dai = {
2949         .name = "wm8962",
2950         .playback = {
2951                 .stream_name = "Playback",
2952                 .channels_min = 1,
2953                 .channels_max = 2,
2954                 .rates = WM8962_RATES,
2955                 .formats = WM8962_FORMATS,
2956         },
2957         .capture = {
2958                 .stream_name = "Capture",
2959                 .channels_min = 1,
2960                 .channels_max = 2,
2961                 .rates = WM8962_RATES,
2962                 .formats = WM8962_FORMATS,
2963         },
2964         .ops = &wm8962_dai_ops,
2965         .symmetric_rates = 1,
2966 };
2967
2968 static void wm8962_mic_work(struct work_struct *work)
2969 {
2970         struct wm8962_priv *wm8962 = container_of(work,
2971                                                   struct wm8962_priv,
2972                                                   mic_work.work);
2973         struct snd_soc_codec *codec = wm8962->codec;
2974         int status = 0;
2975         int irq_pol = 0;
2976         int reg;
2977
2978         reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2979
2980         if (reg & WM8962_MICDET_STS) {
2981                 status |= SND_JACK_MICROPHONE;
2982                 irq_pol |= WM8962_MICD_IRQ_POL;
2983         }
2984
2985         if (reg & WM8962_MICSHORT_STS) {
2986                 status |= SND_JACK_BTN_0;
2987                 irq_pol |= WM8962_MICSCD_IRQ_POL;
2988         }
2989
2990         snd_soc_jack_report(wm8962->jack, status,
2991                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2992
2993         snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2994                             WM8962_MICSCD_IRQ_POL |
2995                             WM8962_MICD_IRQ_POL, irq_pol);
2996 }
2997
2998 static irqreturn_t wm8962_irq(int irq, void *data)
2999 {
3000         struct device *dev = data;
3001         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3002         unsigned int mask;
3003         unsigned int active;
3004         int reg, ret;
3005
3006         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3007                           &mask);
3008         if (ret != 0) {
3009                 dev_err(dev, "Failed to read interrupt mask: %d\n",
3010                         ret);
3011                 return IRQ_NONE;
3012         }
3013
3014         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3015         if (ret != 0) {
3016                 dev_err(dev, "Failed to read interrupt: %d\n", ret);
3017                 return IRQ_NONE;
3018         }
3019
3020         active &= ~mask;
3021
3022         if (!active)
3023                 return IRQ_NONE;
3024
3025         /* Acknowledge the interrupts */
3026         ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3027         if (ret != 0)
3028                 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3029
3030         if (active & WM8962_FLL_LOCK_EINT) {
3031                 dev_dbg(dev, "FLL locked\n");
3032                 complete(&wm8962->fll_lock);
3033         }
3034
3035         if (active & WM8962_FIFOS_ERR_EINT)
3036                 dev_err(dev, "FIFO error\n");
3037
3038         if (active & WM8962_TEMP_SHUT_EINT) {
3039                 dev_crit(dev, "Thermal shutdown\n");
3040
3041                 ret = regmap_read(wm8962->regmap,
3042                                   WM8962_THERMAL_SHUTDOWN_STATUS,  &reg);
3043                 if (ret != 0) {
3044                         dev_warn(dev, "Failed to read thermal status: %d\n",
3045                                  ret);
3046                         reg = 0;
3047                 }
3048
3049                 if (reg & WM8962_TEMP_ERR_HP)
3050                         dev_crit(dev, "Headphone thermal error\n");
3051                 if (reg & WM8962_TEMP_WARN_HP)
3052                         dev_crit(dev, "Headphone thermal warning\n");
3053                 if (reg & WM8962_TEMP_ERR_SPK)
3054                         dev_crit(dev, "Speaker thermal error\n");
3055                 if (reg & WM8962_TEMP_WARN_SPK)
3056                         dev_crit(dev, "Speaker thermal warning\n");
3057         }
3058
3059         if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3060                 dev_dbg(dev, "Microphone event detected\n");
3061
3062 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3063                 trace_snd_soc_jack_irq(dev_name(dev));
3064 #endif
3065
3066                 pm_wakeup_event(dev, 300);
3067
3068                 queue_delayed_work(system_power_efficient_wq,
3069                                    &wm8962->mic_work,
3070                                    msecs_to_jiffies(250));
3071         }
3072
3073         return IRQ_HANDLED;
3074 }
3075
3076 /**
3077  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3078  *
3079  * @codec:  WM8962 codec
3080  * @jack:   jack to report detection events on
3081  *
3082  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3083  * being used to bring out signals to the processor then only platform
3084  * data configuration is needed for WM8962 and processor GPIOs should
3085  * be configured using snd_soc_jack_add_gpios() instead.
3086  *
3087  * If no jack is supplied detection will be disabled.
3088  */
3089 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3090 {
3091         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3092         int irq_mask, enable;
3093
3094         wm8962->jack = jack;
3095         if (jack) {
3096                 irq_mask = 0;
3097                 enable = WM8962_MICDET_ENA;
3098         } else {
3099                 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3100                 enable = 0;
3101         }
3102
3103         snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3104                             WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3105         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3106                             WM8962_MICDET_ENA, enable);
3107
3108         /* Send an initial empty report */
3109         snd_soc_jack_report(wm8962->jack, 0,
3110                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3111
3112         if (jack) {
3113                 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
3114                 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
3115         } else {
3116                 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3117                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
3118         }
3119
3120         return 0;
3121 }
3122 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3123
3124 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3125 static int beep_rates[] = {
3126         500, 1000, 2000, 4000,
3127 };
3128
3129 static void wm8962_beep_work(struct work_struct *work)
3130 {
3131         struct wm8962_priv *wm8962 =
3132                 container_of(work, struct wm8962_priv, beep_work);
3133         struct snd_soc_codec *codec = wm8962->codec;
3134         struct snd_soc_dapm_context *dapm = &codec->dapm;
3135         int i;
3136         int reg = 0;
3137         int best = 0;
3138
3139         if (wm8962->beep_rate) {
3140                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3141                         if (abs(wm8962->beep_rate - beep_rates[i]) <
3142                             abs(wm8962->beep_rate - beep_rates[best]))
3143                                 best = i;
3144                 }
3145
3146                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3147                         beep_rates[best], wm8962->beep_rate);
3148
3149                 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3150
3151                 snd_soc_dapm_enable_pin(dapm, "Beep");
3152         } else {
3153                 dev_dbg(codec->dev, "Disabling beep\n");
3154                 snd_soc_dapm_disable_pin(dapm, "Beep");
3155         }
3156
3157         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3158                             WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3159
3160         snd_soc_dapm_sync(dapm);
3161 }
3162
3163 /* For usability define a way of injecting beep events for the device -
3164  * many systems will not have a keyboard.
3165  */
3166 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3167                              unsigned int code, int hz)
3168 {
3169         struct snd_soc_codec *codec = input_get_drvdata(dev);
3170         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3171
3172         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3173
3174         switch (code) {
3175         case SND_BELL:
3176                 if (hz)
3177                         hz = 1000;
3178         case SND_TONE:
3179                 break;
3180         default:
3181                 return -1;
3182         }
3183
3184         /* Kick the beep from a workqueue */
3185         wm8962->beep_rate = hz;
3186         schedule_work(&wm8962->beep_work);
3187         return 0;
3188 }
3189
3190 static ssize_t wm8962_beep_set(struct device *dev,
3191                                struct device_attribute *attr,
3192                                const char *buf, size_t count)
3193 {
3194         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3195         long int time;
3196         int ret;
3197
3198         ret = kstrtol(buf, 10, &time);
3199         if (ret != 0)
3200                 return ret;
3201
3202         input_event(wm8962->beep, EV_SND, SND_TONE, time);
3203
3204         return count;
3205 }
3206
3207 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3208
3209 static void wm8962_init_beep(struct snd_soc_codec *codec)
3210 {
3211         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3212         int ret;
3213
3214         wm8962->beep = devm_input_allocate_device(codec->dev);
3215         if (!wm8962->beep) {
3216                 dev_err(codec->dev, "Failed to allocate beep device\n");
3217                 return;
3218         }
3219
3220         INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3221         wm8962->beep_rate = 0;
3222
3223         wm8962->beep->name = "WM8962 Beep Generator";
3224         wm8962->beep->phys = dev_name(codec->dev);
3225         wm8962->beep->id.bustype = BUS_I2C;
3226
3227         wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3228         wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3229         wm8962->beep->event = wm8962_beep_event;
3230         wm8962->beep->dev.parent = codec->dev;
3231         input_set_drvdata(wm8962->beep, codec);
3232
3233         ret = input_register_device(wm8962->beep);
3234         if (ret != 0) {
3235                 wm8962->beep = NULL;
3236                 dev_err(codec->dev, "Failed to register beep device\n");
3237         }
3238
3239         ret = device_create_file(codec->dev, &dev_attr_beep);
3240         if (ret != 0) {
3241                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3242                         ret);
3243         }
3244 }
3245
3246 static void wm8962_free_beep(struct snd_soc_codec *codec)
3247 {
3248         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3249
3250         device_remove_file(codec->dev, &dev_attr_beep);
3251         cancel_work_sync(&wm8962->beep_work);
3252         wm8962->beep = NULL;
3253
3254         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3255 }
3256 #else
3257 static void wm8962_init_beep(struct snd_soc_codec *codec)
3258 {
3259 }
3260
3261 static void wm8962_free_beep(struct snd_soc_codec *codec)
3262 {
3263 }
3264 #endif
3265
3266 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3267 {
3268         int mask = 0;
3269         int val = 0;
3270
3271         /* Some of the GPIOs are behind MFP configuration and need to
3272          * be put into GPIO mode. */
3273         switch (gpio) {
3274         case 2:
3275                 mask = WM8962_CLKOUT2_SEL_MASK;
3276                 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3277                 break;
3278         case 3:
3279                 mask = WM8962_CLKOUT3_SEL_MASK;
3280                 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3281                 break;
3282         default:
3283                 break;
3284         }
3285
3286         if (mask)
3287                 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3288                                    mask, val);
3289 }
3290
3291 #ifdef CONFIG_GPIOLIB
3292 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3293 {
3294         return container_of(chip, struct wm8962_priv, gpio_chip);
3295 }
3296
3297 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3298 {
3299         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3300
3301         /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3302          * we export linear numbers and error out if the unsupported
3303          * ones are requsted.
3304          */
3305         switch (offset + 1) {
3306         case 2:
3307         case 3:
3308         case 5:
3309         case 6:
3310                 break;
3311         default:
3312                 return -EINVAL;
3313         }
3314
3315         wm8962_set_gpio_mode(wm8962, offset + 1);
3316
3317         return 0;
3318 }
3319
3320 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3321 {
3322         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3323         struct snd_soc_codec *codec = wm8962->codec;
3324
3325         snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3326                             WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3327 }
3328
3329 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3330                                      unsigned offset, int value)
3331 {
3332         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3333         struct snd_soc_codec *codec = wm8962->codec;
3334         int ret, val;
3335
3336         /* Force function 1 (logic output) */
3337         val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3338
3339         ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3340                                   WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3341         if (ret < 0)
3342                 return ret;
3343
3344         return 0;
3345 }
3346
3347 static struct gpio_chip wm8962_template_chip = {
3348         .label                  = "wm8962",
3349         .owner                  = THIS_MODULE,
3350         .request                = wm8962_gpio_request,
3351         .direction_output       = wm8962_gpio_direction_out,
3352         .set                    = wm8962_gpio_set,
3353         .can_sleep              = 1,
3354 };
3355
3356 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3357 {
3358         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3359         struct wm8962_pdata *pdata = &wm8962->pdata;
3360         int ret;
3361
3362         wm8962->gpio_chip = wm8962_template_chip;
3363         wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3364         wm8962->gpio_chip.dev = codec->dev;
3365
3366         if (pdata->gpio_base)
3367                 wm8962->gpio_chip.base = pdata->gpio_base;
3368         else
3369                 wm8962->gpio_chip.base = -1;
3370
3371         ret = gpiochip_add(&wm8962->gpio_chip);
3372         if (ret != 0)
3373                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3374 }
3375
3376 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3377 {
3378         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3379         int ret;
3380
3381         ret = gpiochip_remove(&wm8962->gpio_chip);
3382         if (ret != 0)
3383                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3384 }
3385 #else
3386 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3387 {
3388 }
3389
3390 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3391 {
3392 }
3393 #endif
3394
3395 static int wm8962_probe(struct snd_soc_codec *codec)
3396 {
3397         int ret;
3398         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3399         int i;
3400         bool dmicclk, dmicdat;
3401
3402         wm8962->codec = codec;
3403         codec->control_data = wm8962->regmap;
3404
3405         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3406         if (ret != 0) {
3407                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3408                 return ret;
3409         }
3410
3411         wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3412         wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3413         wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3414         wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3415         wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3416         wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3417         wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3418         wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3419
3420         /* This should really be moved into the regulator core */
3421         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3422                 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3423                                                   &wm8962->disable_nb[i]);
3424                 if (ret != 0) {
3425                         dev_err(codec->dev,
3426                                 "Failed to register regulator notifier: %d\n",
3427                                 ret);
3428                 }
3429         }
3430
3431         wm8962_add_widgets(codec);
3432
3433         /* Save boards having to disable DMIC when not in use */
3434         dmicclk = false;
3435         dmicdat = false;
3436         for (i = 0; i < WM8962_MAX_GPIO; i++) {
3437                 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3438                         & WM8962_GP2_FN_MASK) {
3439                 case WM8962_GPIO_FN_DMICCLK:
3440                         dmicclk = true;
3441                         break;
3442                 case WM8962_GPIO_FN_DMICDAT:
3443                         dmicdat = true;
3444                         break;
3445                 default:
3446                         break;
3447                 }
3448         }
3449         if (!dmicclk || !dmicdat) {
3450                 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3451                 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3452         }
3453         if (dmicclk != dmicdat)
3454                 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3455
3456         wm8962_init_beep(codec);
3457         wm8962_init_gpio(codec);
3458
3459         return 0;
3460 }
3461
3462 static int wm8962_remove(struct snd_soc_codec *codec)
3463 {
3464         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3465         int i;
3466
3467         cancel_delayed_work_sync(&wm8962->mic_work);
3468
3469         wm8962_free_gpio(codec);
3470         wm8962_free_beep(codec);
3471         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3472                 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3473                                               &wm8962->disable_nb[i]);
3474
3475         return 0;
3476 }
3477
3478 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3479         .probe =        wm8962_probe,
3480         .remove =       wm8962_remove,
3481         .set_bias_level = wm8962_set_bias_level,
3482         .set_pll = wm8962_set_fll,
3483         .idle_bias_off = true,
3484 };
3485
3486 /* Improve power consumption for IN4 DC measurement mode */
3487 static const struct reg_default wm8962_dc_measure[] = {
3488         { 0xfd, 0x1 },
3489         { 0xcc, 0x40 },
3490         { 0xfd, 0 },
3491 };
3492
3493 static const struct regmap_config wm8962_regmap = {
3494         .reg_bits = 16,
3495         .val_bits = 16,
3496
3497         .max_register = WM8962_MAX_REGISTER,
3498         .reg_defaults = wm8962_reg,
3499         .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3500         .volatile_reg = wm8962_volatile_register,
3501         .readable_reg = wm8962_readable_register,
3502         .cache_type = REGCACHE_RBTREE,
3503 };
3504
3505 static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3506                                     struct wm8962_pdata *pdata)
3507 {
3508         const struct device_node *np = i2c->dev.of_node;
3509         u32 val32;
3510         int i;
3511
3512         if (of_property_read_bool(np, "spk-mono"))
3513                 pdata->spk_mono = true;
3514
3515         if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3516                 pdata->mic_cfg = val32;
3517
3518         if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3519                                        ARRAY_SIZE(pdata->gpio_init)) >= 0)
3520                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3521                         /*
3522                          * The range of GPIO register value is [0x0, 0xffff]
3523                          * While the default value of each register is 0x0
3524                          * Any other value will be regarded as default value
3525                          */
3526                         if (pdata->gpio_init[i] > 0xffff)
3527                                 pdata->gpio_init[i] = 0x0;
3528                 }
3529
3530         return 0;
3531 }
3532
3533 static int wm8962_i2c_probe(struct i2c_client *i2c,
3534                             const struct i2c_device_id *id)
3535 {
3536         struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3537         struct wm8962_priv *wm8962;
3538         unsigned int reg;
3539         int ret, i, irq_pol, trigger;
3540
3541         wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3542                               GFP_KERNEL);
3543         if (wm8962 == NULL)
3544                 return -ENOMEM;
3545
3546         i2c_set_clientdata(i2c, wm8962);
3547
3548         INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3549         init_completion(&wm8962->fll_lock);
3550         wm8962->irq = i2c->irq;
3551
3552         /* If platform data was supplied, update the default data in priv */
3553         if (pdata) {
3554                 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3555         } else if (i2c->dev.of_node) {
3556                 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3557                 if (ret != 0)
3558                         return ret;
3559         }
3560
3561         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3562                 wm8962->supplies[i].supply = wm8962_supply_names[i];
3563
3564         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3565                                  wm8962->supplies);
3566         if (ret != 0) {
3567                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3568                 goto err;
3569         }
3570
3571         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3572                                     wm8962->supplies);
3573         if (ret != 0) {
3574                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3575                 return ret;
3576         }
3577
3578         wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3579         if (IS_ERR(wm8962->regmap)) {
3580                 ret = PTR_ERR(wm8962->regmap);
3581                 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3582                 goto err_enable;
3583         }
3584
3585         /*
3586          * We haven't marked the chip revision as volatile due to
3587          * sharing a register with the right input volume; explicitly
3588          * bypass the cache to read it.
3589          */
3590         regcache_cache_bypass(wm8962->regmap, true);
3591
3592         ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3593         if (ret < 0) {
3594                 dev_err(&i2c->dev, "Failed to read ID register\n");
3595                 goto err_enable;
3596         }
3597         if (reg != 0x6243) {
3598                 dev_err(&i2c->dev,
3599                         "Device is not a WM8962, ID %x != 0x6243\n", reg);
3600                 ret = -EINVAL;
3601                 goto err_enable;
3602         }
3603
3604         ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3605         if (ret < 0) {
3606                 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3607                         ret);
3608                 goto err_enable;
3609         }
3610
3611         dev_info(&i2c->dev, "customer id %x revision %c\n",
3612                  (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3613                  ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3614                  + 'A');
3615
3616         regcache_cache_bypass(wm8962->regmap, false);
3617
3618         ret = wm8962_reset(wm8962);
3619         if (ret < 0) {
3620                 dev_err(&i2c->dev, "Failed to issue reset\n");
3621                 goto err_enable;
3622         }
3623
3624         /* SYSCLK defaults to on; make sure it is off so we can safely
3625          * write to registers if the device is declocked.
3626          */
3627         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3628                            WM8962_SYSCLK_ENA, 0);
3629
3630         /* Ensure we have soft control over all registers */
3631         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3632                            WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3633
3634         /* Ensure that the oscillator and PLLs are disabled */
3635         regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3636                            WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3637                            0);
3638
3639         /* Apply static configuration for GPIOs */
3640         for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3641                 if (wm8962->pdata.gpio_init[i]) {
3642                         wm8962_set_gpio_mode(wm8962, i + 1);
3643                         regmap_write(wm8962->regmap, 0x200 + i,
3644                                      wm8962->pdata.gpio_init[i] & 0xffff);
3645                 }
3646
3647
3648         /* Put the speakers into mono mode? */
3649         if (wm8962->pdata.spk_mono)
3650                 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3651                                    WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3652
3653         /* Micbias setup, detection enable and detection
3654          * threasholds. */
3655         if (wm8962->pdata.mic_cfg)
3656                 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3657                                    WM8962_MICDET_ENA |
3658                                    WM8962_MICDET_THR_MASK |
3659                                    WM8962_MICSHORT_THR_MASK |
3660                                    WM8962_MICBIAS_LVL,
3661                                    wm8962->pdata.mic_cfg);
3662
3663         /* Latch volume update bits */
3664         regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3665                            WM8962_IN_VU, WM8962_IN_VU);
3666         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3667                            WM8962_IN_VU, WM8962_IN_VU);
3668         regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3669                            WM8962_ADC_VU, WM8962_ADC_VU);
3670         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3671                            WM8962_ADC_VU, WM8962_ADC_VU);
3672         regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3673                            WM8962_DAC_VU, WM8962_DAC_VU);
3674         regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3675                            WM8962_DAC_VU, WM8962_DAC_VU);
3676         regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3677                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3678         regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3679                            WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3680         regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3681                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3682         regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3683                            WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3684
3685         /* Stereo control for EQ */
3686         regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3687                            WM8962_EQ_SHARED_COEFF, 0);
3688
3689         /* Don't debouce interrupts so we don't need SYSCLK */
3690         regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3691                            WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3692                            WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3693                            0);
3694
3695         if (wm8962->pdata.in4_dc_measure) {
3696                 ret = regmap_register_patch(wm8962->regmap,
3697                                             wm8962_dc_measure,
3698                                             ARRAY_SIZE(wm8962_dc_measure));
3699                 if (ret != 0)
3700                         dev_err(&i2c->dev,
3701                                 "Failed to configure for DC mesurement: %d\n",
3702                                 ret);
3703         }
3704
3705         if (wm8962->irq) {
3706                 if (wm8962->pdata.irq_active_low) {
3707                         trigger = IRQF_TRIGGER_LOW;
3708                         irq_pol = WM8962_IRQ_POL;
3709                 } else {
3710                         trigger = IRQF_TRIGGER_HIGH;
3711                         irq_pol = 0;
3712                 }
3713
3714                 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3715                                    WM8962_IRQ_POL, irq_pol);
3716
3717                 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3718                                                 wm8962_irq,
3719                                                 trigger | IRQF_ONESHOT,
3720                                                 "wm8962", &i2c->dev);
3721                 if (ret != 0) {
3722                         dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3723                                 wm8962->irq, ret);
3724                         wm8962->irq = 0;
3725                         /* Non-fatal */
3726                 } else {
3727                         /* Enable some IRQs by default */
3728                         regmap_update_bits(wm8962->regmap,
3729                                            WM8962_INTERRUPT_STATUS_2_MASK,
3730                                            WM8962_FLL_LOCK_EINT |
3731                                            WM8962_TEMP_SHUT_EINT |
3732                                            WM8962_FIFOS_ERR_EINT, 0);
3733                 }
3734         }
3735
3736         pm_runtime_enable(&i2c->dev);
3737         pm_request_idle(&i2c->dev);
3738
3739         ret = snd_soc_register_codec(&i2c->dev,
3740                                      &soc_codec_dev_wm8962, &wm8962_dai, 1);
3741         if (ret < 0)
3742                 goto err_enable;
3743
3744         regcache_cache_only(wm8962->regmap, true);
3745
3746         /* The drivers should power up as needed */
3747         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3748
3749         return 0;
3750
3751 err_enable:
3752         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3753 err:
3754         return ret;
3755 }
3756
3757 static int wm8962_i2c_remove(struct i2c_client *client)
3758 {
3759         snd_soc_unregister_codec(&client->dev);
3760         return 0;
3761 }
3762
3763 #ifdef CONFIG_PM_RUNTIME
3764 static int wm8962_runtime_resume(struct device *dev)
3765 {
3766         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3767         int ret;
3768
3769         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3770                                     wm8962->supplies);
3771         if (ret != 0) {
3772                 dev_err(dev,
3773                         "Failed to enable supplies: %d\n", ret);
3774                 return ret;
3775         }
3776
3777         regcache_cache_only(wm8962->regmap, false);
3778
3779         wm8962_reset(wm8962);
3780
3781         /* SYSCLK defaults to on; make sure it is off so we can safely
3782          * write to registers if the device is declocked.
3783          */
3784         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3785                            WM8962_SYSCLK_ENA, 0);
3786
3787         /* Ensure we have soft control over all registers */
3788         regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3789                            WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3790
3791         /* Ensure that the oscillator and PLLs are disabled */
3792         regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3793                            WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3794                            0);
3795
3796         regcache_sync(wm8962->regmap);
3797
3798         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3799                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3800                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3801
3802         /* Bias enable at 2*5k (fast start-up) */
3803         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3804                            WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3805                            WM8962_BIAS_ENA | 0x180);
3806
3807         msleep(5);
3808
3809         return 0;
3810 }
3811
3812 static int wm8962_runtime_suspend(struct device *dev)
3813 {
3814         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3815
3816         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3817                            WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3818
3819         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3820                            WM8962_STARTUP_BIAS_ENA |
3821                            WM8962_VMID_BUF_ENA, 0);
3822
3823         regcache_cache_only(wm8962->regmap, true);
3824
3825         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3826                                wm8962->supplies);
3827
3828         return 0;
3829 }
3830 #endif
3831
3832 static struct dev_pm_ops wm8962_pm = {
3833         SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3834 };
3835
3836 static const struct i2c_device_id wm8962_i2c_id[] = {
3837         { "wm8962", 0 },
3838         { }
3839 };
3840 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3841
3842 static const struct of_device_id wm8962_of_match[] = {
3843         { .compatible = "wlf,wm8962", },
3844         { }
3845 };
3846 MODULE_DEVICE_TABLE(of, wm8962_of_match);
3847
3848 static struct i2c_driver wm8962_i2c_driver = {
3849         .driver = {
3850                 .name = "wm8962",
3851                 .owner = THIS_MODULE,
3852                 .of_match_table = wm8962_of_match,
3853                 .pm = &wm8962_pm,
3854         },
3855         .probe =    wm8962_i2c_probe,
3856         .remove =   wm8962_i2c_remove,
3857         .id_table = wm8962_i2c_id,
3858 };
3859
3860 module_i2c_driver(wm8962_i2c_driver);
3861
3862 MODULE_DESCRIPTION("ASoC WM8962 driver");
3863 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3864 MODULE_LICENSE("GPL");