sound/soc/codecs/wm8350.c

   1 /*
   2  * wm8350.c -- WM8350 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/mfd/wm8350/audio.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <trace/events/asoc.h>
  30
  31 #include "wm8350.h"
  32
  33 #define WM8350_OUTn_0dB 0x39
  34
  35 #define WM8350_RAMP_NONE        0
  36 #define WM8350_RAMP_UP          1
  37 #define WM8350_RAMP_DOWN        2
  38
  39 /* We only include the analogue supplies here; the digital supplies
  40  * need to be available well before this driver can be probed.
  41  */
  42 static const char *supply_names[] = {
  43         "AVDD",
  44         "HPVDD",
  45 };
  46
  47 struct wm8350_output {
  48         u16 active;
  49         u16 left_vol;
  50         u16 right_vol;
  51         u16 ramp;
  52         u16 mute;
  53 };
  54
  55 struct wm8350_jack_data {
  56         struct snd_soc_jack *jack;
  57         struct delayed_work work;
  58         int report;
  59         int short_report;
  60 };
  61
  62 struct wm8350_data {
  63         struct wm8350 *wm8350;
  64         struct wm8350_output out1;
  65         struct wm8350_output out2;
  66         struct wm8350_jack_data hpl;
  67         struct wm8350_jack_data hpr;
  68         struct wm8350_jack_data mic;
  69         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  70         int fll_freq_out;
  71         int fll_freq_in;
  72         struct delayed_work pga_work;
  73 };
  74
  75 /*
  76  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  77  */
  78 static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
  79 {
  80         struct wm8350_output *out1 = &wm8350_data->out1;
  81         struct wm8350 *wm8350 = wm8350_data->wm8350;
  82         int left_complete = 0, right_complete = 0;
  83         u16 reg, val;
  84
  85         /* left channel */
  86         reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
  87         val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  88
  89         if (out1->ramp == WM8350_RAMP_UP) {
  90                 /* ramp step up */
  91                 if (val < out1->left_vol) {
  92                         val++;
  93                         reg &= ~WM8350_OUT1L_VOL_MASK;
  94                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  95                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
  96                 } else
  97                         left_complete = 1;
  98         } else if (out1->ramp == WM8350_RAMP_DOWN) {
  99                 /* ramp step down */
 100                 if (val > 0) {
 101                         val--;
 102                         reg &= ~WM8350_OUT1L_VOL_MASK;
 103                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 104                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 105                 } else
 106                         left_complete = 1;
 107         } else
 108                 return 1;
 109
 110         /* right channel */
 111         reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 112         val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 113         if (out1->ramp == WM8350_RAMP_UP) {
 114                 /* ramp step up */
 115                 if (val < out1->right_vol) {
 116                         val++;
 117                         reg &= ~WM8350_OUT1R_VOL_MASK;
 118                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 119                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 120                 } else
 121                         right_complete = 1;
 122         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 123                 /* ramp step down */
 124                 if (val > 0) {
 125                         val--;
 126                         reg &= ~WM8350_OUT1R_VOL_MASK;
 127                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 128                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 129                 } else
 130                         right_complete = 1;
 131         }
 132
 133         /* only hit the update bit if either volume has changed this step */
 134         if (!left_complete || !right_complete)
 135                 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 136
 137         return left_complete & right_complete;
 138 }
 139
 140 /*
 141  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 142  */
 143 static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
 144 {
 145         struct wm8350_output *out2 = &wm8350_data->out2;
 146         struct wm8350 *wm8350 = wm8350_data->wm8350;
 147         int left_complete = 0, right_complete = 0;
 148         u16 reg, val;
 149
 150         /* left channel */
 151         reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 152         val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 153         if (out2->ramp == WM8350_RAMP_UP) {
 154                 /* ramp step up */
 155                 if (val < out2->left_vol) {
 156                         val++;
 157                         reg &= ~WM8350_OUT2L_VOL_MASK;
 158                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 159                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 160                 } else
 161                         left_complete = 1;
 162         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 163                 /* ramp step down */
 164                 if (val > 0) {
 165                         val--;
 166                         reg &= ~WM8350_OUT2L_VOL_MASK;
 167                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 168                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 169                 } else
 170                         left_complete = 1;
 171         } else
 172                 return 1;
 173
 174         /* right channel */
 175         reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 176         val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 177         if (out2->ramp == WM8350_RAMP_UP) {
 178                 /* ramp step up */
 179                 if (val < out2->right_vol) {
 180                         val++;
 181                         reg &= ~WM8350_OUT2R_VOL_MASK;
 182                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 183                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 184                 } else
 185                         right_complete = 1;
 186         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 187                 /* ramp step down */
 188                 if (val > 0) {
 189                         val--;
 190                         reg &= ~WM8350_OUT2R_VOL_MASK;
 191                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 192                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 193                 } else
 194                         right_complete = 1;
 195         }
 196
 197         /* only hit the update bit if either volume has changed this step */
 198         if (!left_complete || !right_complete)
 199                 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 200
 201         return left_complete & right_complete;
 202 }
 203
 204 /*
 205  * This work ramps both output PGAs at stream start/stop time to
 206  * minimise pop associated with DAPM power switching.
 207  * It's best to enable Zero Cross when ramping occurs to minimise any
 208  * zipper noises.
 209  */
 210 static void wm8350_pga_work(struct work_struct *work)
 211 {
 212         struct wm8350_data *wm8350_data =
 213                 container_of(work, struct wm8350_data, pga_work.work);
 214         struct wm8350_output *out1 = &wm8350_data->out1,
 215             *out2 = &wm8350_data->out2;
 216         int i, out1_complete, out2_complete;
 217
 218         /* do we need to ramp at all ? */
 219         if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 220                 return;
 221
 222         /* PGA volumes have 6 bits of resolution to ramp */
 223         for (i = 0; i <= 63; i++) {
 224                 out1_complete = 1, out2_complete = 1;
 225                 if (out1->ramp != WM8350_RAMP_NONE)
 226                         out1_complete = wm8350_out1_ramp_step(wm8350_data);
 227                 if (out2->ramp != WM8350_RAMP_NONE)
 228                         out2_complete = wm8350_out2_ramp_step(wm8350_data);
 229
 230                 /* ramp finished ? */
 231                 if (out1_complete && out2_complete)
 232                         break;
 233
 234                 /* we need to delay longer on the up ramp */
 235                 if (out1->ramp == WM8350_RAMP_UP ||
 236                     out2->ramp == WM8350_RAMP_UP) {
 237                         /* delay is longer over 0dB as increases are larger */
 238                         if (i >= WM8350_OUTn_0dB)
 239                                 schedule_timeout_interruptible(msecs_to_jiffies
 240                                                                (2));
 241                         else
 242                                 schedule_timeout_interruptible(msecs_to_jiffies
 243                                                                (1));
 244                 } else
 245                         udelay(50);     /* doesn't matter if we delay longer */
 246         }
 247
 248         out1->ramp = WM8350_RAMP_NONE;
 249         out2->ramp = WM8350_RAMP_NONE;
 250 }
 251
 252 /*
 253  * WM8350 Controls
 254  */
 255
 256 static int pga_event(struct snd_soc_dapm_widget *w,
 257                      struct snd_kcontrol *kcontrol, int event)
 258 {
 259         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 260         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 261         struct wm8350_output *out;
 262
 263         switch (w->shift) {
 264         case 0:
 265         case 1:
 266                 out = &wm8350_data->out1;
 267                 break;
 268         case 2:
 269         case 3:
 270                 out = &wm8350_data->out2;
 271                 break;
 272
 273         default:
 274                 WARN(1, "Invalid shift %d\n", w->shift);
 275                 return -1;
 276         }
 277
 278         switch (event) {
 279         case SND_SOC_DAPM_POST_PMU:
 280                 out->ramp = WM8350_RAMP_UP;
 281                 out->active = 1;
 282
 283                 schedule_delayed_work(&wm8350_data->pga_work,
 284                                       msecs_to_jiffies(1));
 285                 break;
 286
 287         case SND_SOC_DAPM_PRE_PMD:
 288                 out->ramp = WM8350_RAMP_DOWN;
 289                 out->active = 0;
 290
 291                 schedule_delayed_work(&wm8350_data->pga_work,
 292                                       msecs_to_jiffies(1));
 293                 break;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 300                                   struct snd_ctl_elem_value *ucontrol)
 301 {
 302         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 303         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 304         struct wm8350_output *out = NULL;
 305         struct soc_mixer_control *mc =
 306                 (struct soc_mixer_control *)kcontrol->private_value;
 307         int ret;
 308         unsigned int reg = mc->reg;
 309         u16 val;
 310
 311         /* For OUT1 and OUT2 we shadow the values and only actually write
 312          * them out when active in order to ensure the amplifier comes on
 313          * as quietly as possible. */
 314         switch (reg) {
 315         case WM8350_LOUT1_VOLUME:
 316                 out = &wm8350_priv->out1;
 317                 break;
 318         case WM8350_LOUT2_VOLUME:
 319                 out = &wm8350_priv->out2;
 320                 break;
 321         default:
 322                 break;
 323         }
 324
 325         if (out) {
 326                 out->left_vol = ucontrol->value.integer.value[0];
 327                 out->right_vol = ucontrol->value.integer.value[1];
 328                 if (!out->active)
 329                         return 1;
 330         }
 331
 332         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 333         if (ret < 0)
 334                 return ret;
 335
 336         /* now hit the volume update bits (always bit 8) */
 337         val = snd_soc_read(codec, reg);
 338         snd_soc_write(codec, reg, val | WM8350_OUT1_VU);
 339         return 1;
 340 }
 341
 342 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 343                                struct snd_ctl_elem_value *ucontrol)
 344 {
 345         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 346         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 347         struct wm8350_output *out1 = &wm8350_priv->out1;
 348         struct wm8350_output *out2 = &wm8350_priv->out2;
 349         struct soc_mixer_control *mc =
 350                 (struct soc_mixer_control *)kcontrol->private_value;
 351         unsigned int reg = mc->reg;
 352
 353         /* If these are cached registers use the cache */
 354         switch (reg) {
 355         case WM8350_LOUT1_VOLUME:
 356                 ucontrol->value.integer.value[0] = out1->left_vol;
 357                 ucontrol->value.integer.value[1] = out1->right_vol;
 358                 return 0;
 359
 360         case WM8350_LOUT2_VOLUME:
 361                 ucontrol->value.integer.value[0] = out2->left_vol;
 362                 ucontrol->value.integer.value[1] = out2->right_vol;
 363                 return 0;
 364
 365         default:
 366                 break;
 367         }
 368
 369         return snd_soc_get_volsw(kcontrol, ucontrol);
 370 }
 371
 372 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 373 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 374 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 375 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 376 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 377 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 378 static const char *wm8350_lr[] = { "Left", "Right" };
 379
 380 static const struct soc_enum wm8350_enum[] = {
 381         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 382         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 383         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 384         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 385         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 386         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 387         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 388         SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 389 };
 390
 391 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
 392 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
 393 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 394 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 395 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 396
 397 static const unsigned int capture_sd_tlv[] = {
 398         TLV_DB_RANGE_HEAD(2),
 399         0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 400         13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
 401 };
 402
 403 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 404         SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 405         SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 406         SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
 407                                 WM8350_DAC_DIGITAL_VOLUME_L,
 408                                 WM8350_DAC_DIGITAL_VOLUME_R,
 409                                 0, 255, 0, wm8350_get_volsw_2r,
 410                                 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
 411         SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 412         SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 413         SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
 414         SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
 415         SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
 416         SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
 417                                 WM8350_ADC_DIGITAL_VOLUME_L,
 418                                 WM8350_ADC_DIGITAL_VOLUME_R,
 419                                 0, 255, 0, wm8350_get_volsw_2r,
 420                                 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
 421         SOC_DOUBLE_TLV("Capture Sidetone Volume",
 422                        WM8350_ADC_DIVIDER,
 423                        8, 4, 15, 1, capture_sd_tlv),
 424         SOC_DOUBLE_R_EXT_TLV("Capture Volume",
 425                                 WM8350_LEFT_INPUT_VOLUME,
 426                                 WM8350_RIGHT_INPUT_VOLUME,
 427                                 2, 63, 0, wm8350_get_volsw_2r,
 428                                 wm8350_put_volsw_2r_vu, pre_amp_tlv),
 429         SOC_DOUBLE_R("Capture ZC Switch",
 430                      WM8350_LEFT_INPUT_VOLUME,
 431                      WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 432         SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 433                        WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 434         SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 435                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 436                        5, 7, 0, out_mix_tlv),
 437         SOC_SINGLE_TLV("Left Input Bypass Volume",
 438                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 439                        9, 7, 0, out_mix_tlv),
 440         SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 441                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 442                        1, 7, 0, out_mix_tlv),
 443         SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 444                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 445                        5, 7, 0, out_mix_tlv),
 446         SOC_SINGLE_TLV("Right Input Bypass Volume",
 447                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 448                        13, 7, 0, out_mix_tlv),
 449         SOC_SINGLE("Left Input Mixer +20dB Switch",
 450                    WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 451         SOC_SINGLE("Right Input Mixer +20dB Switch",
 452                    WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 453         SOC_SINGLE_TLV("Out4 Capture Volume",
 454                        WM8350_INPUT_MIXER_VOLUME,
 455                        1, 7, 0, out_mix_tlv),
 456         SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
 457                                 WM8350_LOUT1_VOLUME,
 458                                 WM8350_ROUT1_VOLUME,
 459                                 2, 63, 0, wm8350_get_volsw_2r,
 460                                 wm8350_put_volsw_2r_vu, out_pga_tlv),
 461         SOC_DOUBLE_R("Out1 Playback ZC Switch",
 462                      WM8350_LOUT1_VOLUME,
 463                      WM8350_ROUT1_VOLUME, 13, 1, 0),
 464         SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
 465                                 WM8350_LOUT2_VOLUME,
 466                                 WM8350_ROUT2_VOLUME,
 467                                 2, 63, 0, wm8350_get_volsw_2r,
 468                                 wm8350_put_volsw_2r_vu, out_pga_tlv),
 469         SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 470                      WM8350_ROUT2_VOLUME, 13, 1, 0),
 471         SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 472         SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 473                        5, 7, 0, out_mix_tlv),
 474
 475         SOC_DOUBLE_R("Out1 Playback Switch",
 476                      WM8350_LOUT1_VOLUME,
 477                      WM8350_ROUT1_VOLUME,
 478                      14, 1, 1),
 479         SOC_DOUBLE_R("Out2 Playback Switch",
 480                      WM8350_LOUT2_VOLUME,
 481                      WM8350_ROUT2_VOLUME,
 482                      14, 1, 1),
 483 };
 484
 485 /*
 486  * DAPM Controls
 487  */
 488
 489 /* Left Playback Mixer */
 490 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 491         SOC_DAPM_SINGLE("Playback Switch",
 492                         WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 493         SOC_DAPM_SINGLE("Left Bypass Switch",
 494                         WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 495         SOC_DAPM_SINGLE("Right Playback Switch",
 496                         WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 497         SOC_DAPM_SINGLE("Left Sidetone Switch",
 498                         WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 499         SOC_DAPM_SINGLE("Right Sidetone Switch",
 500                         WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 501 };
 502
 503 /* Right Playback Mixer */
 504 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 505         SOC_DAPM_SINGLE("Playback Switch",
 506                         WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 507         SOC_DAPM_SINGLE("Right Bypass Switch",
 508                         WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 509         SOC_DAPM_SINGLE("Left Playback Switch",
 510                         WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 511         SOC_DAPM_SINGLE("Left Sidetone Switch",
 512                         WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 513         SOC_DAPM_SINGLE("Right Sidetone Switch",
 514                         WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 515 };
 516
 517 /* Out4 Mixer */
 518 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 519         SOC_DAPM_SINGLE("Right Playback Switch",
 520                         WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 521         SOC_DAPM_SINGLE("Left Playback Switch",
 522                         WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 523         SOC_DAPM_SINGLE("Right Capture Switch",
 524                         WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 525         SOC_DAPM_SINGLE("Out3 Playback Switch",
 526                         WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 527         SOC_DAPM_SINGLE("Right Mixer Switch",
 528                         WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 529         SOC_DAPM_SINGLE("Left Mixer Switch",
 530                         WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 531 };
 532
 533 /* Out3 Mixer */
 534 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 535         SOC_DAPM_SINGLE("Left Playback Switch",
 536                         WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 537         SOC_DAPM_SINGLE("Left Capture Switch",
 538                         WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 539         SOC_DAPM_SINGLE("Out4 Playback Switch",
 540                         WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 541         SOC_DAPM_SINGLE("Left Mixer Switch",
 542                         WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 543 };
 544
 545 /* Left Input Mixer */
 546 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 547         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 548                             WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 549         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 550                             WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 551         SOC_DAPM_SINGLE("PGA Capture Switch",
 552                         WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
 553 };
 554
 555 /* Right Input Mixer */
 556 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 557         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 558                             WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 559         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 560                             WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 561         SOC_DAPM_SINGLE("PGA Capture Switch",
 562                         WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
 563 };
 564
 565 /* Left Mic Mixer */
 566 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 567         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 568         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 569         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 570 };
 571
 572 /* Right Mic Mixer */
 573 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 574         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 575         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 576         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 577 };
 578
 579 /* Beep Switch */
 580 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 581 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 582
 583 /* Out4 Capture Mux */
 584 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 585 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
 586
 587 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 588
 589         SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 590         SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 591         SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 592                            0, pga_event,
 593                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 594         SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 595                            pga_event,
 596                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 597         SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 598                            0, pga_event,
 599                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 600         SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 601                            pga_event,
 602                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 603
 604         SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 605                            7, 0, &wm8350_right_capt_mixer_controls[0],
 606                            ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 607
 608         SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 609                            6, 0, &wm8350_left_capt_mixer_controls[0],
 610                            ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 611
 612         SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 613                            &wm8350_out4_mixer_controls[0],
 614                            ARRAY_SIZE(wm8350_out4_mixer_controls)),
 615
 616         SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 617                            &wm8350_out3_mixer_controls[0],
 618                            ARRAY_SIZE(wm8350_out3_mixer_controls)),
 619
 620         SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 621                            &wm8350_right_play_mixer_controls[0],
 622                            ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 623
 624         SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 625                            &wm8350_left_play_mixer_controls[0],
 626                            ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 627
 628         SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 629                            &wm8350_left_mic_mixer_controls[0],
 630                            ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 631
 632         SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 633                            &wm8350_right_mic_mixer_controls[0],
 634                            ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 635
 636         /* virtual mixer for Beep and Out2R */
 637         SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 638
 639         SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 640                             &wm8350_beep_switch_controls),
 641
 642         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 643                          WM8350_POWER_MGMT_4, 3, 0),
 644         SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 645                          WM8350_POWER_MGMT_4, 2, 0),
 646         SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 647                          WM8350_POWER_MGMT_4, 5, 0),
 648         SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 649                          WM8350_POWER_MGMT_4, 4, 0),
 650
 651         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 652
 653         SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 654                          &wm8350_out4_capture_controls),
 655
 656         SND_SOC_DAPM_OUTPUT("OUT1R"),
 657         SND_SOC_DAPM_OUTPUT("OUT1L"),
 658         SND_SOC_DAPM_OUTPUT("OUT2R"),
 659         SND_SOC_DAPM_OUTPUT("OUT2L"),
 660         SND_SOC_DAPM_OUTPUT("OUT3"),
 661         SND_SOC_DAPM_OUTPUT("OUT4"),
 662
 663         SND_SOC_DAPM_INPUT("IN1RN"),
 664         SND_SOC_DAPM_INPUT("IN1RP"),
 665         SND_SOC_DAPM_INPUT("IN2R"),
 666         SND_SOC_DAPM_INPUT("IN1LP"),
 667         SND_SOC_DAPM_INPUT("IN1LN"),
 668         SND_SOC_DAPM_INPUT("IN2L"),
 669         SND_SOC_DAPM_INPUT("IN3R"),
 670         SND_SOC_DAPM_INPUT("IN3L"),
 671 };
 672
 673 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
 674
 675         /* left playback mixer */
 676         {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 677         {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 678         {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 679         {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 680         {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 681
 682         /* right playback mixer */
 683         {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 684         {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 685         {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 686         {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 687         {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 688
 689         /* out4 playback mixer */
 690         {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 691         {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 692         {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 693         {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 694         {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 695         {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 696         {"OUT4", NULL, "Out4 Mixer"},
 697
 698         /* out3 playback mixer */
 699         {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 700         {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 701         {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 702         {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 703         {"OUT3", NULL, "Out3 Mixer"},
 704
 705         /* out2 */
 706         {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 707         {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 708         {"OUT2L", NULL, "Left Out2 PGA"},
 709         {"OUT2R", NULL, "Right Out2 PGA"},
 710
 711         /* out1 */
 712         {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 713         {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 714         {"OUT1L", NULL, "Left Out1 PGA"},
 715         {"OUT1R", NULL, "Right Out1 PGA"},
 716
 717         /* ADCs */
 718         {"Left ADC", NULL, "Left Capture Mixer"},
 719         {"Right ADC", NULL, "Right Capture Mixer"},
 720
 721         /* Left capture mixer */
 722         {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 723         {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 724         {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 725         {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 726
 727         /* Right capture mixer */
 728         {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 729         {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 730         {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 731         {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 732
 733         /* L3 Inputs */
 734         {"IN3L PGA", NULL, "IN3L"},
 735         {"IN3R PGA", NULL, "IN3R"},
 736
 737         /* Left Mic mixer */
 738         {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 739         {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 740         {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 741
 742         /* Right Mic mixer */
 743         {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 744         {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 745         {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 746
 747         /* out 4 capture */
 748         {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 749
 750         /* Beep */
 751         {"Beep", NULL, "IN3R PGA"},
 752 };
 753
 754 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 755                                  int clk_id, unsigned int freq, int dir)
 756 {
 757         struct snd_soc_codec *codec = codec_dai->codec;
 758         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 759         struct wm8350 *wm8350 = wm8350_data->wm8350;
 760         u16 fll_4;
 761
 762         switch (clk_id) {
 763         case WM8350_MCLK_SEL_MCLK:
 764                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 765                                   WM8350_MCLK_SEL);
 766                 break;
 767         case WM8350_MCLK_SEL_PLL_MCLK:
 768         case WM8350_MCLK_SEL_PLL_DAC:
 769         case WM8350_MCLK_SEL_PLL_ADC:
 770         case WM8350_MCLK_SEL_PLL_32K:
 771                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 772                                 WM8350_MCLK_SEL);
 773                 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
 774                     ~WM8350_FLL_CLK_SRC_MASK;
 775                 snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 776                 break;
 777         }
 778
 779         /* MCLK direction */
 780         if (dir == SND_SOC_CLOCK_OUT)
 781                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 782                                 WM8350_MCLK_DIR);
 783         else
 784                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 785                                   WM8350_MCLK_DIR);
 786
 787         return 0;
 788 }
 789
 790 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 791 {
 792         struct snd_soc_codec *codec = codec_dai->codec;
 793         u16 val;
 794
 795         switch (div_id) {
 796         case WM8350_ADC_CLKDIV:
 797                 val = snd_soc_read(codec, WM8350_ADC_DIVIDER) &
 798                     ~WM8350_ADC_CLKDIV_MASK;
 799                 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div);
 800                 break;
 801         case WM8350_DAC_CLKDIV:
 802                 val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) &
 803                     ~WM8350_DAC_CLKDIV_MASK;
 804                 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
 805                 break;
 806         case WM8350_BCLK_CLKDIV:
 807                 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 808                     ~WM8350_BCLK_DIV_MASK;
 809                 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 810                 break;
 811         case WM8350_OPCLK_CLKDIV:
 812                 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 813                     ~WM8350_OPCLK_DIV_MASK;
 814                 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 815                 break;
 816         case WM8350_SYS_CLKDIV:
 817                 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 818                     ~WM8350_MCLK_DIV_MASK;
 819                 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 820                 break;
 821         case WM8350_DACLR_CLKDIV:
 822                 val = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
 823                     ~WM8350_DACLRC_RATE_MASK;
 824                 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div);
 825                 break;
 826         case WM8350_ADCLR_CLKDIV:
 827                 val = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
 828                     ~WM8350_ADCLRC_RATE_MASK;
 829                 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div);
 830                 break;
 831         default:
 832                 return -EINVAL;
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 839 {
 840         struct snd_soc_codec *codec = codec_dai->codec;
 841         u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
 842             ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 843         u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) &
 844             ~WM8350_BCLK_MSTR;
 845         u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
 846             ~WM8350_DACLRC_ENA;
 847         u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
 848             ~WM8350_ADCLRC_ENA;
 849
 850         /* set master/slave audio interface */
 851         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 852         case SND_SOC_DAIFMT_CBM_CFM:
 853                 master |= WM8350_BCLK_MSTR;
 854                 dac_lrc |= WM8350_DACLRC_ENA;
 855                 adc_lrc |= WM8350_ADCLRC_ENA;
 856                 break;
 857         case SND_SOC_DAIFMT_CBS_CFS:
 858                 break;
 859         default:
 860                 return -EINVAL;
 861         }
 862
 863         /* interface format */
 864         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 865         case SND_SOC_DAIFMT_I2S:
 866                 iface |= 0x2 << 8;
 867                 break;
 868         case SND_SOC_DAIFMT_RIGHT_J:
 869                 break;
 870         case SND_SOC_DAIFMT_LEFT_J:
 871                 iface |= 0x1 << 8;
 872                 break;
 873         case SND_SOC_DAIFMT_DSP_A:
 874                 iface |= 0x3 << 8;
 875                 break;
 876         case SND_SOC_DAIFMT_DSP_B:
 877                 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
 878                 break;
 879         default:
 880                 return -EINVAL;
 881         }
 882
 883         /* clock inversion */
 884         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 885         case SND_SOC_DAIFMT_NB_NF:
 886                 break;
 887         case SND_SOC_DAIFMT_IB_IF:
 888                 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 889                 break;
 890         case SND_SOC_DAIFMT_IB_NF:
 891                 iface |= WM8350_AIF_BCLK_INV;
 892                 break;
 893         case SND_SOC_DAIFMT_NB_IF:
 894                 iface |= WM8350_AIF_LRCLK_INV;
 895                 break;
 896         default:
 897                 return -EINVAL;
 898         }
 899
 900         snd_soc_write(codec, WM8350_AI_FORMATING, iface);
 901         snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master);
 902         snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
 903         snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
 904         return 0;
 905 }
 906
 907 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
 908                                 struct snd_pcm_hw_params *params,
 909                                 struct snd_soc_dai *codec_dai)
 910 {
 911         struct snd_soc_codec *codec = codec_dai->codec;
 912         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 913         struct wm8350 *wm8350 = wm8350_data->wm8350;
 914         u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
 915             ~WM8350_AIF_WL_MASK;
 916
 917         /* bit size */
 918         switch (params_width(params)) {
 919         case 16:
 920                 break;
 921         case 20:
 922                 iface |= 0x1 << 10;
 923                 break;
 924         case 24:
 925                 iface |= 0x2 << 10;
 926                 break;
 927         case 32:
 928                 iface |= 0x3 << 10;
 929                 break;
 930         }
 931
 932         snd_soc_write(codec, WM8350_AI_FORMATING, iface);
 933
 934         /* The sloping stopband filter is recommended for use with
 935          * lower sample rates to improve performance.
 936          */
 937         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 938                 if (params_rate(params) < 24000)
 939                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 940                                         WM8350_DAC_SB_FILT);
 941                 else
 942                         wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 943                                           WM8350_DAC_SB_FILT);
 944         }
 945
 946         return 0;
 947 }
 948
 949 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
 950 {
 951         struct snd_soc_codec *codec = dai->codec;
 952         unsigned int val;
 953
 954         if (mute)
 955                 val = WM8350_DAC_MUTE_ENA;
 956         else
 957                 val = 0;
 958
 959         snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
 960
 961         return 0;
 962 }
 963
 964 /* FLL divisors */
 965 struct _fll_div {
 966         int div;                /* FLL_OUTDIV */
 967         int n;
 968         int k;
 969         int ratio;              /* FLL_FRATIO */
 970 };
 971
 972 /* The size in bits of the fll divide multiplied by 10
 973  * to allow rounding later */
 974 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 975
 976 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
 977                               unsigned int output)
 978 {
 979         u64 Kpart;
 980         unsigned int t1, t2, K, Nmod;
 981
 982         if (output >= 2815250 && output <= 3125000)
 983                 fll_div->div = 0x4;
 984         else if (output >= 5625000 && output <= 6250000)
 985                 fll_div->div = 0x3;
 986         else if (output >= 11250000 && output <= 12500000)
 987                 fll_div->div = 0x2;
 988         else if (output >= 22500000 && output <= 25000000)
 989                 fll_div->div = 0x1;
 990         else {
 991                 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
 992                 return -EINVAL;
 993         }
 994
 995         if (input > 48000)
 996                 fll_div->ratio = 1;
 997         else
 998                 fll_div->ratio = 8;
 999
1000         t1 = output * (1 << (fll_div->div + 1));
1001         t2 = input * fll_div->ratio;
1002
1003         fll_div->n = t1 / t2;
1004         Nmod = t1 % t2;
1005
1006         if (Nmod) {
1007                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1008                 do_div(Kpart, t2);
1009                 K = Kpart & 0xFFFFFFFF;
1010
1011                 /* Check if we need to round */
1012                 if ((K % 10) >= 5)
1013                         K += 5;
1014
1015                 /* Move down to proper range now rounding is done */
1016                 K /= 10;
1017                 fll_div->k = K;
1018         } else
1019                 fll_div->k = 0;
1020
1021         return 0;
1022 }
1023
1024 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1025                           int pll_id, int source, unsigned int freq_in,
1026                           unsigned int freq_out)
1027 {
1028         struct snd_soc_codec *codec = codec_dai->codec;
1029         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1030         struct wm8350 *wm8350 = priv->wm8350;
1031         struct _fll_div fll_div;
1032         int ret = 0;
1033         u16 fll_1, fll_4;
1034
1035         if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1036                 return 0;
1037
1038         /* power down FLL - we need to do this for reconfiguration */
1039         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1040                           WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1041
1042         if (freq_out == 0 || freq_in == 0)
1043                 return ret;
1044
1045         ret = fll_factors(&fll_div, freq_in, freq_out);
1046         if (ret < 0)
1047                 return ret;
1048         dev_dbg(wm8350->dev,
1049                 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1050                 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1051                 fll_div.ratio);
1052
1053         /* set up N.K & dividers */
1054         fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) &
1055             ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1056         snd_soc_write(codec, WM8350_FLL_CONTROL_1,
1057                            fll_1 | (fll_div.div << 8) | 0x50);
1058         snd_soc_write(codec, WM8350_FLL_CONTROL_2,
1059                            (fll_div.ratio << 11) | (fll_div.
1060                                                     n & WM8350_FLL_N_MASK));
1061         snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1062         fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
1063             ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1064         snd_soc_write(codec, WM8350_FLL_CONTROL_4,
1065                            fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1066                            (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1067
1068         /* power FLL on */
1069         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1070         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1071
1072         priv->fll_freq_out = freq_out;
1073         priv->fll_freq_in = freq_in;
1074
1075         return 0;
1076 }
1077
1078 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1079                                  enum snd_soc_bias_level level)
1080 {
1081         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1082         struct wm8350 *wm8350 = priv->wm8350;
1083         struct wm8350_audio_platform_data *platform =
1084                 wm8350->codec.platform_data;
1085         u16 pm1;
1086         int ret;
1087
1088         switch (level) {
1089         case SND_SOC_BIAS_ON:
1090                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1091                     ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1092                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1093                                  pm1 | WM8350_VMID_50K |
1094                                  platform->codec_current_on << 14);
1095                 break;
1096
1097         case SND_SOC_BIAS_PREPARE:
1098                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1099                 pm1 &= ~WM8350_VMID_MASK;
1100                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1101                                  pm1 | WM8350_VMID_50K);
1102                 break;
1103
1104         case SND_SOC_BIAS_STANDBY:
1105                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1106                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1107                                                     priv->supplies);
1108                         if (ret != 0)
1109                                 return ret;
1110
1111                         /* Enable the system clock */
1112                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1113                                         WM8350_SYSCLK_ENA);
1114
1115                         /* mute DAC & outputs */
1116                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1117                                         WM8350_DAC_MUTE_ENA);
1118
1119                         /* discharge cap memory */
1120                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1121                                          platform->dis_out1 |
1122                                          (platform->dis_out2 << 2) |
1123                                          (platform->dis_out3 << 4) |
1124                                          (platform->dis_out4 << 6));
1125
1126                         /* wait for discharge */
1127                         schedule_timeout_interruptible(msecs_to_jiffies
1128                                                        (platform->
1129                                                         cap_discharge_msecs));
1130
1131                         /* enable antipop */
1132                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1133                                          (platform->vmid_s_curve << 8));
1134
1135                         /* ramp up vmid */
1136                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1137                                          (platform->
1138                                           codec_current_charge << 14) |
1139                                          WM8350_VMID_5K | WM8350_VMIDEN |
1140                                          WM8350_VBUFEN);
1141
1142                         /* wait for vmid */
1143                         schedule_timeout_interruptible(msecs_to_jiffies
1144                                                        (platform->
1145                                                         vmid_charge_msecs));
1146
1147                         /* turn on vmid 300k  */
1148                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1149                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1150                         pm1 |= WM8350_VMID_300K |
1151                                 (platform->codec_current_standby << 14);
1152                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1153                                          pm1);
1154
1155
1156                         /* enable analogue bias */
1157                         pm1 |= WM8350_BIASEN;
1158                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1159
1160                         /* disable antipop */
1161                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1162
1163                 } else {
1164                         /* turn on vmid 300k and reduce current */
1165                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1166                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1167                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1168                                          pm1 | WM8350_VMID_300K |
1169                                          (platform->
1170                                           codec_current_standby << 14));
1171
1172                 }
1173                 break;
1174
1175         case SND_SOC_BIAS_OFF:
1176
1177                 /* mute DAC & enable outputs */
1178                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1179
1180                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1181                                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1182                                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1183
1184                 /* enable anti pop S curve */
1185                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1186                                  (platform->vmid_s_curve << 8));
1187
1188                 /* turn off vmid  */
1189                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1190                     ~WM8350_VMIDEN;
1191                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1192
1193                 /* wait */
1194                 schedule_timeout_interruptible(msecs_to_jiffies
1195                                                (platform->
1196                                                 vmid_discharge_msecs));
1197
1198                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1199                                  (platform->vmid_s_curve << 8) |
1200                                  platform->dis_out1 |
1201                                  (platform->dis_out2 << 2) |
1202                                  (platform->dis_out3 << 4) |
1203                                  (platform->dis_out4 << 6));
1204
1205                 /* turn off VBuf and drain */
1206                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1207                     ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1208                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1209                                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1210
1211                 /* wait */
1212                 schedule_timeout_interruptible(msecs_to_jiffies
1213                                                (platform->drain_msecs));
1214
1215                 pm1 &= ~WM8350_BIASEN;
1216                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1217
1218                 /* disable anti-pop */
1219                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1220
1221                 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1222                                   WM8350_OUT1L_ENA);
1223                 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1224                                   WM8350_OUT1R_ENA);
1225                 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1226                                   WM8350_OUT2L_ENA);
1227                 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1228                                   WM8350_OUT2R_ENA);
1229
1230                 /* disable clock gen */
1231                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1232                                   WM8350_SYSCLK_ENA);
1233
1234                 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1235                                        priv->supplies);
1236                 break;
1237         }
1238         codec->dapm.bias_level = level;
1239         return 0;
1240 }
1241
1242 static void wm8350_hp_work(struct wm8350_data *priv,
1243                            struct wm8350_jack_data *jack,
1244                            u16 mask)
1245 {
1246         struct wm8350 *wm8350 = priv->wm8350;
1247         u16 reg;
1248         int report;
1249
1250         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1251         if (reg & mask)
1252                 report = jack->report;
1253         else
1254                 report = 0;
1255
1256         snd_soc_jack_report(jack->jack, report, jack->report);
1257
1258 }
1259
1260 static void wm8350_hpl_work(struct work_struct *work)
1261 {
1262         struct wm8350_data *priv =
1263             container_of(work, struct wm8350_data, hpl.work.work);
1264
1265         wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1266 }
1267
1268 static void wm8350_hpr_work(struct work_struct *work)
1269 {
1270         struct wm8350_data *priv =
1271             container_of(work, struct wm8350_data, hpr.work.work);
1272
1273         wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1274 }
1275
1276 static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
1277 {
1278         struct wm8350_data *priv = data;
1279         struct wm8350 *wm8350 = priv->wm8350;
1280
1281 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1282         trace_snd_soc_jack_irq("WM8350 HPL");
1283 #endif
1284
1285         if (device_may_wakeup(wm8350->dev))
1286                 pm_wakeup_event(wm8350->dev, 250);
1287
1288         queue_delayed_work(system_power_efficient_wq,
1289                            &priv->hpl.work, msecs_to_jiffies(200));
1290
1291         return IRQ_HANDLED;
1292 }
1293
1294 static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1295 {
1296         struct wm8350_data *priv = data;
1297         struct wm8350 *wm8350 = priv->wm8350;
1298
1299 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1300         trace_snd_soc_jack_irq("WM8350 HPR");
1301 #endif
1302
1303         if (device_may_wakeup(wm8350->dev))
1304                 pm_wakeup_event(wm8350->dev, 250);
1305
1306         queue_delayed_work(system_power_efficient_wq,
1307                            &priv->hpr.work, msecs_to_jiffies(200));
1308
1309         return IRQ_HANDLED;
1310 }
1311
1312 /**
1313  * wm8350_hp_jack_detect - Enable headphone jack detection.
1314  *
1315  * @codec:  WM8350 codec
1316  * @which:  left or right jack detect signal
1317  * @jack:   jack to report detection events on
1318  * @report: value to report
1319  *
1320  * Enables the headphone jack detection of the WM8350.  If no report
1321  * is specified then detection is disabled.
1322  */
1323 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1324                           struct snd_soc_jack *jack, int report)
1325 {
1326         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1327         struct wm8350 *wm8350 = priv->wm8350;
1328         int ena;
1329
1330         switch (which) {
1331         case WM8350_JDL:
1332                 priv->hpl.jack = jack;
1333                 priv->hpl.report = report;
1334                 ena = WM8350_JDL_ENA;
1335                 break;
1336
1337         case WM8350_JDR:
1338                 priv->hpr.jack = jack;
1339                 priv->hpr.report = report;
1340                 ena = WM8350_JDR_ENA;
1341                 break;
1342
1343         default:
1344                 return -EINVAL;
1345         }
1346
1347         if (report) {
1348                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1349                 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1350         } else {
1351                 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1352         }
1353
1354         /* Sync status */
1355         switch (which) {
1356         case WM8350_JDL:
1357                 wm8350_hpl_jack_handler(0, priv);
1358                 break;
1359         case WM8350_JDR:
1360                 wm8350_hpr_jack_handler(0, priv);
1361                 break;
1362         }
1363
1364         return 0;
1365 }
1366 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1367
1368 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1369 {
1370         struct wm8350_data *priv = data;
1371         struct wm8350 *wm8350 = priv->wm8350;
1372         u16 reg;
1373         int report = 0;
1374
1375 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1376         trace_snd_soc_jack_irq("WM8350 mic");
1377 #endif
1378
1379         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1380         if (reg & WM8350_JACK_MICSCD_LVL)
1381                 report |= priv->mic.short_report;
1382         if (reg & WM8350_JACK_MICSD_LVL)
1383                 report |= priv->mic.report;
1384
1385         snd_soc_jack_report(priv->mic.jack, report,
1386                             priv->mic.report | priv->mic.short_report);
1387
1388         return IRQ_HANDLED;
1389 }
1390
1391 /**
1392  * wm8350_mic_jack_detect - Enable microphone jack detection.
1393  *
1394  * @codec:         WM8350 codec
1395  * @jack:          jack to report detection events on
1396  * @detect_report: value to report when presence detected
1397  * @short_report:  value to report when microphone short detected
1398  *
1399  * Enables the microphone jack detection of the WM8350.  If both reports
1400  * are specified as zero then detection is disabled.
1401  */
1402 int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1403                            struct snd_soc_jack *jack,
1404                            int detect_report, int short_report)
1405 {
1406         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1407         struct wm8350 *wm8350 = priv->wm8350;
1408
1409         priv->mic.jack = jack;
1410         priv->mic.report = detect_report;
1411         priv->mic.short_report = short_report;
1412
1413         if (detect_report || short_report) {
1414                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1415                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1416                                 WM8350_MIC_DET_ENA);
1417         } else {
1418                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1419                                   WM8350_MIC_DET_ENA);
1420         }
1421
1422         return 0;
1423 }
1424 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1425
1426 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1427
1428 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1429                         SNDRV_PCM_FMTBIT_S20_3LE |\
1430                         SNDRV_PCM_FMTBIT_S24_LE)
1431
1432 static const struct snd_soc_dai_ops wm8350_dai_ops = {
1433          .hw_params     = wm8350_pcm_hw_params,
1434          .digital_mute  = wm8350_mute,
1435          .set_fmt       = wm8350_set_dai_fmt,
1436          .set_sysclk    = wm8350_set_dai_sysclk,
1437          .set_pll       = wm8350_set_fll,
1438          .set_clkdiv    = wm8350_set_clkdiv,
1439 };
1440
1441 static struct snd_soc_dai_driver wm8350_dai = {
1442         .name = "wm8350-hifi",
1443         .playback = {
1444                 .stream_name = "Playback",
1445                 .channels_min = 1,
1446                 .channels_max = 2,
1447                 .rates = WM8350_RATES,
1448                 .formats = WM8350_FORMATS,
1449         },
1450         .capture = {
1451                  .stream_name = "Capture",
1452                  .channels_min = 1,
1453                  .channels_max = 2,
1454                  .rates = WM8350_RATES,
1455                  .formats = WM8350_FORMATS,
1456          },
1457         .ops = &wm8350_dai_ops,
1458 };
1459
1460 static  int wm8350_codec_probe(struct snd_soc_codec *codec)
1461 {
1462         struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1463         struct wm8350_data *priv;
1464         struct wm8350_output *out1;
1465         struct wm8350_output *out2;
1466         int ret, i;
1467
1468         if (wm8350->codec.platform_data == NULL) {
1469                 dev_err(codec->dev, "No audio platform data supplied\n");
1470                 return -EINVAL;
1471         }
1472
1473         priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data),
1474                             GFP_KERNEL);
1475         if (priv == NULL)
1476                 return -ENOMEM;
1477         snd_soc_codec_set_drvdata(codec, priv);
1478
1479         priv->wm8350 = wm8350;
1480
1481         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1482                 priv->supplies[i].supply = supply_names[i];
1483
1484         ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1485                                  priv->supplies);
1486         if (ret != 0)
1487                 return ret;
1488
1489         /* Put the codec into reset if it wasn't already */
1490         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1491
1492         INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
1493         INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1494         INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1495
1496         /* Enable the codec */
1497         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1498
1499         /* Enable robust clocking mode in ADC */
1500         snd_soc_write(codec, WM8350_SECURITY, 0xa7);
1501         snd_soc_write(codec, 0xde, 0x13);
1502         snd_soc_write(codec, WM8350_SECURITY, 0);
1503
1504         /* read OUT1 & OUT2 volumes */
1505         out1 = &priv->out1;
1506         out2 = &priv->out2;
1507         out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1508                           WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1509         out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1510                            WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1511         out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1512                           WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1513         out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1514                            WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1515         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1516         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1517         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1518         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1519
1520         /* Latch VU bits & mute */
1521         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1522                         WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1523         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1524                         WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1525         wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1526                         WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1527         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1528                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1529
1530         /* Make sure AIF tristating is disabled by default */
1531         wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1532
1533         /* Make sure we've got a sane companding setup too */
1534         wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1535                           WM8350_DAC_COMP | WM8350_LOOPBACK);
1536
1537         /* Make sure jack detect is disabled to start off with */
1538         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1539                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1540
1541         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1542                             wm8350_hpl_jack_handler, 0, "Left jack detect",
1543                             priv);
1544         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1545                             wm8350_hpr_jack_handler, 0, "Right jack detect",
1546                             priv);
1547         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1548                             wm8350_mic_handler, 0, "Microphone short", priv);
1549         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1550                             wm8350_mic_handler, 0, "Microphone detect", priv);
1551
1552         return 0;
1553 }
1554
1555 static int  wm8350_codec_remove(struct snd_soc_codec *codec)
1556 {
1557         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1558         struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1559
1560         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1561                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1562         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1563
1564         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1565         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1566         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1567         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1568
1569         priv->hpl.jack = NULL;
1570         priv->hpr.jack = NULL;
1571         priv->mic.jack = NULL;
1572
1573         cancel_delayed_work_sync(&priv->hpl.work);
1574         cancel_delayed_work_sync(&priv->hpr.work);
1575
1576         /* if there was any work waiting then we run it now and
1577          * wait for its completion */
1578         flush_delayed_work(&priv->pga_work);
1579
1580         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1581
1582         return 0;
1583 }
1584
1585 static struct regmap *wm8350_get_regmap(struct device *dev)
1586 {
1587         struct wm8350 *wm8350 = dev_get_platdata(dev);
1588
1589         return wm8350->regmap;
1590 }
1591
1592 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1593         .probe =        wm8350_codec_probe,
1594         .remove =       wm8350_codec_remove,
1595         .get_regmap =   wm8350_get_regmap,
1596         .set_bias_level = wm8350_set_bias_level,
1597         .suspend_bias_off = true,
1598
1599         .controls = wm8350_snd_controls,
1600         .num_controls = ARRAY_SIZE(wm8350_snd_controls),
1601         .dapm_widgets = wm8350_dapm_widgets,
1602         .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
1603         .dapm_routes = wm8350_dapm_routes,
1604         .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
1605 };
1606
1607 static int wm8350_probe(struct platform_device *pdev)
1608 {
1609         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1610                         &wm8350_dai, 1);
1611 }
1612
1613 static int wm8350_remove(struct platform_device *pdev)
1614 {
1615         snd_soc_unregister_codec(&pdev->dev);
1616         return 0;
1617 }
1618
1619 static struct platform_driver wm8350_codec_driver = {
1620         .driver = {
1621                    .name = "wm8350-codec",
1622                    },
1623         .probe = wm8350_probe,
1624         .remove = wm8350_remove,
1625 };
1626
1627 module_platform_driver(wm8350_codec_driver);
1628
1629 MODULE_DESCRIPTION("ASoC WM8350 driver");
1630 MODULE_AUTHOR("Liam Girdwood");
1631 MODULE_LICENSE("GPL");
1632 MODULE_ALIAS("platform:wm8350-codec");