sound/soc/codecs/wm8350.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * wm8350.c -- WM8350 ALSA SoC audio driver
   4  *
   5  * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
   6  *
   7  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/delay.h>
  15 #include <linux/pm.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mfd/wm8350/audio.h>
  18 #include <linux/mfd/wm8350/core.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <sound/core.h>
  21 #include <sound/pcm.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include <sound/initval.h>
  25 #include <sound/tlv.h>
  26 #include <trace/events/asoc.h>
  27
  28 #include "wm8350.h"
  29
  30 #define WM8350_OUTn_0dB 0x39
  31
  32 #define WM8350_RAMP_NONE        0
  33 #define WM8350_RAMP_UP          1
  34 #define WM8350_RAMP_DOWN        2
  35
  36 /* We only include the analogue supplies here; the digital supplies
  37  * need to be available well before this driver can be probed.
  38  */
  39 static const char *supply_names[] = {
  40         "AVDD",
  41         "HPVDD",
  42 };
  43
  44 struct wm8350_output {
  45         u16 active;
  46         u16 left_vol;
  47         u16 right_vol;
  48         u16 ramp;
  49         u16 mute;
  50 };
  51
  52 struct wm8350_jack_data {
  53         struct snd_soc_jack *jack;
  54         struct delayed_work work;
  55         int report;
  56         int short_report;
  57 };
  58
  59 struct wm8350_data {
  60         struct wm8350 *wm8350;
  61         struct wm8350_output out1;
  62         struct wm8350_output out2;
  63         struct wm8350_jack_data hpl;
  64         struct wm8350_jack_data hpr;
  65         struct wm8350_jack_data mic;
  66         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  67         int fll_freq_out;
  68         int fll_freq_in;
  69         struct delayed_work pga_work;
  70 };
  71
  72 /*
  73  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  74  */
  75 static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
  76 {
  77         struct wm8350_output *out1 = &wm8350_data->out1;
  78         struct wm8350 *wm8350 = wm8350_data->wm8350;
  79         int left_complete = 0, right_complete = 0;
  80         u16 reg, val;
  81
  82         /* left channel */
  83         reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
  84         val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  85
  86         if (out1->ramp == WM8350_RAMP_UP) {
  87                 /* ramp step up */
  88                 if (val < out1->left_vol) {
  89                         val++;
  90                         reg &= ~WM8350_OUT1L_VOL_MASK;
  91                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  92                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
  93                 } else
  94                         left_complete = 1;
  95         } else if (out1->ramp == WM8350_RAMP_DOWN) {
  96                 /* ramp step down */
  97                 if (val > 0) {
  98                         val--;
  99                         reg &= ~WM8350_OUT1L_VOL_MASK;
 100                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 101                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 102                 } else
 103                         left_complete = 1;
 104         } else
 105                 return 1;
 106
 107         /* right channel */
 108         reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 109         val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 110         if (out1->ramp == WM8350_RAMP_UP) {
 111                 /* ramp step up */
 112                 if (val < out1->right_vol) {
 113                         val++;
 114                         reg &= ~WM8350_OUT1R_VOL_MASK;
 115                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 116                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 117                 } else
 118                         right_complete = 1;
 119         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 120                 /* ramp step down */
 121                 if (val > 0) {
 122                         val--;
 123                         reg &= ~WM8350_OUT1R_VOL_MASK;
 124                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 125                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 126                 } else
 127                         right_complete = 1;
 128         }
 129
 130         /* only hit the update bit if either volume has changed this step */
 131         if (!left_complete || !right_complete)
 132                 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 133
 134         return left_complete & right_complete;
 135 }
 136
 137 /*
 138  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 139  */
 140 static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
 141 {
 142         struct wm8350_output *out2 = &wm8350_data->out2;
 143         struct wm8350 *wm8350 = wm8350_data->wm8350;
 144         int left_complete = 0, right_complete = 0;
 145         u16 reg, val;
 146
 147         /* left channel */
 148         reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 149         val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 150         if (out2->ramp == WM8350_RAMP_UP) {
 151                 /* ramp step up */
 152                 if (val < out2->left_vol) {
 153                         val++;
 154                         reg &= ~WM8350_OUT2L_VOL_MASK;
 155                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 156                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 157                 } else
 158                         left_complete = 1;
 159         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 160                 /* ramp step down */
 161                 if (val > 0) {
 162                         val--;
 163                         reg &= ~WM8350_OUT2L_VOL_MASK;
 164                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 165                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 166                 } else
 167                         left_complete = 1;
 168         } else
 169                 return 1;
 170
 171         /* right channel */
 172         reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 173         val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 174         if (out2->ramp == WM8350_RAMP_UP) {
 175                 /* ramp step up */
 176                 if (val < out2->right_vol) {
 177                         val++;
 178                         reg &= ~WM8350_OUT2R_VOL_MASK;
 179                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 180                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 181                 } else
 182                         right_complete = 1;
 183         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 184                 /* ramp step down */
 185                 if (val > 0) {
 186                         val--;
 187                         reg &= ~WM8350_OUT2R_VOL_MASK;
 188                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 189                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 190                 } else
 191                         right_complete = 1;
 192         }
 193
 194         /* only hit the update bit if either volume has changed this step */
 195         if (!left_complete || !right_complete)
 196                 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 197
 198         return left_complete & right_complete;
 199 }
 200
 201 /*
 202  * This work ramps both output PGAs at stream start/stop time to
 203  * minimise pop associated with DAPM power switching.
 204  * It's best to enable Zero Cross when ramping occurs to minimise any
 205  * zipper noises.
 206  */
 207 static void wm8350_pga_work(struct work_struct *work)
 208 {
 209         struct wm8350_data *wm8350_data =
 210                 container_of(work, struct wm8350_data, pga_work.work);
 211         struct wm8350_output *out1 = &wm8350_data->out1,
 212             *out2 = &wm8350_data->out2;
 213         int i, out1_complete, out2_complete;
 214
 215         /* do we need to ramp at all ? */
 216         if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 217                 return;
 218
 219         /* PGA volumes have 6 bits of resolution to ramp */
 220         for (i = 0; i <= 63; i++) {
 221                 out1_complete = 1, out2_complete = 1;
 222                 if (out1->ramp != WM8350_RAMP_NONE)
 223                         out1_complete = wm8350_out1_ramp_step(wm8350_data);
 224                 if (out2->ramp != WM8350_RAMP_NONE)
 225                         out2_complete = wm8350_out2_ramp_step(wm8350_data);
 226
 227                 /* ramp finished ? */
 228                 if (out1_complete && out2_complete)
 229                         break;
 230
 231                 /* we need to delay longer on the up ramp */
 232                 if (out1->ramp == WM8350_RAMP_UP ||
 233                     out2->ramp == WM8350_RAMP_UP) {
 234                         /* delay is longer over 0dB as increases are larger */
 235                         if (i >= WM8350_OUTn_0dB)
 236                                 schedule_timeout_interruptible(msecs_to_jiffies
 237                                                                (2));
 238                         else
 239                                 schedule_timeout_interruptible(msecs_to_jiffies
 240                                                                (1));
 241                 } else
 242                         udelay(50);     /* doesn't matter if we delay longer */
 243         }
 244
 245         out1->ramp = WM8350_RAMP_NONE;
 246         out2->ramp = WM8350_RAMP_NONE;
 247 }
 248
 249 /*
 250  * WM8350 Controls
 251  */
 252
 253 static int pga_event(struct snd_soc_dapm_widget *w,
 254                      struct snd_kcontrol *kcontrol, int event)
 255 {
 256         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 257         struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
 258         struct wm8350_output *out;
 259
 260         switch (w->shift) {
 261         case 0:
 262         case 1:
 263                 out = &wm8350_data->out1;
 264                 break;
 265         case 2:
 266         case 3:
 267                 out = &wm8350_data->out2;
 268                 break;
 269
 270         default:
 271                 WARN(1, "Invalid shift %d\n", w->shift);
 272                 return -1;
 273         }
 274
 275         switch (event) {
 276         case SND_SOC_DAPM_POST_PMU:
 277                 out->ramp = WM8350_RAMP_UP;
 278                 out->active = 1;
 279
 280                 schedule_delayed_work(&wm8350_data->pga_work,
 281                                       msecs_to_jiffies(1));
 282                 break;
 283
 284         case SND_SOC_DAPM_PRE_PMD:
 285                 out->ramp = WM8350_RAMP_DOWN;
 286                 out->active = 0;
 287
 288                 schedule_delayed_work(&wm8350_data->pga_work,
 289                                       msecs_to_jiffies(1));
 290                 break;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 297                                   struct snd_ctl_elem_value *ucontrol)
 298 {
 299         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 300         struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
 301         struct wm8350_output *out = NULL;
 302         struct soc_mixer_control *mc =
 303                 (struct soc_mixer_control *)kcontrol->private_value;
 304         int ret;
 305         unsigned int reg = mc->reg;
 306         u16 val;
 307
 308         /* For OUT1 and OUT2 we shadow the values and only actually write
 309          * them out when active in order to ensure the amplifier comes on
 310          * as quietly as possible. */
 311         switch (reg) {
 312         case WM8350_LOUT1_VOLUME:
 313                 out = &wm8350_priv->out1;
 314                 break;
 315         case WM8350_LOUT2_VOLUME:
 316                 out = &wm8350_priv->out2;
 317                 break;
 318         default:
 319                 break;
 320         }
 321
 322         if (out) {
 323                 out->left_vol = ucontrol->value.integer.value[0];
 324                 out->right_vol = ucontrol->value.integer.value[1];
 325                 if (!out->active)
 326                         return 1;
 327         }
 328
 329         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 330         if (ret < 0)
 331                 return ret;
 332
 333         /* now hit the volume update bits (always bit 8) */
 334         val = snd_soc_component_read(component, reg);
 335         snd_soc_component_write(component, reg, val | WM8350_OUT1_VU);
 336         return 1;
 337 }
 338
 339 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 340                                struct snd_ctl_elem_value *ucontrol)
 341 {
 342         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 343         struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
 344         struct wm8350_output *out1 = &wm8350_priv->out1;
 345         struct wm8350_output *out2 = &wm8350_priv->out2;
 346         struct soc_mixer_control *mc =
 347                 (struct soc_mixer_control *)kcontrol->private_value;
 348         unsigned int reg = mc->reg;
 349
 350         /* If these are cached registers use the cache */
 351         switch (reg) {
 352         case WM8350_LOUT1_VOLUME:
 353                 ucontrol->value.integer.value[0] = out1->left_vol;
 354                 ucontrol->value.integer.value[1] = out1->right_vol;
 355                 return 0;
 356
 357         case WM8350_LOUT2_VOLUME:
 358                 ucontrol->value.integer.value[0] = out2->left_vol;
 359                 ucontrol->value.integer.value[1] = out2->right_vol;
 360                 return 0;
 361
 362         default:
 363                 break;
 364         }
 365
 366         return snd_soc_get_volsw(kcontrol, ucontrol);
 367 }
 368
 369 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 370 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 371 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 372 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 373 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 374 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 375 static const char *wm8350_lr[] = { "Left", "Right" };
 376
 377 static const struct soc_enum wm8350_enum[] = {
 378         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 379         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 380         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 381         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 382         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 383         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 384         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 385         SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 386 };
 387
 388 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
 389 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
 390 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 391 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 392 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 393
 394 static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,
 395         0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 396         13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)
 397 );
 398
 399 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 400         SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 401         SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 402         SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
 403                                 WM8350_DAC_DIGITAL_VOLUME_L,
 404                                 WM8350_DAC_DIGITAL_VOLUME_R,
 405                                 0, 255, 0, wm8350_get_volsw_2r,
 406                                 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
 407         SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 408         SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 409         SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
 410         SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
 411         SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
 412         SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
 413                                 WM8350_ADC_DIGITAL_VOLUME_L,
 414                                 WM8350_ADC_DIGITAL_VOLUME_R,
 415                                 0, 255, 0, wm8350_get_volsw_2r,
 416                                 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
 417         SOC_DOUBLE_TLV("Capture Sidetone Volume",
 418                        WM8350_ADC_DIVIDER,
 419                        8, 4, 15, 1, capture_sd_tlv),
 420         SOC_DOUBLE_R_EXT_TLV("Capture Volume",
 421                                 WM8350_LEFT_INPUT_VOLUME,
 422                                 WM8350_RIGHT_INPUT_VOLUME,
 423                                 2, 63, 0, wm8350_get_volsw_2r,
 424                                 wm8350_put_volsw_2r_vu, pre_amp_tlv),
 425         SOC_DOUBLE_R("Capture ZC Switch",
 426                      WM8350_LEFT_INPUT_VOLUME,
 427                      WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 428         SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 429                        WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 430         SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 431                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 432                        5, 7, 0, out_mix_tlv),
 433         SOC_SINGLE_TLV("Left Input Bypass Volume",
 434                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 435                        9, 7, 0, out_mix_tlv),
 436         SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 437                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 438                        1, 7, 0, out_mix_tlv),
 439         SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 440                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 441                        5, 7, 0, out_mix_tlv),
 442         SOC_SINGLE_TLV("Right Input Bypass Volume",
 443                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 444                        13, 7, 0, out_mix_tlv),
 445         SOC_SINGLE("Left Input Mixer +20dB Switch",
 446                    WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 447         SOC_SINGLE("Right Input Mixer +20dB Switch",
 448                    WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 449         SOC_SINGLE_TLV("Out4 Capture Volume",
 450                        WM8350_INPUT_MIXER_VOLUME,
 451                        1, 7, 0, out_mix_tlv),
 452         SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
 453                                 WM8350_LOUT1_VOLUME,
 454                                 WM8350_ROUT1_VOLUME,
 455                                 2, 63, 0, wm8350_get_volsw_2r,
 456                                 wm8350_put_volsw_2r_vu, out_pga_tlv),
 457         SOC_DOUBLE_R("Out1 Playback ZC Switch",
 458                      WM8350_LOUT1_VOLUME,
 459                      WM8350_ROUT1_VOLUME, 13, 1, 0),
 460         SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
 461                                 WM8350_LOUT2_VOLUME,
 462                                 WM8350_ROUT2_VOLUME,
 463                                 2, 63, 0, wm8350_get_volsw_2r,
 464                                 wm8350_put_volsw_2r_vu, out_pga_tlv),
 465         SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 466                      WM8350_ROUT2_VOLUME, 13, 1, 0),
 467         SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 468         SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 469                        5, 7, 0, out_mix_tlv),
 470
 471         SOC_DOUBLE_R("Out1 Playback Switch",
 472                      WM8350_LOUT1_VOLUME,
 473                      WM8350_ROUT1_VOLUME,
 474                      14, 1, 1),
 475         SOC_DOUBLE_R("Out2 Playback Switch",
 476                      WM8350_LOUT2_VOLUME,
 477                      WM8350_ROUT2_VOLUME,
 478                      14, 1, 1),
 479 };
 480
 481 /*
 482  * DAPM Controls
 483  */
 484
 485 /* Left Playback Mixer */
 486 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 487         SOC_DAPM_SINGLE("Playback Switch",
 488                         WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 489         SOC_DAPM_SINGLE("Left Bypass Switch",
 490                         WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 491         SOC_DAPM_SINGLE("Right Playback Switch",
 492                         WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 493         SOC_DAPM_SINGLE("Left Sidetone Switch",
 494                         WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 495         SOC_DAPM_SINGLE("Right Sidetone Switch",
 496                         WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 497 };
 498
 499 /* Right Playback Mixer */
 500 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 501         SOC_DAPM_SINGLE("Playback Switch",
 502                         WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 503         SOC_DAPM_SINGLE("Right Bypass Switch",
 504                         WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 505         SOC_DAPM_SINGLE("Left Playback Switch",
 506                         WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 507         SOC_DAPM_SINGLE("Left Sidetone Switch",
 508                         WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 509         SOC_DAPM_SINGLE("Right Sidetone Switch",
 510                         WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 511 };
 512
 513 /* Out4 Mixer */
 514 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 515         SOC_DAPM_SINGLE("Right Playback Switch",
 516                         WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 517         SOC_DAPM_SINGLE("Left Playback Switch",
 518                         WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 519         SOC_DAPM_SINGLE("Right Capture Switch",
 520                         WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 521         SOC_DAPM_SINGLE("Out3 Playback Switch",
 522                         WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 523         SOC_DAPM_SINGLE("Right Mixer Switch",
 524                         WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 525         SOC_DAPM_SINGLE("Left Mixer Switch",
 526                         WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 527 };
 528
 529 /* Out3 Mixer */
 530 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 531         SOC_DAPM_SINGLE("Left Playback Switch",
 532                         WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 533         SOC_DAPM_SINGLE("Left Capture Switch",
 534                         WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 535         SOC_DAPM_SINGLE("Out4 Playback Switch",
 536                         WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 537         SOC_DAPM_SINGLE("Left Mixer Switch",
 538                         WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 539 };
 540
 541 /* Left Input Mixer */
 542 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 543         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 544                             WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 545         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 546                             WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 547         SOC_DAPM_SINGLE("PGA Capture Switch",
 548                         WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
 549 };
 550
 551 /* Right Input Mixer */
 552 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 553         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 554                             WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 555         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 556                             WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 557         SOC_DAPM_SINGLE("PGA Capture Switch",
 558                         WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
 559 };
 560
 561 /* Left Mic Mixer */
 562 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 563         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 564         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 565         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 566 };
 567
 568 /* Right Mic Mixer */
 569 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 570         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 571         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 572         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 573 };
 574
 575 /* Beep Switch */
 576 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 577 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 578
 579 /* Out4 Capture Mux */
 580 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 581 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
 582
 583 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 584
 585         SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 586         SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 587         SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 588                            0, pga_event,
 589                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 590         SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 591                            pga_event,
 592                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 593         SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 594                            0, pga_event,
 595                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 596         SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 597                            pga_event,
 598                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 599
 600         SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 601                            7, 0, &wm8350_right_capt_mixer_controls[0],
 602                            ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 603
 604         SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 605                            6, 0, &wm8350_left_capt_mixer_controls[0],
 606                            ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 607
 608         SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 609                            &wm8350_out4_mixer_controls[0],
 610                            ARRAY_SIZE(wm8350_out4_mixer_controls)),
 611
 612         SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 613                            &wm8350_out3_mixer_controls[0],
 614                            ARRAY_SIZE(wm8350_out3_mixer_controls)),
 615
 616         SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 617                            &wm8350_right_play_mixer_controls[0],
 618                            ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 619
 620         SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 621                            &wm8350_left_play_mixer_controls[0],
 622                            ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 623
 624         SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 625                            &wm8350_left_mic_mixer_controls[0],
 626                            ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 627
 628         SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 629                            &wm8350_right_mic_mixer_controls[0],
 630                            ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 631
 632         /* virtual mixer for Beep and Out2R */
 633         SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 634
 635         SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 636                             &wm8350_beep_switch_controls),
 637
 638         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 639                          WM8350_POWER_MGMT_4, 3, 0),
 640         SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 641                          WM8350_POWER_MGMT_4, 2, 0),
 642         SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 643                          WM8350_POWER_MGMT_4, 5, 0),
 644         SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 645                          WM8350_POWER_MGMT_4, 4, 0),
 646
 647         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 648
 649         SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 650                          &wm8350_out4_capture_controls),
 651
 652         SND_SOC_DAPM_OUTPUT("OUT1R"),
 653         SND_SOC_DAPM_OUTPUT("OUT1L"),
 654         SND_SOC_DAPM_OUTPUT("OUT2R"),
 655         SND_SOC_DAPM_OUTPUT("OUT2L"),
 656         SND_SOC_DAPM_OUTPUT("OUT3"),
 657         SND_SOC_DAPM_OUTPUT("OUT4"),
 658
 659         SND_SOC_DAPM_INPUT("IN1RN"),
 660         SND_SOC_DAPM_INPUT("IN1RP"),
 661         SND_SOC_DAPM_INPUT("IN2R"),
 662         SND_SOC_DAPM_INPUT("IN1LP"),
 663         SND_SOC_DAPM_INPUT("IN1LN"),
 664         SND_SOC_DAPM_INPUT("IN2L"),
 665         SND_SOC_DAPM_INPUT("IN3R"),
 666         SND_SOC_DAPM_INPUT("IN3L"),
 667 };
 668
 669 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
 670
 671         /* left playback mixer */
 672         {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 673         {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 674         {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 675         {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 676         {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 677
 678         /* right playback mixer */
 679         {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 680         {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 681         {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 682         {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 683         {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 684
 685         /* out4 playback mixer */
 686         {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 687         {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 688         {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 689         {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 690         {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 691         {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 692         {"OUT4", NULL, "Out4 Mixer"},
 693
 694         /* out3 playback mixer */
 695         {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 696         {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 697         {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 698         {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 699         {"OUT3", NULL, "Out3 Mixer"},
 700
 701         /* out2 */
 702         {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 703         {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 704         {"OUT2L", NULL, "Left Out2 PGA"},
 705         {"OUT2R", NULL, "Right Out2 PGA"},
 706
 707         /* out1 */
 708         {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 709         {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 710         {"OUT1L", NULL, "Left Out1 PGA"},
 711         {"OUT1R", NULL, "Right Out1 PGA"},
 712
 713         /* ADCs */
 714         {"Left ADC", NULL, "Left Capture Mixer"},
 715         {"Right ADC", NULL, "Right Capture Mixer"},
 716
 717         /* Left capture mixer */
 718         {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 719         {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 720         {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 721         {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 722
 723         /* Right capture mixer */
 724         {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 725         {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 726         {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 727         {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 728
 729         /* L3 Inputs */
 730         {"IN3L PGA", NULL, "IN3L"},
 731         {"IN3R PGA", NULL, "IN3R"},
 732
 733         /* Left Mic mixer */
 734         {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 735         {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 736         {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 737
 738         /* Right Mic mixer */
 739         {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 740         {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 741         {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 742
 743         /* out 4 capture */
 744         {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 745
 746         /* Beep */
 747         {"Beep", NULL, "IN3R PGA"},
 748 };
 749
 750 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 751                                  int clk_id, unsigned int freq, int dir)
 752 {
 753         struct snd_soc_component *component = codec_dai->component;
 754         struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
 755         struct wm8350 *wm8350 = wm8350_data->wm8350;
 756         u16 fll_4;
 757
 758         switch (clk_id) {
 759         case WM8350_MCLK_SEL_MCLK:
 760                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 761                                   WM8350_MCLK_SEL);
 762                 break;
 763         case WM8350_MCLK_SEL_PLL_MCLK:
 764         case WM8350_MCLK_SEL_PLL_DAC:
 765         case WM8350_MCLK_SEL_PLL_ADC:
 766         case WM8350_MCLK_SEL_PLL_32K:
 767                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 768                                 WM8350_MCLK_SEL);
 769                 fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
 770                     ~WM8350_FLL_CLK_SRC_MASK;
 771                 snd_soc_component_write(component, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 772                 break;
 773         }
 774
 775         /* MCLK direction */
 776         if (dir == SND_SOC_CLOCK_OUT)
 777                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 778                                 WM8350_MCLK_DIR);
 779         else
 780                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 781                                   WM8350_MCLK_DIR);
 782
 783         return 0;
 784 }
 785
 786 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 787 {
 788         struct snd_soc_component *component = codec_dai->component;
 789         u16 val;
 790
 791         switch (div_id) {
 792         case WM8350_ADC_CLKDIV:
 793                 val = snd_soc_component_read(component, WM8350_ADC_DIVIDER) &
 794                     ~WM8350_ADC_CLKDIV_MASK;
 795                 snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div);
 796                 break;
 797         case WM8350_DAC_CLKDIV:
 798                 val = snd_soc_component_read(component, WM8350_DAC_CLOCK_CONTROL) &
 799                     ~WM8350_DAC_CLKDIV_MASK;
 800                 snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div);
 801                 break;
 802         case WM8350_BCLK_CLKDIV:
 803                 val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
 804                     ~WM8350_BCLK_DIV_MASK;
 805                 snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
 806                 break;
 807         case WM8350_OPCLK_CLKDIV:
 808                 val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
 809                     ~WM8350_OPCLK_DIV_MASK;
 810                 snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
 811                 break;
 812         case WM8350_SYS_CLKDIV:
 813                 val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
 814                     ~WM8350_MCLK_DIV_MASK;
 815                 snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
 816                 break;
 817         case WM8350_DACLR_CLKDIV:
 818                 val = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
 819                     ~WM8350_DACLRC_RATE_MASK;
 820                 snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div);
 821                 break;
 822         case WM8350_ADCLR_CLKDIV:
 823                 val = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
 824                     ~WM8350_ADCLRC_RATE_MASK;
 825                 snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div);
 826                 break;
 827         default:
 828                 return -EINVAL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 835 {
 836         struct snd_soc_component *component = codec_dai->component;
 837         u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
 838             ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 839         u16 master = snd_soc_component_read(component, WM8350_AI_DAC_CONTROL) &
 840             ~WM8350_BCLK_MSTR;
 841         u16 dac_lrc = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
 842             ~WM8350_DACLRC_ENA;
 843         u16 adc_lrc = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
 844             ~WM8350_ADCLRC_ENA;
 845
 846         /* set master/slave audio interface */
 847         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 848         case SND_SOC_DAIFMT_CBM_CFM:
 849                 master |= WM8350_BCLK_MSTR;
 850                 dac_lrc |= WM8350_DACLRC_ENA;
 851                 adc_lrc |= WM8350_ADCLRC_ENA;
 852                 break;
 853         case SND_SOC_DAIFMT_CBS_CFS:
 854                 break;
 855         default:
 856                 return -EINVAL;
 857         }
 858
 859         /* interface format */
 860         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 861         case SND_SOC_DAIFMT_I2S:
 862                 iface |= 0x2 << 8;
 863                 break;
 864         case SND_SOC_DAIFMT_RIGHT_J:
 865                 break;
 866         case SND_SOC_DAIFMT_LEFT_J:
 867                 iface |= 0x1 << 8;
 868                 break;
 869         case SND_SOC_DAIFMT_DSP_A:
 870                 iface |= 0x3 << 8;
 871                 break;
 872         case SND_SOC_DAIFMT_DSP_B:
 873                 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
 874                 break;
 875         default:
 876                 return -EINVAL;
 877         }
 878
 879         /* clock inversion */
 880         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 881         case SND_SOC_DAIFMT_NB_NF:
 882                 break;
 883         case SND_SOC_DAIFMT_IB_IF:
 884                 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 885                 break;
 886         case SND_SOC_DAIFMT_IB_NF:
 887                 iface |= WM8350_AIF_BCLK_INV;
 888                 break;
 889         case SND_SOC_DAIFMT_NB_IF:
 890                 iface |= WM8350_AIF_LRCLK_INV;
 891                 break;
 892         default:
 893                 return -EINVAL;
 894         }
 895
 896         snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
 897         snd_soc_component_write(component, WM8350_AI_DAC_CONTROL, master);
 898         snd_soc_component_write(component, WM8350_DAC_LR_RATE, dac_lrc);
 899         snd_soc_component_write(component, WM8350_ADC_LR_RATE, adc_lrc);
 900         return 0;
 901 }
 902
 903 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
 904                                 struct snd_pcm_hw_params *params,
 905                                 struct snd_soc_dai *codec_dai)
 906 {
 907         struct snd_soc_component *component = codec_dai->component;
 908         struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
 909         struct wm8350 *wm8350 = wm8350_data->wm8350;
 910         u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
 911             ~WM8350_AIF_WL_MASK;
 912
 913         /* bit size */
 914         switch (params_width(params)) {
 915         case 16:
 916                 break;
 917         case 20:
 918                 iface |= 0x1 << 10;
 919                 break;
 920         case 24:
 921                 iface |= 0x2 << 10;
 922                 break;
 923         case 32:
 924                 iface |= 0x3 << 10;
 925                 break;
 926         }
 927
 928         snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
 929
 930         /* The sloping stopband filter is recommended for use with
 931          * lower sample rates to improve performance.
 932          */
 933         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 934                 if (params_rate(params) < 24000)
 935                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 936                                         WM8350_DAC_SB_FILT);
 937                 else
 938                         wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 939                                           WM8350_DAC_SB_FILT);
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int wm8350_mute(struct snd_soc_dai *dai, int mute, int direction)
 946 {
 947         struct snd_soc_component *component = dai->component;
 948         unsigned int val;
 949
 950         if (mute)
 951                 val = WM8350_DAC_MUTE_ENA;
 952         else
 953                 val = 0;
 954
 955         snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
 956
 957         return 0;
 958 }
 959
 960 /* FLL divisors */
 961 struct _fll_div {
 962         int div;                /* FLL_OUTDIV */
 963         int n;
 964         int k;
 965         int ratio;              /* FLL_FRATIO */
 966 };
 967
 968 /* The size in bits of the fll divide multiplied by 10
 969  * to allow rounding later */
 970 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 971
 972 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
 973                               unsigned int output)
 974 {
 975         u64 Kpart;
 976         unsigned int t1, t2, K, Nmod;
 977
 978         if (output >= 2815250 && output <= 3125000)
 979                 fll_div->div = 0x4;
 980         else if (output >= 5625000 && output <= 6250000)
 981                 fll_div->div = 0x3;
 982         else if (output >= 11250000 && output <= 12500000)
 983                 fll_div->div = 0x2;
 984         else if (output >= 22500000 && output <= 25000000)
 985                 fll_div->div = 0x1;
 986         else {
 987                 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
 988                 return -EINVAL;
 989         }
 990
 991         if (input > 48000)
 992                 fll_div->ratio = 1;
 993         else
 994                 fll_div->ratio = 8;
 995
 996         t1 = output * (1 << (fll_div->div + 1));
 997         t2 = input * fll_div->ratio;
 998
 999         fll_div->n = t1 / t2;
1000         Nmod = t1 % t2;
1001
1002         if (Nmod) {
1003                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1004                 do_div(Kpart, t2);
1005                 K = Kpart & 0xFFFFFFFF;
1006
1007                 /* Check if we need to round */
1008                 if ((K % 10) >= 5)
1009                         K += 5;
1010
1011                 /* Move down to proper range now rounding is done */
1012                 K /= 10;
1013                 fll_div->k = K;
1014         } else
1015                 fll_div->k = 0;
1016
1017         return 0;
1018 }
1019
1020 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1021                           int pll_id, int source, unsigned int freq_in,
1022                           unsigned int freq_out)
1023 {
1024         struct snd_soc_component *component = codec_dai->component;
1025         struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1026         struct wm8350 *wm8350 = priv->wm8350;
1027         struct _fll_div fll_div;
1028         int ret = 0;
1029         u16 fll_1, fll_4;
1030
1031         if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1032                 return 0;
1033
1034         /* power down FLL - we need to do this for reconfiguration */
1035         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1036                           WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1037
1038         if (freq_out == 0 || freq_in == 0)
1039                 return ret;
1040
1041         ret = fll_factors(&fll_div, freq_in, freq_out);
1042         if (ret < 0)
1043                 return ret;
1044         dev_dbg(wm8350->dev,
1045                 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1046                 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1047                 fll_div.ratio);
1048
1049         /* set up N.K & dividers */
1050         fll_1 = snd_soc_component_read(component, WM8350_FLL_CONTROL_1) &
1051             ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1052         snd_soc_component_write(component, WM8350_FLL_CONTROL_1,
1053                            fll_1 | (fll_div.div << 8) | 0x50);
1054         snd_soc_component_write(component, WM8350_FLL_CONTROL_2,
1055                            (fll_div.ratio << 11) | (fll_div.
1056                                                     n & WM8350_FLL_N_MASK));
1057         snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);
1058         fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
1059             ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1060         snd_soc_component_write(component, WM8350_FLL_CONTROL_4,
1061                            fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1062                            (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1063
1064         /* power FLL on */
1065         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1066         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1067
1068         priv->fll_freq_out = freq_out;
1069         priv->fll_freq_in = freq_in;
1070
1071         return 0;
1072 }
1073
1074 static int wm8350_set_bias_level(struct snd_soc_component *component,
1075                                  enum snd_soc_bias_level level)
1076 {
1077         struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1078         struct wm8350 *wm8350 = priv->wm8350;
1079         struct wm8350_audio_platform_data *platform =
1080                 wm8350->codec.platform_data;
1081         u16 pm1;
1082         int ret;
1083
1084         switch (level) {
1085         case SND_SOC_BIAS_ON:
1086                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1087                     ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1088                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1089                                  pm1 | WM8350_VMID_50K |
1090                                  platform->codec_current_on << 14);
1091                 break;
1092
1093         case SND_SOC_BIAS_PREPARE:
1094                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1095                 pm1 &= ~WM8350_VMID_MASK;
1096                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1097                                  pm1 | WM8350_VMID_50K);
1098                 break;
1099
1100         case SND_SOC_BIAS_STANDBY:
1101                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1102                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1103                                                     priv->supplies);
1104                         if (ret != 0)
1105                                 return ret;
1106
1107                         /* Enable the system clock */
1108                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1109                                         WM8350_SYSCLK_ENA);
1110
1111                         /* mute DAC & outputs */
1112                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1113                                         WM8350_DAC_MUTE_ENA);
1114
1115                         /* discharge cap memory */
1116                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1117                                          platform->dis_out1 |
1118                                          (platform->dis_out2 << 2) |
1119                                          (platform->dis_out3 << 4) |
1120                                          (platform->dis_out4 << 6));
1121
1122                         /* wait for discharge */
1123                         schedule_timeout_interruptible(msecs_to_jiffies
1124                                                        (platform->
1125                                                         cap_discharge_msecs));
1126
1127                         /* enable antipop */
1128                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1129                                          (platform->vmid_s_curve << 8));
1130
1131                         /* ramp up vmid */
1132                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1133                                          (platform->
1134                                           codec_current_charge << 14) |
1135                                          WM8350_VMID_5K | WM8350_VMIDEN |
1136                                          WM8350_VBUFEN);
1137
1138                         /* wait for vmid */
1139                         schedule_timeout_interruptible(msecs_to_jiffies
1140                                                        (platform->
1141                                                         vmid_charge_msecs));
1142
1143                         /* turn on vmid 300k  */
1144                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1145                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1146                         pm1 |= WM8350_VMID_300K |
1147                                 (platform->codec_current_standby << 14);
1148                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1149                                          pm1);
1150
1151
1152                         /* enable analogue bias */
1153                         pm1 |= WM8350_BIASEN;
1154                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1155
1156                         /* disable antipop */
1157                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1158
1159                 } else {
1160                         /* turn on vmid 300k and reduce current */
1161                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1162                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1163                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1164                                          pm1 | WM8350_VMID_300K |
1165                                          (platform->
1166                                           codec_current_standby << 14));
1167
1168                 }
1169                 break;
1170
1171         case SND_SOC_BIAS_OFF:
1172
1173                 /* mute DAC & enable outputs */
1174                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1175
1176                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1177                                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1178                                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1179
1180                 /* enable anti pop S curve */
1181                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1182                                  (platform->vmid_s_curve << 8));
1183
1184                 /* turn off vmid  */
1185                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1186                     ~WM8350_VMIDEN;
1187                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1188
1189                 /* wait */
1190                 schedule_timeout_interruptible(msecs_to_jiffies
1191                                                (platform->
1192                                                 vmid_discharge_msecs));
1193
1194                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1195                                  (platform->vmid_s_curve << 8) |
1196                                  platform->dis_out1 |
1197                                  (platform->dis_out2 << 2) |
1198                                  (platform->dis_out3 << 4) |
1199                                  (platform->dis_out4 << 6));
1200
1201                 /* turn off VBuf and drain */
1202                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1203                     ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1204                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1205                                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1206
1207                 /* wait */
1208                 schedule_timeout_interruptible(msecs_to_jiffies
1209                                                (platform->drain_msecs));
1210
1211                 pm1 &= ~WM8350_BIASEN;
1212                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1213
1214                 /* disable anti-pop */
1215                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1216
1217                 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1218                                   WM8350_OUT1L_ENA);
1219                 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1220                                   WM8350_OUT1R_ENA);
1221                 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1222                                   WM8350_OUT2L_ENA);
1223                 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1224                                   WM8350_OUT2R_ENA);
1225
1226                 /* disable clock gen */
1227                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1228                                   WM8350_SYSCLK_ENA);
1229
1230                 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1231                                        priv->supplies);
1232                 break;
1233         }
1234         return 0;
1235 }
1236
1237 static void wm8350_hp_work(struct wm8350_data *priv,
1238                            struct wm8350_jack_data *jack,
1239                            u16 mask)
1240 {
1241         struct wm8350 *wm8350 = priv->wm8350;
1242         u16 reg;
1243         int report;
1244
1245         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1246         if (reg & mask)
1247                 report = jack->report;
1248         else
1249                 report = 0;
1250
1251         snd_soc_jack_report(jack->jack, report, jack->report);
1252
1253 }
1254
1255 static void wm8350_hpl_work(struct work_struct *work)
1256 {
1257         struct wm8350_data *priv =
1258             container_of(work, struct wm8350_data, hpl.work.work);
1259
1260         wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1261 }
1262
1263 static void wm8350_hpr_work(struct work_struct *work)
1264 {
1265         struct wm8350_data *priv =
1266             container_of(work, struct wm8350_data, hpr.work.work);
1267
1268         wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1269 }
1270
1271 static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
1272 {
1273         struct wm8350_data *priv = data;
1274         struct wm8350 *wm8350 = priv->wm8350;
1275
1276 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1277         trace_snd_soc_jack_irq("WM8350 HPL");
1278 #endif
1279
1280         if (device_may_wakeup(wm8350->dev))
1281                 pm_wakeup_event(wm8350->dev, 250);
1282
1283         queue_delayed_work(system_power_efficient_wq,
1284                            &priv->hpl.work, msecs_to_jiffies(200));
1285
1286         return IRQ_HANDLED;
1287 }
1288
1289 static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1290 {
1291         struct wm8350_data *priv = data;
1292         struct wm8350 *wm8350 = priv->wm8350;
1293
1294 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1295         trace_snd_soc_jack_irq("WM8350 HPR");
1296 #endif
1297
1298         if (device_may_wakeup(wm8350->dev))
1299                 pm_wakeup_event(wm8350->dev, 250);
1300
1301         queue_delayed_work(system_power_efficient_wq,
1302                            &priv->hpr.work, msecs_to_jiffies(200));
1303
1304         return IRQ_HANDLED;
1305 }
1306
1307 /**
1308  * wm8350_hp_jack_detect - Enable headphone jack detection.
1309  *
1310  * @component:  WM8350 component
1311  * @which:  left or right jack detect signal
1312  * @jack:   jack to report detection events on
1313  * @report: value to report
1314  *
1315  * Enables the headphone jack detection of the WM8350.  If no report
1316  * is specified then detection is disabled.
1317  */
1318 int wm8350_hp_jack_detect(struct snd_soc_component *component, enum wm8350_jack which,
1319                           struct snd_soc_jack *jack, int report)
1320 {
1321         struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1322         struct wm8350 *wm8350 = priv->wm8350;
1323         int ena;
1324
1325         switch (which) {
1326         case WM8350_JDL:
1327                 priv->hpl.jack = jack;
1328                 priv->hpl.report = report;
1329                 ena = WM8350_JDL_ENA;
1330                 break;
1331
1332         case WM8350_JDR:
1333                 priv->hpr.jack = jack;
1334                 priv->hpr.report = report;
1335                 ena = WM8350_JDR_ENA;
1336                 break;
1337
1338         default:
1339                 return -EINVAL;
1340         }
1341
1342         if (report) {
1343                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1344                 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1345         } else {
1346                 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1347         }
1348
1349         /* Sync status */
1350         switch (which) {
1351         case WM8350_JDL:
1352                 wm8350_hpl_jack_handler(0, priv);
1353                 break;
1354         case WM8350_JDR:
1355                 wm8350_hpr_jack_handler(0, priv);
1356                 break;
1357         }
1358
1359         return 0;
1360 }
1361 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1362
1363 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1364 {
1365         struct wm8350_data *priv = data;
1366         struct wm8350 *wm8350 = priv->wm8350;
1367         u16 reg;
1368         int report = 0;
1369
1370 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1371         trace_snd_soc_jack_irq("WM8350 mic");
1372 #endif
1373
1374         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1375         if (reg & WM8350_JACK_MICSCD_LVL)
1376                 report |= priv->mic.short_report;
1377         if (reg & WM8350_JACK_MICSD_LVL)
1378                 report |= priv->mic.report;
1379
1380         snd_soc_jack_report(priv->mic.jack, report,
1381                             priv->mic.report | priv->mic.short_report);
1382
1383         return IRQ_HANDLED;
1384 }
1385
1386 /**
1387  * wm8350_mic_jack_detect - Enable microphone jack detection.
1388  *
1389  * @component:         WM8350 component
1390  * @jack:          jack to report detection events on
1391  * @detect_report: value to report when presence detected
1392  * @short_report:  value to report when microphone short detected
1393  *
1394  * Enables the microphone jack detection of the WM8350.  If both reports
1395  * are specified as zero then detection is disabled.
1396  */
1397 int wm8350_mic_jack_detect(struct snd_soc_component *component,
1398                            struct snd_soc_jack *jack,
1399                            int detect_report, int short_report)
1400 {
1401         struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1402         struct wm8350 *wm8350 = priv->wm8350;
1403
1404         priv->mic.jack = jack;
1405         priv->mic.report = detect_report;
1406         priv->mic.short_report = short_report;
1407
1408         if (detect_report || short_report) {
1409                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1410                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1411                                 WM8350_MIC_DET_ENA);
1412         } else {
1413                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1414                                   WM8350_MIC_DET_ENA);
1415         }
1416
1417         return 0;
1418 }
1419 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1420
1421 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1422
1423 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1424                         SNDRV_PCM_FMTBIT_S20_3LE |\
1425                         SNDRV_PCM_FMTBIT_S24_LE)
1426
1427 static const struct snd_soc_dai_ops wm8350_dai_ops = {
1428          .hw_params     = wm8350_pcm_hw_params,
1429          .mute_stream   = wm8350_mute,
1430          .set_fmt       = wm8350_set_dai_fmt,
1431          .set_sysclk    = wm8350_set_dai_sysclk,
1432          .set_pll       = wm8350_set_fll,
1433          .set_clkdiv    = wm8350_set_clkdiv,
1434          .no_capture_mute = 1,
1435 };
1436
1437 static struct snd_soc_dai_driver wm8350_dai = {
1438         .name = "wm8350-hifi",
1439         .playback = {
1440                 .stream_name = "Playback",
1441                 .channels_min = 1,
1442                 .channels_max = 2,
1443                 .rates = WM8350_RATES,
1444                 .formats = WM8350_FORMATS,
1445         },
1446         .capture = {
1447                  .stream_name = "Capture",
1448                  .channels_min = 1,
1449                  .channels_max = 2,
1450                  .rates = WM8350_RATES,
1451                  .formats = WM8350_FORMATS,
1452          },
1453         .ops = &wm8350_dai_ops,
1454 };
1455
1456 static  int wm8350_component_probe(struct snd_soc_component *component)
1457 {
1458         struct wm8350 *wm8350 = dev_get_platdata(component->dev);
1459         struct wm8350_data *priv;
1460         struct wm8350_output *out1;
1461         struct wm8350_output *out2;
1462         int ret, i;
1463
1464         if (wm8350->codec.platform_data == NULL) {
1465                 dev_err(component->dev, "No audio platform data supplied\n");
1466                 return -EINVAL;
1467         }
1468
1469         priv = devm_kzalloc(component->dev, sizeof(struct wm8350_data),
1470                             GFP_KERNEL);
1471         if (priv == NULL)
1472                 return -ENOMEM;
1473
1474         snd_soc_component_init_regmap(component, wm8350->regmap);
1475         snd_soc_component_set_drvdata(component, priv);
1476
1477         priv->wm8350 = wm8350;
1478
1479         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1480                 priv->supplies[i].supply = supply_names[i];
1481
1482         ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1483                                  priv->supplies);
1484         if (ret != 0)
1485                 return ret;
1486
1487         /* Put the codec into reset if it wasn't already */
1488         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1489
1490         INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
1491         INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1492         INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1493
1494         /* Enable the codec */
1495         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1496
1497         /* Enable robust clocking mode in ADC */
1498         snd_soc_component_write(component, WM8350_SECURITY, 0xa7);
1499         snd_soc_component_write(component, 0xde, 0x13);
1500         snd_soc_component_write(component, WM8350_SECURITY, 0);
1501
1502         /* read OUT1 & OUT2 volumes */
1503         out1 = &priv->out1;
1504         out2 = &priv->out2;
1505         out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1506                           WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1507         out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1508                            WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1509         out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1510                           WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1511         out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1512                            WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1513         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1514         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1515         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1516         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1517
1518         /* Latch VU bits & mute */
1519         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1520                         WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1521         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1522                         WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1523         wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1524                         WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1525         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1526                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1527
1528         /* Make sure AIF tristating is disabled by default */
1529         wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1530
1531         /* Make sure we've got a sane companding setup too */
1532         wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1533                           WM8350_DAC_COMP | WM8350_LOOPBACK);
1534
1535         /* Make sure jack detect is disabled to start off with */
1536         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1537                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1538
1539         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1540                             wm8350_hpl_jack_handler, 0, "Left jack detect",
1541                             priv);
1542         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1543                             wm8350_hpr_jack_handler, 0, "Right jack detect",
1544                             priv);
1545         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1546                             wm8350_mic_handler, 0, "Microphone short", priv);
1547         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1548                             wm8350_mic_handler, 0, "Microphone detect", priv);
1549
1550         return 0;
1551 }
1552
1553 static void wm8350_component_remove(struct snd_soc_component *component)
1554 {
1555         struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1556         struct wm8350 *wm8350 = dev_get_platdata(component->dev);
1557
1558         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1559                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1560         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1561
1562         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1563         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1564         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1565         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1566
1567         priv->hpl.jack = NULL;
1568         priv->hpr.jack = NULL;
1569         priv->mic.jack = NULL;
1570
1571         cancel_delayed_work_sync(&priv->hpl.work);
1572         cancel_delayed_work_sync(&priv->hpr.work);
1573
1574         /* if there was any work waiting then we run it now and
1575          * wait for its completion */
1576         flush_delayed_work(&priv->pga_work);
1577
1578         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1579 }
1580
1581 static const struct snd_soc_component_driver soc_component_dev_wm8350 = {
1582         .probe                  = wm8350_component_probe,
1583         .remove                 = wm8350_component_remove,
1584         .set_bias_level         = wm8350_set_bias_level,
1585         .controls               = wm8350_snd_controls,
1586         .num_controls           = ARRAY_SIZE(wm8350_snd_controls),
1587         .dapm_widgets           = wm8350_dapm_widgets,
1588         .num_dapm_widgets       = ARRAY_SIZE(wm8350_dapm_widgets),
1589         .dapm_routes            = wm8350_dapm_routes,
1590         .num_dapm_routes        = ARRAY_SIZE(wm8350_dapm_routes),
1591         .suspend_bias_off       = 1,
1592         .idle_bias_on           = 1,
1593         .use_pmdown_time        = 1,
1594         .endianness             = 1,
1595         .non_legacy_dai_naming  = 1,
1596 };
1597
1598 static int wm8350_probe(struct platform_device *pdev)
1599 {
1600         return devm_snd_soc_register_component(&pdev->dev,
1601                         &soc_component_dev_wm8350,
1602                         &wm8350_dai, 1);
1603 }
1604
1605 static struct platform_driver wm8350_codec_driver = {
1606         .driver = {
1607                    .name = "wm8350-codec",
1608                    },
1609         .probe = wm8350_probe,
1610 };
1611
1612 module_platform_driver(wm8350_codec_driver);
1613
1614 MODULE_DESCRIPTION("ASoC WM8350 driver");
1615 MODULE_AUTHOR("Liam Girdwood");
1616 MODULE_LICENSE("GPL");
1617 MODULE_ALIAS("platform:wm8350-codec");