sound/soc/codecs/wcd934x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/clk-provider.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/kernel.h>
   8 #include <linux/mfd/wcd934x/registers.h>
   9 #include <linux/mfd/wcd934x/wcd934x.h>
  10 #include <linux/module.h>
  11 #include <linux/mutex.h>
  12 #include <linux/of_clk.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/slab.h>
  18 #include <linux/slimbus.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <sound/tlv.h>
  23 #include "wcd-clsh-v2.h"
  24 #include "wcd-mbhc-v2.h"
  25
  26 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  27                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  28                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  29 /* Fractional Rates */
  30 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  31                                  SNDRV_PCM_RATE_176400)
  32 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  33                                     SNDRV_PCM_FMTBIT_S24_LE)
  34
  35 /* slave port water mark level
  36  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  37  */
  38 #define SLAVE_PORT_WATER_MARK_6BYTES    0
  39 #define SLAVE_PORT_WATER_MARK_9BYTES    1
  40 #define SLAVE_PORT_WATER_MARK_12BYTES   2
  41 #define SLAVE_PORT_WATER_MARK_15BYTES   3
  42 #define SLAVE_PORT_WATER_MARK_SHIFT     1
  43 #define SLAVE_PORT_ENABLE               1
  44 #define SLAVE_PORT_DISABLE              0
  45 #define WCD934X_SLIM_WATER_MARK_VAL \
  46         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  47          (SLAVE_PORT_ENABLE))
  48
  49 #define WCD934X_SLIM_NUM_PORT_REG       3
  50 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  51 #define WCD934X_SLIM_IRQ_OVERFLOW       BIT(0)
  52 #define WCD934X_SLIM_IRQ_UNDERFLOW      BIT(1)
  53 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
  54
  55 #define WCD934X_MCLK_CLK_12P288MHZ      12288000
  56 #define WCD934X_MCLK_CLK_9P6MHZ         9600000
  57
  58 /* Only valid for 9.6 MHz mclk */
  59 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  60 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  61
  62 /* Only valid for 12.288 MHz mclk */
  63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  64
  65 #define WCD934X_DMIC_CLK_DIV_2          0x0
  66 #define WCD934X_DMIC_CLK_DIV_3          0x1
  67 #define WCD934X_DMIC_CLK_DIV_4          0x2
  68 #define WCD934X_DMIC_CLK_DIV_6          0x3
  69 #define WCD934X_DMIC_CLK_DIV_8          0x4
  70 #define WCD934X_DMIC_CLK_DIV_16         0x5
  71 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  72
  73 #define TX_HPF_CUT_OFF_FREQ_MASK        0x60
  74 #define CF_MIN_3DB_4HZ                  0x0
  75 #define CF_MIN_3DB_75HZ                 0x1
  76 #define CF_MIN_3DB_150HZ                0x2
  77
  78 #define WCD934X_RX_START                16
  79 #define WCD934X_NUM_INTERPOLATORS       9
  80 #define WCD934X_RX_PATH_CTL_OFFSET      20
  81 #define WCD934X_MAX_VALID_ADC_MUX       13
  82 #define WCD934X_INVALID_ADC_MUX         9
  83
  84 #define WCD934X_SLIM_RX_CH(p) \
  85         {.port = p + WCD934X_RX_START, .shift = p,}
  86
  87 #define WCD934X_SLIM_TX_CH(p) \
  88         {.port = p, .shift = p,}
  89
  90 /* Feature masks to distinguish codec version */
  91 #define DSD_DISABLED_MASK   0
  92 #define SLNQ_DISABLED_MASK  1
  93
  94 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
  95 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
  96
  97 /* As fine version info cannot be retrieved before wcd probe.
  98  * Define three coarse versions for possible future use before wcd probe.
  99  */
 100 #define WCD_VERSION_WCD9340_1_0     0x400
 101 #define WCD_VERSION_WCD9341_1_0     0x410
 102 #define WCD_VERSION_WCD9340_1_1     0x401
 103 #define WCD_VERSION_WCD9341_1_1     0x411
 104 #define WCD934X_AMIC_PWR_LEVEL_LP       0
 105 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
 106 #define WCD934X_AMIC_PWR_LEVEL_HP       2
 107 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
 108 #define WCD934X_AMIC_PWR_LVL_MASK       0x60
 109 #define WCD934X_AMIC_PWR_LVL_SHIFT      0x5
 110
 111 #define WCD934X_DEC_PWR_LVL_MASK        0x06
 112 #define WCD934X_DEC_PWR_LVL_LP          0x02
 113 #define WCD934X_DEC_PWR_LVL_HP          0x04
 114 #define WCD934X_DEC_PWR_LVL_DF          0x00
 115 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
 116
 117 #define WCD934X_DEF_MICBIAS_MV  1800
 118 #define WCD934X_MAX_MICBIAS_MV  2850
 119
 120 #define WCD_IIR_FILTER_SIZE     (sizeof(u32) * BAND_MAX)
 121
 122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
 123 { \
 124         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 125         .info = wcd934x_iir_filter_info, \
 126         .get = wcd934x_get_iir_band_audio_mixer, \
 127         .put = wcd934x_put_iir_band_audio_mixer, \
 128         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 129                 .iir_idx = iidx, \
 130                 .band_idx = bidx, \
 131                 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
 132         } \
 133 }
 134
 135 /* Z value defined in milliohm */
 136 #define WCD934X_ZDET_VAL_32             32000
 137 #define WCD934X_ZDET_VAL_400            400000
 138 #define WCD934X_ZDET_VAL_1200           1200000
 139 #define WCD934X_ZDET_VAL_100K           100000000
 140 /* Z floating defined in ohms */
 141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
 142
 143 #define WCD934X_ZDET_NUM_MEASUREMENTS   900
 144 #define WCD934X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
 145 #define WCD934X_MBHC_GET_X1(x)          (x & 0x3FFF)
 146 /* Z value compared in milliOhm */
 147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
 148 #define WCD934X_MBHC_ZDET_CONST         (86 * 16384)
 149 #define WCD934X_MBHC_MOISTURE_RREF      R_24_KOHM
 150 #define WCD934X_MBHC_MAX_BUTTONS        (8)
 151 #define WCD_MBHC_HS_V_MAX           1600
 152
 153 #define WCD934X_INTERPOLATOR_PATH(id)                   \
 154         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 155         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 156         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 157         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 158         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 159         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 160         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 161         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 162         {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},  \
 163         {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},  \
 164         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 165         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 166         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 167         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 168         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 169         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 170         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 171         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 172         {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},  \
 173         {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},  \
 174         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 175         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 176         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 177         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 178         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 179         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 180         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 181         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 182         {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},          \
 183         {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},          \
 184         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
 185         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
 186         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
 187         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 188         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 189         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 190         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 191         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 192         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 193         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 194         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 195         {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
 196         {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
 197         {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},        \
 198         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},      \
 199         {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},       \
 200         {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"},     \
 201         {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},  \
 202         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
 203
 204 #define WCD934X_INTERPOLATOR_MIX2(id)                   \
 205         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
 206         {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
 207
 208 #define WCD934X_SLIM_RX_AIF_PATH(id)    \
 209         {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"},     \
 210         {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"},     \
 211         {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"},     \
 212         {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \
 213         {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
 214
 215 #define WCD934X_ADC_MUX(id) \
 216         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id },       \
 217         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id },       \
 218         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 219         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 220         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 221         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 222         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 223         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 224         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 225         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 226         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 227         {"AMIC MUX" #id, "ADC4", "ADC4"}
 228
 229 #define WCD934X_IIR_INP_MUX(id) \
 230         {"IIR" #id, NULL, "IIR" #id " INP0 MUX"},       \
 231         {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},    \
 232         {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},    \
 233         {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},    \
 234         {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},    \
 235         {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},    \
 236         {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},    \
 237         {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},    \
 238         {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},    \
 239         {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},    \
 240         {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"},     \
 241         {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"},     \
 242         {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"},     \
 243         {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"},     \
 244         {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"},     \
 245         {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"},     \
 246         {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"},     \
 247         {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"},     \
 248         {"IIR" #id, NULL, "IIR" #id " INP1 MUX"},       \
 249         {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},    \
 250         {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},    \
 251         {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},    \
 252         {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},    \
 253         {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},    \
 254         {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},    \
 255         {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},    \
 256         {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},    \
 257         {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},    \
 258         {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"},     \
 259         {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"},     \
 260         {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"},     \
 261         {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"},     \
 262         {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"},     \
 263         {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"},     \
 264         {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"},     \
 265         {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"},     \
 266         {"IIR" #id, NULL, "IIR" #id " INP2 MUX"},       \
 267         {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},    \
 268         {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},    \
 269         {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},    \
 270         {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},    \
 271         {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},    \
 272         {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},    \
 273         {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},    \
 274         {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},    \
 275         {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},    \
 276         {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"},     \
 277         {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"},     \
 278         {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"},     \
 279         {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"},     \
 280         {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"},     \
 281         {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"},     \
 282         {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"},     \
 283         {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"},     \
 284         {"IIR" #id, NULL, "IIR" #id " INP3 MUX"},       \
 285         {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},    \
 286         {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},    \
 287         {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},    \
 288         {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},    \
 289         {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},    \
 290         {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},    \
 291         {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},    \
 292         {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},    \
 293         {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},    \
 294         {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"},     \
 295         {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"},     \
 296         {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"},     \
 297         {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"},     \
 298         {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"},     \
 299         {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"},     \
 300         {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"},     \
 301         {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
 302
 303 #define WCD934X_SLIM_TX_AIF_PATH(id)    \
 304         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 305         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 306         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 307         {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
 308
 309 #define WCD934X_MAX_MICBIAS     MIC_BIAS_4
 310
 311 enum {
 312         SIDO_SOURCE_INTERNAL,
 313         SIDO_SOURCE_RCO_BG,
 314 };
 315
 316 enum {
 317         INTERP_EAR = 0,
 318         INTERP_HPHL,
 319         INTERP_HPHR,
 320         INTERP_LO1,
 321         INTERP_LO2,
 322         INTERP_LO3_NA, /* LO3 not avalible in Tavil */
 323         INTERP_LO4_NA,
 324         INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
 325         INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
 326         INTERP_MAX,
 327 };
 328
 329 enum {
 330         WCD934X_RX0 = 0,
 331         WCD934X_RX1,
 332         WCD934X_RX2,
 333         WCD934X_RX3,
 334         WCD934X_RX4,
 335         WCD934X_RX5,
 336         WCD934X_RX6,
 337         WCD934X_RX7,
 338         WCD934X_RX8,
 339         WCD934X_RX9,
 340         WCD934X_RX10,
 341         WCD934X_RX11,
 342         WCD934X_RX12,
 343         WCD934X_RX_MAX,
 344 };
 345
 346 enum {
 347         WCD934X_TX0 = 0,
 348         WCD934X_TX1,
 349         WCD934X_TX2,
 350         WCD934X_TX3,
 351         WCD934X_TX4,
 352         WCD934X_TX5,
 353         WCD934X_TX6,
 354         WCD934X_TX7,
 355         WCD934X_TX8,
 356         WCD934X_TX9,
 357         WCD934X_TX10,
 358         WCD934X_TX11,
 359         WCD934X_TX12,
 360         WCD934X_TX13,
 361         WCD934X_TX14,
 362         WCD934X_TX15,
 363         WCD934X_TX_MAX,
 364 };
 365
 366 struct wcd934x_slim_ch {
 367         u32 ch_num;
 368         u16 port;
 369         u16 shift;
 370         struct list_head list;
 371 };
 372
 373 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
 374         WCD934X_SLIM_TX_CH(0),
 375         WCD934X_SLIM_TX_CH(1),
 376         WCD934X_SLIM_TX_CH(2),
 377         WCD934X_SLIM_TX_CH(3),
 378         WCD934X_SLIM_TX_CH(4),
 379         WCD934X_SLIM_TX_CH(5),
 380         WCD934X_SLIM_TX_CH(6),
 381         WCD934X_SLIM_TX_CH(7),
 382         WCD934X_SLIM_TX_CH(8),
 383         WCD934X_SLIM_TX_CH(9),
 384         WCD934X_SLIM_TX_CH(10),
 385         WCD934X_SLIM_TX_CH(11),
 386         WCD934X_SLIM_TX_CH(12),
 387         WCD934X_SLIM_TX_CH(13),
 388         WCD934X_SLIM_TX_CH(14),
 389         WCD934X_SLIM_TX_CH(15),
 390 };
 391
 392 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
 393         WCD934X_SLIM_RX_CH(0),   /* 16 */
 394         WCD934X_SLIM_RX_CH(1),   /* 17 */
 395         WCD934X_SLIM_RX_CH(2),
 396         WCD934X_SLIM_RX_CH(3),
 397         WCD934X_SLIM_RX_CH(4),
 398         WCD934X_SLIM_RX_CH(5),
 399         WCD934X_SLIM_RX_CH(6),
 400         WCD934X_SLIM_RX_CH(7),
 401         WCD934X_SLIM_RX_CH(8),
 402         WCD934X_SLIM_RX_CH(9),
 403         WCD934X_SLIM_RX_CH(10),
 404         WCD934X_SLIM_RX_CH(11),
 405         WCD934X_SLIM_RX_CH(12),
 406 };
 407
 408 /* Codec supports 2 IIR filters */
 409 enum {
 410         IIR0 = 0,
 411         IIR1,
 412         IIR_MAX,
 413 };
 414
 415 /* Each IIR has 5 Filter Stages */
 416 enum {
 417         BAND1 = 0,
 418         BAND2,
 419         BAND3,
 420         BAND4,
 421         BAND5,
 422         BAND_MAX,
 423 };
 424
 425 enum {
 426         COMPANDER_1, /* HPH_L */
 427         COMPANDER_2, /* HPH_R */
 428         COMPANDER_3, /* LO1_DIFF */
 429         COMPANDER_4, /* LO2_DIFF */
 430         COMPANDER_5, /* LO3_SE - not used in Tavil */
 431         COMPANDER_6, /* LO4_SE - not used in Tavil */
 432         COMPANDER_7, /* SWR SPK CH1 */
 433         COMPANDER_8, /* SWR SPK CH2 */
 434         COMPANDER_MAX,
 435 };
 436
 437 enum {
 438         AIF1_PB = 0,
 439         AIF1_CAP,
 440         AIF2_PB,
 441         AIF2_CAP,
 442         AIF3_PB,
 443         AIF3_CAP,
 444         AIF4_PB,
 445         AIF4_VIFEED,
 446         AIF4_MAD_TX,
 447         NUM_CODEC_DAIS,
 448 };
 449
 450 enum {
 451         INTn_1_INP_SEL_ZERO = 0,
 452         INTn_1_INP_SEL_DEC0,
 453         INTn_1_INP_SEL_DEC1,
 454         INTn_1_INP_SEL_IIR0,
 455         INTn_1_INP_SEL_IIR1,
 456         INTn_1_INP_SEL_RX0,
 457         INTn_1_INP_SEL_RX1,
 458         INTn_1_INP_SEL_RX2,
 459         INTn_1_INP_SEL_RX3,
 460         INTn_1_INP_SEL_RX4,
 461         INTn_1_INP_SEL_RX5,
 462         INTn_1_INP_SEL_RX6,
 463         INTn_1_INP_SEL_RX7,
 464 };
 465
 466 enum {
 467         INTn_2_INP_SEL_ZERO = 0,
 468         INTn_2_INP_SEL_RX0,
 469         INTn_2_INP_SEL_RX1,
 470         INTn_2_INP_SEL_RX2,
 471         INTn_2_INP_SEL_RX3,
 472         INTn_2_INP_SEL_RX4,
 473         INTn_2_INP_SEL_RX5,
 474         INTn_2_INP_SEL_RX6,
 475         INTn_2_INP_SEL_RX7,
 476         INTn_2_INP_SEL_PROXIMITY,
 477 };
 478
 479 enum {
 480         INTERP_MAIN_PATH,
 481         INTERP_MIX_PATH,
 482 };
 483
 484 struct interp_sample_rate {
 485         int sample_rate;
 486         int rate_val;
 487 };
 488
 489 static struct interp_sample_rate sr_val_tbl[] = {
 490         {8000, 0x0},
 491         {16000, 0x1},
 492         {32000, 0x3},
 493         {48000, 0x4},
 494         {96000, 0x5},
 495         {192000, 0x6},
 496         {384000, 0x7},
 497         {44100, 0x9},
 498         {88200, 0xA},
 499         {176400, 0xB},
 500         {352800, 0xC},
 501 };
 502
 503 struct wcd934x_mbhc_zdet_param {
 504         u16 ldo_ctl;
 505         u16 noff;
 506         u16 nshift;
 507         u16 btn5;
 508         u16 btn6;
 509         u16 btn7;
 510 };
 511
 512 struct wcd_slim_codec_dai_data {
 513         struct list_head slim_ch_list;
 514         struct slim_stream_config sconfig;
 515         struct slim_stream_runtime *sruntime;
 516 };
 517
 518 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
 519         {
 520                 .name = "WCD9335-IFC-DEV",
 521                 .range_min =  0x0,
 522                 .range_max = 0xffff,
 523                 .selector_reg = 0x800,
 524                 .selector_mask = 0xfff,
 525                 .selector_shift = 0,
 526                 .window_start = 0x800,
 527                 .window_len = 0x400,
 528         },
 529 };
 530
 531 static struct regmap_config wcd934x_ifc_regmap_config = {
 532         .reg_bits = 16,
 533         .val_bits = 8,
 534         .max_register = 0xffff,
 535         .ranges = wcd934x_ifc_ranges,
 536         .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
 537 };
 538
 539 struct wcd934x_codec {
 540         struct device *dev;
 541         struct clk_hw hw;
 542         struct clk *extclk;
 543         struct regmap *regmap;
 544         struct regmap *if_regmap;
 545         struct slim_device *sdev;
 546         struct slim_device *sidev;
 547         struct wcd_clsh_ctrl *clsh_ctrl;
 548         struct snd_soc_component *component;
 549         struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
 550         struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
 551         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 552         int rate;
 553         u32 version;
 554         u32 hph_mode;
 555         int num_rx_port;
 556         int num_tx_port;
 557         u32 tx_port_value[WCD934X_TX_MAX];
 558         u32 rx_port_value[WCD934X_RX_MAX];
 559         int sido_input_src;
 560         int dmic_0_1_clk_cnt;
 561         int dmic_2_3_clk_cnt;
 562         int dmic_4_5_clk_cnt;
 563         int dmic_sample_rate;
 564         int comp_enabled[COMPANDER_MAX];
 565         int sysclk_users;
 566         struct mutex sysclk_mutex;
 567         /* mbhc module */
 568         struct wcd_mbhc *mbhc;
 569         struct wcd_mbhc_config mbhc_cfg;
 570         struct wcd_mbhc_intr intr_ids;
 571         bool mbhc_started;
 572         struct mutex micb_lock;
 573         u32 micb_ref[WCD934X_MAX_MICBIAS];
 574         u32 pullup_ref[WCD934X_MAX_MICBIAS];
 575         u32 micb1_mv;
 576         u32 micb2_mv;
 577         u32 micb3_mv;
 578         u32 micb4_mv;
 579 };
 580
 581 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
 582
 583 struct wcd_iir_filter_ctl {
 584         unsigned int iir_idx;
 585         unsigned int band_idx;
 586         struct soc_bytes_ext bytes_ext;
 587 };
 588
 589 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 590 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 591 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 592 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 593
 594 /* Cutoff frequency for high pass filter */
 595 static const char * const cf_text[] = {
 596         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 597 };
 598
 599 static const char * const rx_cf_text[] = {
 600         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 601         "CF_NEG_3DB_0P48HZ"
 602 };
 603
 604 static const char * const rx_hph_mode_mux_text[] = {
 605         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 606         "Class-H Hi-Fi Low Power"
 607 };
 608
 609 static const char *const slim_rx_mux_text[] = {
 610         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 611 };
 612
 613 static const char * const rx_int0_7_mix_mux_text[] = {
 614         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 615         "RX6", "RX7", "PROXIMITY"
 616 };
 617
 618 static const char * const rx_int_mix_mux_text[] = {
 619         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 620         "RX6", "RX7"
 621 };
 622
 623 static const char * const rx_prim_mix_text[] = {
 624         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 625         "RX3", "RX4", "RX5", "RX6", "RX7"
 626 };
 627
 628 static const char * const rx_sidetone_mix_text[] = {
 629         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 630 };
 631
 632 static const char * const iir_inp_mux_text[] = {
 633         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
 634         "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
 635 };
 636
 637 static const char * const rx_int_dem_inp_mux_text[] = {
 638         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 639 };
 640
 641 static const char * const rx_int0_1_interp_mux_text[] = {
 642         "ZERO", "RX INT0_1 MIX1",
 643 };
 644
 645 static const char * const rx_int1_1_interp_mux_text[] = {
 646         "ZERO", "RX INT1_1 MIX1",
 647 };
 648
 649 static const char * const rx_int2_1_interp_mux_text[] = {
 650         "ZERO", "RX INT2_1 MIX1",
 651 };
 652
 653 static const char * const rx_int3_1_interp_mux_text[] = {
 654         "ZERO", "RX INT3_1 MIX1",
 655 };
 656
 657 static const char * const rx_int4_1_interp_mux_text[] = {
 658         "ZERO", "RX INT4_1 MIX1",
 659 };
 660
 661 static const char * const rx_int7_1_interp_mux_text[] = {
 662         "ZERO", "RX INT7_1 MIX1",
 663 };
 664
 665 static const char * const rx_int8_1_interp_mux_text[] = {
 666         "ZERO", "RX INT8_1 MIX1",
 667 };
 668
 669 static const char * const rx_int0_2_interp_mux_text[] = {
 670         "ZERO", "RX INT0_2 MUX",
 671 };
 672
 673 static const char * const rx_int1_2_interp_mux_text[] = {
 674         "ZERO", "RX INT1_2 MUX",
 675 };
 676
 677 static const char * const rx_int2_2_interp_mux_text[] = {
 678         "ZERO", "RX INT2_2 MUX",
 679 };
 680
 681 static const char * const rx_int3_2_interp_mux_text[] = {
 682         "ZERO", "RX INT3_2 MUX",
 683 };
 684
 685 static const char * const rx_int4_2_interp_mux_text[] = {
 686         "ZERO", "RX INT4_2 MUX",
 687 };
 688
 689 static const char * const rx_int7_2_interp_mux_text[] = {
 690         "ZERO", "RX INT7_2 MUX",
 691 };
 692
 693 static const char * const rx_int8_2_interp_mux_text[] = {
 694         "ZERO", "RX INT8_2 MUX",
 695 };
 696
 697 static const char * const dmic_mux_text[] = {
 698         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
 699 };
 700
 701 static const char * const amic_mux_text[] = {
 702         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
 703 };
 704
 705 static const char * const amic4_5_sel_text[] = {
 706         "AMIC4", "AMIC5"
 707 };
 708
 709 static const char * const adc_mux_text[] = {
 710         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 711 };
 712
 713 static const char * const cdc_if_tx0_mux_text[] = {
 714         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 715 };
 716
 717 static const char * const cdc_if_tx1_mux_text[] = {
 718         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 719 };
 720
 721 static const char * const cdc_if_tx2_mux_text[] = {
 722         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 723 };
 724
 725 static const char * const cdc_if_tx3_mux_text[] = {
 726         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 727 };
 728
 729 static const char * const cdc_if_tx4_mux_text[] = {
 730         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 731 };
 732
 733 static const char * const cdc_if_tx5_mux_text[] = {
 734         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 735 };
 736
 737 static const char * const cdc_if_tx6_mux_text[] = {
 738         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 739 };
 740
 741 static const char * const cdc_if_tx7_mux_text[] = {
 742         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 743 };
 744
 745 static const char * const cdc_if_tx8_mux_text[] = {
 746         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 747 };
 748
 749 static const char * const cdc_if_tx9_mux_text[] = {
 750         "ZERO", "DEC7", "DEC7_192"
 751 };
 752
 753 static const char * const cdc_if_tx10_mux_text[] = {
 754         "ZERO", "DEC6", "DEC6_192"
 755 };
 756
 757 static const char * const cdc_if_tx11_mux_text[] = {
 758         "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
 759 };
 760
 761 static const char * const cdc_if_tx11_inp1_mux_text[] = {
 762         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
 763         "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
 764 };
 765
 766 static const char * const cdc_if_tx13_mux_text[] = {
 767         "CDC_DEC_5", "MAD_BRDCST"
 768 };
 769
 770 static const char * const cdc_if_tx13_inp1_mux_text[] = {
 771         "ZERO", "DEC5", "DEC5_192"
 772 };
 773
 774 static const struct soc_enum cf_dec0_enum =
 775         SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 776
 777 static const struct soc_enum cf_dec1_enum =
 778         SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 779
 780 static const struct soc_enum cf_dec2_enum =
 781         SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 782
 783 static const struct soc_enum cf_dec3_enum =
 784         SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 785
 786 static const struct soc_enum cf_dec4_enum =
 787         SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 788
 789 static const struct soc_enum cf_dec5_enum =
 790         SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 791
 792 static const struct soc_enum cf_dec6_enum =
 793         SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 794
 795 static const struct soc_enum cf_dec7_enum =
 796         SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 797
 798 static const struct soc_enum cf_dec8_enum =
 799         SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 800
 801 static const struct soc_enum cf_int0_1_enum =
 802         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 803
 804 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
 805                      rx_cf_text);
 806
 807 static const struct soc_enum cf_int1_1_enum =
 808         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 809
 810 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
 811                      rx_cf_text);
 812
 813 static const struct soc_enum cf_int2_1_enum =
 814         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 815
 816 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
 817                      rx_cf_text);
 818
 819 static const struct soc_enum cf_int3_1_enum =
 820         SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 821
 822 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
 823                             rx_cf_text);
 824
 825 static const struct soc_enum cf_int4_1_enum =
 826         SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 827
 828 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
 829                             rx_cf_text);
 830
 831 static const struct soc_enum cf_int7_1_enum =
 832         SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 833
 834 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
 835                             rx_cf_text);
 836
 837 static const struct soc_enum cf_int8_1_enum =
 838         SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 839
 840 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
 841                             rx_cf_text);
 842
 843 static const struct soc_enum rx_hph_mode_mux_enum =
 844         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 845                             rx_hph_mode_mux_text);
 846
 847 static const struct soc_enum slim_rx_mux_enum =
 848         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 849
 850 static const struct soc_enum rx_int0_2_mux_chain_enum =
 851         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 852                         rx_int0_7_mix_mux_text);
 853
 854 static const struct soc_enum rx_int1_2_mux_chain_enum =
 855         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 856                         rx_int_mix_mux_text);
 857
 858 static const struct soc_enum rx_int2_2_mux_chain_enum =
 859         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 860                         rx_int_mix_mux_text);
 861
 862 static const struct soc_enum rx_int3_2_mux_chain_enum =
 863         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 864                         rx_int_mix_mux_text);
 865
 866 static const struct soc_enum rx_int4_2_mux_chain_enum =
 867         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 868                         rx_int_mix_mux_text);
 869
 870 static const struct soc_enum rx_int7_2_mux_chain_enum =
 871         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 872                         rx_int0_7_mix_mux_text);
 873
 874 static const struct soc_enum rx_int8_2_mux_chain_enum =
 875         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 876                         rx_int_mix_mux_text);
 877
 878 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 879         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 880                         rx_prim_mix_text);
 881
 882 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 883         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 884                         rx_prim_mix_text);
 885
 886 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 887         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 888                         rx_prim_mix_text);
 889
 890 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 891         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 892                         rx_prim_mix_text);
 893
 894 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 895         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 896                         rx_prim_mix_text);
 897
 898 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 899         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 900                         rx_prim_mix_text);
 901
 902 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 903         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 904                         rx_prim_mix_text);
 905
 906 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 907         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 908                         rx_prim_mix_text);
 909
 910 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 911         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 912                         rx_prim_mix_text);
 913
 914 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 915         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 916                         rx_prim_mix_text);
 917
 918 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 919         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 920                         rx_prim_mix_text);
 921
 922 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 923         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 924                         rx_prim_mix_text);
 925
 926 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 927         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 928                         rx_prim_mix_text);
 929
 930 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 931         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 932                         rx_prim_mix_text);
 933
 934 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 935         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 936                         rx_prim_mix_text);
 937
 938 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 939         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 940                         rx_prim_mix_text);
 941
 942 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 943         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 944                         rx_prim_mix_text);
 945
 946 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 947         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 948                         rx_prim_mix_text);
 949
 950 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 951         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 952                         rx_prim_mix_text);
 953
 954 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 955         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 956                         rx_prim_mix_text);
 957
 958 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 959         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 960                         rx_prim_mix_text);
 961
 962 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
 963         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
 964                         rx_sidetone_mix_text);
 965
 966 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
 967         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
 968                         rx_sidetone_mix_text);
 969
 970 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
 971         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
 972                         rx_sidetone_mix_text);
 973
 974 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
 975         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
 976                         rx_sidetone_mix_text);
 977
 978 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
 979         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
 980                         rx_sidetone_mix_text);
 981
 982 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
 983         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
 984                         rx_sidetone_mix_text);
 985
 986 static const struct soc_enum iir0_inp0_mux_enum =
 987         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
 988                         0, 18, iir_inp_mux_text);
 989
 990 static const struct soc_enum iir0_inp1_mux_enum =
 991         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
 992                         0, 18, iir_inp_mux_text);
 993
 994 static const struct soc_enum iir0_inp2_mux_enum =
 995         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
 996                         0, 18, iir_inp_mux_text);
 997
 998 static const struct soc_enum iir0_inp3_mux_enum =
 999         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
1000                         0, 18, iir_inp_mux_text);
1001
1002 static const struct soc_enum iir1_inp0_mux_enum =
1003         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
1004                         0, 18, iir_inp_mux_text);
1005
1006 static const struct soc_enum iir1_inp1_mux_enum =
1007         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
1008                         0, 18, iir_inp_mux_text);
1009
1010 static const struct soc_enum iir1_inp2_mux_enum =
1011         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
1012                         0, 18, iir_inp_mux_text);
1013
1014 static const struct soc_enum iir1_inp3_mux_enum =
1015         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
1016                         0, 18, iir_inp_mux_text);
1017
1018 static const struct soc_enum rx_int0_dem_inp_mux_enum =
1019         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
1020                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
1021                         rx_int_dem_inp_mux_text);
1022
1023 static const struct soc_enum rx_int1_dem_inp_mux_enum =
1024         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
1025                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
1026                         rx_int_dem_inp_mux_text);
1027
1028 static const struct soc_enum rx_int2_dem_inp_mux_enum =
1029         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
1030                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
1031                         rx_int_dem_inp_mux_text);
1032
1033 static const struct soc_enum tx_adc_mux0_enum =
1034         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1035                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1036 static const struct soc_enum tx_adc_mux1_enum =
1037         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1038                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1039 static const struct soc_enum tx_adc_mux2_enum =
1040         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1041                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1042 static const struct soc_enum tx_adc_mux3_enum =
1043         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1044                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1045 static const struct soc_enum tx_adc_mux4_enum =
1046         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1047                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1048 static const struct soc_enum tx_adc_mux5_enum =
1049         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1050                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1051 static const struct soc_enum tx_adc_mux6_enum =
1052         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1053                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1054 static const struct soc_enum tx_adc_mux7_enum =
1055         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1056                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1057 static const struct soc_enum tx_adc_mux8_enum =
1058         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1059                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1060
1061 static const struct soc_enum rx_int0_1_interp_mux_enum =
1062         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1063                         rx_int0_1_interp_mux_text);
1064
1065 static const struct soc_enum rx_int1_1_interp_mux_enum =
1066         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1067                         rx_int1_1_interp_mux_text);
1068
1069 static const struct soc_enum rx_int2_1_interp_mux_enum =
1070         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1071                         rx_int2_1_interp_mux_text);
1072
1073 static const struct soc_enum rx_int3_1_interp_mux_enum =
1074         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_1_interp_mux_text);
1075
1076 static const struct soc_enum rx_int4_1_interp_mux_enum =
1077         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_1_interp_mux_text);
1078
1079 static const struct soc_enum rx_int7_1_interp_mux_enum =
1080         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_1_interp_mux_text);
1081
1082 static const struct soc_enum rx_int8_1_interp_mux_enum =
1083         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_1_interp_mux_text);
1084
1085 static const struct soc_enum rx_int0_2_interp_mux_enum =
1086         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int0_2_interp_mux_text);
1087
1088 static const struct soc_enum rx_int1_2_interp_mux_enum =
1089         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int1_2_interp_mux_text);
1090
1091 static const struct soc_enum rx_int2_2_interp_mux_enum =
1092         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int2_2_interp_mux_text);
1093
1094 static const struct soc_enum rx_int3_2_interp_mux_enum =
1095         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_2_interp_mux_text);
1096
1097 static const struct soc_enum rx_int4_2_interp_mux_enum =
1098         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_2_interp_mux_text);
1099
1100 static const struct soc_enum rx_int7_2_interp_mux_enum =
1101         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_2_interp_mux_text);
1102
1103 static const struct soc_enum rx_int8_2_interp_mux_enum =
1104         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_2_interp_mux_text);
1105
1106 static const struct soc_enum tx_dmic_mux0_enum =
1107         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1108                         dmic_mux_text);
1109
1110 static const struct soc_enum tx_dmic_mux1_enum =
1111         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1112                         dmic_mux_text);
1113
1114 static const struct soc_enum tx_dmic_mux2_enum =
1115         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1116                         dmic_mux_text);
1117
1118 static const struct soc_enum tx_dmic_mux3_enum =
1119         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1120                         dmic_mux_text);
1121
1122 static const struct soc_enum tx_dmic_mux4_enum =
1123         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1124                         dmic_mux_text);
1125
1126 static const struct soc_enum tx_dmic_mux5_enum =
1127         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1128                         dmic_mux_text);
1129
1130 static const struct soc_enum tx_dmic_mux6_enum =
1131         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1132                         dmic_mux_text);
1133
1134 static const struct soc_enum tx_dmic_mux7_enum =
1135         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1136                         dmic_mux_text);
1137
1138 static const struct soc_enum tx_dmic_mux8_enum =
1139         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1140                         dmic_mux_text);
1141
1142 static const struct soc_enum tx_amic_mux0_enum =
1143         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1144                         amic_mux_text);
1145 static const struct soc_enum tx_amic_mux1_enum =
1146         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1147                         amic_mux_text);
1148 static const struct soc_enum tx_amic_mux2_enum =
1149         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1150                         amic_mux_text);
1151 static const struct soc_enum tx_amic_mux3_enum =
1152         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1153                         amic_mux_text);
1154 static const struct soc_enum tx_amic_mux4_enum =
1155         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1156                         amic_mux_text);
1157 static const struct soc_enum tx_amic_mux5_enum =
1158         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1159                         amic_mux_text);
1160 static const struct soc_enum tx_amic_mux6_enum =
1161         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1162                         amic_mux_text);
1163 static const struct soc_enum tx_amic_mux7_enum =
1164         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1165                         amic_mux_text);
1166 static const struct soc_enum tx_amic_mux8_enum =
1167         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1168                         amic_mux_text);
1169
1170 static const struct soc_enum tx_amic4_5_enum =
1171         SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1172
1173 static const struct soc_enum cdc_if_tx0_mux_enum =
1174         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1175                         ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1176 static const struct soc_enum cdc_if_tx1_mux_enum =
1177         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1178                         ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1179 static const struct soc_enum cdc_if_tx2_mux_enum =
1180         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1181                         ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1182 static const struct soc_enum cdc_if_tx3_mux_enum =
1183         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1184                         ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1185 static const struct soc_enum cdc_if_tx4_mux_enum =
1186         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1187                         ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1188 static const struct soc_enum cdc_if_tx5_mux_enum =
1189         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1190                         ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1191 static const struct soc_enum cdc_if_tx6_mux_enum =
1192         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1193                         ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1194 static const struct soc_enum cdc_if_tx7_mux_enum =
1195         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1196                         ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1197 static const struct soc_enum cdc_if_tx8_mux_enum =
1198         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1199                         ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1200 static const struct soc_enum cdc_if_tx9_mux_enum =
1201         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1202                         ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1203 static const struct soc_enum cdc_if_tx10_mux_enum =
1204         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1205                         ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1206 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1207         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1208                         ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1209                         cdc_if_tx11_inp1_mux_text);
1210 static const struct soc_enum cdc_if_tx11_mux_enum =
1211         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1212                         ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1213 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1214         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1215                         ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1216                         cdc_if_tx13_inp1_mux_text);
1217 static const struct soc_enum cdc_if_tx13_mux_enum =
1218         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1219                         ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1220
1221 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
1222         WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
1223         WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
1224         WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
1225         WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
1226         WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
1227         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
1228         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
1229         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
1230         WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
1231         WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
1232         WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
1233         WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
1234         WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
1235         WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
1236         WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
1237         WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
1238         WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1239         WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
1240         WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
1241         WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
1242         WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
1243         WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
1244         WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
1245         WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
1246         WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
1247         WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
1248         WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
1249         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
1250         WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
1251         WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1252         WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
1253         WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
1254         WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
1255         WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
1256         WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
1257         WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
1258         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
1259         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
1260         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
1261         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
1262         WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
1263         WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
1264         WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
1265         WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
1266         WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
1267         WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
1268         WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
1269         WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
1270 };
1271
1272 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1273 {
1274         if (sido_src == wcd->sido_input_src)
1275                 return 0;
1276
1277         if (sido_src == SIDO_SOURCE_INTERNAL) {
1278                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1279                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
1280                 usleep_range(100, 110);
1281                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1282                                    WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
1283                 usleep_range(100, 110);
1284                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1285                                    WCD934X_ANA_RCO_BG_EN_MASK, 0);
1286                 usleep_range(100, 110);
1287                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1288                                    WCD934X_ANA_BUCK_PRE_EN1_MASK,
1289                                    WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
1290                 usleep_range(100, 110);
1291                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1292                                    WCD934X_ANA_BUCK_PRE_EN2_MASK,
1293                                    WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
1294                 usleep_range(100, 110);
1295                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1296                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
1297                                    WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
1298                 usleep_range(100, 110);
1299         } else if (sido_src == SIDO_SOURCE_RCO_BG) {
1300                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1301                                    WCD934X_ANA_RCO_BG_EN_MASK,
1302                                    WCD934X_ANA_RCO_BG_ENABLE);
1303                 usleep_range(100, 110);
1304         }
1305         wcd->sido_input_src = sido_src;
1306
1307         return 0;
1308 }
1309
1310 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1311 {
1312         mutex_lock(&wcd->sysclk_mutex);
1313
1314         if (++wcd->sysclk_users != 1) {
1315                 mutex_unlock(&wcd->sysclk_mutex);
1316                 return 0;
1317         }
1318         mutex_unlock(&wcd->sysclk_mutex);
1319
1320         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1321                            WCD934X_ANA_BIAS_EN_MASK,
1322                            WCD934X_ANA_BIAS_EN);
1323         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1324                            WCD934X_ANA_PRECHRG_EN_MASK,
1325                            WCD934X_ANA_PRECHRG_EN);
1326         /*
1327          * 1ms delay is required after pre-charge is enabled
1328          * as per HW requirement
1329          */
1330         usleep_range(1000, 1100);
1331         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1332                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1333         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1334                            WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1335
1336         /*
1337          * In data clock contrl register is changed
1338          * to CLK_SYS_MCLK_PRG
1339          */
1340
1341         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1342                            WCD934X_EXT_CLK_BUF_EN_MASK,
1343                            WCD934X_EXT_CLK_BUF_EN);
1344         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1345                            WCD934X_EXT_CLK_DIV_RATIO_MASK,
1346                            WCD934X_EXT_CLK_DIV_BY_2);
1347         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1348                            WCD934X_MCLK_SRC_MASK,
1349                            WCD934X_MCLK_SRC_EXT_CLK);
1350         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1351                            WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1352         regmap_update_bits(wcd->regmap,
1353                            WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1354                            WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1355                            WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1356         regmap_update_bits(wcd->regmap,
1357                            WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1358                            WCD934X_MCLK_EN_MASK,
1359                            WCD934X_MCLK_EN);
1360         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1361                            WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1362         /*
1363          * 10us sleep is required after clock is enabled
1364          * as per HW requirement
1365          */
1366         usleep_range(10, 15);
1367
1368         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1369
1370         return 0;
1371 }
1372
1373 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1374 {
1375         mutex_lock(&wcd->sysclk_mutex);
1376         if (--wcd->sysclk_users != 0) {
1377                 mutex_unlock(&wcd->sysclk_mutex);
1378                 return 0;
1379         }
1380         mutex_unlock(&wcd->sysclk_mutex);
1381
1382         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1383                            WCD934X_EXT_CLK_BUF_EN_MASK |
1384                            WCD934X_MCLK_EN_MASK, 0x0);
1385         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
1386
1387         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1388                            WCD934X_ANA_BIAS_EN_MASK, 0);
1389         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1390                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1391
1392         return 0;
1393 }
1394
1395 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1396 {
1397         int ret = 0;
1398
1399         if (enable) {
1400                 ret = clk_prepare_enable(wcd->extclk);
1401
1402                 if (ret) {
1403                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
1404                                 __func__);
1405                         return ret;
1406                 }
1407                 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1408         } else {
1409                 int val;
1410
1411                 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1412                             &val);
1413
1414                 /* Don't disable clock if soundwire using it.*/
1415                 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1416                         return 0;
1417
1418                 wcd934x_disable_ana_bias_and_syclk(wcd);
1419                 clk_disable_unprepare(wcd->extclk);
1420         }
1421
1422         return ret;
1423 }
1424
1425 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1426                                      struct snd_kcontrol *kc, int event)
1427 {
1428         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1429         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1430
1431         switch (event) {
1432         case SND_SOC_DAPM_PRE_PMU:
1433                 return __wcd934x_cdc_mclk_enable(wcd, true);
1434         case SND_SOC_DAPM_POST_PMD:
1435                 return __wcd934x_cdc_mclk_enable(wcd, false);
1436         }
1437
1438         return 0;
1439 }
1440
1441 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1442 {
1443         int val1, val2, ver, ret;
1444         struct regmap *regmap;
1445         u16 id_minor;
1446         u32 version_mask = 0;
1447
1448         regmap = wcd->regmap;
1449         ver = 0;
1450
1451         ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1452                                (u8 *)&id_minor, sizeof(u16));
1453
1454         if (ret)
1455                 return ret;
1456
1457         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1458         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1459
1460         version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1461         version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1462
1463         switch (version_mask) {
1464         case DSD_DISABLED | SLNQ_DISABLED:
1465                 if (id_minor == 0)
1466                         ver = WCD_VERSION_WCD9340_1_0;
1467                 else if (id_minor == 0x01)
1468                         ver = WCD_VERSION_WCD9340_1_1;
1469                 break;
1470         case SLNQ_DISABLED:
1471                 if (id_minor == 0)
1472                         ver = WCD_VERSION_WCD9341_1_0;
1473                 else if (id_minor == 0x01)
1474                         ver = WCD_VERSION_WCD9341_1_1;
1475                 break;
1476         }
1477
1478         wcd->version = ver;
1479         dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1480
1481         return 0;
1482 }
1483
1484 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1485 {
1486         int rc, val;
1487
1488         __wcd934x_cdc_mclk_enable(wcd, true);
1489
1490         regmap_update_bits(wcd->regmap,
1491                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1492                            WCD934X_EFUSE_SENSE_STATE_MASK,
1493                            WCD934X_EFUSE_SENSE_STATE_DEF);
1494         regmap_update_bits(wcd->regmap,
1495                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1496                            WCD934X_EFUSE_SENSE_EN_MASK,
1497                            WCD934X_EFUSE_SENSE_ENABLE);
1498         /*
1499          * 5ms sleep required after enabling efuse control
1500          * before checking the status.
1501          */
1502         usleep_range(5000, 5500);
1503         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1504
1505         rc = regmap_read(wcd->regmap,
1506                          WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1507         if (rc || (!(val & 0x01)))
1508                 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1509                      __func__, val, rc);
1510
1511         __wcd934x_cdc_mclk_enable(wcd, false);
1512 }
1513
1514 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1515 {
1516         if (enable) {
1517                 __wcd934x_cdc_mclk_enable(wcd, true);
1518                 regmap_update_bits(wcd->regmap,
1519                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1520                                    WCD934X_CDC_SWR_CLK_EN_MASK,
1521                                    WCD934X_CDC_SWR_CLK_ENABLE);
1522         } else {
1523                 regmap_update_bits(wcd->regmap,
1524                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1525                                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1526                 __wcd934x_cdc_mclk_enable(wcd, false);
1527         }
1528
1529         return 0;
1530 }
1531
1532 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1533                                               u8 rate_val, u32 rate)
1534 {
1535         struct snd_soc_component *comp = dai->component;
1536         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1537         struct wcd934x_slim_ch *ch;
1538         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1539         int inp, j;
1540
1541         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1542                 inp = ch->shift + INTn_1_INP_SEL_RX0;
1543                 /*
1544                  * Loop through all interpolator MUX inputs and find out
1545                  * to which interpolator input, the slim rx port
1546                  * is connected
1547                  */
1548                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1549                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1550                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1551                                 continue;
1552
1553                         cfg0 = snd_soc_component_read(comp,
1554                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1555                         cfg1 = snd_soc_component_read(comp,
1556                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1557
1558                         inp0_sel = cfg0 &
1559                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1560                         inp1_sel = (cfg0 >> 4) &
1561                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1562                         inp2_sel = (cfg1 >> 4) &
1563                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1564
1565                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1566                             (inp2_sel == inp)) {
1567                                 /* rate is in Hz */
1568                                 /*
1569                                  * Ear and speaker primary path does not support
1570                                  * native sample rates
1571                                  */
1572                                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1573                                      j == INTERP_SPKR2) && rate == 44100)
1574                                         dev_err(wcd->dev,
1575                                                 "Cannot set 44.1KHz on INT%d\n",
1576                                                 j);
1577                                 else
1578                                         snd_soc_component_update_bits(comp,
1579                                               WCD934X_CDC_RX_PATH_CTL(j),
1580                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1581                                               rate_val);
1582                         }
1583                 }
1584         }
1585
1586         return 0;
1587 }
1588
1589 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1590                                              int rate_val, u32 rate)
1591 {
1592         struct snd_soc_component *component = dai->component;
1593         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1594         struct wcd934x_slim_ch *ch;
1595         int val, j;
1596
1597         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1598                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1599                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1600                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1601                                 continue;
1602                         val = snd_soc_component_read(component,
1603                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1604                                         WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1605
1606                         if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1607                                 /*
1608                                  * Ear mix path supports only 48, 96, 192,
1609                                  * 384KHz only
1610                                  */
1611                                 if ((j == INTERP_EAR) &&
1612                                     (rate_val < 0x4 ||
1613                                      rate_val > 0x7)) {
1614                                         dev_err(component->dev,
1615                                                 "Invalid rate for AIF_PB DAI(%d)\n",
1616                                                 dai->id);
1617                                         return -EINVAL;
1618                                 }
1619
1620                                 snd_soc_component_update_bits(component,
1621                                               WCD934X_CDC_RX_PATH_MIX_CTL(j),
1622                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1623                                               rate_val);
1624                         }
1625                 }
1626         }
1627
1628         return 0;
1629 }
1630
1631 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1632                                          u32 sample_rate)
1633 {
1634         int rate_val = 0;
1635         int i, ret;
1636
1637         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1638                 if (sample_rate == sr_val_tbl[i].sample_rate) {
1639                         rate_val = sr_val_tbl[i].rate_val;
1640                         break;
1641                 }
1642         }
1643         if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1644                 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1645                 return -EINVAL;
1646         }
1647
1648         ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1649                                                  sample_rate);
1650         if (ret)
1651                 return ret;
1652         ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1653                                                 sample_rate);
1654
1655         return ret;
1656 }
1657
1658 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1659                                       u8 rate_val, u32 rate)
1660 {
1661         struct snd_soc_component *comp = dai->component;
1662         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1663         u8 shift = 0, shift_val = 0, tx_mux_sel;
1664         struct wcd934x_slim_ch *ch;
1665         int tx_port, tx_port_reg;
1666         int decimator = -1;
1667
1668         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1669                 tx_port = ch->port;
1670                 /* Find the SB TX MUX input - which decimator is connected */
1671                 switch (tx_port) {
1672                 case 0 ...  3:
1673                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1674                         shift = (tx_port << 1);
1675                         shift_val = 0x03;
1676                         break;
1677                 case 4 ... 7:
1678                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1679                         shift = ((tx_port - 4) << 1);
1680                         shift_val = 0x03;
1681                         break;
1682                 case 8 ... 10:
1683                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1684                         shift = ((tx_port - 8) << 1);
1685                         shift_val = 0x03;
1686                         break;
1687                 case 11:
1688                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1689                         shift = 0;
1690                         shift_val = 0x0F;
1691                         break;
1692                 case 13:
1693                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1694                         shift = 4;
1695                         shift_val = 0x03;
1696                         break;
1697                 default:
1698                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1699                                 tx_port, dai->id);
1700                         return -EINVAL;
1701                 }
1702
1703                 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1704                                                       (shift_val << shift);
1705
1706                 tx_mux_sel = tx_mux_sel >> shift;
1707                 switch (tx_port) {
1708                 case 0 ... 8:
1709                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1710                                 decimator = tx_port;
1711                         break;
1712                 case 9 ... 10:
1713                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1714                                 decimator = ((tx_port == 9) ? 7 : 6);
1715                         break;
1716                 case 11:
1717                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1718                                 decimator = tx_mux_sel - 1;
1719                         break;
1720                 case 13:
1721                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1722                                 decimator = 5;
1723                         break;
1724                 default:
1725                         dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1726                                 tx_port);
1727                         return -EINVAL;
1728                 }
1729
1730                 snd_soc_component_update_bits(comp,
1731                                       WCD934X_CDC_TX_PATH_CTL(decimator),
1732                                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1733                                       rate_val);
1734         }
1735
1736         return 0;
1737 }
1738
1739 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1740                                       struct wcd_slim_codec_dai_data *dai_data,
1741                                       int direction)
1742 {
1743         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1744         struct slim_stream_config *cfg = &dai_data->sconfig;
1745         struct wcd934x_slim_ch *ch;
1746         u16 payload = 0;
1747         int ret, i;
1748
1749         cfg->ch_count = 0;
1750         cfg->direction = direction;
1751         cfg->port_mask = 0;
1752
1753         /* Configure slave interface device */
1754         list_for_each_entry(ch, slim_ch_list, list) {
1755                 cfg->ch_count++;
1756                 payload |= 1 << ch->shift;
1757                 cfg->port_mask |= BIT(ch->port);
1758         }
1759
1760         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1761         if (!cfg->chs)
1762                 return -ENOMEM;
1763
1764         i = 0;
1765         list_for_each_entry(ch, slim_ch_list, list) {
1766                 cfg->chs[i++] = ch->ch_num;
1767                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1768                         /* write to interface device */
1769                         ret = regmap_write(wcd->if_regmap,
1770                            WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1771                            payload);
1772
1773                         if (ret < 0)
1774                                 goto err;
1775
1776                         /* configure the slave port for water mark and enable*/
1777                         ret = regmap_write(wcd->if_regmap,
1778                                         WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1779                                         WCD934X_SLIM_WATER_MARK_VAL);
1780                         if (ret < 0)
1781                                 goto err;
1782                 } else {
1783                         ret = regmap_write(wcd->if_regmap,
1784                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1785                                 payload & 0x00FF);
1786                         if (ret < 0)
1787                                 goto err;
1788
1789                         /* ports 8,9 */
1790                         ret = regmap_write(wcd->if_regmap,
1791                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1792                                 (payload & 0xFF00) >> 8);
1793                         if (ret < 0)
1794                                 goto err;
1795
1796                         /* configure the slave port for water mark and enable*/
1797                         ret = regmap_write(wcd->if_regmap,
1798                                         WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1799                                         WCD934X_SLIM_WATER_MARK_VAL);
1800
1801                         if (ret < 0)
1802                                 goto err;
1803                 }
1804         }
1805
1806         dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1807
1808         return 0;
1809
1810 err:
1811         dev_err(wcd->dev, "Error Setting slim hw params\n");
1812         kfree(cfg->chs);
1813         cfg->chs = NULL;
1814
1815         return ret;
1816 }
1817
1818 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1819                              struct snd_pcm_hw_params *params,
1820                              struct snd_soc_dai *dai)
1821 {
1822         struct wcd934x_codec *wcd;
1823         int ret, tx_fs_rate = 0;
1824
1825         wcd = snd_soc_component_get_drvdata(dai->component);
1826
1827         switch (substream->stream) {
1828         case SNDRV_PCM_STREAM_PLAYBACK:
1829                 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1830                 if (ret) {
1831                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1832                                 params_rate(params));
1833                         return ret;
1834                 }
1835                 switch (params_width(params)) {
1836                 case 16 ... 24:
1837                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1838                         break;
1839                 default:
1840                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1841                                 params_width(params));
1842                         return -EINVAL;
1843                 }
1844                 break;
1845
1846         case SNDRV_PCM_STREAM_CAPTURE:
1847                 switch (params_rate(params)) {
1848                 case 8000:
1849                         tx_fs_rate = 0;
1850                         break;
1851                 case 16000:
1852                         tx_fs_rate = 1;
1853                         break;
1854                 case 32000:
1855                         tx_fs_rate = 3;
1856                         break;
1857                 case 48000:
1858                         tx_fs_rate = 4;
1859                         break;
1860                 case 96000:
1861                         tx_fs_rate = 5;
1862                         break;
1863                 case 192000:
1864                         tx_fs_rate = 6;
1865                         break;
1866                 case 384000:
1867                         tx_fs_rate = 7;
1868                         break;
1869                 default:
1870                         dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1871                                 params_rate(params));
1872                         return -EINVAL;
1873
1874                 }
1875
1876                 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1877                                                  params_rate(params));
1878                 if (ret < 0) {
1879                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1880                         return ret;
1881                 }
1882                 switch (params_width(params)) {
1883                 case 16 ... 32:
1884                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1885                         break;
1886                 default:
1887                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1888                                 params_width(params));
1889                         return -EINVAL;
1890                 }
1891                 break;
1892         default:
1893                 dev_err(wcd->dev, "Invalid stream type %d\n",
1894                         substream->stream);
1895                 return -EINVAL;
1896         }
1897
1898         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1899
1900         return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1901 }
1902
1903 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1904                            struct snd_soc_dai *dai)
1905 {
1906         struct wcd_slim_codec_dai_data *dai_data;
1907         struct wcd934x_codec *wcd;
1908
1909         wcd = snd_soc_component_get_drvdata(dai->component);
1910
1911         dai_data = &wcd->dai[dai->id];
1912
1913         kfree(dai_data->sconfig.chs);
1914
1915         return 0;
1916 }
1917
1918 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1919                            struct snd_soc_dai *dai)
1920 {
1921         struct wcd_slim_codec_dai_data *dai_data;
1922         struct wcd934x_codec *wcd;
1923         struct slim_stream_config *cfg;
1924
1925         wcd = snd_soc_component_get_drvdata(dai->component);
1926
1927         dai_data = &wcd->dai[dai->id];
1928
1929         switch (cmd) {
1930         case SNDRV_PCM_TRIGGER_START:
1931         case SNDRV_PCM_TRIGGER_RESUME:
1932         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1933                 cfg = &dai_data->sconfig;
1934                 slim_stream_prepare(dai_data->sruntime, cfg);
1935                 slim_stream_enable(dai_data->sruntime);
1936                 break;
1937         case SNDRV_PCM_TRIGGER_STOP:
1938         case SNDRV_PCM_TRIGGER_SUSPEND:
1939         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1940                 slim_stream_unprepare(dai_data->sruntime);
1941                 slim_stream_disable(dai_data->sruntime);
1942                 break;
1943         default:
1944                 break;
1945         }
1946
1947         return 0;
1948 }
1949
1950 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1951                                    unsigned int tx_num, unsigned int *tx_slot,
1952                                    unsigned int rx_num, unsigned int *rx_slot)
1953 {
1954         struct wcd934x_codec *wcd;
1955         int i;
1956
1957         wcd = snd_soc_component_get_drvdata(dai->component);
1958
1959         if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1960                 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1961                         tx_num, rx_num);
1962                 return -EINVAL;
1963         }
1964
1965         if (!tx_slot || !rx_slot) {
1966                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1967                         tx_slot, rx_slot);
1968                 return -EINVAL;
1969         }
1970
1971         wcd->num_rx_port = rx_num;
1972         for (i = 0; i < rx_num; i++) {
1973                 wcd->rx_chs[i].ch_num = rx_slot[i];
1974                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1975         }
1976
1977         wcd->num_tx_port = tx_num;
1978         for (i = 0; i < tx_num; i++) {
1979                 wcd->tx_chs[i].ch_num = tx_slot[i];
1980                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1981         }
1982
1983         return 0;
1984 }
1985
1986 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1987                                    unsigned int *tx_num, unsigned int *tx_slot,
1988                                    unsigned int *rx_num, unsigned int *rx_slot)
1989 {
1990         struct wcd934x_slim_ch *ch;
1991         struct wcd934x_codec *wcd;
1992         int i = 0;
1993
1994         wcd = snd_soc_component_get_drvdata(dai->component);
1995
1996         switch (dai->id) {
1997         case AIF1_PB:
1998         case AIF2_PB:
1999         case AIF3_PB:
2000         case AIF4_PB:
2001                 if (!rx_slot || !rx_num) {
2002                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2003                                 rx_slot, rx_num);
2004                         return -EINVAL;
2005                 }
2006
2007                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2008                         rx_slot[i++] = ch->ch_num;
2009
2010                 *rx_num = i;
2011                 break;
2012         case AIF1_CAP:
2013         case AIF2_CAP:
2014         case AIF3_CAP:
2015                 if (!tx_slot || !tx_num) {
2016                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2017                                 tx_slot, tx_num);
2018                         return -EINVAL;
2019                 }
2020
2021                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2022                         tx_slot[i++] = ch->ch_num;
2023
2024                 *tx_num = i;
2025                 break;
2026         default:
2027                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2028                 break;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static const struct snd_soc_dai_ops wcd934x_dai_ops = {
2035         .hw_params = wcd934x_hw_params,
2036         .hw_free = wcd934x_hw_free,
2037         .trigger = wcd934x_trigger,
2038         .set_channel_map = wcd934x_set_channel_map,
2039         .get_channel_map = wcd934x_get_channel_map,
2040 };
2041
2042 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
2043         [0] = {
2044                 .name = "wcd934x_rx1",
2045                 .id = AIF1_PB,
2046                 .playback = {
2047                         .stream_name = "AIF1 Playback",
2048                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2049                         .formats = WCD934X_FORMATS_S16_S24_LE,
2050                         .rate_max = 192000,
2051                         .rate_min = 8000,
2052                         .channels_min = 1,
2053                         .channels_max = 2,
2054                 },
2055                 .ops = &wcd934x_dai_ops,
2056         },
2057         [1] = {
2058                 .name = "wcd934x_tx1",
2059                 .id = AIF1_CAP,
2060                 .capture = {
2061                         .stream_name = "AIF1 Capture",
2062                         .rates = WCD934X_RATES_MASK,
2063                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2064                         .rate_min = 8000,
2065                         .rate_max = 192000,
2066                         .channels_min = 1,
2067                         .channels_max = 4,
2068                 },
2069                 .ops = &wcd934x_dai_ops,
2070         },
2071         [2] = {
2072                 .name = "wcd934x_rx2",
2073                 .id = AIF2_PB,
2074                 .playback = {
2075                         .stream_name = "AIF2 Playback",
2076                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2077                         .formats = WCD934X_FORMATS_S16_S24_LE,
2078                         .rate_min = 8000,
2079                         .rate_max = 192000,
2080                         .channels_min = 1,
2081                         .channels_max = 2,
2082                 },
2083                 .ops = &wcd934x_dai_ops,
2084         },
2085         [3] = {
2086                 .name = "wcd934x_tx2",
2087                 .id = AIF2_CAP,
2088                 .capture = {
2089                         .stream_name = "AIF2 Capture",
2090                         .rates = WCD934X_RATES_MASK,
2091                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2092                         .rate_min = 8000,
2093                         .rate_max = 192000,
2094                         .channels_min = 1,
2095                         .channels_max = 4,
2096                 },
2097                 .ops = &wcd934x_dai_ops,
2098         },
2099         [4] = {
2100                 .name = "wcd934x_rx3",
2101                 .id = AIF3_PB,
2102                 .playback = {
2103                         .stream_name = "AIF3 Playback",
2104                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2105                         .formats = WCD934X_FORMATS_S16_S24_LE,
2106                         .rate_min = 8000,
2107                         .rate_max = 192000,
2108                         .channels_min = 1,
2109                         .channels_max = 2,
2110                 },
2111                 .ops = &wcd934x_dai_ops,
2112         },
2113         [5] = {
2114                 .name = "wcd934x_tx3",
2115                 .id = AIF3_CAP,
2116                 .capture = {
2117                         .stream_name = "AIF3 Capture",
2118                         .rates = WCD934X_RATES_MASK,
2119                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2120                         .rate_min = 8000,
2121                         .rate_max = 192000,
2122                         .channels_min = 1,
2123                         .channels_max = 4,
2124                 },
2125                 .ops = &wcd934x_dai_ops,
2126         },
2127         [6] = {
2128                 .name = "wcd934x_rx4",
2129                 .id = AIF4_PB,
2130                 .playback = {
2131                         .stream_name = "AIF4 Playback",
2132                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2133                         .formats = WCD934X_FORMATS_S16_S24_LE,
2134                         .rate_min = 8000,
2135                         .rate_max = 192000,
2136                         .channels_min = 1,
2137                         .channels_max = 2,
2138                 },
2139                 .ops = &wcd934x_dai_ops,
2140         },
2141 };
2142
2143 static int swclk_gate_enable(struct clk_hw *hw)
2144 {
2145         return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2146 }
2147
2148 static void swclk_gate_disable(struct clk_hw *hw)
2149 {
2150         wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2151 }
2152
2153 static int swclk_gate_is_enabled(struct clk_hw *hw)
2154 {
2155         struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2156         int ret, val;
2157
2158         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2159         ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2160
2161         return ret;
2162 }
2163
2164 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2165                                        unsigned long parent_rate)
2166 {
2167         return parent_rate / 2;
2168 }
2169
2170 static const struct clk_ops swclk_gate_ops = {
2171         .prepare = swclk_gate_enable,
2172         .unprepare = swclk_gate_disable,
2173         .is_enabled = swclk_gate_is_enabled,
2174         .recalc_rate = swclk_recalc_rate,
2175
2176 };
2177
2178 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2179 {
2180         struct clk *parent = wcd->extclk;
2181         struct device *dev = wcd->dev;
2182         struct device_node *np = dev->parent->of_node;
2183         const char *parent_clk_name = NULL;
2184         const char *clk_name = "mclk";
2185         struct clk_hw *hw;
2186         struct clk_init_data init;
2187         int ret;
2188
2189         if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2190                 return NULL;
2191
2192         parent_clk_name = __clk_get_name(parent);
2193
2194         of_property_read_string(np, "clock-output-names", &clk_name);
2195
2196         init.name = clk_name;
2197         init.ops = &swclk_gate_ops;
2198         init.flags = 0;
2199         init.parent_names = &parent_clk_name;
2200         init.num_parents = 1;
2201         wcd->hw.init = &init;
2202
2203         hw = &wcd->hw;
2204         ret = devm_clk_hw_register(wcd->dev->parent, hw);
2205         if (ret)
2206                 return ERR_PTR(ret);
2207
2208         ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2209         if (ret)
2210                 return ERR_PTR(ret);
2211
2212         return NULL;
2213 }
2214
2215 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
2216                                    u32 *micb_mv)
2217 {
2218         int mv;
2219
2220         if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2221                 dev_err(dev, "%s value not found, using default\n", micbias);
2222                 mv = WCD934X_DEF_MICBIAS_MV;
2223         } else {
2224                 /* convert it to milli volts */
2225                 mv = mv/1000;
2226         }
2227
2228         if (mv < 1000 || mv > 2850) {
2229                 dev_err(dev, "%s value not in valid range, using default\n",
2230                         micbias);
2231                 mv = WCD934X_DEF_MICBIAS_MV;
2232         }
2233
2234         *micb_mv = mv;
2235
2236         return (mv - 1000) / 50;
2237 }
2238
2239 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2240 {
2241         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2242         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2243         u32 def_dmic_rate, dmic_clk_drv;
2244
2245         vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2246                                              "qcom,micbias1-microvolt",
2247                                              &wcd->micb1_mv);
2248         vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2249                                              "qcom,micbias2-microvolt",
2250                                              &wcd->micb2_mv);
2251         vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2252                                              "qcom,micbias3-microvolt",
2253                                              &wcd->micb3_mv);
2254         vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2255                                              "qcom,micbias4-microvolt",
2256                                              &wcd->micb4_mv);
2257
2258         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2259                                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
2260         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2261                                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
2262         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2263                                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
2264         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2265                                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
2266
2267         if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2268                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2269         else
2270                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2271
2272         wcd->dmic_sample_rate = def_dmic_rate;
2273
2274         dmic_clk_drv = 0;
2275         snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2276                                       0x0C, dmic_clk_drv << 2);
2277
2278         return 0;
2279 }
2280
2281 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2282 {
2283         struct regmap *rm = wcd->regmap;
2284
2285         /* set SPKR rate to FS_2P4_3P072 */
2286         regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2287         regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2288
2289         /* Take DMICs out of reset */
2290         regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2291 }
2292
2293 static int wcd934x_comp_init(struct snd_soc_component *component)
2294 {
2295         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2296
2297         wcd934x_hw_init(wcd);
2298         wcd934x_enable_efuse_sensing(wcd);
2299         wcd934x_get_version(wcd);
2300
2301         return 0;
2302 }
2303
2304 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2305 {
2306         struct wcd934x_codec *wcd = data;
2307         unsigned long status = 0;
2308         int i, j, port_id;
2309         unsigned int val, int_val = 0;
2310         irqreturn_t ret = IRQ_NONE;
2311         bool tx;
2312         unsigned short reg = 0;
2313
2314         for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2315              i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2316                 regmap_read(wcd->if_regmap, i, &val);
2317                 status |= ((u32)val << (8 * j));
2318         }
2319
2320         for_each_set_bit(j, &status, 32) {
2321                 tx = false;
2322                 port_id = j;
2323
2324                 if (j >= 16) {
2325                         tx = true;
2326                         port_id = j - 16;
2327                 }
2328
2329                 regmap_read(wcd->if_regmap,
2330                             WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2331                 if (val) {
2332                         if (!tx)
2333                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2334                                         (port_id / 8);
2335                         else
2336                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2337                                         (port_id / 8);
2338                         regmap_read(wcd->if_regmap, reg, &int_val);
2339                 }
2340
2341                 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2342                         dev_err_ratelimited(wcd->dev,
2343                                             "overflow error on %s port %d, value %x\n",
2344                                             (tx ? "TX" : "RX"), port_id, val);
2345
2346                 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2347                         dev_err_ratelimited(wcd->dev,
2348                                             "underflow error on %s port %d, value %x\n",
2349                                             (tx ? "TX" : "RX"), port_id, val);
2350
2351                 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2352                     (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2353                         if (!tx)
2354                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2355                                         (port_id / 8);
2356                         else
2357                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2358                                         (port_id / 8);
2359                         regmap_read(
2360                                 wcd->if_regmap, reg, &int_val);
2361                         if (int_val & (1 << (port_id % 8))) {
2362                                 int_val = int_val ^ (1 << (port_id % 8));
2363                                 regmap_write(wcd->if_regmap,
2364                                              reg, int_val);
2365                         }
2366                 }
2367
2368                 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2369                         dev_err_ratelimited(wcd->dev,
2370                                             "Port Closed %s port %d, value %x\n",
2371                                             (tx ? "TX" : "RX"), port_id, val);
2372
2373                 regmap_write(wcd->if_regmap,
2374                              WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2375                                 BIT(j % 8));
2376                 ret = IRQ_HANDLED;
2377         }
2378
2379         return ret;
2380 }
2381
2382 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
2383                                    bool enable)
2384 {
2385         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
2386                                       WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
2387 }
2388
2389 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2390                                            bool enable)
2391 {
2392         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
2393                                       WCD934X_ANA_MBHC_BIAS_EN, enable);
2394 }
2395
2396 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
2397                                          int *btn_low, int *btn_high,
2398                                          int num_btn, bool is_micbias)
2399 {
2400         int i, vth;
2401
2402         if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2403                 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2404                         __func__, num_btn);
2405                 return;
2406         }
2407
2408         for (i = 0; i < num_btn; i++) {
2409                 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2410                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
2411                                            WCD934X_MBHC_BTN_VTH_MASK, vth);
2412         }
2413 }
2414
2415 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2416 {
2417         u8 val;
2418
2419         if (micb_num == MIC_BIAS_2) {
2420                 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2421                                                    WCD934X_ANA_MICB2_ENABLE_MASK);
2422                 if (val == WCD934X_MICB_ENABLE)
2423                         return true;
2424         }
2425         return false;
2426 }
2427
2428 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2429                                                enum mbhc_hs_pullup_iref pull_up_cur)
2430 {
2431         /* Default pull up current to 2uA */
2432         if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
2433             pull_up_cur == I_DEFAULT)
2434                 pull_up_cur = I_2P0_UA;
2435
2436
2437         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
2438                                       WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
2439 }
2440
2441 static int wcd934x_micbias_control(struct snd_soc_component *component,
2442                             int micb_num, int req, bool is_dapm)
2443 {
2444         struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2445         int micb_index = micb_num - 1;
2446         u16 micb_reg;
2447
2448         switch (micb_num) {
2449         case MIC_BIAS_1:
2450                 micb_reg = WCD934X_ANA_MICB1;
2451                 break;
2452         case MIC_BIAS_2:
2453                 micb_reg = WCD934X_ANA_MICB2;
2454                 break;
2455         case MIC_BIAS_3:
2456                 micb_reg = WCD934X_ANA_MICB3;
2457                 break;
2458         case MIC_BIAS_4:
2459                 micb_reg = WCD934X_ANA_MICB4;
2460                 break;
2461         default:
2462                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2463                         __func__, micb_num);
2464                 return -EINVAL;
2465         }
2466         mutex_lock(&wcd934x->micb_lock);
2467
2468         switch (req) {
2469         case MICB_PULLUP_ENABLE:
2470                 wcd934x->pullup_ref[micb_index]++;
2471                 if ((wcd934x->pullup_ref[micb_index] == 1) &&
2472                     (wcd934x->micb_ref[micb_index] == 0))
2473                         snd_soc_component_write_field(component, micb_reg,
2474                                                       WCD934X_ANA_MICB_EN_MASK,
2475                                                       WCD934X_MICB_PULL_UP);
2476                 break;
2477         case MICB_PULLUP_DISABLE:
2478                 if (wcd934x->pullup_ref[micb_index] > 0)
2479                         wcd934x->pullup_ref[micb_index]--;
2480
2481                 if ((wcd934x->pullup_ref[micb_index] == 0) &&
2482                     (wcd934x->micb_ref[micb_index] == 0))
2483                         snd_soc_component_write_field(component, micb_reg,
2484                                                       WCD934X_ANA_MICB_EN_MASK, 0);
2485                 break;
2486         case MICB_ENABLE:
2487                 wcd934x->micb_ref[micb_index]++;
2488                 if (wcd934x->micb_ref[micb_index] == 1) {
2489                         snd_soc_component_write_field(component, micb_reg,
2490                                                       WCD934X_ANA_MICB_EN_MASK,
2491                                                       WCD934X_MICB_ENABLE);
2492                         if (micb_num  == MIC_BIAS_2)
2493                                 wcd_mbhc_event_notify(wcd934x->mbhc,
2494                                                       WCD_EVENT_POST_MICBIAS_2_ON);
2495                 }
2496
2497                 if (micb_num  == MIC_BIAS_2 && is_dapm)
2498                         wcd_mbhc_event_notify(wcd934x->mbhc,
2499                                               WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2500                 break;
2501         case MICB_DISABLE:
2502                 if (wcd934x->micb_ref[micb_index] > 0)
2503                         wcd934x->micb_ref[micb_index]--;
2504
2505                 if ((wcd934x->micb_ref[micb_index] == 0) &&
2506                     (wcd934x->pullup_ref[micb_index] > 0))
2507                         snd_soc_component_write_field(component, micb_reg,
2508                                                       WCD934X_ANA_MICB_EN_MASK,
2509                                                       WCD934X_MICB_PULL_UP);
2510                 else if ((wcd934x->micb_ref[micb_index] == 0) &&
2511                          (wcd934x->pullup_ref[micb_index] == 0)) {
2512                         if (micb_num  == MIC_BIAS_2)
2513                                 wcd_mbhc_event_notify(wcd934x->mbhc,
2514                                                       WCD_EVENT_PRE_MICBIAS_2_OFF);
2515
2516                         snd_soc_component_write_field(component, micb_reg,
2517                                                       WCD934X_ANA_MICB_EN_MASK, 0);
2518                         if (micb_num  == MIC_BIAS_2)
2519                                 wcd_mbhc_event_notify(wcd934x->mbhc,
2520                                                       WCD_EVENT_POST_MICBIAS_2_OFF);
2521                 }
2522                 if (is_dapm && micb_num  == MIC_BIAS_2)
2523                         wcd_mbhc_event_notify(wcd934x->mbhc,
2524                                               WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2525                 break;
2526         }
2527
2528         mutex_unlock(&wcd934x->micb_lock);
2529
2530         return 0;
2531 }
2532
2533 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
2534                                         int micb_num, int req)
2535 {
2536         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2537         int ret;
2538
2539         if (req == MICB_ENABLE)
2540                 __wcd934x_cdc_mclk_enable(wcd, true);
2541
2542         ret = wcd934x_micbias_control(component, micb_num, req, false);
2543
2544         if (req == MICB_DISABLE)
2545                 __wcd934x_cdc_mclk_enable(wcd, false);
2546
2547         return ret;
2548 }
2549
2550 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2551                                            bool enable)
2552 {
2553         if (enable) {
2554                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2555                                     WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
2556                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2557                                     WCD934X_RAMP_EN_MASK, 1);
2558         } else {
2559                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2560                                     WCD934X_RAMP_EN_MASK, 0);
2561                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2562                                     WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
2563         }
2564 }
2565
2566 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
2567 {
2568         /* min micbias voltage is 1V and maximum is 2.85V */
2569         if (micb_mv < 1000 || micb_mv > 2850)
2570                 return -EINVAL;
2571
2572         return (micb_mv - 1000) / 50;
2573 }
2574
2575 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
2576                                             int req_volt, int micb_num)
2577 {
2578         struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2579         int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
2580
2581         switch (micb_num) {
2582         case MIC_BIAS_1:
2583                 micb_reg = WCD934X_ANA_MICB1;
2584                 break;
2585         case MIC_BIAS_2:
2586                 micb_reg = WCD934X_ANA_MICB2;
2587                 break;
2588         case MIC_BIAS_3:
2589                 micb_reg = WCD934X_ANA_MICB3;
2590                 break;
2591         case MIC_BIAS_4:
2592                 micb_reg = WCD934X_ANA_MICB4;
2593                 break;
2594         default:
2595                 return -EINVAL;
2596         }
2597         mutex_lock(&wcd934x->micb_lock);
2598         /*
2599          * If requested micbias voltage is same as current micbias
2600          * voltage, then just return. Otherwise, adjust voltage as
2601          * per requested value. If micbias is already enabled, then
2602          * to avoid slow micbias ramp-up or down enable pull-up
2603          * momentarily, change the micbias value and then re-enable
2604          * micbias.
2605          */
2606         micb_en = snd_soc_component_read_field(component, micb_reg,
2607                                                 WCD934X_ANA_MICB_EN_MASK);
2608         cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2609                                                     WCD934X_MICB_VAL_MASK);
2610
2611         req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
2612         if (req_vout_ctl < 0) {
2613                 ret = -EINVAL;
2614                 goto exit;
2615         }
2616
2617         if (cur_vout_ctl == req_vout_ctl) {
2618                 ret = 0;
2619                 goto exit;
2620         }
2621
2622         if (micb_en == WCD934X_MICB_ENABLE)
2623                 snd_soc_component_write_field(component, micb_reg,
2624                                               WCD934X_ANA_MICB_EN_MASK,
2625                                               WCD934X_MICB_PULL_UP);
2626
2627         snd_soc_component_write_field(component, micb_reg,
2628                                       WCD934X_MICB_VAL_MASK,
2629                                       req_vout_ctl);
2630
2631         if (micb_en == WCD934X_MICB_ENABLE) {
2632                 snd_soc_component_write_field(component, micb_reg,
2633                                               WCD934X_ANA_MICB_EN_MASK,
2634                                               WCD934X_MICB_ENABLE);
2635                 /*
2636                  * Add 2ms delay as per HW requirement after enabling
2637                  * micbias
2638                  */
2639                 usleep_range(2000, 2100);
2640         }
2641 exit:
2642         mutex_unlock(&wcd934x->micb_lock);
2643         return ret;
2644 }
2645
2646 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2647                                                 int micb_num, bool req_en)
2648 {
2649         struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2650         int rc, micb_mv;
2651
2652         if (micb_num != MIC_BIAS_2)
2653                 return -EINVAL;
2654         /*
2655          * If device tree micbias level is already above the minimum
2656          * voltage needed to detect threshold microphone, then do
2657          * not change the micbias, just return.
2658          */
2659         if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2660                 return 0;
2661
2662         micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
2663
2664         rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2665
2666         return rc;
2667 }
2668
2669 static inline void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
2670                                                 s16 *d1_a, u16 noff,
2671                                                 int32_t *zdet)
2672 {
2673         int i;
2674         int val, val1;
2675         s16 c1;
2676         s32 x1, d1;
2677         int32_t denom;
2678         int minCode_param[] = {
2679                         3277, 1639, 820, 410, 205, 103, 52, 26
2680         };
2681
2682         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
2683         for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
2684                 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2685                 if (val & 0x80)
2686                         break;
2687         }
2688         val = val << 0x8;
2689         regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
2690         val |= val1;
2691         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
2692         x1 = WCD934X_MBHC_GET_X1(val);
2693         c1 = WCD934X_MBHC_GET_C1(val);
2694         /* If ramp is not complete, give additional 5ms */
2695         if ((c1 < 2) && x1)
2696                 usleep_range(5000, 5050);
2697
2698         if (!c1 || !x1) {
2699                 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2700                         __func__, c1, x1);
2701                 goto ramp_down;
2702         }
2703         d1 = d1_a[c1];
2704         denom = (x1 * d1) - (1 << (14 - noff));
2705         if (denom > 0)
2706                 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
2707         else if (x1 < minCode_param[noff])
2708                 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
2709
2710         dev_info(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2711                 __func__, d1, c1, x1, *zdet);
2712 ramp_down:
2713         i = 0;
2714
2715         while (x1) {
2716                 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2717                 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
2718                 val = val << 0x08;
2719                 val |= val1;
2720                 x1 = WCD934X_MBHC_GET_X1(val);
2721                 i++;
2722                 if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
2723                         break;
2724         }
2725 }
2726
2727 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
2728                                  struct wcd934x_mbhc_zdet_param *zdet_param,
2729                                  int32_t *zl, int32_t *zr, s16 *d1_a)
2730 {
2731         struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2732         int32_t zdet = 0;
2733
2734         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2735                                 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2736         snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
2737                                     WCD934X_VTH_MASK, zdet_param->btn5);
2738         snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
2739                                       WCD934X_VTH_MASK, zdet_param->btn6);
2740         snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
2741                                      WCD934X_VTH_MASK, zdet_param->btn7);
2742         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2743                                 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2744         snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
2745                                 0x0F, zdet_param->nshift);
2746
2747         if (!zl)
2748                 goto z_right;
2749         /* Start impedance measurement for HPH_L */
2750         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
2751         wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2752         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
2753
2754         *zl = zdet;
2755
2756 z_right:
2757         if (!zr)
2758                 return;
2759         /* Start impedance measurement for HPH_R */
2760         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
2761         wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2762         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
2763
2764         *zr = zdet;
2765 }
2766
2767 static inline void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2768                                               int32_t *z_val, int flag_l_r)
2769 {
2770         s16 q1;
2771         int q1_cal;
2772
2773         if (*z_val < (WCD934X_ZDET_VAL_400/1000))
2774                 q1 = snd_soc_component_read(component,
2775                         WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
2776         else
2777                 q1 = snd_soc_component_read(component,
2778                         WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
2779         if (q1 & 0x80)
2780                 q1_cal = (10000 - ((q1 & 0x7F) * 25));
2781         else
2782                 q1_cal = (10000 + (q1 * 25));
2783         if (q1_cal > 0)
2784                 *z_val = ((*z_val) * 10000) / q1_cal;
2785 }
2786
2787 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2788                                             uint32_t *zl, uint32_t *zr)
2789 {
2790         struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2791         s16 reg0, reg1, reg2, reg3, reg4;
2792         int32_t z1L, z1R, z1Ls;
2793         int zMono, z_diff1, z_diff2;
2794         bool is_fsm_disable = false;
2795         struct wcd934x_mbhc_zdet_param zdet_param[] = {
2796                 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2797                 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2798                 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2799                 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2800         };
2801         struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
2802         s16 d1_a[][4] = {
2803                 {0, 30, 90, 30},
2804                 {0, 30, 30, 5},
2805                 {0, 30, 30, 5},
2806                 {0, 30, 30, 5},
2807         };
2808         s16 *d1 = NULL;
2809
2810         reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
2811         reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2812         reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
2813         reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
2814         reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
2815
2816         if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
2817                 is_fsm_disable = true;
2818                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
2819         }
2820
2821         /* For NO-jack, disable L_DET_EN before Z-det measurements */
2822         if (wcd934x->mbhc_cfg.hphl_swh)
2823                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
2824
2825         /* Turn off 100k pull down on HPHL */
2826         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
2827
2828         /* First get impedance on Left */
2829         d1 = d1_a[1];
2830         zdet_param_ptr = &zdet_param[1];
2831         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2832
2833         if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2834                 goto left_ch_impedance;
2835
2836         /* Second ramp for left ch */
2837         if (z1L < WCD934X_ZDET_VAL_32) {
2838                 zdet_param_ptr = &zdet_param[0];
2839                 d1 = d1_a[0];
2840         } else if ((z1L > WCD934X_ZDET_VAL_400) &&
2841                   (z1L <= WCD934X_ZDET_VAL_1200)) {
2842                 zdet_param_ptr = &zdet_param[2];
2843                 d1 = d1_a[2];
2844         } else if (z1L > WCD934X_ZDET_VAL_1200) {
2845                 zdet_param_ptr = &zdet_param[3];
2846                 d1 = d1_a[3];
2847         }
2848         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2849
2850 left_ch_impedance:
2851         if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2852                 (z1L > WCD934X_ZDET_VAL_100K)) {
2853                 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
2854                 zdet_param_ptr = &zdet_param[1];
2855                 d1 = d1_a[1];
2856         } else {
2857                 *zl = z1L/1000;
2858                 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
2859         }
2860         dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2861                 __func__, *zl);
2862
2863         /* Start of right impedance ramp and calculation */
2864         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2865         if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2866                 if (((z1R > WCD934X_ZDET_VAL_1200) &&
2867                         (zdet_param_ptr->noff == 0x6)) ||
2868                         ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
2869                         goto right_ch_impedance;
2870                 /* Second ramp for right ch */
2871                 if (z1R < WCD934X_ZDET_VAL_32) {
2872                         zdet_param_ptr = &zdet_param[0];
2873                         d1 = d1_a[0];
2874                 } else if ((z1R > WCD934X_ZDET_VAL_400) &&
2875                         (z1R <= WCD934X_ZDET_VAL_1200)) {
2876                         zdet_param_ptr = &zdet_param[2];
2877                         d1 = d1_a[2];
2878                 } else if (z1R > WCD934X_ZDET_VAL_1200) {
2879                         zdet_param_ptr = &zdet_param[3];
2880                         d1 = d1_a[3];
2881                 }
2882                 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2883         }
2884 right_ch_impedance:
2885         if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2886                 (z1R > WCD934X_ZDET_VAL_100K)) {
2887                 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
2888         } else {
2889                 *zr = z1R/1000;
2890                 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
2891         }
2892         dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2893                 __func__, *zr);
2894
2895         /* Mono/stereo detection */
2896         if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
2897                 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
2898                 dev_dbg(component->dev,
2899                         "%s: plug type is invalid or extension cable\n",
2900                         __func__);
2901                 goto zdet_complete;
2902         }
2903         if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2904             (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2905             ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2906             ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2907                 dev_dbg(component->dev,
2908                         "%s: Mono plug type with one ch floating or shorted to GND\n",
2909                         __func__);
2910                 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2911                 goto zdet_complete;
2912         }
2913         snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2914                                       WCD934X_HPHPA_GND_OVR_MASK, 1);
2915         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2916                                       WCD934X_HPHPA_GND_R_MASK, 1);
2917         if (*zl < (WCD934X_ZDET_VAL_32/1000))
2918                 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2919         else
2920                 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2921         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2922                                       WCD934X_HPHPA_GND_R_MASK, 0);
2923         snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2924                                       WCD934X_HPHPA_GND_OVR_MASK, 0);
2925         z1Ls /= 1000;
2926         wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2927         /* Parallel of left Z and 9 ohm pull down resistor */
2928         zMono = ((*zl) * 9) / ((*zl) + 9);
2929         z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2930         z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2931         if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2932                 dev_err(component->dev, "%s: stereo plug type detected\n",
2933                         __func__);
2934                 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
2935         } else {
2936                 dev_err(component->dev, "%s: MONO plug type detected\n",
2937                         __func__);
2938                 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2939         }
2940
2941 zdet_complete:
2942         snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
2943         snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
2944         snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
2945         /* Turn on 100k pull down on HPHL */
2946         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
2947
2948         /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2949         if (wcd934x->mbhc_cfg.hphl_swh)
2950                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
2951
2952         snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2953         snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
2954         if (is_fsm_disable)
2955                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
2956 }
2957
2958 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2959                         bool enable)
2960 {
2961         if (enable) {
2962                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2963                                               WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
2964                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2965                                               WCD934X_MBHC_GND_DET_EN_MASK, 1);
2966         } else {
2967                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2968                                               WCD934X_MBHC_GND_DET_EN_MASK, 0);
2969                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2970                                               WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
2971         }
2972 }
2973
2974 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2975                                           bool enable)
2976 {
2977         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2978                                       WCD934X_HPHPA_GND_R_MASK, enable);
2979         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2980                                       WCD934X_HPHPA_GND_L_MASK, enable);
2981 }
2982
2983 static const struct wcd_mbhc_cb mbhc_cb = {
2984         .clk_setup = wcd934x_mbhc_clk_setup,
2985         .mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
2986         .set_btn_thr = wcd934x_mbhc_program_btn_thr,
2987         .micbias_enable_status = wcd934x_mbhc_micb_en_status,
2988         .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
2989         .mbhc_micbias_control = wcd934x_mbhc_request_micbias,
2990         .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
2991         .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
2992         .compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
2993         .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
2994         .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
2995 };
2996
2997 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
2998                               struct snd_ctl_elem_value *ucontrol)
2999 {
3000         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3001         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3002
3003         ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
3004
3005         return 0;
3006 }
3007
3008 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
3009                                    struct snd_ctl_elem_value *ucontrol)
3010 {
3011         uint32_t zl, zr;
3012         bool hphr;
3013         struct soc_mixer_control *mc;
3014         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3015         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3016
3017         mc = (struct soc_mixer_control *)(kcontrol->private_value);
3018         hphr = mc->shift;
3019         wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
3020         dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
3021         ucontrol->value.integer.value[0] = hphr ? zr : zl;
3022
3023         return 0;
3024 }
3025 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3026         SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
3027                        wcd934x_get_hph_type, NULL),
3028 };
3029
3030 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3031         SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3032                        wcd934x_hph_impedance_get, NULL),
3033         SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3034                        wcd934x_hph_impedance_get, NULL),
3035 };
3036
3037 static int wcd934x_mbhc_init(struct snd_soc_component *component)
3038 {
3039         struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
3040         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3041         struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
3042
3043         intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
3044                                                      WCD934X_IRQ_MBHC_SW_DET);
3045         intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
3046                                                             WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
3047         intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
3048                                                               WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
3049         intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
3050                                                          WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3051         intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
3052                                                          WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
3053         intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
3054                                                      WCD934X_IRQ_HPH_PA_OCPL_FAULT);
3055         intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
3056                                                       WCD934X_IRQ_HPH_PA_OCPR_FAULT);
3057
3058         wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3059         if (IS_ERR(wcd->mbhc)) {
3060                 wcd->mbhc = NULL;
3061                 return -EINVAL;
3062         }
3063
3064         snd_soc_add_component_controls(component, impedance_detect_controls,
3065                                        ARRAY_SIZE(impedance_detect_controls));
3066         snd_soc_add_component_controls(component, hph_type_detect_controls,
3067                                        ARRAY_SIZE(hph_type_detect_controls));
3068
3069         return 0;
3070 }
3071 static int wcd934x_comp_probe(struct snd_soc_component *component)
3072 {
3073         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3074         int i;
3075
3076         snd_soc_component_init_regmap(component, wcd->regmap);
3077         wcd->component = component;
3078
3079         /* Class-H Init*/
3080         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
3081         if (IS_ERR(wcd->clsh_ctrl))
3082                 return PTR_ERR(wcd->clsh_ctrl);
3083
3084         /* Default HPH Mode to Class-H Low HiFi */
3085         wcd->hph_mode = CLS_H_LOHIFI;
3086
3087         wcd934x_comp_init(component);
3088
3089         for (i = 0; i < NUM_CODEC_DAIS; i++)
3090                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
3091
3092         wcd934x_init_dmic(component);
3093
3094         if (wcd934x_mbhc_init(component))
3095                 dev_err(component->dev, "Failed to Initialize MBHC\n");
3096
3097         return 0;
3098 }
3099
3100 static void wcd934x_comp_remove(struct snd_soc_component *comp)
3101 {
3102         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3103
3104         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
3105 }
3106
3107 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
3108                                    int clk_id, int source,
3109                                    unsigned int freq, int dir)
3110 {
3111         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3112         int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3113
3114         wcd->rate = freq;
3115
3116         if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
3117                 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3118
3119         snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
3120                                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
3121                                       val);
3122
3123         return clk_set_rate(wcd->extclk, freq);
3124 }
3125
3126 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
3127                                    int iir_idx, int band_idx, int coeff_idx)
3128 {
3129         u32 value = 0;
3130         int reg, b2_reg;
3131
3132         /* Address does not automatically update if reading */
3133         reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3134         b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3135
3136         snd_soc_component_write(component, reg,
3137                                 ((band_idx * BAND_MAX + coeff_idx) *
3138                                  sizeof(uint32_t)) & 0x7F);
3139
3140         value |= snd_soc_component_read(component, b2_reg);
3141         snd_soc_component_write(component, reg,
3142                                 ((band_idx * BAND_MAX + coeff_idx)
3143                                  * sizeof(uint32_t) + 1) & 0x7F);
3144
3145         value |= (snd_soc_component_read(component, b2_reg) << 8);
3146         snd_soc_component_write(component, reg,
3147                                 ((band_idx * BAND_MAX + coeff_idx)
3148                                  * sizeof(uint32_t) + 2) & 0x7F);
3149
3150         value |= (snd_soc_component_read(component, b2_reg) << 16);
3151         snd_soc_component_write(component, reg,
3152                 ((band_idx * BAND_MAX + coeff_idx)
3153                 * sizeof(uint32_t) + 3) & 0x7F);
3154
3155         /* Mask bits top 2 bits since they are reserved */
3156         value |= (snd_soc_component_read(component, b2_reg) << 24);
3157         return value;
3158 }
3159
3160 static void set_iir_band_coeff(struct snd_soc_component *component,
3161                                int iir_idx, int band_idx, uint32_t value)
3162 {
3163         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3164
3165         snd_soc_component_write(component, reg, (value & 0xFF));
3166         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
3167         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
3168         /* Mask top 2 bits, 7-8 are reserved */
3169         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
3170 }
3171
3172 static int wcd934x_put_iir_band_audio_mixer(
3173                                         struct snd_kcontrol *kcontrol,
3174                                         struct snd_ctl_elem_value *ucontrol)
3175 {
3176         struct snd_soc_component *component =
3177                         snd_soc_kcontrol_component(kcontrol);
3178         struct wcd_iir_filter_ctl *ctl =
3179                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3180         struct soc_bytes_ext *params = &ctl->bytes_ext;
3181         int iir_idx = ctl->iir_idx;
3182         int band_idx = ctl->band_idx;
3183         u32 coeff[BAND_MAX];
3184         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3185
3186         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
3187
3188         /* Mask top bit it is reserved */
3189         /* Updates addr automatically for each B2 write */
3190         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
3191                                                  sizeof(uint32_t)) & 0x7F);
3192
3193         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
3194         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
3195         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
3196         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
3197         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
3198
3199         return 0;
3200 }
3201
3202 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
3203                                     struct snd_ctl_elem_value *ucontrol)
3204 {
3205         struct snd_soc_component *component =
3206                         snd_soc_kcontrol_component(kcontrol);
3207         struct wcd_iir_filter_ctl *ctl =
3208                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3209         struct soc_bytes_ext *params = &ctl->bytes_ext;
3210         int iir_idx = ctl->iir_idx;
3211         int band_idx = ctl->band_idx;
3212         u32 coeff[BAND_MAX];
3213
3214         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
3215         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
3216         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
3217         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
3218         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
3219
3220         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
3221
3222         return 0;
3223 }
3224
3225 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
3226                                    struct snd_ctl_elem_info *ucontrol)
3227 {
3228         struct wcd_iir_filter_ctl *ctl =
3229                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3230         struct soc_bytes_ext *params = &ctl->bytes_ext;
3231
3232         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3233         ucontrol->count = params->max;
3234
3235         return 0;
3236 }
3237
3238 static int wcd934x_compander_get(struct snd_kcontrol *kc,
3239                                  struct snd_ctl_elem_value *ucontrol)
3240 {
3241         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3242         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3243         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3244
3245         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
3246
3247         return 0;
3248 }
3249
3250 static int wcd934x_compander_set(struct snd_kcontrol *kc,
3251                                  struct snd_ctl_elem_value *ucontrol)
3252 {
3253         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3254         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3255         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3256         int value = ucontrol->value.integer.value[0];
3257         int sel;
3258
3259         if (wcd->comp_enabled[comp] == value)
3260                 return 0;
3261
3262         wcd->comp_enabled[comp] = value;
3263         sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
3264                 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
3265
3266         /* Any specific register configuration for compander */
3267         switch (comp) {
3268         case COMPANDER_1:
3269                 /* Set Gain Source Select based on compander enable/disable */
3270                 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
3271                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
3272                                               sel);
3273                 break;
3274         case COMPANDER_2:
3275                 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
3276                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
3277                                               sel);
3278                 break;
3279         case COMPANDER_3:
3280         case COMPANDER_4:
3281         case COMPANDER_7:
3282         case COMPANDER_8:
3283                 break;
3284         default:
3285                 return 0;
3286         }
3287
3288         return 1;
3289 }
3290
3291 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
3292                                    struct snd_ctl_elem_value *ucontrol)
3293 {
3294         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3295         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3296
3297         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
3298
3299         return 0;
3300 }
3301
3302 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
3303                                    struct snd_ctl_elem_value *ucontrol)
3304 {
3305         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3306         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3307         u32 mode_val;
3308
3309         mode_val = ucontrol->value.enumerated.item[0];
3310
3311         if (mode_val == wcd->hph_mode)
3312                 return 0;
3313
3314         if (mode_val == 0) {
3315                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
3316                 mode_val = CLS_H_LOHIFI;
3317         }
3318         wcd->hph_mode = mode_val;
3319
3320         return 1;
3321 }
3322
3323 static int slim_rx_mux_get(struct snd_kcontrol *kc,
3324                            struct snd_ctl_elem_value *ucontrol)
3325 {
3326         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3327         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3328         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3329
3330         ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
3331
3332         return 0;
3333 }
3334
3335 static int slim_rx_mux_to_dai_id(int mux)
3336 {
3337         int aif_id;
3338
3339         switch (mux) {
3340         case 1:
3341                 aif_id = AIF1_PB;
3342                 break;
3343         case 2:
3344                 aif_id = AIF2_PB;
3345                 break;
3346         case 3:
3347                 aif_id = AIF3_PB;
3348                 break;
3349         case 4:
3350                 aif_id = AIF4_PB;
3351                 break;
3352         default:
3353                 aif_id = -1;
3354                 break;
3355         }
3356
3357         return aif_id;
3358 }
3359
3360 static int slim_rx_mux_put(struct snd_kcontrol *kc,
3361                            struct snd_ctl_elem_value *ucontrol)
3362 {
3363         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3364         struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
3365         struct soc_enum *e = (struct soc_enum *)kc->private_value;
3366         struct snd_soc_dapm_update *update = NULL;
3367         struct wcd934x_slim_ch *ch, *c;
3368         u32 port_id = w->shift;
3369         bool found = false;
3370         int mux_idx;
3371         int prev_mux_idx = wcd->rx_port_value[port_id];
3372         int aif_id;
3373
3374         mux_idx = ucontrol->value.enumerated.item[0];
3375
3376         if (mux_idx == prev_mux_idx)
3377                 return 0;
3378
3379         switch(mux_idx) {
3380         case 0:
3381                 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
3382                 if (aif_id < 0)
3383                         return 0;
3384
3385                 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
3386                         if (ch->port == port_id + WCD934X_RX_START) {
3387                                 found = true;
3388                                 list_del_init(&ch->list);
3389                                 break;
3390                         }
3391                 }
3392                 if (!found)
3393                         return 0;
3394
3395                 break;
3396         case 1 ... 4:
3397                 aif_id = slim_rx_mux_to_dai_id(mux_idx);
3398                 if (aif_id < 0)
3399                         return 0;
3400
3401                 if (list_empty(&wcd->rx_chs[port_id].list)) {
3402                         list_add_tail(&wcd->rx_chs[port_id].list,
3403                                       &wcd->dai[aif_id].slim_ch_list);
3404                 } else {
3405                         dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
3406                         return 0;
3407                 }
3408                 break;
3409
3410         default:
3411                 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
3412                 goto err;
3413         }
3414
3415         wcd->rx_port_value[port_id] = mux_idx;
3416         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
3417                                       e, update);
3418
3419         return 1;
3420 err:
3421         return -EINVAL;
3422 }
3423
3424 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
3425                                        struct snd_ctl_elem_value *ucontrol)
3426 {
3427         struct soc_enum *e = (struct soc_enum *)kc->private_value;
3428         struct snd_soc_component *component;
3429         int reg, val;
3430
3431         component = snd_soc_dapm_kcontrol_component(kc);
3432         val = ucontrol->value.enumerated.item[0];
3433         if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
3434                 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
3435         else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
3436                 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3437         else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
3438                 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3439         else
3440                 return -EINVAL;
3441
3442         /* Set Look Ahead Delay */
3443         if (val)
3444                 snd_soc_component_update_bits(component, reg,
3445                                               WCD934X_RX_DLY_ZN_EN_MASK,
3446                                               WCD934X_RX_DLY_ZN_ENABLE);
3447         else
3448                 snd_soc_component_update_bits(component, reg,
3449                                               WCD934X_RX_DLY_ZN_EN_MASK,
3450                                               WCD934X_RX_DLY_ZN_DISABLE);
3451
3452         return snd_soc_dapm_put_enum_double(kc, ucontrol);
3453 }
3454
3455 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
3456                                 struct snd_ctl_elem_value *ucontrol)
3457 {
3458         struct snd_soc_component *comp;
3459         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3460         unsigned int val;
3461         u16 mic_sel_reg = 0;
3462         u8 mic_sel;
3463
3464         comp = snd_soc_dapm_kcontrol_component(kcontrol);
3465
3466         val = ucontrol->value.enumerated.item[0];
3467         if (val > e->items - 1)
3468                 return -EINVAL;
3469
3470         switch (e->reg) {
3471         case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
3472                 if (e->shift_l == 0)
3473                         mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
3474                 else if (e->shift_l == 2)
3475                         mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
3476                 else if (e->shift_l == 4)
3477                         mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
3478                 break;
3479         case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
3480                 if (e->shift_l == 0)
3481                         mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
3482                 else if (e->shift_l == 2)
3483                         mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
3484                 break;
3485         case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
3486                 if (e->shift_l == 0)
3487                         mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
3488                 else if (e->shift_l == 2)
3489                         mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
3490                 break;
3491         case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
3492                 if (e->shift_l == 0)
3493                         mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
3494                 else if (e->shift_l == 2)
3495                         mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
3496                 break;
3497         default:
3498                 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
3499                         __func__, e->reg);
3500                 return -EINVAL;
3501         }
3502
3503         /* ADC: 0, DMIC: 1 */
3504         mic_sel = val ? 0x0 : 0x1;
3505         if (mic_sel_reg)
3506                 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
3507                                               mic_sel << 7);
3508
3509         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
3510 }
3511
3512 static const struct snd_kcontrol_new rx_int0_2_mux =
3513         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
3514
3515 static const struct snd_kcontrol_new rx_int1_2_mux =
3516         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
3517
3518 static const struct snd_kcontrol_new rx_int2_2_mux =
3519         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
3520
3521 static const struct snd_kcontrol_new rx_int3_2_mux =
3522         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
3523
3524 static const struct snd_kcontrol_new rx_int4_2_mux =
3525         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
3526
3527 static const struct snd_kcontrol_new rx_int7_2_mux =
3528         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
3529
3530 static const struct snd_kcontrol_new rx_int8_2_mux =
3531         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
3532
3533 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
3534         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
3535
3536 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
3537         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
3538
3539 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
3540         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
3541
3542 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
3543         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
3544
3545 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
3546         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
3547
3548 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
3549         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
3550
3551 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
3552         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
3553
3554 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
3555         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
3556
3557 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
3558         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
3559
3560 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
3561         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
3562
3563 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
3564         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
3565
3566 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
3567         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
3568
3569 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
3570         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
3571
3572 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
3573         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
3574
3575 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
3576         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
3577
3578 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
3579         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
3580
3581 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
3582         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
3583
3584 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
3585         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
3586
3587 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
3588         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
3589
3590 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
3591         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
3592
3593 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
3594         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
3595
3596 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
3597         SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
3598
3599 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
3600         SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
3601
3602 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
3603         SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
3604
3605 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
3606         SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
3607
3608 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
3609         SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
3610
3611 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
3612         SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
3613
3614 static const struct snd_kcontrol_new iir0_inp0_mux =
3615         SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
3616 static const struct snd_kcontrol_new iir0_inp1_mux =
3617         SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
3618 static const struct snd_kcontrol_new iir0_inp2_mux =
3619         SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
3620 static const struct snd_kcontrol_new iir0_inp3_mux =
3621         SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
3622
3623 static const struct snd_kcontrol_new iir1_inp0_mux =
3624         SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3625 static const struct snd_kcontrol_new iir1_inp1_mux =
3626         SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3627 static const struct snd_kcontrol_new iir1_inp2_mux =
3628         SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3629 static const struct snd_kcontrol_new iir1_inp3_mux =
3630         SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3631
3632 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
3633         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
3634                           slim_rx_mux_get, slim_rx_mux_put),
3635         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
3636                           slim_rx_mux_get, slim_rx_mux_put),
3637         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
3638                           slim_rx_mux_get, slim_rx_mux_put),
3639         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
3640                           slim_rx_mux_get, slim_rx_mux_put),
3641         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
3642                           slim_rx_mux_get, slim_rx_mux_put),
3643         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
3644                           slim_rx_mux_get, slim_rx_mux_put),
3645         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
3646                           slim_rx_mux_get, slim_rx_mux_put),
3647         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
3648                           slim_rx_mux_get, slim_rx_mux_put),
3649 };
3650
3651 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
3652         SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
3653 };
3654
3655 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
3656         SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
3657 };
3658
3659 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
3660         SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
3661 };
3662
3663 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
3664         SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
3665 };
3666
3667 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
3668         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
3669                           snd_soc_dapm_get_enum_double,
3670                           wcd934x_int_dem_inp_mux_put);
3671
3672 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
3673         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
3674                           snd_soc_dapm_get_enum_double,
3675                           wcd934x_int_dem_inp_mux_put);
3676
3677 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
3678         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
3679                           snd_soc_dapm_get_enum_double,
3680                           wcd934x_int_dem_inp_mux_put);
3681
3682 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
3683         SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
3684
3685 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
3686         SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
3687
3688 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
3689         SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
3690
3691 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
3692         SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
3693
3694 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
3695         SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
3696
3697 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
3698         SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
3699
3700 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
3701         SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
3702
3703 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
3704         SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
3705
3706 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
3707         SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
3708
3709 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
3710         SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
3711
3712 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
3713         SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
3714
3715 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
3716         SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
3717
3718 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
3719         SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
3720
3721 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
3722         SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
3723
3724 static const struct snd_kcontrol_new tx_dmic_mux0 =
3725         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
3726
3727 static const struct snd_kcontrol_new tx_dmic_mux1 =
3728         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
3729
3730 static const struct snd_kcontrol_new tx_dmic_mux2 =
3731         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
3732
3733 static const struct snd_kcontrol_new tx_dmic_mux3 =
3734         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
3735
3736 static const struct snd_kcontrol_new tx_dmic_mux4 =
3737         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
3738
3739 static const struct snd_kcontrol_new tx_dmic_mux5 =
3740         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
3741
3742 static const struct snd_kcontrol_new tx_dmic_mux6 =
3743         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
3744
3745 static const struct snd_kcontrol_new tx_dmic_mux7 =
3746         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
3747
3748 static const struct snd_kcontrol_new tx_dmic_mux8 =
3749         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
3750
3751 static const struct snd_kcontrol_new tx_amic_mux0 =
3752         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
3753
3754 static const struct snd_kcontrol_new tx_amic_mux1 =
3755         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
3756
3757 static const struct snd_kcontrol_new tx_amic_mux2 =
3758         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
3759
3760 static const struct snd_kcontrol_new tx_amic_mux3 =
3761         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
3762
3763 static const struct snd_kcontrol_new tx_amic_mux4 =
3764         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
3765
3766 static const struct snd_kcontrol_new tx_amic_mux5 =
3767         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
3768
3769 static const struct snd_kcontrol_new tx_amic_mux6 =
3770         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
3771
3772 static const struct snd_kcontrol_new tx_amic_mux7 =
3773         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
3774
3775 static const struct snd_kcontrol_new tx_amic_mux8 =
3776         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
3777
3778 static const struct snd_kcontrol_new tx_amic4_5 =
3779         SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
3780
3781 static const struct snd_kcontrol_new tx_adc_mux0_mux =
3782         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
3783                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3784 static const struct snd_kcontrol_new tx_adc_mux1_mux =
3785         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
3786                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3787 static const struct snd_kcontrol_new tx_adc_mux2_mux =
3788         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3789                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3790 static const struct snd_kcontrol_new tx_adc_mux3_mux =
3791         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3792                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3793 static const struct snd_kcontrol_new tx_adc_mux4_mux =
3794         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3795                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3796 static const struct snd_kcontrol_new tx_adc_mux5_mux =
3797         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3798                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3799 static const struct snd_kcontrol_new tx_adc_mux6_mux =
3800         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3801                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3802 static const struct snd_kcontrol_new tx_adc_mux7_mux =
3803         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3804                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3805 static const struct snd_kcontrol_new tx_adc_mux8_mux =
3806         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3807                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3808
3809 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3810         SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3811 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3812         SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3813 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3814         SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3815 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3816         SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3817 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3818         SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3819 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3820         SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3821 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3822         SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3823 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3824         SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3825 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3826         SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3827 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3828         SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3829 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3830         SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3831 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3832         SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3833 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3834         SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3835 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3836         SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3837 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3838         SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3839
3840 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3841                              struct snd_ctl_elem_value *ucontrol)
3842 {
3843         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3844         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3845         struct soc_mixer_control *mixer =
3846                         (struct soc_mixer_control *)kc->private_value;
3847         int port_id = mixer->shift;
3848
3849         ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3850
3851         return 0;
3852 }
3853
3854 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3855                              struct snd_ctl_elem_value *ucontrol)
3856 {
3857         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3858         struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3859         struct snd_soc_dapm_update *update = NULL;
3860         struct soc_mixer_control *mixer =
3861                         (struct soc_mixer_control *)kc->private_value;
3862         int enable = ucontrol->value.integer.value[0];
3863         struct wcd934x_slim_ch *ch, *c;
3864         int dai_id = widget->shift;
3865         int port_id = mixer->shift;
3866
3867         /* only add to the list if value not set */
3868         if (enable == wcd->tx_port_value[port_id])
3869                 return 0;
3870
3871         if (enable) {
3872                 if (list_empty(&wcd->tx_chs[port_id].list)) {
3873                         list_add_tail(&wcd->tx_chs[port_id].list,
3874                                       &wcd->dai[dai_id].slim_ch_list);
3875                 } else {
3876                         dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3877                         return 0;
3878                 }
3879          } else {
3880                 bool found = false;
3881
3882                 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3883                         if (ch->port == port_id) {
3884                                 found = true;
3885                                 list_del_init(&wcd->tx_chs[port_id].list);
3886                                 break;
3887                         }
3888                 }
3889                 if (!found)
3890                         return 0;
3891          }
3892
3893         wcd->tx_port_value[port_id] = enable;
3894         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3895
3896         return 1;
3897 }
3898
3899 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3900         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3901                        slim_tx_mixer_get, slim_tx_mixer_put),
3902         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3903                        slim_tx_mixer_get, slim_tx_mixer_put),
3904         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3905                        slim_tx_mixer_get, slim_tx_mixer_put),
3906         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3907                        slim_tx_mixer_get, slim_tx_mixer_put),
3908         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3909                        slim_tx_mixer_get, slim_tx_mixer_put),
3910         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3911                        slim_tx_mixer_get, slim_tx_mixer_put),
3912         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3913                        slim_tx_mixer_get, slim_tx_mixer_put),
3914         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3915                        slim_tx_mixer_get, slim_tx_mixer_put),
3916         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3917                        slim_tx_mixer_get, slim_tx_mixer_put),
3918         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3919                        slim_tx_mixer_get, slim_tx_mixer_put),
3920         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3921                        slim_tx_mixer_get, slim_tx_mixer_put),
3922         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3923                        slim_tx_mixer_get, slim_tx_mixer_put),
3924         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3925                        slim_tx_mixer_get, slim_tx_mixer_put),
3926 };
3927
3928 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3929         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3930                        slim_tx_mixer_get, slim_tx_mixer_put),
3931         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3932                        slim_tx_mixer_get, slim_tx_mixer_put),
3933         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3934                        slim_tx_mixer_get, slim_tx_mixer_put),
3935         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3936                        slim_tx_mixer_get, slim_tx_mixer_put),
3937         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3938                        slim_tx_mixer_get, slim_tx_mixer_put),
3939         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3940                        slim_tx_mixer_get, slim_tx_mixer_put),
3941         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3942                        slim_tx_mixer_get, slim_tx_mixer_put),
3943         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3944                        slim_tx_mixer_get, slim_tx_mixer_put),
3945         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3946                        slim_tx_mixer_get, slim_tx_mixer_put),
3947         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3948                        slim_tx_mixer_get, slim_tx_mixer_put),
3949         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3950                        slim_tx_mixer_get, slim_tx_mixer_put),
3951         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3952                        slim_tx_mixer_get, slim_tx_mixer_put),
3953         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3954                        slim_tx_mixer_get, slim_tx_mixer_put),
3955 };
3956
3957 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3958         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3959                        slim_tx_mixer_get, slim_tx_mixer_put),
3960         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3961                        slim_tx_mixer_get, slim_tx_mixer_put),
3962         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3963                        slim_tx_mixer_get, slim_tx_mixer_put),
3964         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3965                        slim_tx_mixer_get, slim_tx_mixer_put),
3966         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3967                        slim_tx_mixer_get, slim_tx_mixer_put),
3968         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3969                        slim_tx_mixer_get, slim_tx_mixer_put),
3970         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3971                        slim_tx_mixer_get, slim_tx_mixer_put),
3972         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3973                        slim_tx_mixer_get, slim_tx_mixer_put),
3974         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3975                        slim_tx_mixer_get, slim_tx_mixer_put),
3976         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3977                        slim_tx_mixer_get, slim_tx_mixer_put),
3978         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3979                        slim_tx_mixer_get, slim_tx_mixer_put),
3980         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3981                        slim_tx_mixer_get, slim_tx_mixer_put),
3982         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3983                        slim_tx_mixer_get, slim_tx_mixer_put),
3984 };
3985
3986 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3987         /* Gain Controls */
3988         SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3989         SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3990         SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3991         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3992                        3, 16, 1, line_gain),
3993         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3994                        3, 16, 1, line_gain),
3995
3996         SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3997         SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3998         SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3999         SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
4000
4001         SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
4002                           -84, 40, digital_gain), /* -84dB min - 40dB max */
4003         SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
4004                           -84, 40, digital_gain),
4005         SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
4006                           -84, 40, digital_gain),
4007         SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
4008                           -84, 40, digital_gain),
4009         SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
4010                           -84, 40, digital_gain),
4011         SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
4012                           -84, 40, digital_gain),
4013         SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
4014                           -84, 40, digital_gain),
4015         SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
4016                           WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
4017                           -84, 40, digital_gain),
4018         SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
4019                           WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
4020                           -84, 40, digital_gain),
4021         SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
4022                           WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
4023                           -84, 40, digital_gain),
4024         SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
4025                           WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
4026                           -84, 40, digital_gain),
4027         SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
4028                           WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
4029                           -84, 40, digital_gain),
4030         SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
4031                           WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
4032                           -84, 40, digital_gain),
4033         SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
4034                           WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
4035                           -84, 40, digital_gain),
4036
4037         SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
4038                           -84, 40, digital_gain),
4039         SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
4040                           -84, 40, digital_gain),
4041         SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
4042                           -84, 40, digital_gain),
4043         SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
4044                           -84, 40, digital_gain),
4045         SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
4046                           -84, 40, digital_gain),
4047         SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
4048                           -84, 40, digital_gain),
4049         SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
4050                           -84, 40, digital_gain),
4051         SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
4052                           -84, 40, digital_gain),
4053         SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
4054                           -84, 40, digital_gain),
4055
4056         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
4057                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
4058                           digital_gain),
4059         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
4060                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
4061                           digital_gain),
4062         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
4063                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
4064                           digital_gain),
4065         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
4066                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
4067                           digital_gain),
4068         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4069                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
4070                           digital_gain),
4071         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4072                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
4073                           digital_gain),
4074         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4075                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
4076                           digital_gain),
4077         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4078                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
4079                           digital_gain),
4080
4081         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
4082         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
4083         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
4084         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
4085         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
4086         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
4087         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
4088         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
4089         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
4090
4091         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
4092         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
4093         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
4094         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
4095         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
4096         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
4097         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
4098         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
4099         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
4100         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
4101         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
4102         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
4103         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
4104         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
4105
4106         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
4107                      wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
4108
4109         SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4110                    0, 1, 0),
4111         SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4112                    1, 1, 0),
4113         SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4114                    2, 1, 0),
4115         SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4116                    3, 1, 0),
4117         SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4118                    4, 1, 0),
4119         SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4120                    0, 1, 0),
4121         SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4122                    1, 1, 0),
4123         SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4124                    2, 1, 0),
4125         SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4126                    3, 1, 0),
4127         SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4128                    4, 1, 0),
4129         WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
4130         WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
4131         WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
4132         WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
4133         WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
4134
4135         WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4136         WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4137         WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4138         WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4139         WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4140
4141         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
4142                        wcd934x_compander_get, wcd934x_compander_set),
4143         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
4144                        wcd934x_compander_get, wcd934x_compander_set),
4145         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
4146                        wcd934x_compander_get, wcd934x_compander_set),
4147         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
4148                        wcd934x_compander_get, wcd934x_compander_set),
4149         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
4150                        wcd934x_compander_get, wcd934x_compander_set),
4151         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
4152                        wcd934x_compander_get, wcd934x_compander_set),
4153 };
4154
4155 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
4156                                           struct snd_soc_component *component)
4157 {
4158         int port_num = 0;
4159         unsigned short reg = 0;
4160         unsigned int val = 0;
4161         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
4162         struct wcd934x_slim_ch *ch;
4163
4164         list_for_each_entry(ch, &dai->slim_ch_list, list) {
4165                 if (ch->port >= WCD934X_RX_START) {
4166                         port_num = ch->port - WCD934X_RX_START;
4167                         reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
4168                 } else {
4169                         port_num = ch->port;
4170                         reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
4171                 }
4172
4173                 regmap_read(wcd->if_regmap, reg, &val);
4174                 if (!(val & BIT(port_num % 8)))
4175                         regmap_write(wcd->if_regmap, reg,
4176                                      val | BIT(port_num % 8));
4177         }
4178 }
4179
4180 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
4181                                      struct snd_kcontrol *kc, int event)
4182 {
4183         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4184         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4185         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
4186
4187         switch (event) {
4188         case SND_SOC_DAPM_POST_PMU:
4189                 wcd934x_codec_enable_int_port(dai, comp);
4190                 break;
4191         }
4192
4193         return 0;
4194 }
4195
4196 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
4197                                       u16 interp_idx, int event)
4198 {
4199         u16 hd2_scale_reg;
4200         u16 hd2_enable_reg = 0;
4201
4202         switch (interp_idx) {
4203         case INTERP_HPHL:
4204                 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
4205                 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
4206                 break;
4207         case INTERP_HPHR:
4208                 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
4209                 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
4210                 break;
4211         default:
4212                 return;
4213         }
4214
4215         if (SND_SOC_DAPM_EVENT_ON(event)) {
4216                 snd_soc_component_update_bits(component, hd2_scale_reg,
4217                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4218                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
4219                 snd_soc_component_update_bits(component, hd2_enable_reg,
4220                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4221                                       WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
4222         }
4223
4224         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4225                 snd_soc_component_update_bits(component, hd2_enable_reg,
4226                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4227                                       WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
4228                 snd_soc_component_update_bits(component, hd2_scale_reg,
4229                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4230                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
4231         }
4232 }
4233
4234 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
4235                                              u16 interp_idx, int event)
4236 {
4237         u8 hph_dly_mask;
4238         u16 hph_lut_bypass_reg = 0;
4239
4240         switch (interp_idx) {
4241         case INTERP_HPHL:
4242                 hph_dly_mask = 1;
4243                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
4244                 break;
4245         case INTERP_HPHR:
4246                 hph_dly_mask = 2;
4247                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
4248                 break;
4249         default:
4250                 return;
4251         }
4252
4253         if (SND_SOC_DAPM_EVENT_ON(event)) {
4254                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4255                                               hph_dly_mask, 0x0);
4256                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4257                                               WCD934X_HPH_LUT_BYPASS_MASK,
4258                                               WCD934X_HPH_LUT_BYPASS_ENABLE);
4259         }
4260
4261         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4262                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4263                                               hph_dly_mask, hph_dly_mask);
4264                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4265                                               WCD934X_HPH_LUT_BYPASS_MASK,
4266                                               WCD934X_HPH_LUT_BYPASS_DISABLE);
4267         }
4268 }
4269
4270 static int wcd934x_config_compander(struct snd_soc_component *comp,
4271                                     int interp_n, int event)
4272 {
4273         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4274         int compander;
4275         u16 comp_ctl0_reg, rx_path_cfg0_reg;
4276
4277         /* EAR does not have compander */
4278         if (!interp_n)
4279                 return 0;
4280
4281         compander = interp_n - 1;
4282         if (!wcd->comp_enabled[compander])
4283                 return 0;
4284
4285         comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
4286         rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
4287
4288         switch (event) {
4289         case SND_SOC_DAPM_PRE_PMU:
4290                 /* Enable Compander Clock */
4291                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4292                                               WCD934X_COMP_CLK_EN_MASK,
4293                                               WCD934X_COMP_CLK_ENABLE);
4294                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4295                                               WCD934X_COMP_SOFT_RST_MASK,
4296                                               WCD934X_COMP_SOFT_RST_ENABLE);
4297                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4298                                               WCD934X_COMP_SOFT_RST_MASK,
4299                                               WCD934X_COMP_SOFT_RST_DISABLE);
4300                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4301                                               WCD934X_HPH_CMP_EN_MASK,
4302                                               WCD934X_HPH_CMP_ENABLE);
4303                 break;
4304         case SND_SOC_DAPM_POST_PMD:
4305                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4306                                               WCD934X_HPH_CMP_EN_MASK,
4307                                               WCD934X_HPH_CMP_DISABLE);
4308                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4309                                               WCD934X_COMP_HALT_MASK,
4310                                               WCD934X_COMP_HALT);
4311                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4312                                               WCD934X_COMP_SOFT_RST_MASK,
4313                                               WCD934X_COMP_SOFT_RST_ENABLE);
4314                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4315                                               WCD934X_COMP_SOFT_RST_MASK,
4316                                               WCD934X_COMP_SOFT_RST_DISABLE);
4317                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4318                                               WCD934X_COMP_CLK_EN_MASK, 0x0);
4319                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4320                                               WCD934X_COMP_SOFT_RST_MASK, 0x0);
4321                 break;
4322         }
4323
4324         return 0;
4325 }
4326
4327 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
4328                                          struct snd_kcontrol *kc, int event)
4329 {
4330         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4331         int interp_idx = w->shift;
4332         u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
4333
4334         switch (event) {
4335         case SND_SOC_DAPM_PRE_PMU:
4336                 /* Clk enable */
4337                 snd_soc_component_update_bits(comp, main_reg,
4338                                              WCD934X_RX_CLK_EN_MASK,
4339                                              WCD934X_RX_CLK_ENABLE);
4340                 wcd934x_codec_hd2_control(comp, interp_idx, event);
4341                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4342                 wcd934x_config_compander(comp, interp_idx, event);
4343                 break;
4344         case SND_SOC_DAPM_POST_PMD:
4345                 wcd934x_config_compander(comp, interp_idx, event);
4346                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4347                 wcd934x_codec_hd2_control(comp, interp_idx, event);
4348                 /* Clk Disable */
4349                 snd_soc_component_update_bits(comp, main_reg,
4350                                              WCD934X_RX_CLK_EN_MASK, 0);
4351                 /* Reset enable and disable */
4352                 snd_soc_component_update_bits(comp, main_reg,
4353                                               WCD934X_RX_RESET_MASK,
4354                                               WCD934X_RX_RESET_ENABLE);
4355                 snd_soc_component_update_bits(comp, main_reg,
4356                                               WCD934X_RX_RESET_MASK,
4357                                               WCD934X_RX_RESET_DISABLE);
4358                 /* Reset rate to 48K*/
4359                 snd_soc_component_update_bits(comp, main_reg,
4360                                               WCD934X_RX_PCM_RATE_MASK,
4361                                               WCD934X_RX_PCM_RATE_F_48K);
4362                 break;
4363         }
4364
4365         return 0;
4366 }
4367
4368 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
4369                                          struct snd_kcontrol *kc, int event)
4370 {
4371         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4372         int offset_val = 0;
4373         u16 gain_reg, mix_reg;
4374         int val = 0;
4375
4376         gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
4377                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4378         mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
4379                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4380
4381         switch (event) {
4382         case SND_SOC_DAPM_PRE_PMU:
4383                 /* Clk enable */
4384                 snd_soc_component_update_bits(comp, mix_reg,
4385                                               WCD934X_CDC_RX_MIX_CLK_EN_MASK,
4386                                               WCD934X_CDC_RX_MIX_CLK_ENABLE);
4387                 break;
4388
4389         case SND_SOC_DAPM_POST_PMU:
4390                 val = snd_soc_component_read(comp, gain_reg);
4391                 val += offset_val;
4392                 snd_soc_component_write(comp, gain_reg, val);
4393                 break;
4394         }
4395
4396         return 0;
4397 }
4398
4399 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
4400                                       struct snd_kcontrol *kcontrol, int event)
4401 {
4402         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4403         int reg = w->reg;
4404
4405         switch (event) {
4406         case SND_SOC_DAPM_POST_PMU:
4407                 /* B1 GAIN */
4408                 snd_soc_component_write(comp, reg,
4409                                         snd_soc_component_read(comp, reg));
4410                 /* B2 GAIN */
4411                 reg++;
4412                 snd_soc_component_write(comp, reg,
4413                                         snd_soc_component_read(comp, reg));
4414                 /* B3 GAIN */
4415                 reg++;
4416                 snd_soc_component_write(comp, reg,
4417                                         snd_soc_component_read(comp, reg));
4418                 /* B4 GAIN */
4419                 reg++;
4420                 snd_soc_component_write(comp, reg,
4421                                         snd_soc_component_read(comp, reg));
4422                 /* B5 GAIN */
4423                 reg++;
4424                 snd_soc_component_write(comp, reg,
4425                                         snd_soc_component_read(comp, reg));
4426                 break;
4427         default:
4428                 break;
4429         }
4430         return 0;
4431 }
4432
4433 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
4434                                           struct snd_kcontrol *kcontrol,
4435                                           int event)
4436 {
4437         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4438         u16 gain_reg;
4439
4440         gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
4441                                                  WCD934X_RX_PATH_CTL_OFFSET);
4442
4443         switch (event) {
4444         case SND_SOC_DAPM_POST_PMU:
4445                 snd_soc_component_write(comp, gain_reg,
4446                                 snd_soc_component_read(comp, gain_reg));
4447                 break;
4448         }
4449
4450         return 0;
4451 }
4452
4453 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4454                                        struct snd_kcontrol *kc, int event)
4455 {
4456         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4457         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4458
4459         switch (event) {
4460         case SND_SOC_DAPM_PRE_PMU:
4461                 /* Disable AutoChop timer during power up */
4462                 snd_soc_component_update_bits(comp,
4463                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4464                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4465                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4466                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4467
4468                 break;
4469         case SND_SOC_DAPM_POST_PMD:
4470                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4471                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4472                 break;
4473         }
4474
4475         return 0;
4476 }
4477
4478 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4479                                         struct snd_kcontrol *kcontrol,
4480                                         int event)
4481 {
4482         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4483         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4484         int hph_mode = wcd->hph_mode;
4485         u8 dem_inp;
4486
4487         switch (event) {
4488         case SND_SOC_DAPM_PRE_PMU:
4489                 /* Read DEM INP Select */
4490                 dem_inp = snd_soc_component_read(comp,
4491                                    WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
4492
4493                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4494                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4495                         return -EINVAL;
4496                 }
4497                 if (hph_mode != CLS_H_LP)
4498                         /* Ripple freq control enable */
4499                         snd_soc_component_update_bits(comp,
4500                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4501                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4502                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4503                 /* Disable AutoChop timer during power up */
4504                 snd_soc_component_update_bits(comp,
4505                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4506                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4507                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4508                                         WCD_CLSH_STATE_HPHL, hph_mode);
4509
4510                 break;
4511         case SND_SOC_DAPM_POST_PMD:
4512                 /* 1000us required as per HW requirement */
4513                 usleep_range(1000, 1100);
4514                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4515                                         WCD_CLSH_STATE_HPHL, hph_mode);
4516                 if (hph_mode != CLS_H_LP)
4517                         /* Ripple freq control disable */
4518                         snd_soc_component_update_bits(comp,
4519                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4520                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4521
4522                 break;
4523         default:
4524                 break;
4525         }
4526
4527         return 0;
4528 }
4529
4530 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4531                                         struct snd_kcontrol *kcontrol,
4532                                         int event)
4533 {
4534         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4535         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4536         int hph_mode = wcd->hph_mode;
4537         u8 dem_inp;
4538
4539         switch (event) {
4540         case SND_SOC_DAPM_PRE_PMU:
4541                 dem_inp = snd_soc_component_read(comp,
4542                                         WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
4543                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4544                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4545                         return -EINVAL;
4546                 }
4547                 if (hph_mode != CLS_H_LP)
4548                         /* Ripple freq control enable */
4549                         snd_soc_component_update_bits(comp,
4550                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4551                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4552                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4553                 /* Disable AutoChop timer during power up */
4554                 snd_soc_component_update_bits(comp,
4555                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4556                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4557                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4558                                         WCD_CLSH_STATE_HPHR,
4559                              hph_mode);
4560                 break;
4561         case SND_SOC_DAPM_POST_PMD:
4562                 /* 1000us required as per HW requirement */
4563                 usleep_range(1000, 1100);
4564
4565                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4566                                         WCD_CLSH_STATE_HPHR, hph_mode);
4567                 if (hph_mode != CLS_H_LP)
4568                         /* Ripple freq control disable */
4569                         snd_soc_component_update_bits(comp,
4570                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4571                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4572                 break;
4573         default:
4574                 break;
4575         }
4576
4577         return 0;
4578 }
4579
4580 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4581                                            struct snd_kcontrol *kc, int event)
4582 {
4583         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4584         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4585
4586         switch (event) {
4587         case SND_SOC_DAPM_PRE_PMU:
4588                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4589                                         WCD_CLSH_STATE_LO, CLS_AB);
4590                 break;
4591         case SND_SOC_DAPM_POST_PMD:
4592                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4593                                         WCD_CLSH_STATE_LO, CLS_AB);
4594                 break;
4595         }
4596
4597         return 0;
4598 }
4599
4600 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4601                                         struct snd_kcontrol *kcontrol,
4602                                         int event)
4603 {
4604         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4605         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4606
4607         switch (event) {
4608         case SND_SOC_DAPM_POST_PMU:
4609                 /*
4610                  * 7ms sleep is required after PA is enabled as per
4611                  * HW requirement. If compander is disabled, then
4612                  * 20ms delay is needed.
4613                  */
4614                 usleep_range(20000, 20100);
4615
4616                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4617                                               WCD934X_HPH_OCP_DET_MASK,
4618                                               WCD934X_HPH_OCP_DET_ENABLE);
4619                 /* Remove Mute on primary path */
4620                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4621                                       WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4622                                       0);
4623                 /* Enable GM3 boost */
4624                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4625                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
4626                                               WCD934X_HPH_GM3_BOOST_ENABLE);
4627                 /* Enable AutoChop timer at the end of power up */
4628                 snd_soc_component_update_bits(comp,
4629                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4630                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4631                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4632                 /* Remove mix path mute */
4633                 snd_soc_component_update_bits(comp,
4634                                 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4635                                 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
4636                 break;
4637         case SND_SOC_DAPM_PRE_PMD:
4638                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4639                 /* Enable DSD Mute before PA disable */
4640                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4641                                               WCD934X_HPH_OCP_DET_MASK,
4642                                               WCD934X_HPH_OCP_DET_DISABLE);
4643                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4644                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4645                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4646                 snd_soc_component_update_bits(comp,
4647                                               WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4648                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4649                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4650                 break;
4651         case SND_SOC_DAPM_POST_PMD:
4652                 /*
4653                  * 5ms sleep is required after PA disable. If compander is
4654                  * disabled, then 20ms delay is needed after PA disable.
4655                  */
4656                 usleep_range(20000, 20100);
4657                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4658                 break;
4659         }
4660
4661         return 0;
4662 }
4663
4664 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4665                                         struct snd_kcontrol *kcontrol,
4666                                         int event)
4667 {
4668         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4669         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4670
4671         switch (event) {
4672         case SND_SOC_DAPM_POST_PMU:
4673                 /*
4674                  * 7ms sleep is required after PA is enabled as per
4675                  * HW requirement. If compander is disabled, then
4676                  * 20ms delay is needed.
4677                  */
4678                 usleep_range(20000, 20100);
4679                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4680                                               WCD934X_HPH_OCP_DET_MASK,
4681                                               WCD934X_HPH_OCP_DET_ENABLE);
4682                 /* Remove mute */
4683                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4684                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4685                                               0);
4686                 /* Enable GM3 boost */
4687                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4688                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
4689                                               WCD934X_HPH_GM3_BOOST_ENABLE);
4690                 /* Enable AutoChop timer at the end of power up */
4691                 snd_soc_component_update_bits(comp,
4692                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4693                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4694                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4695                 /* Remove mix path mute if it is enabled */
4696                 if ((snd_soc_component_read(comp,
4697                                       WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
4698                         snd_soc_component_update_bits(comp,
4699                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4700                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4701                                               WCD934X_CDC_RX_PGA_MUTE_DISABLE);
4702                 break;
4703         case SND_SOC_DAPM_PRE_PMD:
4704                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
4705                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4706                                               WCD934X_HPH_OCP_DET_MASK,
4707                                               WCD934X_HPH_OCP_DET_DISABLE);
4708                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4709                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4710                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4711                 snd_soc_component_update_bits(comp,
4712                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4713                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4714                                               WCD934X_CDC_RX_PGA_MUTE_ENABLE);
4715                 break;
4716         case SND_SOC_DAPM_POST_PMD:
4717                 /*
4718                  * 5ms sleep is required after PA disable. If compander is
4719                  * disabled, then 20ms delay is needed after PA disable.
4720                  */
4721                 usleep_range(20000, 20100);
4722                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
4723                 break;
4724         }
4725
4726         return 0;
4727 }
4728
4729 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
4730                                         unsigned int dmic,
4731                                       struct wcd934x_codec *wcd)
4732 {
4733         u8 tx_stream_fs;
4734         u8 adc_mux_index = 0, adc_mux_sel = 0;
4735         bool dec_found = false;
4736         u16 adc_mux_ctl_reg, tx_fs_reg;
4737         u32 dmic_fs;
4738
4739         while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
4740                 if (adc_mux_index < 4) {
4741                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4742                                                 (adc_mux_index * 2);
4743                 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
4744                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4745                                                 adc_mux_index - 4;
4746                 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
4747                         ++adc_mux_index;
4748                         continue;
4749                 }
4750                 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
4751                                & 0xF8) >> 3) - 1;
4752
4753                 if (adc_mux_sel == dmic) {
4754                         dec_found = true;
4755                         break;
4756                 }
4757
4758                 ++adc_mux_index;
4759         }
4760
4761         if (dec_found && adc_mux_index <= 8) {
4762                 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
4763                 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
4764                 if (tx_stream_fs <= 4)  {
4765                         if (wcd->dmic_sample_rate <=
4766                                         WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
4767                                 dmic_fs = wcd->dmic_sample_rate;
4768                         else
4769                                 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
4770                 } else
4771                         dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
4772         } else {
4773                 dmic_fs = wcd->dmic_sample_rate;
4774         }
4775
4776         return dmic_fs;
4777 }
4778
4779 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
4780                                    u32 mclk_rate, u32 dmic_clk_rate)
4781 {
4782         u32 div_factor;
4783         u8 dmic_ctl_val;
4784
4785         /* Default value to return in case of error */
4786         if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
4787                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4788         else
4789                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4790
4791         if (dmic_clk_rate == 0) {
4792                 dev_err(comp->dev,
4793                         "%s: dmic_sample_rate cannot be 0\n",
4794                         __func__);
4795                 goto done;
4796         }
4797
4798         div_factor = mclk_rate / dmic_clk_rate;
4799         switch (div_factor) {
4800         case 2:
4801                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4802                 break;
4803         case 3:
4804                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4805                 break;
4806         case 4:
4807                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4808                 break;
4809         case 6:
4810                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4811                 break;
4812         case 8:
4813                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4814                 break;
4815         case 16:
4816                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4817                 break;
4818         default:
4819                 dev_err(comp->dev,
4820                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4821                         __func__, div_factor, mclk_rate, dmic_clk_rate);
4822                 break;
4823         }
4824
4825 done:
4826         return dmic_ctl_val;
4827 }
4828
4829 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4830                                      struct snd_kcontrol *kcontrol, int event)
4831 {
4832         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4833         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4834         u8  dmic_clk_en = 0x01;
4835         u16 dmic_clk_reg;
4836         s32 *dmic_clk_cnt;
4837         u8 dmic_rate_val, dmic_rate_shift = 1;
4838         unsigned int dmic;
4839         u32 dmic_sample_rate;
4840         int ret;
4841         char *wname;
4842
4843         wname = strpbrk(w->name, "012345");
4844         if (!wname) {
4845                 dev_err(comp->dev, "%s: widget not found\n", __func__);
4846                 return -EINVAL;
4847         }
4848
4849         ret = kstrtouint(wname, 10, &dmic);
4850         if (ret < 0) {
4851                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4852                         __func__);
4853                 return -EINVAL;
4854         }
4855
4856         switch (dmic) {
4857         case 0:
4858         case 1:
4859                 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4860                 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4861                 break;
4862         case 2:
4863         case 3:
4864                 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4865                 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4866                 break;
4867         case 4:
4868         case 5:
4869                 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4870                 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4871                 break;
4872         default:
4873                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4874                         __func__);
4875                 return -EINVAL;
4876         }
4877
4878         switch (event) {
4879         case SND_SOC_DAPM_PRE_PMU:
4880                 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4881                                                                 wcd);
4882                 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4883                                                          dmic_sample_rate);
4884                 (*dmic_clk_cnt)++;
4885                 if (*dmic_clk_cnt == 1) {
4886                         dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4887                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4888                                                       WCD934X_DMIC_RATE_MASK,
4889                                                       dmic_rate_val);
4890                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4891                                                       dmic_clk_en, dmic_clk_en);
4892                 }
4893
4894                 break;
4895         case SND_SOC_DAPM_POST_PMD:
4896                 (*dmic_clk_cnt)--;
4897                 if (*dmic_clk_cnt == 0)
4898                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4899                                                       dmic_clk_en, 0);
4900                 break;
4901         }
4902
4903         return 0;
4904 }
4905
4906 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4907                                          int adc_mux_n)
4908 {
4909         u16 mask, shift, adc_mux_in_reg;
4910         u16 amic_mux_sel_reg;
4911         bool is_amic;
4912
4913         if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4914             adc_mux_n == WCD934X_INVALID_ADC_MUX)
4915                 return 0;
4916
4917         if (adc_mux_n < 3) {
4918                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4919                                  adc_mux_n;
4920                 mask = 0x03;
4921                 shift = 0;
4922                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4923                                    2 * adc_mux_n;
4924         } else if (adc_mux_n < 4) {
4925                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4926                 mask = 0x03;
4927                 shift = 0;
4928                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4929                                    2 * adc_mux_n;
4930         } else if (adc_mux_n < 7) {
4931                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4932                                  (adc_mux_n - 4);
4933                 mask = 0x0C;
4934                 shift = 2;
4935                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4936                                    adc_mux_n - 4;
4937         } else if (adc_mux_n < 8) {
4938                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4939                 mask = 0x0C;
4940                 shift = 2;
4941                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4942                                    adc_mux_n - 4;
4943         } else if (adc_mux_n < 12) {
4944                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4945                                  ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4946                                   (adc_mux_n - 9));
4947                 mask = 0x30;
4948                 shift = 4;
4949                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4950                                    adc_mux_n - 4;
4951         } else if (adc_mux_n < 13) {
4952                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4953                 mask = 0x30;
4954                 shift = 4;
4955                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4956                                    adc_mux_n - 4;
4957         } else {
4958                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4959                 mask = 0xC0;
4960                 shift = 6;
4961                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4962                                    adc_mux_n - 4;
4963         }
4964
4965         is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4966                      & mask) >> shift) == 1);
4967         if (!is_amic)
4968                 return 0;
4969
4970         return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4971 }
4972
4973 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4974                                             int amic)
4975 {
4976         u16 pwr_level_reg = 0;
4977
4978         switch (amic) {
4979         case 1:
4980         case 2:
4981                 pwr_level_reg = WCD934X_ANA_AMIC1;
4982                 break;
4983
4984         case 3:
4985         case 4:
4986                 pwr_level_reg = WCD934X_ANA_AMIC3;
4987                 break;
4988         default:
4989                 break;
4990         }
4991
4992         return pwr_level_reg;
4993 }
4994
4995 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4996                                     struct snd_kcontrol *kcontrol, int event)
4997 {
4998         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4999         unsigned int decimator;
5000         char *dec_adc_mux_name = NULL;
5001         char *widget_name = NULL;
5002         char *wname;
5003         int ret = 0, amic_n;
5004         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
5005         u16 tx_gain_ctl_reg;
5006         char *dec;
5007         u8 hpf_coff_freq;
5008
5009         widget_name = kstrndup(w->name, 15, GFP_KERNEL);
5010         if (!widget_name)
5011                 return -ENOMEM;
5012
5013         wname = widget_name;
5014         dec_adc_mux_name = strsep(&widget_name, " ");
5015         if (!dec_adc_mux_name) {
5016                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5017                         __func__, w->name);
5018                 ret =  -EINVAL;
5019                 goto out;
5020         }
5021         dec_adc_mux_name = widget_name;
5022
5023         dec = strpbrk(dec_adc_mux_name, "012345678");
5024         if (!dec) {
5025                 dev_err(comp->dev, "%s: decimator index not found\n",
5026                         __func__);
5027                 ret =  -EINVAL;
5028                 goto out;
5029         }
5030
5031         ret = kstrtouint(dec, 10, &decimator);
5032         if (ret < 0) {
5033                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5034                         __func__, wname);
5035                 ret =  -EINVAL;
5036                 goto out;
5037         }
5038
5039         tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
5040         hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
5041         dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5042         tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5043
5044         switch (event) {
5045         case SND_SOC_DAPM_PRE_PMU:
5046                 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
5047                 if (amic_n)
5048                         pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
5049                                                                  amic_n);
5050
5051                 if (!pwr_level_reg)
5052                         break;
5053
5054                 switch ((snd_soc_component_read(comp, pwr_level_reg) &
5055                                       WCD934X_AMIC_PWR_LVL_MASK) >>
5056                                       WCD934X_AMIC_PWR_LVL_SHIFT) {
5057                 case WCD934X_AMIC_PWR_LEVEL_LP:
5058                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5059                                         WCD934X_DEC_PWR_LVL_MASK,
5060                                         WCD934X_DEC_PWR_LVL_LP);
5061                         break;
5062                 case WCD934X_AMIC_PWR_LEVEL_HP:
5063                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5064                                         WCD934X_DEC_PWR_LVL_MASK,
5065                                         WCD934X_DEC_PWR_LVL_HP);
5066                         break;
5067                 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
5068                 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
5069                 default:
5070                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5071                                         WCD934X_DEC_PWR_LVL_MASK,
5072                                         WCD934X_DEC_PWR_LVL_DF);
5073                         break;
5074                 }
5075                 break;
5076         case SND_SOC_DAPM_POST_PMU:
5077                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5078                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5079                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5080                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5081                                                       TX_HPF_CUT_OFF_FREQ_MASK,
5082                                                       CF_MIN_3DB_150HZ << 5);
5083                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5084                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5085                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5086                         /*
5087                          * Minimum 1 clk cycle delay is required as per
5088                          * HW spec.
5089                          */
5090                         usleep_range(1000, 1010);
5091                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5092                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5093                                       0);
5094                 }
5095                 /* apply gain after decimator is enabled */
5096                 snd_soc_component_write(comp, tx_gain_ctl_reg,
5097                                         snd_soc_component_read(comp,
5098                                                          tx_gain_ctl_reg));
5099                 break;
5100         case SND_SOC_DAPM_PRE_PMD:
5101                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5102                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5103
5104                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5105                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5106                                                       TX_HPF_CUT_OFF_FREQ_MASK,
5107                                                       hpf_coff_freq << 5);
5108                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5109                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5110                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5111                                 /*
5112                                  * Minimum 1 clk cycle delay is required as per
5113                                  * HW spec.
5114                                  */
5115                         usleep_range(1000, 1010);
5116                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5117                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5118                                       0);
5119                 }
5120                 break;
5121         case SND_SOC_DAPM_POST_PMD:
5122                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
5123                                               0x10, 0x00);
5124                 snd_soc_component_update_bits(comp, dec_cfg_reg,
5125                                               WCD934X_DEC_PWR_LVL_MASK,
5126                                               WCD934X_DEC_PWR_LVL_DF);
5127                 break;
5128         }
5129 out:
5130         kfree(wname);
5131         return ret;
5132 }
5133
5134 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
5135                                       u16 amic_reg, bool set)
5136 {
5137         u8 mask = 0x20;
5138         u8 val;
5139
5140         if (amic_reg == WCD934X_ANA_AMIC1 ||
5141             amic_reg == WCD934X_ANA_AMIC3)
5142                 mask = 0x40;
5143
5144         val = set ? mask : 0x00;
5145
5146         switch (amic_reg) {
5147         case WCD934X_ANA_AMIC1:
5148         case WCD934X_ANA_AMIC2:
5149                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
5150                                               mask, val);
5151                 break;
5152         case WCD934X_ANA_AMIC3:
5153         case WCD934X_ANA_AMIC4:
5154                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
5155                                               mask, val);
5156                 break;
5157         default:
5158                 break;
5159         }
5160 }
5161
5162 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
5163                                     struct snd_kcontrol *kcontrol, int event)
5164 {
5165         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
5166
5167         switch (event) {
5168         case SND_SOC_DAPM_PRE_PMU:
5169                 wcd934x_codec_set_tx_hold(comp, w->reg, true);
5170                 break;
5171         default:
5172                 break;
5173         }
5174
5175         return 0;
5176 }
5177
5178 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
5179                                         struct snd_kcontrol *kcontrol,
5180                                         int event)
5181 {
5182         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5183         int micb_num = w->shift;
5184
5185         switch (event) {
5186         case SND_SOC_DAPM_PRE_PMU:
5187                 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
5188                 break;
5189         case SND_SOC_DAPM_POST_PMU:
5190                 /* 1 msec delay as per HW requirement */
5191                 usleep_range(1000, 1100);
5192                 break;
5193         case SND_SOC_DAPM_POST_PMD:
5194                 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
5195                 break;
5196         }
5197
5198         return 0;
5199 }
5200
5201 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
5202         /* Analog Outputs */
5203         SND_SOC_DAPM_OUTPUT("EAR"),
5204         SND_SOC_DAPM_OUTPUT("HPHL"),
5205         SND_SOC_DAPM_OUTPUT("HPHR"),
5206         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
5207         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
5208         SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
5209         SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
5210         SND_SOC_DAPM_OUTPUT("ANC EAR"),
5211         SND_SOC_DAPM_OUTPUT("ANC HPHL"),
5212         SND_SOC_DAPM_OUTPUT("ANC HPHR"),
5213         SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
5214         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
5215         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
5216         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
5217                               AIF1_PB, 0, wcd934x_codec_enable_slim,
5218                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5219         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
5220                               AIF2_PB, 0, wcd934x_codec_enable_slim,
5221                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5222         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
5223                               AIF3_PB, 0, wcd934x_codec_enable_slim,
5224                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5225         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
5226                               AIF4_PB, 0, wcd934x_codec_enable_slim,
5227                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5228
5229         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
5230                          &slim_rx_mux[WCD934X_RX0]),
5231         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
5232                          &slim_rx_mux[WCD934X_RX1]),
5233         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
5234                          &slim_rx_mux[WCD934X_RX2]),
5235         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
5236                          &slim_rx_mux[WCD934X_RX3]),
5237         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
5238                          &slim_rx_mux[WCD934X_RX4]),
5239         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
5240                          &slim_rx_mux[WCD934X_RX5]),
5241         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
5242                          &slim_rx_mux[WCD934X_RX6]),
5243         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
5244                          &slim_rx_mux[WCD934X_RX7]),
5245
5246         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5247         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5248         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5249         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5250         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5251         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5252         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5253         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5254
5255         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
5256                            &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
5257                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5258                            SND_SOC_DAPM_POST_PMD),
5259         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
5260                            &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
5261                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5262                            SND_SOC_DAPM_POST_PMD),
5263         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
5264                            &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
5265                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5266                            SND_SOC_DAPM_POST_PMD),
5267         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
5268                            &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
5269                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5270                            SND_SOC_DAPM_POST_PMD),
5271         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
5272                            &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
5273                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5274                            SND_SOC_DAPM_POST_PMD),
5275         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
5276                            &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
5277                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5278                            SND_SOC_DAPM_POST_PMD),
5279         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
5280                            &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
5281                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5282                            SND_SOC_DAPM_POST_PMD),
5283
5284         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5285                          &rx_int0_1_mix_inp0_mux),
5286         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5287                          &rx_int0_1_mix_inp1_mux),
5288         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5289                          &rx_int0_1_mix_inp2_mux),
5290         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5291                          &rx_int1_1_mix_inp0_mux),
5292         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5293                          &rx_int1_1_mix_inp1_mux),
5294         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5295                          &rx_int1_1_mix_inp2_mux),
5296         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5297                          &rx_int2_1_mix_inp0_mux),
5298         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5299                          &rx_int2_1_mix_inp1_mux),
5300         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5301                          &rx_int2_1_mix_inp2_mux),
5302         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5303                          &rx_int3_1_mix_inp0_mux),
5304         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5305                          &rx_int3_1_mix_inp1_mux),
5306         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5307                          &rx_int3_1_mix_inp2_mux),
5308         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5309                          &rx_int4_1_mix_inp0_mux),
5310         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5311                          &rx_int4_1_mix_inp1_mux),
5312         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5313                          &rx_int4_1_mix_inp2_mux),
5314         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5315                            &rx_int7_1_mix_inp0_mux),
5316         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5317                            &rx_int7_1_mix_inp1_mux),
5318         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5319                            &rx_int7_1_mix_inp2_mux),
5320         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5321                            &rx_int8_1_mix_inp0_mux),
5322         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5323                            &rx_int8_1_mix_inp1_mux),
5324         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5325                            &rx_int8_1_mix_inp2_mux),
5326         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5327         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5328         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5329         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
5330                            rx_int1_asrc_switch,
5331                            ARRAY_SIZE(rx_int1_asrc_switch)),
5332         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5333         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
5334                            rx_int2_asrc_switch,
5335                            ARRAY_SIZE(rx_int2_asrc_switch)),
5336         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5337         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
5338                            rx_int3_asrc_switch,
5339                            ARRAY_SIZE(rx_int3_asrc_switch)),
5340         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5341         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
5342                            rx_int4_asrc_switch,
5343                            ARRAY_SIZE(rx_int4_asrc_switch)),
5344         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5345         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5346         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5347         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5348         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5349         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5350         SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5351         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5352         SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5353         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5354         SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5355         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5356         SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5357
5358         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5359         SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
5360                              NULL, 0, NULL, 0),
5361         SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
5362                              NULL, 0, NULL, 0),
5363         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
5364                            0,  &rx_int0_mix2_inp_mux, NULL,
5365                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5366         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
5367                            0, &rx_int1_mix2_inp_mux,  NULL,
5368                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5369         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
5370                            0, &rx_int2_mix2_inp_mux, NULL,
5371                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5372         SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
5373                            0, &rx_int3_mix2_inp_mux, NULL,
5374                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5375         SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
5376                            0, &rx_int4_mix2_inp_mux, NULL,
5377                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5378         SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
5379                            0, &rx_int7_mix2_inp_mux, NULL,
5380                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5381
5382         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
5383         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
5384         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
5385         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
5386         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5387         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5388         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5389         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5390
5391         SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5392                            0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5393                            SND_SOC_DAPM_POST_PMU),
5394         SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5395                            1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5396                            SND_SOC_DAPM_POST_PMU),
5397         SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
5398                            4, 0, NULL, 0),
5399         SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
5400                            4, 0, NULL, 0),
5401         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
5402                          &rx_int0_dem_inp_mux),
5403         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
5404                          &rx_int1_dem_inp_mux),
5405         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
5406                          &rx_int2_dem_inp_mux),
5407
5408         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
5409                            &rx_int0_1_interp_mux,
5410                            wcd934x_codec_enable_main_path,
5411                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5412                            SND_SOC_DAPM_POST_PMD),
5413         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
5414                            &rx_int1_1_interp_mux,
5415                            wcd934x_codec_enable_main_path,
5416                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5417                            SND_SOC_DAPM_POST_PMD),
5418         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
5419                            &rx_int2_1_interp_mux,
5420                            wcd934x_codec_enable_main_path,
5421                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5422                            SND_SOC_DAPM_POST_PMD),
5423         SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
5424                            &rx_int3_1_interp_mux,
5425                            wcd934x_codec_enable_main_path,
5426                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5427                            SND_SOC_DAPM_POST_PMD),
5428         SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
5429                            &rx_int4_1_interp_mux,
5430                            wcd934x_codec_enable_main_path,
5431                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5432                            SND_SOC_DAPM_POST_PMD),
5433         SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
5434                            &rx_int7_1_interp_mux,
5435                            wcd934x_codec_enable_main_path,
5436                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5437                            SND_SOC_DAPM_POST_PMD),
5438         SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
5439                            &rx_int8_1_interp_mux,
5440                            wcd934x_codec_enable_main_path,
5441                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5442                            SND_SOC_DAPM_POST_PMD),
5443
5444         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
5445                          &rx_int0_2_interp_mux),
5446         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
5447                          &rx_int1_2_interp_mux),
5448         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
5449                          &rx_int2_2_interp_mux),
5450         SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
5451                          &rx_int3_2_interp_mux),
5452         SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
5453                          &rx_int4_2_interp_mux),
5454         SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
5455                          &rx_int7_2_interp_mux),
5456         SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
5457                          &rx_int8_2_interp_mux),
5458         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
5459                            0, 0, wcd934x_codec_ear_dac_event,
5460                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5461                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5462         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5463                            5, 0, wcd934x_codec_hphl_dac_event,
5464                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5465                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5466         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
5467                            4, 0, wcd934x_codec_hphr_dac_event,
5468                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5469                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5470         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
5471                            0, 0, wcd934x_codec_lineout_dac_event,
5472                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5473         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
5474                            0, 0, wcd934x_codec_lineout_dac_event,
5475                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5476         SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
5477         SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
5478                            wcd934x_codec_enable_hphl_pa,
5479                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5480                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5481         SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
5482                            wcd934x_codec_enable_hphr_pa,
5483                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5484                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5485         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
5486                            NULL, 0),
5487         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
5488                            NULL, 0),
5489         SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
5490                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5491         SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
5492                          0, 0, NULL, 0),
5493         SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
5494                             0, 0, NULL, 0),
5495         SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
5496                          0, 0, NULL, 0),
5497         SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
5498                             0, 0, NULL, 0),
5499         SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
5500                             wcd934x_codec_enable_interp_clk,
5501                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5502         SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
5503                             wcd934x_codec_enable_interp_clk,
5504                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5505         SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
5506                             wcd934x_codec_enable_interp_clk,
5507                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5508         SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
5509                             wcd934x_codec_enable_interp_clk,
5510                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5511         SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
5512                             wcd934x_codec_enable_interp_clk,
5513                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5514         SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
5515                             wcd934x_codec_enable_interp_clk,
5516                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5517         SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
5518                             wcd934x_codec_enable_interp_clk,
5519                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5520         SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
5521                             0, 0, NULL, 0),
5522         SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
5523                             0, 0, NULL, 0),
5524         SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
5525                             0, 0, NULL, 0),
5526         SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
5527                             0, 0, NULL, 0),
5528         SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
5529                             0, 0, NULL, 0),
5530         SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
5531                             0, 0, NULL, 0),
5532         SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
5533                             0, 0, NULL, 0),
5534         SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
5535                             wcd934x_codec_enable_mclk,
5536                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5537
5538         /* TX */
5539         SND_SOC_DAPM_INPUT("AMIC1"),
5540         SND_SOC_DAPM_INPUT("AMIC2"),
5541         SND_SOC_DAPM_INPUT("AMIC3"),
5542         SND_SOC_DAPM_INPUT("AMIC4"),
5543         SND_SOC_DAPM_INPUT("AMIC5"),
5544         SND_SOC_DAPM_INPUT("DMIC0 Pin"),
5545         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
5546         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
5547         SND_SOC_DAPM_INPUT("DMIC3 Pin"),
5548         SND_SOC_DAPM_INPUT("DMIC4 Pin"),
5549         SND_SOC_DAPM_INPUT("DMIC5 Pin"),
5550
5551         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
5552                                AIF1_CAP, 0, wcd934x_codec_enable_slim,
5553                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5554         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
5555                                AIF2_CAP, 0, wcd934x_codec_enable_slim,
5556                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5557         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
5558                                AIF3_CAP, 0, wcd934x_codec_enable_slim,
5559                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5560
5561         SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5562         SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5563         SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5564         SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5565         SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5566         SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5567         SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5568         SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5569         SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
5570         SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
5571         SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
5572         SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
5573         SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
5574
5575         /* Digital Mic Inputs */
5576         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
5577                            wcd934x_codec_enable_dmic,
5578                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5579         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
5580                            wcd934x_codec_enable_dmic,
5581                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5582         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
5583                            wcd934x_codec_enable_dmic,
5584                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5585         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
5586                            wcd934x_codec_enable_dmic,
5587                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5588         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
5589                            wcd934x_codec_enable_dmic,
5590                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5591         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
5592                            wcd934x_codec_enable_dmic,
5593                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5594         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
5595         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
5596         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
5597         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
5598         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
5599         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
5600         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
5601         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
5602         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
5603         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
5604         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
5605         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
5606         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
5607         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
5608         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
5609         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
5610         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
5611         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
5612         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
5613                            &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
5614                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5615                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5616         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
5617                            &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
5618                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5619                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5620         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
5621                            &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
5622                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5623                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5624         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
5625                            &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
5626                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5627                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5628         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
5629                            &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
5630                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5631                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5632         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
5633                            &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
5634                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5635                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5636         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
5637                            &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
5638                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5639                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5640         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
5641                            &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
5642                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5643                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5644         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
5645                            &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
5646                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5647                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5648         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
5649                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5650         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
5651                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5652         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
5653                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5654         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
5655                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5656         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
5657                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5658                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5659         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
5660                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5661                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5662         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
5663                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5664                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5665         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
5666                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5667                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5668
5669         SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
5670         SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
5671                          &cdc_if_tx0_mux),
5672         SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
5673                          &cdc_if_tx1_mux),
5674         SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
5675                          &cdc_if_tx2_mux),
5676         SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
5677                          &cdc_if_tx3_mux),
5678         SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
5679                          &cdc_if_tx4_mux),
5680         SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
5681                          &cdc_if_tx5_mux),
5682         SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
5683                          &cdc_if_tx6_mux),
5684         SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
5685                          &cdc_if_tx7_mux),
5686         SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
5687                          &cdc_if_tx8_mux),
5688         SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
5689                          &cdc_if_tx9_mux),
5690         SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
5691                          &cdc_if_tx10_mux),
5692         SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5693                          &cdc_if_tx11_mux),
5694         SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5695                          &cdc_if_tx11_inp1_mux),
5696         SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5697                          &cdc_if_tx13_mux),
5698         SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5699                          &cdc_if_tx13_inp1_mux),
5700         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
5701                            aif1_slim_cap_mixer,
5702                            ARRAY_SIZE(aif1_slim_cap_mixer)),
5703         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
5704                            aif2_slim_cap_mixer,
5705                            ARRAY_SIZE(aif2_slim_cap_mixer)),
5706         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
5707                            aif3_slim_cap_mixer,
5708                            ARRAY_SIZE(aif3_slim_cap_mixer)),
5709 };
5710
5711 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
5712         /* RX0-RX7 */
5713         WCD934X_SLIM_RX_AIF_PATH(0),
5714         WCD934X_SLIM_RX_AIF_PATH(1),
5715         WCD934X_SLIM_RX_AIF_PATH(2),
5716         WCD934X_SLIM_RX_AIF_PATH(3),
5717         WCD934X_SLIM_RX_AIF_PATH(4),
5718         WCD934X_SLIM_RX_AIF_PATH(5),
5719         WCD934X_SLIM_RX_AIF_PATH(6),
5720         WCD934X_SLIM_RX_AIF_PATH(7),
5721
5722         /* RX0 Ear out */
5723         WCD934X_INTERPOLATOR_PATH(0),
5724         WCD934X_INTERPOLATOR_MIX2(0),
5725         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
5726         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
5727         {"RX INT0 DAC", NULL, "RX_BIAS"},
5728         {"EAR PA", NULL, "RX INT0 DAC"},
5729         {"EAR", NULL, "EAR PA"},
5730
5731         /* RX1 Headphone left */
5732         WCD934X_INTERPOLATOR_PATH(1),
5733         WCD934X_INTERPOLATOR_MIX2(1),
5734         {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
5735         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
5736         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
5737         {"RX INT1 DAC", NULL, "RX_BIAS"},
5738         {"HPHL PA", NULL, "RX INT1 DAC"},
5739         {"HPHL", NULL, "HPHL PA"},
5740
5741         /* RX2 Headphone right */
5742         WCD934X_INTERPOLATOR_PATH(2),
5743         WCD934X_INTERPOLATOR_MIX2(2),
5744         {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
5745         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
5746         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
5747         {"RX INT2 DAC", NULL, "RX_BIAS"},
5748         {"HPHR PA", NULL, "RX INT2 DAC"},
5749         {"HPHR", NULL, "HPHR PA"},
5750
5751         /* RX3 HIFi LineOut1 */
5752         WCD934X_INTERPOLATOR_PATH(3),
5753         WCD934X_INTERPOLATOR_MIX2(3),
5754         {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
5755         {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
5756         {"RX INT3 DAC", NULL, "RX_BIAS"},
5757         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
5758         {"LINEOUT1", NULL, "LINEOUT1 PA"},
5759
5760         /* RX4 HIFi LineOut2 */
5761         WCD934X_INTERPOLATOR_PATH(4),
5762         WCD934X_INTERPOLATOR_MIX2(4),
5763         {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
5764         {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
5765         {"RX INT4 DAC", NULL, "RX_BIAS"},
5766         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
5767         {"LINEOUT2", NULL, "LINEOUT2 PA"},
5768
5769         /* RX7 Speaker Left Out PA */
5770         WCD934X_INTERPOLATOR_PATH(7),
5771         WCD934X_INTERPOLATOR_MIX2(7),
5772         {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
5773         {"RX INT7 CHAIN", NULL, "RX_BIAS"},
5774         {"RX INT7 CHAIN", NULL, "SBOOST0"},
5775         {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
5776         {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
5777
5778         /* RX8 Speaker Right Out PA */
5779         WCD934X_INTERPOLATOR_PATH(8),
5780         {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
5781         {"RX INT8 CHAIN", NULL, "RX_BIAS"},
5782         {"RX INT8 CHAIN", NULL, "SBOOST1"},
5783         {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
5784         {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
5785
5786         /* Tx */
5787         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
5788         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
5789         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
5790
5791         WCD934X_SLIM_TX_AIF_PATH(0),
5792         WCD934X_SLIM_TX_AIF_PATH(1),
5793         WCD934X_SLIM_TX_AIF_PATH(2),
5794         WCD934X_SLIM_TX_AIF_PATH(3),
5795         WCD934X_SLIM_TX_AIF_PATH(4),
5796         WCD934X_SLIM_TX_AIF_PATH(5),
5797         WCD934X_SLIM_TX_AIF_PATH(6),
5798         WCD934X_SLIM_TX_AIF_PATH(7),
5799         WCD934X_SLIM_TX_AIF_PATH(8),
5800
5801         WCD934X_ADC_MUX(0),
5802         WCD934X_ADC_MUX(1),
5803         WCD934X_ADC_MUX(2),
5804         WCD934X_ADC_MUX(3),
5805         WCD934X_ADC_MUX(4),
5806         WCD934X_ADC_MUX(5),
5807         WCD934X_ADC_MUX(6),
5808         WCD934X_ADC_MUX(7),
5809         WCD934X_ADC_MUX(8),
5810
5811         {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
5812         {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
5813         {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
5814         {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
5815         {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
5816         {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
5817         {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
5818         {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
5819         {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5820
5821         {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5822         {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5823
5824         { "DMIC0", NULL, "DMIC0 Pin" },
5825         { "DMIC1", NULL, "DMIC1 Pin" },
5826         { "DMIC2", NULL, "DMIC2 Pin" },
5827         { "DMIC3", NULL, "DMIC3 Pin" },
5828         { "DMIC4", NULL, "DMIC4 Pin" },
5829         { "DMIC5", NULL, "DMIC5 Pin" },
5830
5831         {"ADC1", NULL, "AMIC1"},
5832         {"ADC2", NULL, "AMIC2"},
5833         {"ADC3", NULL, "AMIC3"},
5834         {"ADC4", NULL, "AMIC4_5 SEL"},
5835
5836         WCD934X_IIR_INP_MUX(0),
5837         WCD934X_IIR_INP_MUX(1),
5838
5839         {"SRC0", NULL, "IIR0"},
5840         {"SRC1", NULL, "IIR1"},
5841 };
5842
5843 static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
5844                                   struct snd_soc_jack *jack, void *data)
5845 {
5846         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
5847         int ret = 0;
5848
5849         if (!wcd->mbhc)
5850                 return -ENOTSUPP;
5851
5852         if (jack && !wcd->mbhc_started) {
5853                 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
5854                 wcd->mbhc_started = true;
5855         } else if (wcd->mbhc_started) {
5856                 wcd_mbhc_stop(wcd->mbhc);
5857                 wcd->mbhc_started = false;
5858         }
5859
5860         return ret;
5861 }
5862
5863 static const struct snd_soc_component_driver wcd934x_component_drv = {
5864         .probe = wcd934x_comp_probe,
5865         .remove = wcd934x_comp_remove,
5866         .set_sysclk = wcd934x_comp_set_sysclk,
5867         .controls = wcd934x_snd_controls,
5868         .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5869         .dapm_widgets = wcd934x_dapm_widgets,
5870         .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5871         .dapm_routes = wcd934x_audio_map,
5872         .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5873         .set_jack = wcd934x_codec_set_jack,
5874 };
5875
5876 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5877 {
5878         struct device *dev = &wcd->sdev->dev;
5879         struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
5880         struct device_node *ifc_dev_np;
5881
5882         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5883         if (!ifc_dev_np) {
5884                 dev_err(dev, "No Interface device found\n");
5885                 return -EINVAL;
5886         }
5887
5888         wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5889         of_node_put(ifc_dev_np);
5890         if (!wcd->sidev) {
5891                 dev_err(dev, "Unable to get SLIM Interface device\n");
5892                 return -EINVAL;
5893         }
5894
5895         slim_get_logical_addr(wcd->sidev);
5896         wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5897                                   &wcd934x_ifc_regmap_config);
5898         if (IS_ERR(wcd->if_regmap)) {
5899                 dev_err(dev, "Failed to allocate ifc register map\n");
5900                 return PTR_ERR(wcd->if_regmap);
5901         }
5902
5903         of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5904                              &wcd->dmic_sample_rate);
5905
5906         cfg->mbhc_micbias = MIC_BIAS_2;
5907         cfg->anc_micbias = MIC_BIAS_2;
5908         cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
5909         cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
5910         cfg->micb_mv = wcd->micb2_mv;
5911         cfg->linein_th = 5000;
5912         cfg->hs_thr = 1700;
5913         cfg->hph_thr = 50;
5914
5915         wcd_dt_parse_mbhc_data(dev, cfg);
5916
5917
5918         return 0;
5919 }
5920
5921 static int wcd934x_codec_probe(struct platform_device *pdev)
5922 {
5923         struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5924         struct wcd934x_codec *wcd;
5925         struct device *dev = &pdev->dev;
5926         int ret, irq;
5927
5928         wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5929         if (!wcd)
5930                 return -ENOMEM;
5931
5932         wcd->dev = dev;
5933         wcd->regmap = data->regmap;
5934         wcd->extclk = data->extclk;
5935         wcd->sdev = to_slim_device(data->dev);
5936         mutex_init(&wcd->sysclk_mutex);
5937         mutex_init(&wcd->micb_lock);
5938
5939         ret = wcd934x_codec_parse_data(wcd);
5940         if (ret) {
5941                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5942                 return ret;
5943         }
5944
5945         /* set default rate 9P6MHz */
5946         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5947                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5948                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5949         memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5950         memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5951
5952         irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5953         if (irq < 0) {
5954                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5955                 return irq;
5956         }
5957
5958         ret = devm_request_threaded_irq(dev, irq, NULL,
5959                                         wcd934x_slim_irq_handler,
5960                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5961                                         "slim", wcd);
5962         if (ret) {
5963                 dev_err(dev, "Failed to request slimbus irq\n");
5964                 return ret;
5965         }
5966
5967         wcd934x_register_mclk_output(wcd);
5968         platform_set_drvdata(pdev, wcd);
5969
5970         return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5971                                                wcd934x_slim_dais,
5972                                                ARRAY_SIZE(wcd934x_slim_dais));
5973 }
5974
5975 static const struct platform_device_id wcd934x_driver_id[] = {
5976         {
5977                 .name = "wcd934x-codec",
5978         },
5979         {},
5980 };
5981 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5982
5983 static struct platform_driver wcd934x_codec_driver = {
5984         .probe  = &wcd934x_codec_probe,
5985         .id_table = wcd934x_driver_id,
5986         .driver = {
5987                 .name   = "wcd934x-codec",
5988         }
5989 };
5990
5991 MODULE_ALIAS("platform:wcd934x-codec");
5992 module_platform_driver(wcd934x_codec_driver);
5993 MODULE_DESCRIPTION("WCD934x codec driver");
5994 MODULE_LICENSE("GPL v2");