1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
5 #include <linux/slab.h>
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
10 #include "wcd-clsh-v2.h"
12 struct wcd_clsh_ctrl {
19 struct snd_soc_component *comp;
22 /* Class-H registers for codecs from and above WCD9335 */
23 #define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0xB, 0x42)
24 #define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK BIT(6)
25 #define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE BIT(6)
26 #define WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE 0
27 #define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0xB, 0x56)
28 #define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0xB, 0x6A)
29 #define WCD9XXX_A_CDC_CLSH_K1_MSB WCD9335_REG(0xC, 0x08)
30 #define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK GENMASK(3, 0)
31 #define WCD9XXX_A_CDC_CLSH_K1_LSB WCD9335_REG(0xC, 0x09)
32 #define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK GENMASK(7, 0)
33 #define WCD9XXX_A_ANA_RX_SUPPLIES WCD9335_REG(0x6, 0x08)
34 #define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK BIT(1)
35 #define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H 0
36 #define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB BIT(1)
37 #define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK BIT(2)
38 #define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA BIT(2)
39 #define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT 0
40 #define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK BIT(3)
41 #define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA BIT(3)
42 #define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT 0
43 #define WCD9XXX_A_ANA_RX_VNEG_EN_MASK BIT(6)
44 #define WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT 6
45 #define WCD9XXX_A_ANA_RX_VNEG_ENABLE BIT(6)
46 #define WCD9XXX_A_ANA_RX_VNEG_DISABLE 0
47 #define WCD9XXX_A_ANA_RX_VPOS_EN_MASK BIT(7)
48 #define WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT 7
49 #define WCD9XXX_A_ANA_RX_VPOS_ENABLE BIT(7)
50 #define WCD9XXX_A_ANA_RX_VPOS_DISABLE 0
51 #define WCD9XXX_A_ANA_HPH WCD9335_REG(0x6, 0x09)
52 #define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK GENMASK(3, 2)
53 #define WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA 0x08
54 #define WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP 0x04
55 #define WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL 0x0
56 #define WCD9XXX_A_CDC_CLSH_CRC WCD9335_REG(0xC, 0x01)
57 #define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK BIT(0)
58 #define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE BIT(0)
59 #define WCD9XXX_A_CDC_CLSH_CRC_CLK_DISABLE 0
60 #define WCD9XXX_FLYBACK_EN WCD9335_REG(0x6, 0xA4)
61 #define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK GENMASK(6, 5)
62 #define WCD9XXX_FLYBACK_EN_DELAY_26P25_US 0x40
63 #define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK BIT(4)
64 #define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY BIT(4)
65 #define WCD9XXX_FLYBACK_EN_PWDN_WITH_DELAY 0
66 #define WCD9XXX_RX_BIAS_FLYB_BUFF WCD9335_REG(0x6, 0xC7)
67 #define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4)
68 #define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0)
69 #define WCD9XXX_HPH_L_EN WCD9335_REG(0x6, 0xD3)
70 #define WCD9XXX_HPH_CONST_SEL_L_MASK GENMASK(7, 3)
71 #define WCD9XXX_HPH_CONST_SEL_BYPASS 0
72 #define WCD9XXX_HPH_CONST_SEL_LP_PATH 0x40
73 #define WCD9XXX_HPH_CONST_SEL_HQ_PATH 0x80
74 #define WCD9XXX_HPH_R_EN WCD9335_REG(0x6, 0xD6)
75 #define WCD9XXX_HPH_REFBUFF_UHQA_CTL WCD9335_REG(0x6, 0xDD)
76 #define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK GENMASK(2, 0)
77 #define WCD9XXX_CLASSH_CTRL_VCL_2 WCD9335_REG(0x6, 0x9B)
78 #define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK GENMASK(5, 4)
79 #define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM 0x20
80 #define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM 0x0
81 #define WCD9XXX_CDC_RX1_RX_PATH_CTL WCD9335_REG(0xB, 0x55)
82 #define WCD9XXX_CDC_RX2_RX_PATH_CTL WCD9335_REG(0xB, 0x69)
83 #define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0xD, 0x41)
84 #define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0)
85 #define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK BIT(1)
86 #define WCD9XXX_CLASSH_CTRL_CCL_1 WCD9335_REG(0x6, 0x9C)
87 #define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK GENMASK(7, 4)
88 #define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA 0x50
89 #define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA 0x30
91 #define WCD9XXX_BASE_ADDRESS 0x3000
92 #define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008)
93 #define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009)
94 #define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098)
95 #define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099)
96 #define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5)
97 #define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8)
98 #define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF)
99 #define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF)
100 #define WCD9XXX_V3_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7)
101 #define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1)
102 #define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138)
104 #define CLSH_REQ_ENABLE true
105 #define CLSH_REQ_DISABLE false
106 #define WCD_USLEEP_RANGE 50
119 static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl,
122 struct snd_soc_component *comp = ctrl->comp;
124 if ((enable && ++ctrl->clsh_users == 1) ||
125 (!enable && --ctrl->clsh_users == 0))
126 snd_soc_component_update_bits(comp, WCD9XXX_A_CDC_CLSH_CRC,
127 WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK,
129 if (ctrl->clsh_users < 0)
130 ctrl->clsh_users = 0;
133 static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp,
137 if (mode == CLS_H_HIFI)
138 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
139 WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK,
140 WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA);
142 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
143 WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK,
144 WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT);
147 static void wcd_clsh_v3_set_buck_mode(struct snd_soc_component *component,
150 if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
151 mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI)
152 snd_soc_component_update_bits(component,
153 WCD9XXX_ANA_RX_SUPPLIES,
154 0x08, 0x08); /* set to HIFI */
156 snd_soc_component_update_bits(component,
157 WCD9XXX_ANA_RX_SUPPLIES,
158 0x08, 0x00); /* set to default */
161 static inline void wcd_clsh_set_flyback_mode(struct snd_soc_component *comp,
165 if (mode == CLS_H_HIFI)
166 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
167 WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK,
168 WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA);
170 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
171 WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK,
172 WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT);
175 static void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl,
179 struct snd_soc_component *comp = ctrl->comp;
181 /* enable/disable buck */
182 if ((enable && (++ctrl->buck_users == 1)) ||
183 (!enable && (--ctrl->buck_users == 0)))
184 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
185 WCD9XXX_A_ANA_RX_VPOS_EN_MASK,
186 enable << WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT);
188 * 500us sleep is required after buck enable/disable
189 * as per HW requirement
191 usleep_range(500, 500 + WCD_USLEEP_RANGE);
194 static void wcd_clsh_v3_buck_ctrl(struct snd_soc_component *component,
195 struct wcd_clsh_ctrl *ctrl,
199 /* enable/disable buck */
200 if ((enable && (++ctrl->buck_users == 1)) ||
201 (!enable && (--ctrl->buck_users == 0))) {
202 snd_soc_component_update_bits(component,
203 WCD9XXX_ANA_RX_SUPPLIES,
204 (1 << 7), (enable << 7));
206 * 500us sleep is required after buck enable/disable
207 * as per HW requirement
209 usleep_range(500, 510);
210 if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
211 mode == CLS_H_HIFI || mode == CLS_H_LP)
212 snd_soc_component_update_bits(component,
213 WCD9XXX_CLASSH_MODE_3,
216 snd_soc_component_update_bits(component,
217 WCD9XXX_CLASSH_MODE_2,
219 /* 500usec delay is needed as per HW requirement */
220 usleep_range(500, 500 + WCD_USLEEP_RANGE);
224 static void wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl *ctrl,
228 struct snd_soc_component *comp = ctrl->comp;
230 /* enable/disable flyback */
231 if ((enable && (++ctrl->flyback_users == 1)) ||
232 (!enable && (--ctrl->flyback_users == 0))) {
233 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
234 WCD9XXX_A_ANA_RX_VNEG_EN_MASK,
235 enable << WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT);
236 /* 100usec delay is needed as per HW requirement */
237 usleep_range(100, 110);
240 * 500us sleep is required after flyback enable/disable
241 * as per HW requirement
243 usleep_range(500, 500 + WCD_USLEEP_RANGE);
246 static void wcd_clsh_set_gain_path(struct wcd_clsh_ctrl *ctrl, int mode)
248 struct snd_soc_component *comp = ctrl->comp;
254 val = WCD9XXX_HPH_CONST_SEL_BYPASS;
257 val = WCD9XXX_HPH_CONST_SEL_HQ_PATH;
260 val = WCD9XXX_HPH_CONST_SEL_LP_PATH;
264 snd_soc_component_update_bits(comp, WCD9XXX_HPH_L_EN,
265 WCD9XXX_HPH_CONST_SEL_L_MASK,
268 snd_soc_component_update_bits(comp, WCD9XXX_HPH_R_EN,
269 WCD9XXX_HPH_CONST_SEL_L_MASK,
273 static void wcd_clsh_v2_set_hph_mode(struct snd_soc_component *comp, int mode)
275 int val = 0, gain = 0, res_val;
276 int ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
278 res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM;
281 res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM;
282 val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL;
284 ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
287 val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL;
289 ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
292 val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA;
293 gain = DAC_GAIN_M0P2DB;
294 ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
297 val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP;
298 ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA;
302 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_HPH,
303 WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK, val);
304 snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_VCL_2,
305 WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK,
307 if (mode != CLS_H_LP)
308 snd_soc_component_update_bits(comp,
309 WCD9XXX_HPH_REFBUFF_UHQA_CTL,
310 WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK,
312 snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_CCL_1,
313 WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK,
317 static void wcd_clsh_v3_set_hph_mode(struct snd_soc_component *component,
341 dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode);
345 snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val);
348 void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, int mode)
350 struct snd_soc_component *comp = ctrl->comp;
352 if (ctrl->codec_version >= WCD937X)
353 wcd_clsh_v3_set_hph_mode(comp, mode);
355 wcd_clsh_v2_set_hph_mode(comp, mode);
359 static void wcd_clsh_set_flyback_current(struct snd_soc_component *comp,
363 snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF,
364 WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK, 0x0A);
365 snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF,
366 WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK, 0x0A);
367 /* Sleep needed to avoid click and pop as per HW requirement */
368 usleep_range(100, 110);
371 static void wcd_clsh_set_buck_regulator_mode(struct snd_soc_component *comp,
375 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
376 WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK,
377 WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB);
379 snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
380 WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK,
381 WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H);
384 static void wcd_clsh_v3_set_buck_regulator_mode(struct snd_soc_component *component,
387 snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES,
391 static void wcd_clsh_v3_set_flyback_mode(struct snd_soc_component *component,
394 if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
395 mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) {
396 snd_soc_component_update_bits(component,
397 WCD9XXX_ANA_RX_SUPPLIES,
399 snd_soc_component_update_bits(component,
400 WCD9XXX_FLYBACK_VNEG_CTRL_4,
403 snd_soc_component_update_bits(component,
404 WCD9XXX_ANA_RX_SUPPLIES,
405 0x04, 0x00); /* set to Default */
406 snd_soc_component_update_bits(component,
407 WCD9XXX_FLYBACK_VNEG_CTRL_4,
412 static void wcd_clsh_v3_force_iq_ctl(struct snd_soc_component *component,
413 int mode, bool enable)
416 snd_soc_component_update_bits(component,
417 WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
419 /* 100usec delay is needed as per HW requirement */
420 usleep_range(100, 110);
421 snd_soc_component_update_bits(component,
422 WCD9XXX_CLASSH_MODE_3,
424 snd_soc_component_update_bits(component,
425 WCD9XXX_CLASSH_MODE_2,
427 if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) {
428 snd_soc_component_update_bits(component,
429 WCD9XXX_HPH_NEW_INT_PA_MISC2,
431 snd_soc_component_update_bits(component,
432 WCD9XXX_RX_BIAS_HPH_LOWPOWER,
434 snd_soc_component_update_bits(component,
439 snd_soc_component_update_bits(component,
440 WCD9XXX_HPH_NEW_INT_PA_MISC2,
442 snd_soc_component_update_bits(component,
443 WCD9XXX_RX_BIAS_HPH_LOWPOWER,
445 snd_soc_component_update_bits(component,
451 static void wcd_clsh_v3_flyback_ctrl(struct snd_soc_component *component,
452 struct wcd_clsh_ctrl *ctrl,
456 /* enable/disable flyback */
457 if ((enable && (++ctrl->flyback_users == 1)) ||
458 (!enable && (--ctrl->flyback_users == 0))) {
459 snd_soc_component_update_bits(component,
460 WCD9XXX_FLYBACK_VNEG_CTRL_1,
462 snd_soc_component_update_bits(component,
463 WCD9XXX_ANA_RX_SUPPLIES,
464 (1 << 6), (enable << 6));
466 * 100us sleep is required after flyback enable/disable
467 * as per HW requirement
469 usleep_range(100, 110);
470 snd_soc_component_update_bits(component,
471 WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
473 /* 500usec delay is needed as per HW requirement */
474 usleep_range(500, 500 + WCD_USLEEP_RANGE);
478 static void wcd_clsh_v3_set_flyback_current(struct snd_soc_component *component,
481 snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
483 snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
485 /* Sleep needed to avoid click and pop as per HW requirement */
486 usleep_range(100, 110);
489 static void wcd_clsh_v3_state_aux(struct wcd_clsh_ctrl *ctrl, int req_state,
490 bool is_enable, int mode)
492 struct snd_soc_component *component = ctrl->comp;
495 wcd_clsh_v3_set_buck_mode(component, mode);
496 wcd_clsh_v3_set_flyback_mode(component, mode);
497 wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
498 wcd_clsh_v3_set_flyback_current(component, mode);
499 wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
501 wcd_clsh_v3_buck_ctrl(component, ctrl, mode, false);
502 wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, false);
503 wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
504 wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
508 static void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state,
509 bool is_enable, int mode)
511 struct snd_soc_component *comp = ctrl->comp;
513 if (mode != CLS_AB) {
514 dev_err(comp->dev, "%s: LO cannot be in this mode: %d\n",
520 wcd_clsh_set_buck_regulator_mode(comp, mode);
521 wcd_clsh_set_buck_mode(comp, mode);
522 wcd_clsh_set_flyback_mode(comp, mode);
523 wcd_clsh_flyback_ctrl(ctrl, mode, true);
524 wcd_clsh_set_flyback_current(comp, mode);
525 wcd_clsh_buck_ctrl(ctrl, mode, true);
527 wcd_clsh_buck_ctrl(ctrl, mode, false);
528 wcd_clsh_flyback_ctrl(ctrl, mode, false);
529 wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
530 wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
531 wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
535 static void wcd_clsh_v3_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
536 bool is_enable, int mode)
538 struct snd_soc_component *component = ctrl->comp;
540 if (mode == CLS_H_NORMAL) {
541 dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n",
547 wcd_clsh_v3_set_buck_regulator_mode(component, mode);
548 wcd_clsh_v3_set_flyback_mode(component, mode);
549 wcd_clsh_v3_force_iq_ctl(component, mode, true);
550 wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
551 wcd_clsh_v3_set_flyback_current(component, mode);
552 wcd_clsh_v3_set_buck_mode(component, mode);
553 wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
554 wcd_clsh_v3_set_hph_mode(component, mode);
556 wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
558 /* buck and flyback set to default mode and disable */
559 wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
560 wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
561 wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
562 wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
563 wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
567 static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
568 bool is_enable, int mode)
570 struct snd_soc_component *comp = ctrl->comp;
572 if (mode == CLS_H_NORMAL) {
573 dev_err(comp->dev, "%s: Normal mode not applicable for hph_r\n",
579 if (mode != CLS_AB) {
580 wcd_enable_clsh_block(ctrl, true);
582 * These K1 values depend on the Headphone Impedance
583 * For now it is assumed to be 16 ohm
585 snd_soc_component_update_bits(comp,
586 WCD9XXX_A_CDC_CLSH_K1_MSB,
587 WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK,
589 snd_soc_component_update_bits(comp,
590 WCD9XXX_A_CDC_CLSH_K1_LSB,
591 WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK,
593 snd_soc_component_update_bits(comp,
594 WCD9XXX_A_CDC_RX2_RX_PATH_CFG0,
595 WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
596 WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
598 wcd_clsh_set_buck_regulator_mode(comp, mode);
599 wcd_clsh_set_flyback_mode(comp, mode);
600 wcd_clsh_flyback_ctrl(ctrl, mode, true);
601 wcd_clsh_set_flyback_current(comp, mode);
602 wcd_clsh_set_buck_mode(comp, mode);
603 wcd_clsh_buck_ctrl(ctrl, mode, true);
604 wcd_clsh_v2_set_hph_mode(comp, mode);
605 wcd_clsh_set_gain_path(ctrl, mode);
607 wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
609 if (mode != CLS_AB) {
610 snd_soc_component_update_bits(comp,
611 WCD9XXX_A_CDC_RX2_RX_PATH_CFG0,
612 WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
613 WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
614 wcd_enable_clsh_block(ctrl, false);
616 /* buck and flyback set to default mode and disable */
617 wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false);
618 wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false);
619 wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
620 wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
621 wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
625 static void wcd_clsh_v3_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
626 bool is_enable, int mode)
628 struct snd_soc_component *component = ctrl->comp;
630 if (mode == CLS_H_NORMAL) {
631 dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n",
637 wcd_clsh_v3_set_buck_regulator_mode(component, mode);
638 wcd_clsh_v3_set_flyback_mode(component, mode);
639 wcd_clsh_v3_force_iq_ctl(component, mode, true);
640 wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
641 wcd_clsh_v3_set_flyback_current(component, mode);
642 wcd_clsh_v3_set_buck_mode(component, mode);
643 wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
644 wcd_clsh_v3_set_hph_mode(component, mode);
646 wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
648 /* set buck and flyback to Default Mode */
649 wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
650 wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
651 wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
652 wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
653 wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
657 static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
658 bool is_enable, int mode)
660 struct snd_soc_component *comp = ctrl->comp;
662 if (mode == CLS_H_NORMAL) {
663 dev_err(comp->dev, "%s: Normal mode not applicable for hph_l\n",
669 if (mode != CLS_AB) {
670 wcd_enable_clsh_block(ctrl, true);
672 * These K1 values depend on the Headphone Impedance
673 * For now it is assumed to be 16 ohm
675 snd_soc_component_update_bits(comp,
676 WCD9XXX_A_CDC_CLSH_K1_MSB,
677 WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK,
679 snd_soc_component_update_bits(comp,
680 WCD9XXX_A_CDC_CLSH_K1_LSB,
681 WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK,
683 snd_soc_component_update_bits(comp,
684 WCD9XXX_A_CDC_RX1_RX_PATH_CFG0,
685 WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
686 WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
688 wcd_clsh_set_buck_regulator_mode(comp, mode);
689 wcd_clsh_set_flyback_mode(comp, mode);
690 wcd_clsh_flyback_ctrl(ctrl, mode, true);
691 wcd_clsh_set_flyback_current(comp, mode);
692 wcd_clsh_set_buck_mode(comp, mode);
693 wcd_clsh_buck_ctrl(ctrl, mode, true);
694 wcd_clsh_v2_set_hph_mode(comp, mode);
695 wcd_clsh_set_gain_path(ctrl, mode);
697 wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
699 if (mode != CLS_AB) {
700 snd_soc_component_update_bits(comp,
701 WCD9XXX_A_CDC_RX1_RX_PATH_CFG0,
702 WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
703 WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
704 wcd_enable_clsh_block(ctrl, false);
706 /* set buck and flyback to Default Mode */
707 wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false);
708 wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false);
709 wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
710 wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
711 wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
715 static void wcd_clsh_v3_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
716 bool is_enable, int mode)
718 struct snd_soc_component *component = ctrl->comp;
721 wcd_clsh_v3_set_buck_regulator_mode(component, mode);
722 wcd_clsh_v3_set_flyback_mode(component, mode);
723 wcd_clsh_v3_force_iq_ctl(component, mode, true);
724 wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
725 wcd_clsh_v3_set_flyback_current(component, mode);
726 wcd_clsh_v3_set_buck_mode(component, mode);
727 wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
728 wcd_clsh_v3_set_hph_mode(component, mode);
730 wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
732 /* set buck and flyback to Default Mode */
733 wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
734 wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
735 wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
736 wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
737 wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
741 static void wcd_clsh_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
742 bool is_enable, int mode)
744 struct snd_soc_component *comp = ctrl->comp;
746 if (mode != CLS_H_NORMAL) {
747 dev_err(comp->dev, "%s: mode: %d cannot be used for EAR\n",
753 wcd_enable_clsh_block(ctrl, true);
754 snd_soc_component_update_bits(comp,
755 WCD9XXX_A_CDC_RX0_RX_PATH_CFG0,
756 WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
757 WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
758 wcd_clsh_set_buck_mode(comp, mode);
759 wcd_clsh_set_flyback_mode(comp, mode);
760 wcd_clsh_flyback_ctrl(ctrl, mode, true);
761 wcd_clsh_set_flyback_current(comp, mode);
762 wcd_clsh_buck_ctrl(ctrl, mode, true);
764 snd_soc_component_update_bits(comp,
765 WCD9XXX_A_CDC_RX0_RX_PATH_CFG0,
766 WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
767 WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
768 wcd_enable_clsh_block(ctrl, false);
769 wcd_clsh_buck_ctrl(ctrl, mode, false);
770 wcd_clsh_flyback_ctrl(ctrl, mode, false);
771 wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
772 wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
776 static int _wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, int req_state,
777 bool is_enable, int mode)
780 case WCD_CLSH_STATE_EAR:
781 if (ctrl->codec_version >= WCD937X)
782 wcd_clsh_v3_state_ear(ctrl, req_state, is_enable, mode);
784 wcd_clsh_state_ear(ctrl, req_state, is_enable, mode);
786 case WCD_CLSH_STATE_HPHL:
787 if (ctrl->codec_version >= WCD937X)
788 wcd_clsh_v3_state_hph_l(ctrl, req_state, is_enable, mode);
790 wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode);
792 case WCD_CLSH_STATE_HPHR:
793 if (ctrl->codec_version >= WCD937X)
794 wcd_clsh_v3_state_hph_r(ctrl, req_state, is_enable, mode);
796 wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode);
798 case WCD_CLSH_STATE_LO:
799 if (ctrl->codec_version < WCD937X)
800 wcd_clsh_state_lo(ctrl, req_state, is_enable, mode);
802 case WCD_CLSH_STATE_AUX:
803 if (ctrl->codec_version >= WCD937X)
804 wcd_clsh_v3_state_aux(ctrl, req_state, is_enable, mode);
814 * Function: wcd_clsh_is_state_valid
817 * Provides information on valid states of Class H configuration
819 static bool wcd_clsh_is_state_valid(int state)
822 case WCD_CLSH_STATE_IDLE:
823 case WCD_CLSH_STATE_EAR:
824 case WCD_CLSH_STATE_HPHL:
825 case WCD_CLSH_STATE_HPHR:
826 case WCD_CLSH_STATE_LO:
827 case WCD_CLSH_STATE_AUX:
835 * Function: wcd_clsh_fsm
836 * Params: ctrl, req_state, req_type, clsh_event
838 * This function handles PRE DAC and POST DAC conditions of different devices
839 * and updates class H configuration of different combination of devices
840 * based on validity of their states. ctrl will contain current
841 * class h state information
843 int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl,
844 enum wcd_clsh_event clsh_event,
846 enum wcd_clsh_mode mode)
848 struct snd_soc_component *comp = ctrl->comp;
850 if (nstate == ctrl->state)
853 if (!wcd_clsh_is_state_valid(nstate)) {
854 dev_err(comp->dev, "Class-H not a valid new state:\n");
858 switch (clsh_event) {
859 case WCD_CLSH_EVENT_PRE_DAC:
860 _wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_ENABLE, mode);
862 case WCD_CLSH_EVENT_POST_PA:
863 _wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_DISABLE, mode);
867 ctrl->state = nstate;
873 int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl)
878 struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(struct snd_soc_component *comp,
881 struct wcd_clsh_ctrl *ctrl;
883 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
885 return ERR_PTR(-ENOMEM);
887 ctrl->state = WCD_CLSH_STATE_IDLE;
889 ctrl->codec_version = version;
894 void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl)