1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/bits.h>
4 #include <linux/bitfield.h>
5 #include <linux/delay.h>
6 #include <linux/gpio/consumer.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/regmap.h>
11 #include <linux/regulator/consumer.h>
12 #include <sound/pcm.h>
13 #include <sound/pcm_params.h>
14 #include <sound/soc.h>
15 #include <sound/tlv.h>
17 #define RT9120_REG_DEVID 0x00
18 #define RT9120_REG_I2SFMT 0x02
19 #define RT9120_REG_I2SWL 0x03
20 #define RT9120_REG_SDIOSEL 0x04
21 #define RT9120_REG_SYSCTL 0x05
22 #define RT9120_REG_SPKGAIN 0x07
23 #define RT9120_REG_VOLRAMP 0x0A
24 #define RT9120_REG_ERRRPT 0x10
25 #define RT9120_REG_MSVOL 0x20
26 #define RT9120_REG_SWRESET 0x40
27 #define RT9120_REG_INTERCFG 0x63
28 #define RT9120_REG_INTERNAL0 0x65
29 #define RT9120_REG_INTERNAL1 0x69
30 #define RT9120_REG_UVPOPT 0x6C
31 #define RT9120_REG_DIGCFG 0xF8
33 #define RT9120_VID_MASK GENMASK(15, 8)
34 #define RT9120_SWRST_MASK BIT(7)
35 #define RT9120_MUTE_MASK GENMASK(5, 4)
36 #define RT9120_I2SFMT_MASK GENMASK(4, 2)
37 #define RT9120_I2SFMT_SHIFT 2
38 #define RT9120_CFG_FMT_I2S 0
39 #define RT9120_CFG_FMT_LEFTJ 1
40 #define RT9120_CFG_FMT_RIGHTJ 2
41 #define RT9120_CFG_FMT_DSPA 3
42 #define RT9120_CFG_FMT_DSPB 7
43 #define RT9120_AUDBIT_MASK GENMASK(1, 0)
44 #define RT9120_CFG_AUDBIT_16 0
45 #define RT9120_CFG_AUDBIT_20 1
46 #define RT9120_CFG_AUDBIT_24 2
47 #define RT9120_AUDWL_MASK GENMASK(5, 0)
48 #define RT9120_CFG_WORDLEN_16 16
49 #define RT9120_CFG_WORDLEN_24 24
50 #define RT9120_CFG_WORDLEN_32 32
51 #define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)
52 #define RT9120_AUTOSYNC_MASK BIT(6)
54 #define RT9120_VENDOR_ID 0x42
55 #define RT9120S_VENDOR_ID 0x43
56 #define RT9120_RESET_WAITMS 20
57 #define RT9120_CHIPON_WAITMS 20
58 #define RT9120_AMPON_WAITMS 50
59 #define RT9120_AMPOFF_WAITMS 100
60 #define RT9120_LVAPP_THRESUV 2000000
62 /* 8000 to 192000 supported , only 176400 not support */
63 #define RT9120_RATES_MASK (SNDRV_PCM_RATE_8000_192000 &\
64 ~SNDRV_PCM_RATE_176400)
65 #define RT9120_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE |\
66 SNDRV_PCM_FMTBIT_S24_LE |\
67 SNDRV_PCM_FMTBIT_S32_LE)
77 struct regmap *regmap;
81 /* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
82 static const DECLARE_TLV_DB_SCALE(digital_tlv, -1039375, 625, 1);
84 /* {6, 8, 10, 12, 13, 14, 15, 16}dB */
85 static const DECLARE_TLV_DB_RANGE(classd_tlv,
86 0, 3, TLV_DB_SCALE_ITEM(600, 200, 0),
87 4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0)
90 static const char * const sdo_select_text[] = {
91 "None", "INTF", "Final", "RMS Detect"
94 static const struct soc_enum sdo_select_enum =
95 SOC_ENUM_SINGLE(RT9120_REG_SDIOSEL, 4, ARRAY_SIZE(sdo_select_text),
98 static const struct snd_kcontrol_new rt9120_snd_controls[] = {
99 SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv),
100 SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv),
101 SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0),
102 SOC_ENUM("SDO Select", sdo_select_enum),
105 static int internal_power_event(struct snd_soc_dapm_widget *w,
106 struct snd_kcontrol *kcontrol, int event)
108 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
111 case SND_SOC_DAPM_PRE_PMU:
112 snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0);
114 case SND_SOC_DAPM_POST_PMU:
115 msleep(RT9120_AMPON_WAITMS);
117 case SND_SOC_DAPM_POST_PMD:
118 msleep(RT9120_AMPOFF_WAITMS);
127 static const struct snd_soc_dapm_widget rt9120_dapm_widgets[] = {
128 SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0),
129 SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0),
130 SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0),
131 SND_SOC_DAPM_SUPPLY("PWND", RT9120_REG_SYSCTL, 6, 1,
132 internal_power_event, SND_SOC_DAPM_PRE_PMU |
133 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
134 SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0),
135 SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0),
136 SND_SOC_DAPM_OUTPUT("SPKL"),
137 SND_SOC_DAPM_OUTPUT("SPKR"),
140 static const struct snd_soc_dapm_route rt9120_dapm_routes[] = {
141 { "DMIX", NULL, "AIF Playback" },
143 { "LDAC", NULL, "PWND" },
144 { "LDAC", NULL, "DMIX" },
145 { "SPKL PA", NULL, "LDAC" },
146 { "SPKL", NULL, "SPKL PA" },
148 { "RDAC", NULL, "PWND" },
149 { "RDAC", NULL, "DMIX" },
150 { "SPKR PA", NULL, "RDAC" },
151 { "SPKR", NULL, "SPKR PA" },
153 { "AIF Capture", NULL, "LDAC" },
154 { "AIF Capture", NULL, "RDAC" },
157 static int rt9120_codec_probe(struct snd_soc_component *comp)
159 struct rt9120_data *data = snd_soc_component_get_drvdata(comp);
161 snd_soc_component_init_regmap(comp, data->regmap);
163 /* Internal setting */
164 if (data->chip_idx == CHIP_IDX_RT9120S) {
165 snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
166 snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
168 snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
173 static const struct snd_soc_component_driver rt9120_component_driver = {
174 .probe = rt9120_codec_probe,
175 .controls = rt9120_snd_controls,
176 .num_controls = ARRAY_SIZE(rt9120_snd_controls),
177 .dapm_widgets = rt9120_dapm_widgets,
178 .num_dapm_widgets = ARRAY_SIZE(rt9120_dapm_widgets),
179 .dapm_routes = rt9120_dapm_routes,
180 .num_dapm_routes = ARRAY_SIZE(rt9120_dapm_routes),
183 static int rt9120_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
185 struct snd_soc_component *comp = dai->component;
188 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
189 case SND_SOC_DAIFMT_I2S:
190 format = RT9120_CFG_FMT_I2S;
192 case SND_SOC_DAIFMT_LEFT_J:
193 format = RT9120_CFG_FMT_LEFTJ;
195 case SND_SOC_DAIFMT_RIGHT_J:
196 format = RT9120_CFG_FMT_RIGHTJ;
198 case SND_SOC_DAIFMT_DSP_A:
199 format = RT9120_CFG_FMT_DSPA;
201 case SND_SOC_DAIFMT_DSP_B:
202 format = RT9120_CFG_FMT_DSPB;
205 dev_err(dai->dev, "Unknown dai format\n");
209 snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
211 format << RT9120_I2SFMT_SHIFT);
215 static int rt9120_hw_params(struct snd_pcm_substream *substream,
216 struct snd_pcm_hw_params *param,
217 struct snd_soc_dai *dai)
219 struct snd_soc_component *comp = dai->component;
220 unsigned int param_width, param_slot_width, auto_sync;
223 switch (width = params_width(param)) {
225 param_width = RT9120_CFG_AUDBIT_16;
228 param_width = RT9120_CFG_AUDBIT_20;
232 param_width = RT9120_CFG_AUDBIT_24;
235 dev_err(dai->dev, "Unsupported data width [%d]\n", width);
239 snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
240 RT9120_AUDBIT_MASK, param_width);
242 switch (width = params_physical_width(param)) {
244 param_slot_width = RT9120_CFG_WORDLEN_16;
247 param_slot_width = RT9120_CFG_WORDLEN_24;
250 param_slot_width = RT9120_CFG_WORDLEN_32;
253 dev_err(dai->dev, "Unsupported slot width [%d]\n", width);
257 snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
258 RT9120_AUDWL_MASK, param_slot_width);
260 fs = width * params_channels(param);
261 /* If fs is divided by 48, disable auto sync */
265 auto_sync = RT9120_AUTOSYNC_MASK;
267 snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
268 RT9120_AUTOSYNC_MASK, auto_sync);
272 static const struct snd_soc_dai_ops rt9120_dai_ops = {
273 .set_fmt = rt9120_set_fmt,
274 .hw_params = rt9120_hw_params,
277 static struct snd_soc_dai_driver rt9120_dai = {
278 .name = "rt9120_aif",
280 .stream_name = "AIF Playback",
281 .rates = RT9120_RATES_MASK,
282 .formats = RT9120_FMTS_MASK,
289 .stream_name = "AIF Capture",
290 .rates = RT9120_RATES_MASK,
291 .formats = RT9120_FMTS_MASK,
297 .ops = &rt9120_dai_ops,
299 .symmetric_sample_bits = 1,
302 static const struct regmap_range rt9120_rd_yes_ranges[] = {
303 regmap_reg_range(0x00, 0x0C),
304 regmap_reg_range(0x10, 0x15),
305 regmap_reg_range(0x20, 0x27),
306 regmap_reg_range(0x30, 0x38),
307 regmap_reg_range(0x3A, 0x40),
308 regmap_reg_range(0x63, 0x63),
309 regmap_reg_range(0x65, 0x65),
310 regmap_reg_range(0x69, 0x69),
311 regmap_reg_range(0x6C, 0x6C),
312 regmap_reg_range(0xF8, 0xF8)
315 static const struct regmap_access_table rt9120_rd_table = {
316 .yes_ranges = rt9120_rd_yes_ranges,
317 .n_yes_ranges = ARRAY_SIZE(rt9120_rd_yes_ranges),
320 static const struct regmap_range rt9120_wr_yes_ranges[] = {
321 regmap_reg_range(0x00, 0x00),
322 regmap_reg_range(0x02, 0x0A),
323 regmap_reg_range(0x10, 0x15),
324 regmap_reg_range(0x20, 0x27),
325 regmap_reg_range(0x30, 0x38),
326 regmap_reg_range(0x3A, 0x3D),
327 regmap_reg_range(0x40, 0x40),
328 regmap_reg_range(0x63, 0x63),
329 regmap_reg_range(0x65, 0x65),
330 regmap_reg_range(0x69, 0x69),
331 regmap_reg_range(0x6C, 0x6C),
332 regmap_reg_range(0xF8, 0xF8)
335 static const struct regmap_access_table rt9120_wr_table = {
336 .yes_ranges = rt9120_wr_yes_ranges,
337 .n_yes_ranges = ARRAY_SIZE(rt9120_wr_yes_ranges),
340 static int rt9120_get_reg_size(unsigned int reg)
356 static int rt9120_reg_read(void *context, unsigned int reg, unsigned int *val)
358 struct rt9120_data *data = context;
359 struct i2c_client *i2c = to_i2c_client(data->dev);
360 int size = rt9120_get_reg_size(reg);
364 ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, raw);
367 else if (ret != size)
372 *val = be32_to_cpup((__be32 *)raw);
375 *val = raw[0] << 16 | raw[1] << 8 | raw[0];
378 *val = be16_to_cpup((__be16 *)raw);
387 static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
389 struct rt9120_data *data = context;
390 struct i2c_client *i2c = to_i2c_client(data->dev);
391 int size = rt9120_get_reg_size(reg);
393 u8 *rawp = (u8 *)&be32_val;
396 be32_val = cpu_to_be32(val);
397 return i2c_smbus_write_i2c_block_data(i2c, reg, size, rawp + offs);
400 static const struct regmap_config rt9120_regmap_config = {
403 .max_register = RT9120_REG_DIGCFG,
405 .reg_read = rt9120_reg_read,
406 .reg_write = rt9120_reg_write,
408 .wr_table = &rt9120_wr_table,
409 .rd_table = &rt9120_rd_table,
412 static int rt9120_check_vendor_info(struct rt9120_data *data)
417 ret = regmap_read(data->regmap, RT9120_REG_DEVID, &devid);
421 devid = FIELD_GET(RT9120_VID_MASK, devid);
423 case RT9120_VENDOR_ID:
424 data->chip_idx = CHIP_IDX_RT9120;
426 case RT9120S_VENDOR_ID:
427 data->chip_idx = CHIP_IDX_RT9120S;
430 dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
437 static int rt9120_do_register_reset(struct rt9120_data *data)
441 ret = regmap_write(data->regmap, RT9120_REG_SWRESET,
446 msleep(RT9120_RESET_WAITMS);
450 static int rt9120_probe(struct i2c_client *i2c)
452 struct rt9120_data *data;
453 struct gpio_desc *pwdnn_gpio;
454 struct regulator *dvdd_supply;
455 int dvdd_supply_volt, ret;
457 data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL);
461 data->dev = &i2c->dev;
462 i2c_set_clientdata(i2c, data);
464 pwdnn_gpio = devm_gpiod_get_optional(&i2c->dev, "pwdnn",
466 if (IS_ERR(pwdnn_gpio)) {
467 dev_err(&i2c->dev, "Failed to initialize 'pwdnn' gpio\n");
468 return PTR_ERR(pwdnn_gpio);
469 } else if (pwdnn_gpio) {
470 dev_dbg(&i2c->dev, "'pwdnn' from low to high, wait chip on\n");
471 msleep(RT9120_CHIPON_WAITMS);
474 data->regmap = devm_regmap_init(&i2c->dev, NULL, data,
475 &rt9120_regmap_config);
476 if (IS_ERR(data->regmap)) {
477 ret = PTR_ERR(data->regmap);
478 dev_err(&i2c->dev, "Failed to init regmap [%d]\n", ret);
482 ret = rt9120_check_vendor_info(data);
484 dev_err(&i2c->dev, "Failed to check vendor info\n");
488 ret = rt9120_do_register_reset(data);
490 dev_err(&i2c->dev, "Failed to do register reset\n");
494 dvdd_supply = devm_regulator_get(&i2c->dev, "dvdd");
495 if (IS_ERR(dvdd_supply)) {
496 dev_err(&i2c->dev, "No dvdd regulator found\n");
497 return PTR_ERR(dvdd_supply);
500 dvdd_supply_volt = regulator_get_voltage(dvdd_supply);
501 if (dvdd_supply_volt <= RT9120_LVAPP_THRESUV) {
502 dev_dbg(&i2c->dev, "dvdd low voltage design\n");
503 ret = regmap_update_bits(data->regmap, RT9120_REG_UVPOPT,
504 RT9120_DVDD_UVSEL_MASK, 0);
506 dev_err(&i2c->dev, "Failed to config dvdd uvsel\n");
511 return devm_snd_soc_register_component(&i2c->dev,
512 &rt9120_component_driver,
516 static const struct of_device_id __maybe_unused rt9120_device_table[] = {
517 { .compatible = "richtek,rt9120", },
520 MODULE_DEVICE_TABLE(of, rt9120_device_table);
522 static struct i2c_driver rt9120_driver = {
525 .of_match_table = rt9120_device_table,
527 .probe_new = rt9120_probe,
529 module_i2c_driver(rt9120_driver);
531 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
532 MODULE_DESCRIPTION("RT9120 Audio Amplifier Driver");
533 MODULE_LICENSE("GPL");