sound/soc/codecs/rt5682s.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682s.c  --  RT5682I-VS ALSA SoC audio component driver
   4 //
   5 // Copyright 2021 Realtek Semiconductor Corp.
   6 // Author: Derek Fang <derek.fang@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/i2c.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/acpi.h>
  19 #include <linux/gpio.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/mutex.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/jack.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30 #include <sound/rt5682s.h>
  31
  32 #include "rt5682s.h"
  33
  34 #define DEVICE_ID 0x6749
  35
  36 static const struct rt5682s_platform_data i2s_default_platform_data = {
  37         .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
  38         .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
  39         .jd_src = RT5682S_JD1,
  40         .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
  41         .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
  42 };
  43
  44 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
  45         [RT5682S_SUPPLY_AVDD] = "AVDD",
  46         [RT5682S_SUPPLY_MICVDD] = "MICVDD",
  47 };
  48
  49 static const struct reg_sequence patch_list[] = {
  50         {RT5682S_I2C_CTRL,                      0x0007},
  51         {RT5682S_DIG_IN_CTRL_1,                 0x0000},
  52         {RT5682S_CHOP_DAC_2,                    0x2020},
  53         {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2,     0x0101},
  54         {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1,     0x80c0},
  55         {RT5682S_HP_CALIB_CTRL_9,               0x0002},
  56         {RT5682S_DEPOP_1,                       0x0000},
  57         {RT5682S_HP_CHARGE_PUMP_2,              0x3c15},
  58         {RT5682S_DAC1_DIG_VOL,                  0xfefe},
  59         {RT5682S_SAR_IL_CMD_2,                  0xac00},
  60         {RT5682S_SAR_IL_CMD_3,                  0x024c},
  61         {RT5682S_CBJ_CTRL_6,                    0x0804},
  62 };
  63
  64 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
  65                 struct device *dev)
  66 {
  67         int ret;
  68
  69         ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
  70         if (ret)
  71                 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  72 }
  73
  74 static const struct reg_default rt5682s_reg[] = {
  75         {0x0002, 0x8080},
  76         {0x0003, 0x0001},
  77         {0x0005, 0x0000},
  78         {0x0006, 0x0000},
  79         {0x0008, 0x8007},
  80         {0x000b, 0x0000},
  81         {0x000f, 0x4000},
  82         {0x0010, 0x4040},
  83         {0x0011, 0x0000},
  84         {0x0012, 0x0000},
  85         {0x0013, 0x1200},
  86         {0x0014, 0x200a},
  87         {0x0015, 0x0404},
  88         {0x0016, 0x0404},
  89         {0x0017, 0x05a4},
  90         {0x0019, 0xffff},
  91         {0x001c, 0x2f2f},
  92         {0x001f, 0x0000},
  93         {0x0022, 0x5757},
  94         {0x0023, 0x0039},
  95         {0x0024, 0x000b},
  96         {0x0026, 0xc0c4},
  97         {0x0029, 0x8080},
  98         {0x002a, 0xa0a0},
  99         {0x002b, 0x0300},
 100         {0x0030, 0x0000},
 101         {0x003c, 0x08c0},
 102         {0x0044, 0x1818},
 103         {0x004b, 0x00c0},
 104         {0x004c, 0x0000},
 105         {0x004d, 0x0000},
 106         {0x0061, 0x00c0},
 107         {0x0062, 0x008a},
 108         {0x0063, 0x0800},
 109         {0x0064, 0x0000},
 110         {0x0065, 0x0000},
 111         {0x0066, 0x0030},
 112         {0x0067, 0x000c},
 113         {0x0068, 0x0000},
 114         {0x0069, 0x0000},
 115         {0x006a, 0x0000},
 116         {0x006b, 0x0000},
 117         {0x006c, 0x0000},
 118         {0x006d, 0x2200},
 119         {0x006e, 0x0810},
 120         {0x006f, 0xe4de},
 121         {0x0070, 0x3320},
 122         {0x0071, 0x0000},
 123         {0x0073, 0x0000},
 124         {0x0074, 0x0000},
 125         {0x0075, 0x0002},
 126         {0x0076, 0x0001},
 127         {0x0079, 0x0000},
 128         {0x007a, 0x0000},
 129         {0x007b, 0x0000},
 130         {0x007c, 0x0100},
 131         {0x007e, 0x0000},
 132         {0x007f, 0x0000},
 133         {0x0080, 0x0000},
 134         {0x0083, 0x0000},
 135         {0x0084, 0x0000},
 136         {0x0085, 0x0000},
 137         {0x0086, 0x0005},
 138         {0x0087, 0x0000},
 139         {0x0088, 0x0000},
 140         {0x008c, 0x0003},
 141         {0x008e, 0x0060},
 142         {0x008f, 0x4da1},
 143         {0x0091, 0x1c15},
 144         {0x0092, 0x0425},
 145         {0x0093, 0x0000},
 146         {0x0094, 0x0080},
 147         {0x0095, 0x008f},
 148         {0x0096, 0x0000},
 149         {0x0097, 0x0000},
 150         {0x0098, 0x0000},
 151         {0x0099, 0x0000},
 152         {0x009a, 0x0000},
 153         {0x009b, 0x0000},
 154         {0x009c, 0x0000},
 155         {0x009d, 0x0000},
 156         {0x009e, 0x0000},
 157         {0x009f, 0x0009},
 158         {0x00a0, 0x0000},
 159         {0x00a3, 0x0002},
 160         {0x00a4, 0x0001},
 161         {0x00b6, 0x0000},
 162         {0x00b7, 0x0000},
 163         {0x00b8, 0x0000},
 164         {0x00b9, 0x0002},
 165         {0x00be, 0x0000},
 166         {0x00c0, 0x0160},
 167         {0x00c1, 0x82a0},
 168         {0x00c2, 0x0000},
 169         {0x00d0, 0x0000},
 170         {0x00d2, 0x3300},
 171         {0x00d3, 0x2200},
 172         {0x00d4, 0x0000},
 173         {0x00d9, 0x0000},
 174         {0x00da, 0x0000},
 175         {0x00db, 0x0000},
 176         {0x00dc, 0x00c0},
 177         {0x00dd, 0x2220},
 178         {0x00de, 0x3131},
 179         {0x00df, 0x3131},
 180         {0x00e0, 0x3131},
 181         {0x00e2, 0x0000},
 182         {0x00e3, 0x4000},
 183         {0x00e4, 0x0aa0},
 184         {0x00e5, 0x3131},
 185         {0x00e6, 0x3131},
 186         {0x00e7, 0x3131},
 187         {0x00e8, 0x3131},
 188         {0x00ea, 0xb320},
 189         {0x00eb, 0x0000},
 190         {0x00f0, 0x0000},
 191         {0x00f6, 0x0000},
 192         {0x00fa, 0x0000},
 193         {0x00fb, 0x0000},
 194         {0x00fc, 0x0000},
 195         {0x00fd, 0x0000},
 196         {0x00fe, 0x10ec},
 197         {0x00ff, 0x6749},
 198         {0x0100, 0xa000},
 199         {0x010b, 0x0066},
 200         {0x010c, 0x6666},
 201         {0x010d, 0x2202},
 202         {0x010e, 0x6666},
 203         {0x010f, 0xa800},
 204         {0x0110, 0x0006},
 205         {0x0111, 0x0460},
 206         {0x0112, 0x2000},
 207         {0x0113, 0x0200},
 208         {0x0117, 0x8000},
 209         {0x0118, 0x0303},
 210         {0x0125, 0x0020},
 211         {0x0132, 0x5026},
 212         {0x0136, 0x8000},
 213         {0x0139, 0x0005},
 214         {0x013a, 0x3030},
 215         {0x013b, 0xa000},
 216         {0x013c, 0x4110},
 217         {0x013f, 0x0000},
 218         {0x0145, 0x0022},
 219         {0x0146, 0x0000},
 220         {0x0147, 0x0000},
 221         {0x0148, 0x0000},
 222         {0x0156, 0x0022},
 223         {0x0157, 0x0303},
 224         {0x0158, 0x2222},
 225         {0x0159, 0x0000},
 226         {0x0160, 0x4ec0},
 227         {0x0161, 0x0080},
 228         {0x0162, 0x0200},
 229         {0x0163, 0x0800},
 230         {0x0164, 0x0000},
 231         {0x0165, 0x0000},
 232         {0x0166, 0x0000},
 233         {0x0167, 0x000f},
 234         {0x0168, 0x000f},
 235         {0x0169, 0x0001},
 236         {0x0190, 0x4131},
 237         {0x0194, 0x0000},
 238         {0x0195, 0x0000},
 239         {0x0197, 0x0022},
 240         {0x0198, 0x0000},
 241         {0x0199, 0x0000},
 242         {0x01ac, 0x0000},
 243         {0x01ad, 0x0000},
 244         {0x01ae, 0x0000},
 245         {0x01af, 0x2000},
 246         {0x01b0, 0x0000},
 247         {0x01b1, 0x0000},
 248         {0x01b2, 0x0000},
 249         {0x01b3, 0x0017},
 250         {0x01b4, 0x004b},
 251         {0x01b5, 0x0000},
 252         {0x01b6, 0x03e8},
 253         {0x01b7, 0x0000},
 254         {0x01b8, 0x0000},
 255         {0x01b9, 0x0400},
 256         {0x01ba, 0xb5b6},
 257         {0x01bb, 0x9124},
 258         {0x01bc, 0x4924},
 259         {0x01bd, 0x0009},
 260         {0x01be, 0x0018},
 261         {0x01bf, 0x002a},
 262         {0x01c0, 0x004c},
 263         {0x01c1, 0x0097},
 264         {0x01c2, 0x01c3},
 265         {0x01c3, 0x03e9},
 266         {0x01c4, 0x1389},
 267         {0x01c5, 0xc351},
 268         {0x01c6, 0x02a0},
 269         {0x01c7, 0x0b0f},
 270         {0x01c8, 0x402f},
 271         {0x01c9, 0x0702},
 272         {0x01ca, 0x0000},
 273         {0x01cb, 0x0000},
 274         {0x01cc, 0x5757},
 275         {0x01cd, 0x5757},
 276         {0x01ce, 0x5757},
 277         {0x01cf, 0x5757},
 278         {0x01d0, 0x5757},
 279         {0x01d1, 0x5757},
 280         {0x01d2, 0x5757},
 281         {0x01d3, 0x5757},
 282         {0x01d4, 0x5757},
 283         {0x01d5, 0x5757},
 284         {0x01d6, 0x0000},
 285         {0x01d7, 0x0000},
 286         {0x01d8, 0x0162},
 287         {0x01d9, 0x0007},
 288         {0x01da, 0x0000},
 289         {0x01db, 0x0004},
 290         {0x01dc, 0x0000},
 291         {0x01de, 0x7c00},
 292         {0x01df, 0x0020},
 293         {0x01e0, 0x04c1},
 294         {0x01e1, 0x0000},
 295         {0x01e2, 0x0000},
 296         {0x01e3, 0x0000},
 297         {0x01e4, 0x0000},
 298         {0x01e5, 0x0000},
 299         {0x01e6, 0x0001},
 300         {0x01e7, 0x0000},
 301         {0x01e8, 0x0000},
 302         {0x01eb, 0x0000},
 303         {0x01ec, 0x0000},
 304         {0x01ed, 0x0000},
 305         {0x01ee, 0x0000},
 306         {0x01ef, 0x0000},
 307         {0x01f0, 0x0000},
 308         {0x01f1, 0x0000},
 309         {0x01f2, 0x0000},
 310         {0x01f3, 0x0000},
 311         {0x01f4, 0x0000},
 312         {0x0210, 0x6297},
 313         {0x0211, 0xa004},
 314         {0x0212, 0x0365},
 315         {0x0213, 0xf7ff},
 316         {0x0214, 0xf24c},
 317         {0x0215, 0x0102},
 318         {0x0216, 0x00a3},
 319         {0x0217, 0x0048},
 320         {0x0218, 0xa2c0},
 321         {0x0219, 0x0400},
 322         {0x021a, 0x00c8},
 323         {0x021b, 0x00c0},
 324         {0x021c, 0x0000},
 325         {0x021d, 0x024c},
 326         {0x02fa, 0x0000},
 327         {0x02fb, 0x0000},
 328         {0x02fc, 0x0000},
 329         {0x03fe, 0x0000},
 330         {0x03ff, 0x0000},
 331         {0x0500, 0x0000},
 332         {0x0600, 0x0000},
 333         {0x0610, 0x6666},
 334         {0x0611, 0xa9aa},
 335         {0x0620, 0x6666},
 336         {0x0621, 0xa9aa},
 337         {0x0630, 0x6666},
 338         {0x0631, 0xa9aa},
 339         {0x0640, 0x6666},
 340         {0x0641, 0xa9aa},
 341         {0x07fa, 0x0000},
 342         {0x08fa, 0x0000},
 343         {0x08fb, 0x0000},
 344         {0x0d00, 0x0000},
 345         {0x1100, 0x0000},
 346         {0x1101, 0x0000},
 347         {0x1102, 0x0000},
 348         {0x1103, 0x0000},
 349         {0x1104, 0x0000},
 350         {0x1105, 0x0000},
 351         {0x1106, 0x0000},
 352         {0x1107, 0x0000},
 353         {0x1108, 0x0000},
 354         {0x1109, 0x0000},
 355         {0x110a, 0x0000},
 356         {0x110b, 0x0000},
 357         {0x110c, 0x0000},
 358         {0x1111, 0x0000},
 359         {0x1112, 0x0000},
 360         {0x1113, 0x0000},
 361         {0x1114, 0x0000},
 362         {0x1115, 0x0000},
 363         {0x1116, 0x0000},
 364         {0x1117, 0x0000},
 365         {0x1118, 0x0000},
 366         {0x1119, 0x0000},
 367         {0x111a, 0x0000},
 368         {0x111b, 0x0000},
 369         {0x111c, 0x0000},
 370         {0x1401, 0x0404},
 371         {0x1402, 0x0007},
 372         {0x1403, 0x0365},
 373         {0x1404, 0x0210},
 374         {0x1405, 0x0365},
 375         {0x1406, 0x0210},
 376         {0x1407, 0x0000},
 377         {0x1408, 0x0000},
 378         {0x1409, 0x0000},
 379         {0x140a, 0x0000},
 380         {0x140b, 0x0000},
 381         {0x140c, 0x0000},
 382         {0x140d, 0x0000},
 383         {0x140e, 0x0000},
 384         {0x140f, 0x0000},
 385         {0x1410, 0x0000},
 386         {0x1411, 0x0000},
 387         {0x1801, 0x0004},
 388         {0x1802, 0x0000},
 389         {0x1803, 0x0000},
 390         {0x1804, 0x0000},
 391         {0x1805, 0x00ff},
 392         {0x2c00, 0x0000},
 393         {0x3400, 0x0200},
 394         {0x3404, 0x0000},
 395         {0x3405, 0x0000},
 396         {0x3406, 0x0000},
 397         {0x3407, 0x0000},
 398         {0x3408, 0x0000},
 399         {0x3409, 0x0000},
 400         {0x340a, 0x0000},
 401         {0x340b, 0x0000},
 402         {0x340c, 0x0000},
 403         {0x340d, 0x0000},
 404         {0x340e, 0x0000},
 405         {0x340f, 0x0000},
 406         {0x3410, 0x0000},
 407         {0x3411, 0x0000},
 408         {0x3412, 0x0000},
 409         {0x3413, 0x0000},
 410         {0x3414, 0x0000},
 411         {0x3415, 0x0000},
 412         {0x3424, 0x0000},
 413         {0x3425, 0x0000},
 414         {0x3426, 0x0000},
 415         {0x3427, 0x0000},
 416         {0x3428, 0x0000},
 417         {0x3429, 0x0000},
 418         {0x342a, 0x0000},
 419         {0x342b, 0x0000},
 420         {0x342c, 0x0000},
 421         {0x342d, 0x0000},
 422         {0x342e, 0x0000},
 423         {0x342f, 0x0000},
 424         {0x3430, 0x0000},
 425         {0x3431, 0x0000},
 426         {0x3432, 0x0000},
 427         {0x3433, 0x0000},
 428         {0x3434, 0x0000},
 429         {0x3435, 0x0000},
 430         {0x3440, 0x6319},
 431         {0x3441, 0x3771},
 432         {0x3500, 0x0002},
 433         {0x3501, 0x5728},
 434         {0x3b00, 0x3010},
 435         {0x3b01, 0x3300},
 436         {0x3b02, 0x2200},
 437         {0x3b03, 0x0100},
 438 };
 439
 440 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
 441 {
 442         switch (reg) {
 443         case RT5682S_RESET:
 444         case RT5682S_CBJ_CTRL_2:
 445         case RT5682S_I2S1_F_DIV_CTRL_2:
 446         case RT5682S_I2S2_F_DIV_CTRL_2:
 447         case RT5682S_INT_ST_1:
 448         case RT5682S_GPIO_ST:
 449         case RT5682S_IL_CMD_1:
 450         case RT5682S_4BTN_IL_CMD_1:
 451         case RT5682S_AJD1_CTRL:
 452         case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
 453         case RT5682S_STO_NG2_CTRL_1:
 454         case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
 455         case RT5682S_STO1_DAC_SIL_DET:
 456         case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
 457         case RT5682S_HP_IMP_SENS_CTRL_13:
 458         case RT5682S_HP_IMP_SENS_CTRL_14:
 459         case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
 460         case RT5682S_HP_CALIB_CTRL_1:
 461         case RT5682S_HP_CALIB_CTRL_10:
 462         case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
 463         case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
 464         case RT5682S_SAR_IL_CMD_10:
 465         case RT5682S_SAR_IL_CMD_11:
 466         case RT5682S_VERSION_ID_HIDE:
 467         case RT5682S_VERSION_ID_CUS:
 468         case RT5682S_I2C_TRANS_CTRL:
 469         case RT5682S_DMIC_FLOAT_DET:
 470         case RT5682S_HA_CMP_OP_1:
 471         case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
 472         case RT5682S_CLK_SW_TEST_1:
 473         case RT5682S_CLK_SW_TEST_2:
 474         case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
 475         case RT5682S_PILOT_DIG_CTL_1:
 476                 return true;
 477         default:
 478                 return false;
 479         }
 480 }
 481
 482 static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
 483 {
 484         switch (reg) {
 485         case RT5682S_RESET:
 486         case RT5682S_VERSION_ID:
 487         case RT5682S_VENDOR_ID:
 488         case RT5682S_DEVICE_ID:
 489         case RT5682S_HP_CTRL_1:
 490         case RT5682S_HP_CTRL_2:
 491         case RT5682S_HPL_GAIN:
 492         case RT5682S_HPR_GAIN:
 493         case RT5682S_I2C_CTRL:
 494         case RT5682S_CBJ_BST_CTRL:
 495         case RT5682S_CBJ_DET_CTRL:
 496         case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
 497         case RT5682S_DAC1_DIG_VOL:
 498         case RT5682S_STO1_ADC_DIG_VOL:
 499         case RT5682S_STO1_ADC_BOOST:
 500         case RT5682S_HP_IMP_GAIN_1:
 501         case RT5682S_HP_IMP_GAIN_2:
 502         case RT5682S_SIDETONE_CTRL:
 503         case RT5682S_STO1_ADC_MIXER:
 504         case RT5682S_AD_DA_MIXER:
 505         case RT5682S_STO1_DAC_MIXER:
 506         case RT5682S_A_DAC1_MUX:
 507         case RT5682S_DIG_INF2_DATA:
 508         case RT5682S_REC_MIXER:
 509         case RT5682S_CAL_REC:
 510         case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
 511         case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
 512         case RT5682S_MB_CTRL:
 513         case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
 514         case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
 515         case RT5682S_I2S1_SDP:
 516         case RT5682S_I2S2_SDP:
 517         case RT5682S_ADDA_CLK_1:
 518         case RT5682S_ADDA_CLK_2:
 519         case RT5682S_I2S1_F_DIV_CTRL_1:
 520         case RT5682S_I2S1_F_DIV_CTRL_2:
 521         case RT5682S_TDM_CTRL:
 522         case RT5682S_TDM_ADDA_CTRL_1:
 523         case RT5682S_TDM_ADDA_CTRL_2:
 524         case RT5682S_DATA_SEL_CTRL_1:
 525         case RT5682S_TDM_TCON_CTRL_1:
 526         case RT5682S_TDM_TCON_CTRL_2:
 527         case RT5682S_GLB_CLK:
 528         case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
 529         case RT5682S_PLL_TRACK_11:
 530         case RT5682S_DEPOP_1:
 531         case RT5682S_HP_CHARGE_PUMP_1:
 532         case RT5682S_HP_CHARGE_PUMP_2:
 533         case RT5682S_HP_CHARGE_PUMP_3:
 534         case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
 535         case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
 536         case RT5682S_RC_CLK_CTRL:
 537         case RT5682S_I2S2_M_CLK_CTRL_1:
 538         case RT5682S_I2S2_F_DIV_CTRL_1:
 539         case RT5682S_I2S2_F_DIV_CTRL_2:
 540         case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
 541         case RT5682S_INT_ST_1:
 542         case RT5682S_GPIO_CTRL_1:
 543         case RT5682S_GPIO_CTRL_2:
 544         case RT5682S_GPIO_ST:
 545         case RT5682S_HP_AMP_DET_CTRL_1:
 546         case RT5682S_MID_HP_AMP_DET:
 547         case RT5682S_LOW_HP_AMP_DET:
 548         case RT5682S_DELAY_BUF_CTRL:
 549         case RT5682S_SV_ZCD_1:
 550         case RT5682S_SV_ZCD_2:
 551         case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
 552         case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
 553         case RT5682S_ADC_STO1_HP_CTRL_1:
 554         case RT5682S_ADC_STO1_HP_CTRL_2:
 555         case RT5682S_AJD1_CTRL:
 556         case RT5682S_JD_CTRL_1:
 557         case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
 558         case RT5682S_DAC_ADC_DIG_VOL1:
 559         case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
 560         case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
 561         case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
 562         case RT5682S_CHARGE_PUMP_1:
 563         case RT5682S_DIG_IN_CTRL_1:
 564         case RT5682S_PAD_DRIVING_CTRL:
 565         case RT5682S_CHOP_DAC_1:
 566         case RT5682S_CHOP_DAC_2:
 567         case RT5682S_CHOP_ADC:
 568         case RT5682S_CALIB_ADC_CTRL:
 569         case RT5682S_VOL_TEST:
 570         case RT5682S_SPKVDD_DET_ST:
 571         case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
 572         case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
 573         case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
 574         case RT5682S_STO1_DAC_SIL_DET:
 575         case RT5682S_SIL_PSV_CTRL1:
 576         case RT5682S_SIL_PSV_CTRL2:
 577         case RT5682S_SIL_PSV_CTRL3:
 578         case RT5682S_SIL_PSV_CTRL4:
 579         case RT5682S_SIL_PSV_CTRL5:
 580         case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
 581         case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
 582         case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
 583         case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
 584         case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
 585         case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
 586         case RT5682S_VERSION_ID_HIDE:
 587         case RT5682S_VERSION_ID_CUS:
 588         case RT5682S_SCAN_CTL:
 589         case RT5682S_HP_AMP_DET:
 590         case RT5682S_BIAS_CUR_CTRL_11:
 591         case RT5682S_BIAS_CUR_CTRL_12:
 592         case RT5682S_BIAS_CUR_CTRL_13:
 593         case RT5682S_BIAS_CUR_CTRL_14:
 594         case RT5682S_BIAS_CUR_CTRL_15:
 595         case RT5682S_BIAS_CUR_CTRL_16:
 596         case RT5682S_BIAS_CUR_CTRL_17:
 597         case RT5682S_BIAS_CUR_CTRL_18:
 598         case RT5682S_I2C_TRANS_CTRL:
 599         case RT5682S_DUMMY_7:
 600         case RT5682S_DUMMY_8:
 601         case RT5682S_DMIC_FLOAT_DET:
 602         case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
 603         case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
 604         case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
 605         case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
 606         case RT5682S_CLK_SW_TEST_1:
 607         case RT5682S_CLK_SW_TEST_2:
 608         case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
 609         case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
 610         case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
 611         case RT5682S_EFUSE_TIMING_CTL_1:
 612         case RT5682S_EFUSE_TIMING_CTL_2:
 613         case RT5682S_PILOT_DIG_CTL_1:
 614         case RT5682S_PILOT_DIG_CTL_2:
 615         case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
 616                 return true;
 617         default:
 618                 return false;
 619         }
 620 }
 621
 622 static void rt5682s_reset(struct rt5682s_priv *rt5682s)
 623 {
 624         regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
 625 }
 626
 627 static int rt5682s_button_detect(struct snd_soc_component *component)
 628 {
 629         int btn_type, val;
 630
 631         val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
 632         btn_type = val & 0xfff0;
 633         snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
 634         dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
 635         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
 636                 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
 637
 638         return btn_type;
 639 }
 640
 641 enum {
 642         SAR_PWR_OFF,
 643         SAR_PWR_NORMAL,
 644         SAR_PWR_SAVING,
 645 };
 646
 647 static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
 648 {
 649         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
 650
 651         mutex_lock(&rt5682s->sar_mutex);
 652
 653         switch (mode) {
 654         case SAR_PWR_SAVING:
 655                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
 656                         RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
 657                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 658                         RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
 659                         RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG);
 660                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 661                         RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
 662                         RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
 663                         RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
 664                 usleep_range(5000, 5500);
 665                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 666                         RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
 667                 usleep_range(5000, 5500);
 668                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
 669                         RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
 670                 break;
 671         case SAR_PWR_NORMAL:
 672                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
 673                         RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
 674                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 675                         RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
 676                         RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
 677                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 678                         RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
 679                 usleep_range(5000, 5500);
 680                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 681                         RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
 682                         RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
 683                 break;
 684         case SAR_PWR_OFF:
 685                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 686                         RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
 687                         RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
 688                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 689                         RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
 690                         RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
 691                         RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
 692                 break;
 693         default:
 694                 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
 695                 break;
 696         }
 697
 698         mutex_unlock(&rt5682s->sar_mutex);
 699 }
 700
 701 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
 702 {
 703         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
 704                 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
 705         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 706                 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
 707                 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
 708                 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
 709         snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040);
 710         snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
 711                 RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
 712                 RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
 713         snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
 714                 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
 715 }
 716
 717 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
 718 {
 719         snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
 720                 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
 721         snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
 722                 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
 723         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
 724                 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
 725         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 726                 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
 727                 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
 728                 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
 729 }
 730
 731 /**
 732  * rt5682s_headset_detect - Detect headset.
 733  * @component: SoC audio component device.
 734  * @jack_insert: Jack insert or not.
 735  *
 736  * Detect whether is headset or not when jack inserted.
 737  *
 738  * Returns detect status.
 739  */
 740 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
 741 {
 742         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
 743         unsigned int val, count;
 744         int jack_type = 0;
 745
 746         if (jack_insert) {
 747                 rt5682s_disable_push_button_irq(component);
 748                 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
 749                         RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
 750                         RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
 751                 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
 752                         RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0);
 753                 usleep_range(15000, 20000);
 754                 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
 755                         RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
 756                         RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
 757                 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
 758                         RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
 759                 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365);
 760                 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
 761                         RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
 762                         RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
 763                 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
 764                         RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
 765                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
 766                         RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
 767                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 768                         RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
 769                 usleep_range(45000, 50000);
 770                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 771                         RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
 772
 773                 count = 0;
 774                 do {
 775                         usleep_range(10000, 15000);
 776                         val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
 777                                 & RT5682S_JACK_TYPE_MASK;
 778                         count++;
 779                 } while (val == 0 && count < 50);
 780
 781                 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
 782
 783                 switch (val) {
 784                 case 0x1:
 785                 case 0x2:
 786                         jack_type = SND_JACK_HEADSET;
 787                         snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c);
 788                         snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 789                                 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN);
 790                         snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
 791                                 RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT);
 792                         rt5682s_enable_push_button_irq(component);
 793                         rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
 794                         break;
 795                 default:
 796                         jack_type = SND_JACK_HEADPHONE;
 797                         break;
 798                 }
 799                 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
 800                         RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
 801                         RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
 802                 usleep_range(35000, 40000);
 803         } else {
 804                 rt5682s_sar_power_mode(component, SAR_PWR_OFF);
 805                 rt5682s_disable_push_button_irq(component);
 806                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 807                         RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
 808
 809                 if (!rt5682s->wclk_enabled) {
 810                         snd_soc_component_update_bits(component,
 811                                 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
 812                 }
 813
 814                 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
 815                         RT5682S_PWR_CBJ, 0);
 816                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
 817                         RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
 818                 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
 819                         RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
 820                 jack_type = 0;
 821         }
 822
 823         dev_dbg(component->dev, "jack_type = %d\n", jack_type);
 824
 825         return jack_type;
 826 }
 827
 828 static void rt5682s_jack_detect_handler(struct work_struct *work)
 829 {
 830         struct rt5682s_priv *rt5682s =
 831                 container_of(work, struct rt5682s_priv, jack_detect_work.work);
 832         struct snd_soc_dapm_context *dapm;
 833         int val, btn_type;
 834
 835         if (!rt5682s->component || !rt5682s->component->card ||
 836             !rt5682s->component->card->instantiated) {
 837                 /* card not yet ready, try later */
 838                 mod_delayed_work(system_power_efficient_wq,
 839                                  &rt5682s->jack_detect_work, msecs_to_jiffies(15));
 840                 return;
 841         }
 842
 843         dapm = snd_soc_component_get_dapm(rt5682s->component);
 844
 845         snd_soc_dapm_mutex_lock(dapm);
 846         mutex_lock(&rt5682s->calibrate_mutex);
 847         mutex_lock(&rt5682s->wclk_mutex);
 848
 849         val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
 850                 & RT5682S_JDH_RS_MASK;
 851         if (!val) {
 852                 /* jack in */
 853                 if (rt5682s->jack_type == 0) {
 854                         /* jack was out, report jack type */
 855                         rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
 856                         rt5682s->irq_work_delay_time = 0;
 857                 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
 858                         /* jack is already in, report button event */
 859                         rt5682s->jack_type = SND_JACK_HEADSET;
 860                         btn_type = rt5682s_button_detect(rt5682s->component);
 861                         /**
 862                          * rt5682s can report three kinds of button behavior,
 863                          * one click, double click and hold. However,
 864                          * currently we will report button pressed/released
 865                          * event. So all the three button behaviors are
 866                          * treated as button pressed.
 867                          */
 868                         switch (btn_type) {
 869                         case 0x8000:
 870                         case 0x4000:
 871                         case 0x2000:
 872                                 rt5682s->jack_type |= SND_JACK_BTN_0;
 873                                 break;
 874                         case 0x1000:
 875                         case 0x0800:
 876                         case 0x0400:
 877                                 rt5682s->jack_type |= SND_JACK_BTN_1;
 878                                 break;
 879                         case 0x0200:
 880                         case 0x0100:
 881                         case 0x0080:
 882                                 rt5682s->jack_type |= SND_JACK_BTN_2;
 883                                 break;
 884                         case 0x0040:
 885                         case 0x0020:
 886                         case 0x0010:
 887                                 rt5682s->jack_type |= SND_JACK_BTN_3;
 888                                 break;
 889                         case 0x0000: /* unpressed */
 890                                 break;
 891                         default:
 892                                 dev_err(rt5682s->component->dev,
 893                                         "Unexpected button code 0x%04x\n", btn_type);
 894                                 break;
 895                         }
 896                 }
 897         } else {
 898                 /* jack out */
 899                 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
 900                 rt5682s->irq_work_delay_time = 50;
 901         }
 902
 903         mutex_unlock(&rt5682s->wclk_mutex);
 904         mutex_unlock(&rt5682s->calibrate_mutex);
 905         snd_soc_dapm_mutex_unlock(dapm);
 906
 907         snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
 908                 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
 909                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
 910
 911         if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
 912                 SND_JACK_BTN_2 | SND_JACK_BTN_3))
 913                 schedule_delayed_work(&rt5682s->jd_check_work, 0);
 914         else
 915                 cancel_delayed_work_sync(&rt5682s->jd_check_work);
 916 }
 917
 918 static void rt5682s_jd_check_handler(struct work_struct *work)
 919 {
 920         struct rt5682s_priv *rt5682s =
 921                 container_of(work, struct rt5682s_priv, jd_check_work.work);
 922
 923         if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
 924                 /* jack out */
 925                 schedule_delayed_work(&rt5682s->jack_detect_work, 0);
 926         } else {
 927                 schedule_delayed_work(&rt5682s->jd_check_work, 500);
 928         }
 929 }
 930
 931 static irqreturn_t rt5682s_irq(int irq, void *data)
 932 {
 933         struct rt5682s_priv *rt5682s = data;
 934
 935         mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
 936                 msecs_to_jiffies(rt5682s->irq_work_delay_time));
 937
 938         return IRQ_HANDLED;
 939 }
 940
 941 static int rt5682s_set_jack_detect(struct snd_soc_component *component,
 942                 struct snd_soc_jack *hs_jack, void *data)
 943 {
 944         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
 945         int btndet_delay = 16;
 946
 947         rt5682s->hs_jack = hs_jack;
 948
 949         if (!hs_jack) {
 950                 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
 951                         RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
 952                 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
 953                         RT5682S_POW_JDH, 0);
 954                 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
 955
 956                 return 0;
 957         }
 958
 959         switch (rt5682s->pdata.jd_src) {
 960         case RT5682S_JD1:
 961                 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
 962                         RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
 963                 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
 964                         RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
 965                 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
 966                         RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
 967                         RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
 968                         RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
 969                         RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS);
 970                 regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
 971                         RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
 972                 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
 973                         RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
 974                 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
 975                         RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
 976                 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
 977                         RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
 978                 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
 979                         RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
 980                 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
 981                         RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
 982                         RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
 983                 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
 984                         RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
 985                         (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
 986                 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
 987                         RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
 988                         (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
 989                 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
 990                         RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
 991                         (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
 992                 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
 993                         RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
 994                         (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
 995
 996                 mod_delayed_work(system_power_efficient_wq,
 997                         &rt5682s->jack_detect_work, msecs_to_jiffies(250));
 998                 break;
 999
1000         case RT5682S_JD_NULL:
1001                 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1002                         RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
1003                 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1004                         RT5682S_POW_JDH, 0);
1005                 break;
1006
1007         default:
1008                 dev_warn(component->dev, "Wrong JD source\n");
1009                 break;
1010         }
1011
1012         return 0;
1013 }
1014
1015 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1016 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1017 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1018 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1019
1020 static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
1021         /* DAC Digital Volume */
1022         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
1023                 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
1024
1025         /* CBJ Boost Volume */
1026         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
1027                 RT5682S_BST_CBJ_SFT, 35, 0,  cbj_bst_tlv),
1028
1029         /* ADC Digital Volume Control */
1030         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
1031                 RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
1032         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
1033                 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1034
1035         /* ADC Boost Volume Control */
1036         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
1037                 RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
1038 };
1039
1040 /**
1041  * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1042  * @component: SoC audio component device.
1043  * @filter_mask: mask of filters.
1044  * @clk_src: clock source
1045  *
1046  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1047  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1048  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1049  * ASRC function will track i2s clock and generate a corresponding system clock
1050  * for codec. This function provides an API to select the clock source for a
1051  * set of filters specified by the mask. And the component driver will turn on
1052  * ASRC for these filters if ASRC is selected as their clock source.
1053  */
1054 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1055                 unsigned int filter_mask, unsigned int clk_src)
1056 {
1057         switch (clk_src) {
1058         case RT5682S_CLK_SEL_SYS:
1059         case RT5682S_CLK_SEL_I2S1_ASRC:
1060         case RT5682S_CLK_SEL_I2S2_ASRC:
1061                 break;
1062
1063         default:
1064                 return -EINVAL;
1065         }
1066
1067         if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
1068                 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
1069                         RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1070         }
1071
1072         if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
1073                 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
1074                         RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1075         }
1076
1077         snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
1078                 RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
1079
1080         return 0;
1081 }
1082 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
1083
1084 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
1085                 int target, const int div[], int size)
1086 {
1087         int i;
1088
1089         if (rt5682s->sysclk < target) {
1090                 dev_err(rt5682s->component->dev,
1091                         "sysclk rate %d is too low\n", rt5682s->sysclk);
1092                 return 0;
1093         }
1094
1095         for (i = 0; i < size - 1; i++) {
1096                 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1097                 if (target * div[i] == rt5682s->sysclk)
1098                         return i;
1099                 if (target * div[i + 1] > rt5682s->sysclk) {
1100                         dev_dbg(rt5682s->component->dev,
1101                                 "can't find div for sysclk %d\n", rt5682s->sysclk);
1102                         return i;
1103                 }
1104         }
1105
1106         if (target * div[i] < rt5682s->sysclk)
1107                 dev_err(rt5682s->component->dev,
1108                         "sysclk rate %d is too high\n", rt5682s->sysclk);
1109
1110         return size - 1;
1111 }
1112
1113 static int get_clk_info(int sclk, int rate)
1114 {
1115         int i;
1116         static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1117
1118         if (sclk <= 0 || rate <= 0)
1119                 return -EINVAL;
1120
1121         rate = rate << 8;
1122         for (i = 0; i < ARRAY_SIZE(pd); i++)
1123                 if (sclk == rate * pd[i])
1124                         return i;
1125
1126         return -EINVAL;
1127 }
1128
1129 /**
1130  * set_dmic_clk - Set parameter of dmic.
1131  *
1132  * @w: DAPM widget.
1133  * @kcontrol: The kcontrol of this widget.
1134  * @event: Event id.
1135  *
1136  * Choose dmic clock between 1MHz and 3MHz.
1137  * It is better for clock to approximate 3MHz.
1138  */
1139 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1140                 struct snd_kcontrol *kcontrol, int event)
1141 {
1142         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1143         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1144         int idx, dmic_clk_rate = 3072000;
1145         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1146
1147         if (rt5682s->pdata.dmic_clk_rate)
1148                 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1149
1150         idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div));
1151
1152         snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
1153                 RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT);
1154
1155         return 0;
1156 }
1157
1158 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1159                 struct snd_kcontrol *kcontrol, int event)
1160 {
1161         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1162         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1163         int ref, val, reg, idx;
1164         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1165         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1166
1167         val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
1168                         & RT5682S_GP4_PIN_MASK;
1169
1170         if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1171                 ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1172         else
1173                 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1174
1175         idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
1176
1177         if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1178                 reg = RT5682S_PLL_TRACK_3;
1179         else
1180                 reg = RT5682S_PLL_TRACK_2;
1181
1182         snd_soc_component_update_bits(component, reg,
1183                 RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT);
1184
1185         /* select over sample rate */
1186         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1187                 if (rt5682s->sysclk <= 12288000 * div_o[idx])
1188                         break;
1189         }
1190
1191         snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
1192                 RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
1193                 (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
1194
1195         return 0;
1196 }
1197
1198 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1199                 struct snd_kcontrol *kcontrol, int event)
1200 {
1201         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1202         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1203         unsigned int delay = 50, val;
1204
1205         if (rt5682s->pdata.dmic_delay)
1206                 delay = rt5682s->pdata.dmic_delay;
1207
1208         switch (event) {
1209         case SND_SOC_DAPM_POST_PMU:
1210                 val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
1211                         & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
1212                 if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
1213                         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1214                                 RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
1215                                 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
1216
1217                 /*Add delay to avoid pop noise*/
1218                 msleep(delay);
1219                 break;
1220
1221         case SND_SOC_DAPM_POST_PMD:
1222                 if (!rt5682s->jack_type && !rt5682s->wclk_enabled) {
1223                         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1224                                 RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
1225                 }
1226                 break;
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int set_i2s_clk(struct snd_soc_dapm_widget *w,
1233                 struct snd_kcontrol *kcontrol, int event)
1234 {
1235         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1236         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1237         int pre_div, id;
1238         unsigned int reg, mask, sft;
1239
1240         if (event != SND_SOC_DAPM_PRE_PMU)
1241                 return 0;
1242
1243         if (w->shift == RT5682S_PWR_I2S2_BIT) {
1244                 id = RT5682S_AIF2;
1245                 reg = RT5682S_I2S2_M_CLK_CTRL_1;
1246                 mask = RT5682S_I2S2_M_D_MASK;
1247                 sft = RT5682S_I2S2_M_D_SFT;
1248         } else {
1249                 id = RT5682S_AIF1;
1250                 reg = RT5682S_ADDA_CLK_1;
1251                 mask = RT5682S_I2S_M_D_MASK;
1252                 sft = RT5682S_I2S_M_D_SFT;
1253         }
1254
1255         if (!rt5682s->master[id])
1256                 return 0;
1257
1258         pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1259         if (pre_div < 0) {
1260                 dev_err(component->dev, "get pre_div failed\n");
1261                 return -EINVAL;
1262         }
1263
1264         dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1265                 rt5682s->lrck[id], pre_div, id);
1266         snd_soc_component_update_bits(component, reg, mask, pre_div << sft);
1267
1268         return 0;
1269 }
1270
1271 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
1272                 struct snd_soc_dapm_widget *sink)
1273 {
1274         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1275         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1276
1277         if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1278             (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1279                 return 1;
1280
1281         return 0;
1282 }
1283
1284 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
1285                 struct snd_soc_dapm_widget *sink)
1286 {
1287         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1288         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1289
1290         if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1291                 return 1;
1292
1293         return 0;
1294 }
1295
1296 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1297                 struct snd_soc_dapm_widget *sink)
1298 {
1299         unsigned int reg, sft, val;
1300         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1301
1302         switch (w->shift) {
1303         case RT5682S_ADC_STO1_ASRC_SFT:
1304                 reg = RT5682S_PLL_TRACK_3;
1305                 sft = RT5682S_FILTER_CLK_SEL_SFT;
1306                 break;
1307         case RT5682S_DAC_STO1_ASRC_SFT:
1308                 reg = RT5682S_PLL_TRACK_2;
1309                 sft = RT5682S_FILTER_CLK_SEL_SFT;
1310                 break;
1311         default:
1312                 return 0;
1313         }
1314
1315         val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
1316         switch (val) {
1317         case RT5682S_CLK_SEL_I2S1_ASRC:
1318         case RT5682S_CLK_SEL_I2S2_ASRC:
1319                 return 1;
1320         default:
1321                 return 0;
1322         }
1323 }
1324
1325 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
1326                 struct snd_kcontrol *kcontrol, int event)
1327 {
1328         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1329
1330         switch (event) {
1331         case SND_SOC_DAPM_POST_PMU:
1332                 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1333                         RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
1334                         RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
1335                 usleep_range(15000, 20000);
1336                 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1337                         RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1338                         RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
1339                         RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1340                         RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
1341                 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666);
1342                 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a);
1343
1344                 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1345                         RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1346                         RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
1347                         RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
1348                 usleep_range(5000, 10000);
1349                 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1350                         RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
1351                 break;
1352
1353         case SND_SOC_DAPM_POST_PMD:
1354                 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1355                         RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1356                         RT5682S_HPO_SEL_IP_EN_SW, 0);
1357                 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1358                         RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
1359                 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1360                         RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1361                         RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0);
1362                 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1363                         RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0);
1364                 break;
1365         }
1366
1367         return 0;
1368 }
1369
1370 static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
1371                 struct snd_kcontrol *kcontrol, int event)
1372 {
1373         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1374         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1375         unsigned int delay = 0;
1376
1377         if (rt5682s->pdata.amic_delay)
1378                 delay = rt5682s->pdata.amic_delay;
1379
1380         switch (event) {
1381         case SND_SOC_DAPM_POST_PMU:
1382                 msleep(delay);
1383                 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1384                         RT5682S_L_MUTE, 0);
1385                 break;
1386         case SND_SOC_DAPM_PRE_PMD:
1387                 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1388                         RT5682S_L_MUTE, RT5682S_L_MUTE);
1389                 break;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int sar_power_event(struct snd_soc_dapm_widget *w,
1396                 struct snd_kcontrol *kcontrol, int event)
1397 {
1398         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1399         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1400
1401         if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1402                 return 0;
1403
1404         switch (event) {
1405         case SND_SOC_DAPM_PRE_PMU:
1406                 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL);
1407                 break;
1408         case SND_SOC_DAPM_POST_PMD:
1409                 rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
1410                 break;
1411         }
1412
1413         return 0;
1414 }
1415
1416 /* Interface data select */
1417 static const char * const rt5682s_data_select[] = {
1418         "L/R", "R/L", "L/L", "R/R"
1419 };
1420
1421 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
1422         RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
1423
1424 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1425         RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
1426
1427 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1428         RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
1429
1430 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1431         RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
1432
1433 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1434         RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
1435
1436 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
1437         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
1438
1439 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
1440         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
1441
1442 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
1443         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
1444
1445 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
1446         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
1447
1448 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
1449         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
1450
1451 /* Digital Mixer */
1452 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
1453         SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1454                         RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
1455         SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1456                         RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
1457 };
1458
1459 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
1460         SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1461                         RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
1462         SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1463                         RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
1464 };
1465
1466 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
1467         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1468                         RT5682S_M_ADCMIX_L_SFT, 1, 1),
1469         SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1470                         RT5682S_M_DAC1_L_SFT, 1, 1),
1471 };
1472
1473 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
1474         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1475                         RT5682S_M_ADCMIX_R_SFT, 1, 1),
1476         SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1477                         RT5682S_M_DAC1_R_SFT, 1, 1),
1478 };
1479
1480 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
1481         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1482                         RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
1483         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1484                         RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
1485 };
1486
1487 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
1488         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1489                         RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
1490         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1491                         RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
1492 };
1493
1494 /* Analog Input Mixer */
1495 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
1496         SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1497                         RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
1498 };
1499
1500 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
1501         SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1502                         RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
1503 };
1504
1505 /* STO1 ADC1 Source */
1506 /* MX-26 [13] [5] */
1507 static const char * const rt5682s_sto1_adc1_src[] = {
1508         "DAC MIX", "ADC"
1509 };
1510
1511 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
1512         RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
1513
1514 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
1515         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
1516
1517 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
1518         RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
1519
1520 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
1521         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
1522
1523 /* STO1 ADC Source */
1524 /* MX-26 [11:10] [3:2] */
1525 static const char * const rt5682s_sto1_adc_src[] = {
1526         "ADC1 L", "ADC1 R"
1527 };
1528
1529 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
1530         RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
1531
1532 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
1533         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
1534
1535 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
1536         RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
1537
1538 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
1539         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
1540
1541 /* STO1 ADC2 Source */
1542 /* MX-26 [12] [4] */
1543 static const char * const rt5682s_sto1_adc2_src[] = {
1544         "DAC MIX", "DMIC"
1545 };
1546
1547 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
1548         RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
1549
1550 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
1551         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
1552
1553 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
1554         RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
1555
1556 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
1557         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
1558
1559 /* MX-79 [6:4] I2S1 ADC data location */
1560 static const unsigned int rt5682s_if1_adc_slot_values[] = {
1561         0, 2, 4, 6,
1562 };
1563
1564 static const char * const rt5682s_if1_adc_slot_src[] = {
1565         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1566 };
1567
1568 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
1569         RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
1570         rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
1571
1572 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
1573         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
1574
1575 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1576 /* MX-2B [4], MX-2B [0]*/
1577 static const char * const rt5682s_alg_dac1_src[] = {
1578         "Stereo1 DAC Mixer", "DAC1"
1579 };
1580
1581 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
1582         RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
1583
1584 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
1585         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
1586
1587 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
1588         RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
1589
1590 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
1591         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
1592
1593 static const unsigned int rt5682s_adcdat_pin_values[] = {
1594         1, 3,
1595 };
1596
1597 static const char * const rt5682s_adcdat_pin_select[] = {
1598         "ADCDAT1", "ADCDAT2",
1599 };
1600
1601 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
1602         RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
1603         rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
1604
1605 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
1606         SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
1607
1608 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
1609         SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
1610                 RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
1611         SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
1612                 RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
1613         SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
1614                 RT5682S_PWR_LDO_BIT, 0, NULL, 0),
1615
1616         /* PLL Powers */
1617         SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
1618                 RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
1619         SND_SOC_DAPM_SUPPLY_S("PLLB_LDO", 0, RT5682S_PWR_ANLG_3,
1620                 RT5682S_PWR_LDO_PLLB_BIT, 0, NULL, 0),
1621         SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
1622                 RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
1623         SND_SOC_DAPM_SUPPLY_S("PLLB_BIAS", 0, RT5682S_PWR_ANLG_3,
1624                 RT5682S_PWR_BIAS_PLLB_BIT, 0, NULL, 0),
1625         SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1626                 RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
1627         SND_SOC_DAPM_SUPPLY_S("PLLB", 0, RT5682S_PWR_ANLG_3,
1628                 RT5682S_PWR_PLLB_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1629         SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
1630                 RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
1631         SND_SOC_DAPM_SUPPLY_S("PLLB_RST", 1, RT5682S_PWR_ANLG_3,
1632                 RT5682S_RSTB_PLLB_BIT, 0, NULL, 0),
1633
1634         /* ASRC */
1635         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1636                 RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1637         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1638                 RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1639         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
1640                 RT5682S_AD_ASRC_SFT, 0, NULL, 0),
1641         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
1642                 RT5682S_DA_ASRC_SFT, 0, NULL, 0),
1643         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1644                 RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
1645
1646         /* Input Side */
1647         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
1648                 RT5682S_PWR_MB1_BIT, 0, NULL, 0),
1649         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
1650                 RT5682S_PWR_MB2_BIT, 0, NULL, 0),
1651
1652         /* Input Lines */
1653         SND_SOC_DAPM_INPUT("DMIC L1"),
1654         SND_SOC_DAPM_INPUT("DMIC R1"),
1655
1656         SND_SOC_DAPM_INPUT("IN1P"),
1657
1658         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1659                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1660         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
1661                 set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1662
1663         /* Boost */
1664         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
1665
1666         /* REC Mixer */
1667         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
1668                 ARRAY_SIZE(rt5682s_rec1_l_mix)),
1669         SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
1670                 ARRAY_SIZE(rt5682s_rec1_r_mix)),
1671         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
1672                 RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
1673         SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
1674                 RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
1675
1676         /* ADCs */
1677         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1678         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1679
1680         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
1681                 RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
1682         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
1683                 RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
1684         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
1685                 RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
1686
1687         /* ADC Mux */
1688         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1689                 &rt5682s_sto1_adc1l_mux),
1690         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1691                 &rt5682s_sto1_adc1r_mux),
1692         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1693                 &rt5682s_sto1_adc2l_mux),
1694         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1695                 &rt5682s_sto1_adc2r_mux),
1696         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1697                 &rt5682s_sto1_adcl_mux),
1698         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1699                 &rt5682s_sto1_adcr_mux),
1700         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1701                 &rt5682s_if1_adc_slot_mux),
1702
1703         /* ADC Mixer */
1704         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
1705                 RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1706         SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1707                 rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
1708                 rt5682s_stereo1_adc_mixl_event,
1709                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1710         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
1711                 RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
1712                 ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
1713
1714         /* ADC PGA */
1715         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1716
1717         /* Digital Interface */
1718         SND_SOC_DAPM_SUPPLY("I2S1", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S1_BIT,
1719                 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU),
1720         SND_SOC_DAPM_SUPPLY("I2S2", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S2_BIT,
1721                 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU),
1722         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1723         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1724
1725         /* Digital Interface Select */
1726         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1727                 &rt5682s_if1_01_adc_swap_mux),
1728         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1729                 &rt5682s_if1_23_adc_swap_mux),
1730         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1731                 &rt5682s_if1_45_adc_swap_mux),
1732         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1733                 &rt5682s_if1_67_adc_swap_mux),
1734         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1735                 &rt5682s_if2_adc_swap_mux),
1736
1737         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
1738
1739         /* Audio Interface */
1740         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
1741                 RT5682S_SEL_ADCDAT_SFT, 1),
1742         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
1743                 RT5682S_I2S2_PIN_CFG_SFT, 1),
1744         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1745
1746         /* Output Side */
1747         /* DAC mixer before sound effect  */
1748         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1749                 rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
1750         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1751                 rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
1752
1753         /* DAC channel Mux */
1754         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
1755         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
1756
1757         /* DAC Mixer */
1758         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
1759                 RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1760         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1761                 rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
1762         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1763                 rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
1764
1765         /* DACs */
1766         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
1767         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
1768
1769         /* HPO */
1770         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
1771                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1772
1773         /* CLK DET */
1774         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
1775                 RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
1776         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
1777                 RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
1778         SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
1779                 RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
1780
1781         /* SAR */
1782         SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
1783                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1784
1785         /* Output Lines */
1786         SND_SOC_DAPM_OUTPUT("HPOL"),
1787         SND_SOC_DAPM_OUTPUT("HPOR"),
1788 };
1789
1790 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
1791         /*PLL*/
1792         {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1793         {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1794         {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1795         {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1796         {"PLLA", NULL, "PLLA_LDO"},
1797         {"PLLA", NULL, "PLLA_BIAS"},
1798         {"PLLA", NULL, "PLLA_RST"},
1799         {"PLLB", NULL, "PLLB_LDO"},
1800         {"PLLB", NULL, "PLLB_BIAS"},
1801         {"PLLB", NULL, "PLLB_RST"},
1802
1803         /*ASRC*/
1804         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1805         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1806         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1807         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1808         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1809         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1810
1811         {"CLKDET SYS", NULL, "MCLK0 DET PWR"},
1812
1813         {"BST1 CBJ", NULL, "IN1P"},
1814         {"BST1 CBJ", NULL, "SAR"},
1815
1816         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1817         {"RECMIX1L", NULL, "RECMIX1L Power"},
1818         {"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
1819         {"RECMIX1R", NULL, "RECMIX1R Power"},
1820
1821         {"ADC1 L", NULL, "RECMIX1L"},
1822         {"ADC1 L", NULL, "ADC1 L Power"},
1823         {"ADC1 L", NULL, "ADC1 clock"},
1824         {"ADC1 R", NULL, "RECMIX1R"},
1825         {"ADC1 R", NULL, "ADC1 R Power"},
1826         {"ADC1 R", NULL, "ADC1 clock"},
1827
1828         {"DMIC L1", NULL, "DMIC CLK"},
1829         {"DMIC L1", NULL, "DMIC1 Power"},
1830         {"DMIC R1", NULL, "DMIC CLK"},
1831         {"DMIC R1", NULL, "DMIC1 Power"},
1832         {"DMIC CLK", NULL, "DMIC ASRC"},
1833
1834         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1835         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1836         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1837         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1838
1839         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1840         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1841         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1842         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1843
1844         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1845         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1846         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1847         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1848
1849         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1850         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1851         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1852
1853         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1854         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1855         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1856
1857         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1858         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1859
1860         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1861         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1862         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1863         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1864         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1865         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1866         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1867         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1868         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1869         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1870         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1871         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1872         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1873         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1874         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1875         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1876
1877         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1878         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1879         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1880         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1881         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1882         {"AIF1TX", NULL, "I2S1"},
1883         {"AIF1TX", NULL, "ADCDAT Mux"},
1884         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1885         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1886         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1887         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1888         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1889         {"AIF2TX", NULL, "ADCDAT Mux"},
1890
1891         {"IF1 DAC1 L", NULL, "AIF1RX"},
1892         {"IF1 DAC1 L", NULL, "I2S1"},
1893         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1894         {"IF1 DAC1 R", NULL, "AIF1RX"},
1895         {"IF1 DAC1 R", NULL, "I2S1"},
1896         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1897
1898         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1899         {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1900         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1901         {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1902
1903         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1904         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1905
1906         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1907         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1908
1909         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1910         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1911         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1912         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1913
1914         {"DAC L1", NULL, "DAC L1 Source"},
1915         {"DAC R1", NULL, "DAC R1 Source"},
1916
1917         {"HP Amp", NULL, "DAC L1"},
1918         {"HP Amp", NULL, "DAC R1"},
1919         {"HP Amp", NULL, "CLKDET SYS"},
1920         {"HP Amp", NULL, "SAR"},
1921
1922         {"HPOL", NULL, "HP Amp"},
1923         {"HPOR", NULL, "HP Amp"},
1924 };
1925
1926 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1927                 unsigned int rx_mask, int slots, int slot_width)
1928 {
1929         struct snd_soc_component *component = dai->component;
1930         unsigned int cl, val = 0;
1931
1932         if (tx_mask || rx_mask)
1933                 snd_soc_component_update_bits(component,
1934                         RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
1935         else
1936                 snd_soc_component_update_bits(component,
1937                         RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0);
1938
1939         switch (slots) {
1940         case 4:
1941                 val |= RT5682S_TDM_TX_CH_4;
1942                 val |= RT5682S_TDM_RX_CH_4;
1943                 break;
1944         case 6:
1945                 val |= RT5682S_TDM_TX_CH_6;
1946                 val |= RT5682S_TDM_RX_CH_6;
1947                 break;
1948         case 8:
1949                 val |= RT5682S_TDM_TX_CH_8;
1950                 val |= RT5682S_TDM_RX_CH_8;
1951                 break;
1952         case 2:
1953                 break;
1954         default:
1955                 return -EINVAL;
1956         }
1957
1958         snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
1959                 RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK, val);
1960
1961         switch (slot_width) {
1962         case 8:
1963                 if (tx_mask || rx_mask)
1964                         return -EINVAL;
1965                 cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
1966                 break;
1967         case 16:
1968                 val = RT5682S_TDM_CL_16;
1969                 cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
1970                 break;
1971         case 20:
1972                 val = RT5682S_TDM_CL_20;
1973                 cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
1974                 break;
1975         case 24:
1976                 val = RT5682S_TDM_CL_24;
1977                 cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
1978                 break;
1979         case 32:
1980                 val = RT5682S_TDM_CL_32;
1981                 cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
1982                 break;
1983         default:
1984                 return -EINVAL;
1985         }
1986
1987         snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
1988                 RT5682S_TDM_CL_MASK, val);
1989         snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
1990                 RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl);
1991
1992         return 0;
1993 }
1994
1995 static int rt5682s_hw_params(struct snd_pcm_substream *substream,
1996                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1997 {
1998         struct snd_soc_component *component = dai->component;
1999         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2000         unsigned int len_1 = 0, len_2 = 0;
2001         int frame_size;
2002
2003         rt5682s->lrck[dai->id] = params_rate(params);
2004
2005         frame_size = snd_soc_params_to_frame_size(params);
2006         if (frame_size < 0) {
2007                 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2008                 return -EINVAL;
2009         }
2010
2011         switch (params_width(params)) {
2012         case 16:
2013                 break;
2014         case 20:
2015                 len_1 |= RT5682S_I2S1_DL_20;
2016                 len_2 |= RT5682S_I2S2_DL_20;
2017                 break;
2018         case 24:
2019                 len_1 |= RT5682S_I2S1_DL_24;
2020                 len_2 |= RT5682S_I2S2_DL_24;
2021                 break;
2022         case 32:
2023                 len_1 |= RT5682S_I2S1_DL_32;
2024                 len_2 |= RT5682S_I2S2_DL_24;
2025                 break;
2026         case 8:
2027                 len_1 |= RT5682S_I2S2_DL_8;
2028                 len_2 |= RT5682S_I2S2_DL_8;
2029                 break;
2030         default:
2031                 return -EINVAL;
2032         }
2033
2034         switch (dai->id) {
2035         case RT5682S_AIF1:
2036                 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2037                         RT5682S_I2S1_DL_MASK, len_1);
2038                 if (params_channels(params) == 1) /* mono mode */
2039                         snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2040                                 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
2041                 else
2042                         snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2043                                 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
2044                 break;
2045         case RT5682S_AIF2:
2046                 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2047                         RT5682S_I2S2_DL_MASK, len_2);
2048                 if (params_channels(params) == 1) /* mono mode */
2049                         snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2050                                 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
2051                 else
2052                         snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2053                                 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
2054                 break;
2055         default:
2056                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2057                 return -EINVAL;
2058         }
2059
2060         return 0;
2061 }
2062
2063 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2064 {
2065         struct snd_soc_component *component = dai->component;
2066         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2067         unsigned int reg_val = 0, tdm_ctrl = 0;
2068
2069         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2070         case SND_SOC_DAIFMT_CBM_CFM:
2071                 rt5682s->master[dai->id] = 1;
2072                 break;
2073         case SND_SOC_DAIFMT_CBS_CFS:
2074                 rt5682s->master[dai->id] = 0;
2075                 break;
2076         default:
2077                 return -EINVAL;
2078         }
2079
2080         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2081         case SND_SOC_DAIFMT_NB_NF:
2082                 break;
2083         case SND_SOC_DAIFMT_IB_NF:
2084                 reg_val |= RT5682S_I2S_BP_INV;
2085                 tdm_ctrl |= RT5682S_TDM_S_BP_INV;
2086                 break;
2087         case SND_SOC_DAIFMT_NB_IF:
2088                 if (dai->id == RT5682S_AIF1)
2089                         tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
2090                 else
2091                         return -EINVAL;
2092                 break;
2093         case SND_SOC_DAIFMT_IB_IF:
2094                 if (dai->id == RT5682S_AIF1)
2095                         tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
2096                                 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
2097                 else
2098                         return -EINVAL;
2099                 break;
2100         default:
2101                 return -EINVAL;
2102         }
2103
2104         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2105         case SND_SOC_DAIFMT_I2S:
2106                 break;
2107         case SND_SOC_DAIFMT_LEFT_J:
2108                 reg_val |= RT5682S_I2S_DF_LEFT;
2109                 tdm_ctrl |= RT5682S_TDM_DF_LEFT;
2110                 break;
2111         case SND_SOC_DAIFMT_DSP_A:
2112                 reg_val |= RT5682S_I2S_DF_PCM_A;
2113                 tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
2114                 break;
2115         case SND_SOC_DAIFMT_DSP_B:
2116                 reg_val |= RT5682S_I2S_DF_PCM_B;
2117                 tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
2118                 break;
2119         default:
2120                 return -EINVAL;
2121         }
2122
2123         switch (dai->id) {
2124         case RT5682S_AIF1:
2125                 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2126                         RT5682S_I2S_DF_MASK, reg_val);
2127                 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2128                         RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
2129                         RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
2130                         RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
2131                         tdm_ctrl | rt5682s->master[dai->id]);
2132                 break;
2133         case RT5682S_AIF2:
2134                 if (rt5682s->master[dai->id] == 0)
2135                         reg_val |= RT5682S_I2S2_MS_S;
2136                 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2137                         RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
2138                         RT5682S_I2S_DF_MASK, reg_val);
2139                 break;
2140         default:
2141                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2142                 return -EINVAL;
2143         }
2144         return 0;
2145 }
2146
2147 static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
2148                 int clk_id, int source, unsigned int freq, int dir)
2149 {
2150         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2151         unsigned int src = 0;
2152
2153         if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2154                 return 0;
2155
2156         switch (clk_id) {
2157         case RT5682S_SCLK_S_MCLK:
2158                 src = RT5682S_CLK_SRC_MCLK;
2159                 break;
2160         case RT5682S_SCLK_S_PLL1:
2161                 src = RT5682S_CLK_SRC_PLL1;
2162                 break;
2163         case RT5682S_SCLK_S_PLL2:
2164                 src = RT5682S_CLK_SRC_PLL2;
2165                 break;
2166         case RT5682S_SCLK_S_RCCLK:
2167                 src = RT5682S_CLK_SRC_RCCLK;
2168                 break;
2169         default:
2170                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2171                 return -EINVAL;
2172         }
2173
2174         snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2175                 RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT);
2176         snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
2177                 RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT);
2178         snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
2179                 RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT);
2180
2181         rt5682s->sysclk = freq;
2182         rt5682s->sysclk_src = clk_id;
2183
2184         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2185                 freq, clk_id);
2186
2187         return 0;
2188 }
2189
2190 static const struct pll_calc_map plla_table[] = {
2191         {2048000, 24576000, 0, 46, 2, true, false, false, false},
2192         {256000, 24576000, 0, 382, 2, true, false, false, false},
2193         {512000, 24576000, 0, 190, 2, true, false, false, false},
2194         {4096000, 24576000, 0, 22, 2, true, false, false, false},
2195         {1024000, 24576000, 0, 94, 2, true, false, false, false},
2196         {11289600, 22579200, 1, 22, 2, false, false, false, false},
2197         {1411200, 22579200, 0, 62, 2, true, false, false, false},
2198         {2822400, 22579200, 0, 30, 2, true, false, false, false},
2199         {12288000, 24576000, 1, 22, 2, false, false, false, false},
2200         {1536000, 24576000, 0, 62, 2, true, false, false, false},
2201         {3072000, 24576000, 0, 30, 2, true, false, false, false},
2202         {24576000, 49152000, 4, 22, 0, false, false, false, false},
2203         {3072000, 49152000, 0, 30, 0, true, false, false, false},
2204         {6144000, 49152000, 0, 30, 0, false, false, false, false},
2205         {49152000, 98304000, 10, 22, 0, false, true, false, false},
2206         {6144000, 98304000, 0, 30, 0, false, true, false, false},
2207         {12288000, 98304000, 1, 22, 0, false, true, false, false},
2208         {48000000, 3840000, 10, 22, 23, false, false, false, false},
2209         {24000000, 3840000, 4, 22, 23, false, false, false, false},
2210         {19200000, 3840000, 3, 23, 23, false, false, false, false},
2211         {38400000, 3840000, 8, 23, 23, false, false, false, false},
2212 };
2213
2214 static const struct pll_calc_map pllb_table[] = {
2215         {48000000, 24576000, 8, 6, 3, false, false, false, false},
2216         {48000000, 22579200, 23, 12, 3, false, false, false, true},
2217         {24000000, 24576000, 3, 6, 3, false, false, false, false},
2218         {24000000, 22579200, 23, 26, 3, false, false, false, true},
2219         {19200000, 24576000, 2, 6, 3, false, false, false, false},
2220         {19200000, 22579200, 3, 5, 3, false, false, false, true},
2221         {38400000, 24576000, 6, 6, 3, false, false, false, false},
2222         {38400000, 22579200, 8, 5, 3, false, false, false, true},
2223         {3840000, 49152000, 0, 6, 0, true, false, false, false},
2224 };
2225
2226 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
2227                 struct pll_calc_map *a, struct pll_calc_map *b)
2228 {
2229         int i, j;
2230
2231         /* Look at PLLA table */
2232         for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
2233                 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
2234                         memcpy(a, plla_table + i, sizeof(*a));
2235                         return USE_PLLA;
2236                 }
2237         }
2238
2239         /* Look at PLLB table */
2240         for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
2241                 if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
2242                         memcpy(b, pllb_table + i, sizeof(*b));
2243                         return USE_PLLB;
2244                 }
2245         }
2246
2247         /* Find a combination of PLLA & PLLB */
2248         for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2249                 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
2250                         for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2251                                 if (pllb_table[j].freq_in == 3840000 &&
2252                                         pllb_table[j].freq_out == f_out) {
2253                                         memcpy(a, plla_table + i, sizeof(*a));
2254                                         memcpy(b, pllb_table + j, sizeof(*b));
2255                                         return USE_PLLAB;
2256                                 }
2257                         }
2258                 }
2259         }
2260
2261         return -EINVAL;
2262 }
2263
2264 static int rt5682s_set_component_pll(struct snd_soc_component *component,
2265                 int pll_id, int source, unsigned int freq_in,
2266                 unsigned int freq_out)
2267 {
2268         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2269         struct pll_calc_map a_map, b_map;
2270
2271         if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2272             freq_out == rt5682s->pll_out[pll_id])
2273                 return 0;
2274
2275         if (!freq_in || !freq_out) {
2276                 dev_dbg(component->dev, "PLL disabled\n");
2277                 rt5682s->pll_in[pll_id] = 0;
2278                 rt5682s->pll_out[pll_id] = 0;
2279                 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2280                         RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
2281                 return 0;
2282         }
2283
2284         switch (source) {
2285         case RT5682S_PLL_S_MCLK:
2286                 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2287                         RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
2288                 break;
2289         case RT5682S_PLL_S_BCLK1:
2290                 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2291                         RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
2292                 break;
2293         default:
2294                 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2295                 return -EINVAL;
2296         }
2297
2298         rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
2299                                                         &a_map, &b_map);
2300
2301         if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2302             (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2303                                         rt5682s->pll_comb == USE_PLLAB))) {
2304                 dev_dbg(component->dev,
2305                         "Supported freq conversion for PLL%d:(%d->%d): %d\n",
2306                         pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2307         } else {
2308                 dev_err(component->dev,
2309                         "Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2310                         pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2311                 return -EINVAL;
2312         }
2313
2314         if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2315                 dev_dbg(component->dev,
2316                         "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
2317                         a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
2318                         (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
2319                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
2320                         RT5682S_PLLA_N_MASK, a_map.n);
2321                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
2322                         RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
2323                         a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
2324                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2325                         RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
2326                         a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
2327                         a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
2328         }
2329
2330         if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2331                 dev_dbg(component->dev,
2332                         "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
2333                         b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
2334                         (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
2335                         b_map.byp_ps, b_map.sel_ps);
2336                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
2337                         RT5682S_PLLB_N_MASK, b_map.n);
2338                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
2339                         RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
2340                         b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
2341                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2342                         RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
2343                         RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
2344                         b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
2345                         b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
2346                         b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
2347                         b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
2348         }
2349
2350         if (rt5682s->pll_comb == USE_PLLB)
2351                 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
2352                         RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
2353
2354         rt5682s->pll_in[pll_id] = freq_in;
2355         rt5682s->pll_out[pll_id] = freq_out;
2356         rt5682s->pll_src[pll_id] = source;
2357
2358         return 0;
2359 }
2360
2361 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
2362                 unsigned int ratio)
2363 {
2364         struct snd_soc_component *component = dai->component;
2365         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2366
2367         rt5682s->bclk[dai->id] = ratio;
2368
2369         switch (ratio) {
2370         case 256:
2371                 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2372                         RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
2373                 break;
2374         case 128:
2375                 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2376                         RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
2377                 break;
2378         case 64:
2379                 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2380                         RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
2381                 break;
2382         case 32:
2383                 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2384                         RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
2385                 break;
2386         default:
2387                 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2388                 return -EINVAL;
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2395 {
2396         struct snd_soc_component *component = dai->component;
2397         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2398
2399         rt5682s->bclk[dai->id] = ratio;
2400
2401         switch (ratio) {
2402         case 64:
2403                 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2404                         RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
2405                 break;
2406         case 32:
2407                 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2408                         RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
2409                 break;
2410         default:
2411                 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2412                 return -EINVAL;
2413         }
2414
2415         return 0;
2416 }
2417
2418 static int rt5682s_set_bias_level(struct snd_soc_component *component,
2419                 enum snd_soc_bias_level level)
2420 {
2421         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2422
2423         switch (level) {
2424         case SND_SOC_BIAS_PREPARE:
2425                 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2426                         RT5682S_PWR_LDO, RT5682S_PWR_LDO);
2427                 break;
2428         case SND_SOC_BIAS_STANDBY:
2429                 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2430                         RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2431                 break;
2432         case SND_SOC_BIAS_OFF:
2433                 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2434                         RT5682S_DIG_GATE_CTRL | RT5682S_PWR_LDO, 0);
2435                 break;
2436         case SND_SOC_BIAS_ON:
2437                 break;
2438         }
2439
2440         return 0;
2441 }
2442
2443 #ifdef CONFIG_COMMON_CLK
2444 #define CLK_PLL2_FIN 48000000
2445 #define CLK_48 48000
2446 #define CLK_44 44100
2447
2448 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
2449 {
2450         if (!rt5682s->master[RT5682S_AIF1]) {
2451                 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2452                 return false;
2453         }
2454         return true;
2455 }
2456
2457 static int rt5682s_wclk_prepare(struct clk_hw *hw)
2458 {
2459         struct rt5682s_priv *rt5682s =
2460                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2461         struct snd_soc_component *component = rt5682s->component;
2462         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2463
2464         if (!rt5682s_clk_check(rt5682s))
2465                 return -EINVAL;
2466
2467         mutex_lock(&rt5682s->wclk_mutex);
2468
2469         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2470                 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB,
2471                 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
2472         usleep_range(15000, 20000);
2473         snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2474                 RT5682S_PWR_FV2, RT5682S_PWR_FV2);
2475
2476         rt5682s->wclk_enabled = 1;
2477
2478         mutex_unlock(&rt5682s->wclk_mutex);
2479
2480         snd_soc_dapm_mutex_lock(dapm);
2481
2482         snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2483         /* Only need to power PLLB due to the rate set restriction */
2484         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLLB");
2485         snd_soc_dapm_sync_unlocked(dapm);
2486
2487         snd_soc_dapm_mutex_unlock(dapm);
2488
2489         return 0;
2490 }
2491
2492 static void rt5682s_wclk_unprepare(struct clk_hw *hw)
2493 {
2494         struct rt5682s_priv *rt5682s =
2495                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2496         struct snd_soc_component *component = rt5682s->component;
2497         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2498
2499         if (!rt5682s_clk_check(rt5682s))
2500                 return;
2501
2502         mutex_lock(&rt5682s->wclk_mutex);
2503
2504         if (!rt5682s->jack_type)
2505                 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2506                         RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0);
2507
2508         rt5682s->wclk_enabled = 0;
2509
2510         mutex_unlock(&rt5682s->wclk_mutex);
2511
2512         snd_soc_dapm_mutex_lock(dapm);
2513
2514         snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2515         snd_soc_dapm_disable_pin_unlocked(dapm, "PLLB");
2516         snd_soc_dapm_sync_unlocked(dapm);
2517
2518         snd_soc_dapm_mutex_unlock(dapm);
2519 }
2520
2521 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
2522                                              unsigned long parent_rate)
2523 {
2524         struct rt5682s_priv *rt5682s =
2525                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2526         struct snd_soc_component *component = rt5682s->component;
2527         const char * const clk_name = clk_hw_get_name(hw);
2528
2529         if (!rt5682s_clk_check(rt5682s))
2530                 return 0;
2531         /*
2532          * Only accept to set wclk rate to 44.1k or 48kHz.
2533          */
2534         if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2535             rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2536                 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2537                         __func__, clk_name, CLK_44, CLK_48);
2538                 return 0;
2539         }
2540
2541         return rt5682s->lrck[RT5682S_AIF1];
2542 }
2543
2544 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2545                                    unsigned long *parent_rate)
2546 {
2547         struct rt5682s_priv *rt5682s =
2548                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2549         struct snd_soc_component *component = rt5682s->component;
2550         const char * const clk_name = clk_hw_get_name(hw);
2551
2552         if (!rt5682s_clk_check(rt5682s))
2553                 return -EINVAL;
2554         /*
2555          * Only accept to set wclk rate to 44.1k or 48kHz.
2556          * It will force to 48kHz if not both.
2557          */
2558         if (rate != CLK_48 && rate != CLK_44) {
2559                 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2560                         __func__, clk_name, CLK_44, CLK_48);
2561                 rate = CLK_48;
2562         }
2563
2564         return rate;
2565 }
2566
2567 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2568                                 unsigned long parent_rate)
2569 {
2570         struct rt5682s_priv *rt5682s =
2571                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2572         struct snd_soc_component *component = rt5682s->component;
2573         struct clk *parent_clk;
2574         const char * const clk_name = clk_hw_get_name(hw);
2575         unsigned int clk_pll2_fout;
2576
2577         if (!rt5682s_clk_check(rt5682s))
2578                 return -EINVAL;
2579
2580         /*
2581          * Whether the wclk's parent clk (mclk) exists or not, please ensure
2582          * it is fixed or set to 48MHz before setting wclk rate. It's a
2583          * temporary limitation. Only accept 48MHz clk as the clk provider.
2584          *
2585          * It will set the codec anyway by assuming mclk is 48MHz.
2586          */
2587         parent_clk = clk_get_parent(hw->clk);
2588         if (!parent_clk)
2589                 dev_warn(component->dev,
2590                         "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2591                         CLK_PLL2_FIN);
2592
2593         if (parent_rate != CLK_PLL2_FIN)
2594                 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2595                         clk_name, CLK_PLL2_FIN);
2596
2597         /*
2598          * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2599          * PLL2 is needed.
2600          */
2601         clk_pll2_fout = rate * 512;
2602         rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
2603                 CLK_PLL2_FIN, clk_pll2_fout);
2604
2605         rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0,
2606                 clk_pll2_fout, SND_SOC_CLOCK_IN);
2607
2608         rt5682s->lrck[RT5682S_AIF1] = rate;
2609
2610         return 0;
2611 }
2612
2613 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
2614                                              unsigned long parent_rate)
2615 {
2616         struct rt5682s_priv *rt5682s =
2617                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2618         struct snd_soc_component *component = rt5682s->component;
2619         unsigned int bclks_per_wclk;
2620
2621         bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
2622
2623         switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
2624         case RT5682S_TDM_BCLK_MS1_256:
2625                 return parent_rate * 256;
2626         case RT5682S_TDM_BCLK_MS1_128:
2627                 return parent_rate * 128;
2628         case RT5682S_TDM_BCLK_MS1_64:
2629                 return parent_rate * 64;
2630         case RT5682S_TDM_BCLK_MS1_32:
2631                 return parent_rate * 32;
2632         default:
2633                 return 0;
2634         }
2635 }
2636
2637 static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2638                                             unsigned long parent_rate)
2639 {
2640         unsigned long factor;
2641
2642         factor = rate / parent_rate;
2643         if (factor < 64)
2644                 return 32;
2645         else if (factor < 128)
2646                 return 64;
2647         else if (factor < 256)
2648                 return 128;
2649         else
2650                 return 256;
2651 }
2652
2653 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2654                                    unsigned long *parent_rate)
2655 {
2656         struct rt5682s_priv *rt5682s =
2657                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2658         unsigned long factor;
2659
2660         if (!*parent_rate || !rt5682s_clk_check(rt5682s))
2661                 return -EINVAL;
2662
2663         /*
2664          * BCLK rates are set as a multiplier of WCLK in HW.
2665          * We don't allow changing the parent WCLK. We just do
2666          * some rounding down based on the parent WCLK rate
2667          * and find the appropriate multiplier of BCLK to
2668          * get the rounded down BCLK value.
2669          */
2670         factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2671
2672         return *parent_rate * factor;
2673 }
2674
2675 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2676                                 unsigned long parent_rate)
2677 {
2678         struct rt5682s_priv *rt5682s =
2679                 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2680         struct snd_soc_component *component = rt5682s->component;
2681         struct snd_soc_dai *dai;
2682         unsigned long factor;
2683
2684         if (!rt5682s_clk_check(rt5682s))
2685                 return -EINVAL;
2686
2687         factor = rt5682s_bclk_get_factor(rate, parent_rate);
2688
2689         for_each_component_dais(component, dai)
2690                 if (dai->id == RT5682S_AIF1)
2691                         return rt5682s_set_bclk1_ratio(dai, factor);
2692
2693         dev_err(component->dev, "dai %d not found in component\n",
2694                 RT5682S_AIF1);
2695         return -ENODEV;
2696 }
2697
2698 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
2699         [RT5682S_DAI_WCLK_IDX] = {
2700                 .prepare = rt5682s_wclk_prepare,
2701                 .unprepare = rt5682s_wclk_unprepare,
2702                 .recalc_rate = rt5682s_wclk_recalc_rate,
2703                 .round_rate = rt5682s_wclk_round_rate,
2704                 .set_rate = rt5682s_wclk_set_rate,
2705         },
2706         [RT5682S_DAI_BCLK_IDX] = {
2707                 .recalc_rate = rt5682s_bclk_recalc_rate,
2708                 .round_rate = rt5682s_bclk_round_rate,
2709                 .set_rate = rt5682s_bclk_set_rate,
2710         },
2711 };
2712
2713 static int rt5682s_register_dai_clks(struct snd_soc_component *component)
2714 {
2715         struct device *dev = component->dev;
2716         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2717         struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2718         struct clk_hw *dai_clk_hw;
2719         int i, ret;
2720
2721         for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
2722                 struct clk_init_data init = { };
2723                 struct clk_parent_data parent_data;
2724                 const struct clk_hw *parent;
2725
2726                 dai_clk_hw = &rt5682s->dai_clks_hw[i];
2727
2728                 switch (i) {
2729                 case RT5682S_DAI_WCLK_IDX:
2730                         /* Make MCLK the parent of WCLK */
2731                         if (rt5682s->mclk) {
2732                                 parent_data = (struct clk_parent_data){
2733                                         .fw_name = "mclk",
2734                                 };
2735                                 init.parent_data = &parent_data;
2736                                 init.num_parents = 1;
2737                         }
2738                         break;
2739                 case RT5682S_DAI_BCLK_IDX:
2740                         /* Make WCLK the parent of BCLK */
2741                         parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2742                         init.parent_hws = &parent;
2743                         init.num_parents = 1;
2744                         break;
2745                 default:
2746                         dev_err(dev, "Invalid clock index\n");
2747                         return -EINVAL;
2748                 }
2749
2750                 init.name = pdata->dai_clk_names[i];
2751                 init.ops = &rt5682s_dai_clk_ops[i];
2752                 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2753                 dai_clk_hw->init = &init;
2754
2755                 ret = devm_clk_hw_register(dev, dai_clk_hw);
2756                 if (ret) {
2757                         dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
2758                         return ret;
2759                 }
2760
2761                 if (dev->of_node) {
2762                         devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw);
2763                 } else {
2764                         ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2765                                                           init.name, dev_name(dev));
2766                         if (ret)
2767                                 return ret;
2768                 }
2769         }
2770
2771         return 0;
2772 }
2773
2774 static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2775 {
2776         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2777         int ret;
2778
2779         /* Check if MCLK provided */
2780         rt5682s->mclk = devm_clk_get(component->dev, "mclk");
2781         if (IS_ERR(rt5682s->mclk)) {
2782                 if (PTR_ERR(rt5682s->mclk) != -ENOENT) {
2783                         ret = PTR_ERR(rt5682s->mclk);
2784                         return ret;
2785                 }
2786                 rt5682s->mclk = NULL;
2787         }
2788
2789         /* Register CCF DAI clock control */
2790         ret = rt5682s_register_dai_clks(component);
2791         if (ret)
2792                 return ret;
2793
2794         /* Initial setup for CCF */
2795         rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2796
2797         return 0;
2798 }
2799 #else
2800 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2801 {
2802         return 0;
2803 }
2804 #endif /* CONFIG_COMMON_CLK */
2805
2806 static int rt5682s_probe(struct snd_soc_component *component)
2807 {
2808         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2809         int ret;
2810
2811         rt5682s->component = component;
2812
2813         ret = rt5682s_dai_probe_clks(component);
2814         if (ret)
2815                 return ret;
2816
2817         return 0;
2818 }
2819
2820 static void rt5682s_remove(struct snd_soc_component *component)
2821 {
2822         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2823
2824         rt5682s_reset(rt5682s);
2825 }
2826
2827 #ifdef CONFIG_PM
2828 static int rt5682s_suspend(struct snd_soc_component *component)
2829 {
2830         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2831
2832         cancel_delayed_work_sync(&rt5682s->jack_detect_work);
2833         cancel_delayed_work_sync(&rt5682s->jd_check_work);
2834
2835         if (rt5682s->hs_jack)
2836                 rt5682s->jack_type = rt5682s_headset_detect(component, 0);
2837
2838         regcache_cache_only(rt5682s->regmap, true);
2839         regcache_mark_dirty(rt5682s->regmap);
2840
2841         return 0;
2842 }
2843
2844 static int rt5682s_resume(struct snd_soc_component *component)
2845 {
2846         struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2847
2848         regcache_cache_only(rt5682s->regmap, false);
2849         regcache_sync(rt5682s->regmap);
2850
2851         if (rt5682s->hs_jack) {
2852                 mod_delayed_work(system_power_efficient_wq,
2853                         &rt5682s->jack_detect_work, msecs_to_jiffies(0));
2854         }
2855
2856         return 0;
2857 }
2858 #else
2859 #define rt5682s_suspend NULL
2860 #define rt5682s_resume NULL
2861 #endif
2862
2863 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
2864         .hw_params = rt5682s_hw_params,
2865         .set_fmt = rt5682s_set_dai_fmt,
2866         .set_tdm_slot = rt5682s_set_tdm_slot,
2867         .set_bclk_ratio = rt5682s_set_bclk1_ratio,
2868 };
2869
2870 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
2871         .hw_params = rt5682s_hw_params,
2872         .set_fmt = rt5682s_set_dai_fmt,
2873         .set_bclk_ratio = rt5682s_set_bclk2_ratio,
2874 };
2875
2876 static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
2877         .probe = rt5682s_probe,
2878         .remove = rt5682s_remove,
2879         .suspend = rt5682s_suspend,
2880         .resume = rt5682s_resume,
2881         .set_bias_level = rt5682s_set_bias_level,
2882         .controls = rt5682s_snd_controls,
2883         .num_controls = ARRAY_SIZE(rt5682s_snd_controls),
2884         .dapm_widgets = rt5682s_dapm_widgets,
2885         .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
2886         .dapm_routes = rt5682s_dapm_routes,
2887         .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
2888         .set_sysclk = rt5682s_set_component_sysclk,
2889         .set_pll = rt5682s_set_component_pll,
2890         .set_jack = rt5682s_set_jack_detect,
2891         .use_pmdown_time        = 1,
2892         .endianness             = 1,
2893 };
2894
2895 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
2896 {
2897         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2898                 &rt5682s->pdata.dmic1_data_pin);
2899         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2900                 &rt5682s->pdata.dmic1_clk_pin);
2901         device_property_read_u32(dev, "realtek,jd-src",
2902                 &rt5682s->pdata.jd_src);
2903         device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2904                 &rt5682s->pdata.dmic_clk_rate);
2905         device_property_read_u32(dev, "realtek,dmic-delay-ms",
2906                 &rt5682s->pdata.dmic_delay);
2907         device_property_read_u32(dev, "realtek,amic-delay-ms",
2908                 &rt5682s->pdata.amic_delay);
2909
2910         rt5682s->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2911                 "realtek,ldo1-en-gpios", 0);
2912
2913         if (device_property_read_string_array(dev, "clock-output-names",
2914                                               rt5682s->pdata.dai_clk_names,
2915                                               RT5682S_DAI_NUM_CLKS) < 0)
2916                 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2917                          rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2918                          rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2919
2920         rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2921                 "realtek,dmic-clk-driving-high");
2922
2923         return 0;
2924 }
2925
2926 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
2927 {
2928         unsigned int count, value;
2929
2930         mutex_lock(&rt5682s->calibrate_mutex);
2931
2932         regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
2933         usleep_range(15000, 20000);
2934         regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
2935         regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
2936         regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
2937         regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
2938         regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
2939         regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
2940         regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
2941         regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
2942         regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
2943         regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
2944         regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
2945         regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
2946         regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
2947
2948         for (count = 0; count < 60; count++) {
2949                 regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
2950                 if (!(value & 0x8000))
2951                         break;
2952
2953                 usleep_range(10000, 10005);
2954         }
2955
2956         if (count >= 60)
2957                 dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
2958
2959         /* restore settings */
2960         regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
2961         regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
2962         regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
2963         regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
2964         regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
2965         regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
2966         regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
2967
2968         mutex_unlock(&rt5682s->calibrate_mutex);
2969 }
2970
2971 static const struct regmap_config rt5682s_regmap = {
2972         .reg_bits = 16,
2973         .val_bits = 16,
2974         .max_register = RT5682S_MAX_REG,
2975         .volatile_reg = rt5682s_volatile_register,
2976         .readable_reg = rt5682s_readable_register,
2977         .cache_type = REGCACHE_RBTREE,
2978         .reg_defaults = rt5682s_reg,
2979         .num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
2980         .use_single_read = true,
2981         .use_single_write = true,
2982 };
2983
2984 static struct snd_soc_dai_driver rt5682s_dai[] = {
2985         {
2986                 .name = "rt5682s-aif1",
2987                 .id = RT5682S_AIF1,
2988                 .playback = {
2989                         .stream_name = "AIF1 Playback",
2990                         .channels_min = 1,
2991                         .channels_max = 2,
2992                         .rates = RT5682S_STEREO_RATES,
2993                         .formats = RT5682S_FORMATS,
2994                 },
2995                 .capture = {
2996                         .stream_name = "AIF1 Capture",
2997                         .channels_min = 1,
2998                         .channels_max = 2,
2999                         .rates = RT5682S_STEREO_RATES,
3000                         .formats = RT5682S_FORMATS,
3001                 },
3002                 .ops = &rt5682s_aif1_dai_ops,
3003         },
3004         {
3005                 .name = "rt5682s-aif2",
3006                 .id = RT5682S_AIF2,
3007                 .capture = {
3008                         .stream_name = "AIF2 Capture",
3009                         .channels_min = 1,
3010                         .channels_max = 2,
3011                         .rates = RT5682S_STEREO_RATES,
3012                         .formats = RT5682S_FORMATS,
3013                 },
3014                 .ops = &rt5682s_aif2_dai_ops,
3015         },
3016 };
3017
3018 static void rt5682s_i2c_disable_regulators(void *data)
3019 {
3020         struct rt5682s_priv *rt5682s = data;
3021         struct device *dev = regmap_get_device(rt5682s->regmap);
3022         int ret;
3023
3024         ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3025         if (ret)
3026                 dev_err(dev, "Failed to disable supply AVDD: %d\n", ret);
3027
3028         usleep_range(1000, 1500);
3029
3030         ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3031         if (ret)
3032                 dev_err(dev, "Failed to disable supply MICVDD: %d\n", ret);
3033 }
3034
3035 static int rt5682s_i2c_probe(struct i2c_client *i2c)
3036 {
3037         struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
3038         struct rt5682s_priv *rt5682s;
3039         int i, ret;
3040         unsigned int val;
3041
3042         rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
3043         if (!rt5682s)
3044                 return -ENOMEM;
3045
3046         i2c_set_clientdata(i2c, rt5682s);
3047
3048         rt5682s->pdata = i2s_default_platform_data;
3049
3050         if (pdata)
3051                 rt5682s->pdata = *pdata;
3052         else
3053                 rt5682s_parse_dt(rt5682s, &i2c->dev);
3054
3055         rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3056         if (IS_ERR(rt5682s->regmap)) {
3057                 ret = PTR_ERR(rt5682s->regmap);
3058                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3059                 return ret;
3060         }
3061
3062         for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3063                 rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3064
3065         ret = devm_regulator_bulk_get(&i2c->dev,
3066                         ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3067         if (ret) {
3068                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3069                 return ret;
3070         }
3071
3072         ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3073         if (ret)
3074                 return ret;
3075
3076         ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3077         if (ret) {
3078                 dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
3079                 return ret;
3080         }
3081         usleep_range(1000, 1500);
3082
3083         ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3084         if (ret) {
3085                 dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
3086                 return ret;
3087         }
3088
3089         if (gpio_is_valid(rt5682s->pdata.ldo1_en)) {
3090                 if (devm_gpio_request_one(&i2c->dev, rt5682s->pdata.ldo1_en,
3091                                           GPIOF_OUT_INIT_HIGH, "rt5682s"))
3092                         dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
3093         }
3094
3095         /* Sleep for 50 ms minimum */
3096         usleep_range(50000, 55000);
3097
3098         regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
3099         if (val != DEVICE_ID) {
3100                 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3101                 return -ENODEV;
3102         }
3103
3104         rt5682s_reset(rt5682s);
3105         rt5682s_apply_patch_list(rt5682s, &i2c->dev);
3106
3107         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
3108                 RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
3109         usleep_range(20000, 25000);
3110
3111         mutex_init(&rt5682s->calibrate_mutex);
3112         mutex_init(&rt5682s->sar_mutex);
3113         mutex_init(&rt5682s->wclk_mutex);
3114         rt5682s_calibrate(rt5682s);
3115
3116         regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
3117                 RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
3118                 RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
3119         regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
3120                 RT5682S_PWR_BG, RT5682S_PWR_BG);
3121         regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3122                 RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
3123         regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3124                 RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
3125         regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3126                 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
3127
3128         /* DMIC data pin */
3129         switch (rt5682s->pdata.dmic1_data_pin) {
3130         case RT5682S_DMIC1_DATA_NULL:
3131                 break;
3132         case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3133                 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3134                         RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
3135                 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3136                         RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
3137                 break;
3138         case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3139                 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3140                         RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
3141                 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3142                         RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
3143                 break;
3144         default:
3145                 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3146                 break;
3147         }
3148
3149         /* DMIC clk pin */
3150         switch (rt5682s->pdata.dmic1_clk_pin) {
3151         case RT5682S_DMIC1_CLK_NULL:
3152                 break;
3153         case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
3154                 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3155                         RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
3156                 break;
3157         case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3158                 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3159                         RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
3160                 if (rt5682s->pdata.dmic_clk_driving_high)
3161                         regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3162                                 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
3163                 break;
3164         default:
3165                 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3166                 break;
3167         }
3168
3169         INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3170         INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3171
3172         if (i2c->irq) {
3173                 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
3174                         IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3175                         "rt5682s", rt5682s);
3176                 if (ret)
3177                         dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3178         }
3179
3180         return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
3181                         rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
3182 }
3183
3184 static void rt5682s_i2c_shutdown(struct i2c_client *client)
3185 {
3186         struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
3187
3188         disable_irq(client->irq);
3189         cancel_delayed_work_sync(&rt5682s->jack_detect_work);
3190         cancel_delayed_work_sync(&rt5682s->jd_check_work);
3191
3192         rt5682s_reset(rt5682s);
3193 }
3194
3195 static int rt5682s_i2c_remove(struct i2c_client *client)
3196 {
3197         rt5682s_i2c_shutdown(client);
3198
3199         return 0;
3200 }
3201
3202 static const struct of_device_id rt5682s_of_match[] = {
3203         {.compatible = "realtek,rt5682s"},
3204         {},
3205 };
3206 MODULE_DEVICE_TABLE(of, rt5682s_of_match);
3207
3208 static const struct acpi_device_id rt5682s_acpi_match[] = {
3209         {"RTL5682", 0,},
3210         {},
3211 };
3212 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
3213
3214 static const struct i2c_device_id rt5682s_i2c_id[] = {
3215         {"rt5682s", 0},
3216         {}
3217 };
3218 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
3219
3220 static struct i2c_driver rt5682s_i2c_driver = {
3221         .driver = {
3222                 .name = "rt5682s",
3223                 .of_match_table = rt5682s_of_match,
3224                 .acpi_match_table = rt5682s_acpi_match,
3225                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3226         },
3227         .probe_new = rt5682s_i2c_probe,
3228         .remove = rt5682s_i2c_remove,
3229         .shutdown = rt5682s_i2c_shutdown,
3230         .id_table = rt5682s_i2c_id,
3231 };
3232 module_i2c_driver(rt5682s_i2c_driver);
3233
3234 MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
3235 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
3236 MODULE_LICENSE("GPL v2");