2 * rt5682.c -- RT5682 ALSA SoC audio component driver
4 * Copyright 2018 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5682.h>
38 #define RT5682_NUM_SUPPLIES 3
40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
47 struct snd_soc_component *component;
48 struct rt5682_platform_data pdata;
49 struct regmap *regmap;
50 struct snd_soc_jack *hs_jack;
51 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
52 struct delayed_work jack_detect_work;
53 struct delayed_work jd_check_work;
54 struct mutex calibrate_mutex;
58 int lrck[RT5682_AIFS];
59 int bclk[RT5682_AIFS];
60 int master[RT5682_AIFS];
69 static const struct reg_sequence patch_list[] = {
73 static const struct reg_default rt5682_reg[] = {
394 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
398 case RT5682_CBJ_CTRL_2:
399 case RT5682_INT_ST_1:
400 case RT5682_4BTN_IL_CMD_1:
401 case RT5682_AJD1_CTRL:
402 case RT5682_HP_CALIB_CTRL_1:
403 case RT5682_DEVICE_ID:
404 case RT5682_I2C_MODE:
405 case RT5682_HP_CALIB_CTRL_10:
406 case RT5682_EFUSE_CTRL_2:
407 case RT5682_JD_TOP_VC_VTRL:
408 case RT5682_HP_IMP_SENS_CTRL_19:
409 case RT5682_IL_CMD_1:
410 case RT5682_SAR_IL_CMD_2:
411 case RT5682_SAR_IL_CMD_4:
412 case RT5682_SAR_IL_CMD_10:
413 case RT5682_SAR_IL_CMD_11:
414 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
415 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
422 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
426 case RT5682_VERSION_ID:
427 case RT5682_VENDOR_ID:
428 case RT5682_DEVICE_ID:
429 case RT5682_HP_CTRL_1:
430 case RT5682_HP_CTRL_2:
431 case RT5682_HPL_GAIN:
432 case RT5682_HPR_GAIN:
433 case RT5682_I2C_CTRL:
434 case RT5682_CBJ_BST_CTRL:
435 case RT5682_CBJ_CTRL_1:
436 case RT5682_CBJ_CTRL_2:
437 case RT5682_CBJ_CTRL_3:
438 case RT5682_CBJ_CTRL_4:
439 case RT5682_CBJ_CTRL_5:
440 case RT5682_CBJ_CTRL_6:
441 case RT5682_CBJ_CTRL_7:
442 case RT5682_DAC1_DIG_VOL:
443 case RT5682_STO1_ADC_DIG_VOL:
444 case RT5682_STO1_ADC_BOOST:
445 case RT5682_HP_IMP_GAIN_1:
446 case RT5682_HP_IMP_GAIN_2:
447 case RT5682_SIDETONE_CTRL:
448 case RT5682_STO1_ADC_MIXER:
449 case RT5682_AD_DA_MIXER:
450 case RT5682_STO1_DAC_MIXER:
451 case RT5682_A_DAC1_MUX:
452 case RT5682_DIG_INF2_DATA:
453 case RT5682_REC_MIXER:
455 case RT5682_ALC_BACK_GAIN:
456 case RT5682_PWR_DIG_1:
457 case RT5682_PWR_DIG_2:
458 case RT5682_PWR_ANLG_1:
459 case RT5682_PWR_ANLG_2:
460 case RT5682_PWR_ANLG_3:
461 case RT5682_PWR_MIXER:
464 case RT5682_RESET_LPF_CTRL:
465 case RT5682_RESET_HPF_CTRL:
466 case RT5682_DMIC_CTRL_1:
467 case RT5682_I2S1_SDP:
468 case RT5682_I2S2_SDP:
469 case RT5682_ADDA_CLK_1:
470 case RT5682_ADDA_CLK_2:
471 case RT5682_I2S1_F_DIV_CTRL_1:
472 case RT5682_I2S1_F_DIV_CTRL_2:
473 case RT5682_TDM_CTRL:
474 case RT5682_TDM_ADDA_CTRL_1:
475 case RT5682_TDM_ADDA_CTRL_2:
476 case RT5682_DATA_SEL_CTRL_1:
477 case RT5682_TDM_TCON_CTRL:
479 case RT5682_PLL_CTRL_1:
480 case RT5682_PLL_CTRL_2:
481 case RT5682_PLL_TRACK_1:
482 case RT5682_PLL_TRACK_2:
483 case RT5682_PLL_TRACK_3:
484 case RT5682_PLL_TRACK_4:
485 case RT5682_PLL_TRACK_5:
486 case RT5682_PLL_TRACK_6:
487 case RT5682_PLL_TRACK_11:
488 case RT5682_SDW_REF_CLK:
491 case RT5682_HP_CHARGE_PUMP_1:
492 case RT5682_HP_CHARGE_PUMP_2:
493 case RT5682_MICBIAS_1:
494 case RT5682_MICBIAS_2:
495 case RT5682_PLL_TRACK_12:
496 case RT5682_PLL_TRACK_14:
497 case RT5682_PLL2_CTRL_1:
498 case RT5682_PLL2_CTRL_2:
499 case RT5682_PLL2_CTRL_3:
500 case RT5682_PLL2_CTRL_4:
501 case RT5682_RC_CLK_CTRL:
502 case RT5682_I2S_M_CLK_CTRL_1:
503 case RT5682_I2S2_F_DIV_CTRL_1:
504 case RT5682_I2S2_F_DIV_CTRL_2:
505 case RT5682_EQ_CTRL_1:
506 case RT5682_EQ_CTRL_2:
507 case RT5682_IRQ_CTRL_1:
508 case RT5682_IRQ_CTRL_2:
509 case RT5682_IRQ_CTRL_3:
510 case RT5682_IRQ_CTRL_4:
511 case RT5682_INT_ST_1:
512 case RT5682_GPIO_CTRL_1:
513 case RT5682_GPIO_CTRL_2:
514 case RT5682_GPIO_CTRL_3:
515 case RT5682_HP_AMP_DET_CTRL_1:
516 case RT5682_HP_AMP_DET_CTRL_2:
517 case RT5682_MID_HP_AMP_DET:
518 case RT5682_LOW_HP_AMP_DET:
519 case RT5682_DELAY_BUF_CTRL:
520 case RT5682_SV_ZCD_1:
521 case RT5682_SV_ZCD_2:
522 case RT5682_IL_CMD_1:
523 case RT5682_IL_CMD_2:
524 case RT5682_IL_CMD_3:
525 case RT5682_IL_CMD_4:
526 case RT5682_IL_CMD_5:
527 case RT5682_IL_CMD_6:
528 case RT5682_4BTN_IL_CMD_1:
529 case RT5682_4BTN_IL_CMD_2:
530 case RT5682_4BTN_IL_CMD_3:
531 case RT5682_4BTN_IL_CMD_4:
532 case RT5682_4BTN_IL_CMD_5:
533 case RT5682_4BTN_IL_CMD_6:
534 case RT5682_4BTN_IL_CMD_7:
535 case RT5682_ADC_STO1_HP_CTRL_1:
536 case RT5682_ADC_STO1_HP_CTRL_2:
537 case RT5682_AJD1_CTRL:
540 case RT5682_JD_CTRL_1:
544 case RT5682_DAC_ADC_DIG_VOL1:
545 case RT5682_BIAS_CUR_CTRL_2:
546 case RT5682_BIAS_CUR_CTRL_3:
547 case RT5682_BIAS_CUR_CTRL_4:
548 case RT5682_BIAS_CUR_CTRL_5:
549 case RT5682_BIAS_CUR_CTRL_6:
550 case RT5682_BIAS_CUR_CTRL_7:
551 case RT5682_BIAS_CUR_CTRL_8:
552 case RT5682_BIAS_CUR_CTRL_9:
553 case RT5682_BIAS_CUR_CTRL_10:
554 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
555 case RT5682_CHARGE_PUMP_1:
556 case RT5682_DIG_IN_CTRL_1:
557 case RT5682_PAD_DRIVING_CTRL:
558 case RT5682_SOFT_RAMP_DEPOP:
559 case RT5682_CHOP_DAC:
560 case RT5682_CHOP_ADC:
561 case RT5682_CALIB_ADC_CTRL:
562 case RT5682_VOL_TEST:
563 case RT5682_SPKVDD_DET_STA:
564 case RT5682_TEST_MODE_CTRL_1:
565 case RT5682_TEST_MODE_CTRL_2:
566 case RT5682_TEST_MODE_CTRL_3:
567 case RT5682_TEST_MODE_CTRL_4:
568 case RT5682_TEST_MODE_CTRL_5:
569 case RT5682_PLL1_INTERNAL:
570 case RT5682_PLL2_INTERNAL:
571 case RT5682_STO_NG2_CTRL_1:
572 case RT5682_STO_NG2_CTRL_2:
573 case RT5682_STO_NG2_CTRL_3:
574 case RT5682_STO_NG2_CTRL_4:
575 case RT5682_STO_NG2_CTRL_5:
576 case RT5682_STO_NG2_CTRL_6:
577 case RT5682_STO_NG2_CTRL_7:
578 case RT5682_STO_NG2_CTRL_8:
579 case RT5682_STO_NG2_CTRL_9:
580 case RT5682_STO_NG2_CTRL_10:
581 case RT5682_STO1_DAC_SIL_DET:
582 case RT5682_SIL_PSV_CTRL1:
583 case RT5682_SIL_PSV_CTRL2:
584 case RT5682_SIL_PSV_CTRL3:
585 case RT5682_SIL_PSV_CTRL4:
586 case RT5682_SIL_PSV_CTRL5:
587 case RT5682_HP_IMP_SENS_CTRL_01:
588 case RT5682_HP_IMP_SENS_CTRL_02:
589 case RT5682_HP_IMP_SENS_CTRL_03:
590 case RT5682_HP_IMP_SENS_CTRL_04:
591 case RT5682_HP_IMP_SENS_CTRL_05:
592 case RT5682_HP_IMP_SENS_CTRL_06:
593 case RT5682_HP_IMP_SENS_CTRL_07:
594 case RT5682_HP_IMP_SENS_CTRL_08:
595 case RT5682_HP_IMP_SENS_CTRL_09:
596 case RT5682_HP_IMP_SENS_CTRL_10:
597 case RT5682_HP_IMP_SENS_CTRL_11:
598 case RT5682_HP_IMP_SENS_CTRL_12:
599 case RT5682_HP_IMP_SENS_CTRL_13:
600 case RT5682_HP_IMP_SENS_CTRL_14:
601 case RT5682_HP_IMP_SENS_CTRL_15:
602 case RT5682_HP_IMP_SENS_CTRL_16:
603 case RT5682_HP_IMP_SENS_CTRL_17:
604 case RT5682_HP_IMP_SENS_CTRL_18:
605 case RT5682_HP_IMP_SENS_CTRL_19:
606 case RT5682_HP_IMP_SENS_CTRL_20:
607 case RT5682_HP_IMP_SENS_CTRL_21:
608 case RT5682_HP_IMP_SENS_CTRL_22:
609 case RT5682_HP_IMP_SENS_CTRL_23:
610 case RT5682_HP_IMP_SENS_CTRL_24:
611 case RT5682_HP_IMP_SENS_CTRL_25:
612 case RT5682_HP_IMP_SENS_CTRL_26:
613 case RT5682_HP_IMP_SENS_CTRL_27:
614 case RT5682_HP_IMP_SENS_CTRL_28:
615 case RT5682_HP_IMP_SENS_CTRL_29:
616 case RT5682_HP_IMP_SENS_CTRL_30:
617 case RT5682_HP_IMP_SENS_CTRL_31:
618 case RT5682_HP_IMP_SENS_CTRL_32:
619 case RT5682_HP_IMP_SENS_CTRL_33:
620 case RT5682_HP_IMP_SENS_CTRL_34:
621 case RT5682_HP_IMP_SENS_CTRL_35:
622 case RT5682_HP_IMP_SENS_CTRL_36:
623 case RT5682_HP_IMP_SENS_CTRL_37:
624 case RT5682_HP_IMP_SENS_CTRL_38:
625 case RT5682_HP_IMP_SENS_CTRL_39:
626 case RT5682_HP_IMP_SENS_CTRL_40:
627 case RT5682_HP_IMP_SENS_CTRL_41:
628 case RT5682_HP_IMP_SENS_CTRL_42:
629 case RT5682_HP_IMP_SENS_CTRL_43:
630 case RT5682_HP_LOGIC_CTRL_1:
631 case RT5682_HP_LOGIC_CTRL_2:
632 case RT5682_HP_LOGIC_CTRL_3:
633 case RT5682_HP_CALIB_CTRL_1:
634 case RT5682_HP_CALIB_CTRL_2:
635 case RT5682_HP_CALIB_CTRL_3:
636 case RT5682_HP_CALIB_CTRL_4:
637 case RT5682_HP_CALIB_CTRL_5:
638 case RT5682_HP_CALIB_CTRL_6:
639 case RT5682_HP_CALIB_CTRL_7:
640 case RT5682_HP_CALIB_CTRL_9:
641 case RT5682_HP_CALIB_CTRL_10:
642 case RT5682_HP_CALIB_CTRL_11:
643 case RT5682_HP_CALIB_STA_1:
644 case RT5682_HP_CALIB_STA_2:
645 case RT5682_HP_CALIB_STA_3:
646 case RT5682_HP_CALIB_STA_4:
647 case RT5682_HP_CALIB_STA_5:
648 case RT5682_HP_CALIB_STA_6:
649 case RT5682_HP_CALIB_STA_7:
650 case RT5682_HP_CALIB_STA_8:
651 case RT5682_HP_CALIB_STA_9:
652 case RT5682_HP_CALIB_STA_10:
653 case RT5682_HP_CALIB_STA_11:
654 case RT5682_SAR_IL_CMD_1:
655 case RT5682_SAR_IL_CMD_2:
656 case RT5682_SAR_IL_CMD_3:
657 case RT5682_SAR_IL_CMD_4:
658 case RT5682_SAR_IL_CMD_5:
659 case RT5682_SAR_IL_CMD_6:
660 case RT5682_SAR_IL_CMD_7:
661 case RT5682_SAR_IL_CMD_8:
662 case RT5682_SAR_IL_CMD_9:
663 case RT5682_SAR_IL_CMD_10:
664 case RT5682_SAR_IL_CMD_11:
665 case RT5682_SAR_IL_CMD_12:
666 case RT5682_SAR_IL_CMD_13:
667 case RT5682_EFUSE_CTRL_1:
668 case RT5682_EFUSE_CTRL_2:
669 case RT5682_EFUSE_CTRL_3:
670 case RT5682_EFUSE_CTRL_4:
671 case RT5682_EFUSE_CTRL_5:
672 case RT5682_EFUSE_CTRL_6:
673 case RT5682_EFUSE_CTRL_7:
674 case RT5682_EFUSE_CTRL_8:
675 case RT5682_EFUSE_CTRL_9:
676 case RT5682_EFUSE_CTRL_10:
677 case RT5682_EFUSE_CTRL_11:
678 case RT5682_JD_TOP_VC_VTRL:
679 case RT5682_DRC1_CTRL_0:
680 case RT5682_DRC1_CTRL_1:
681 case RT5682_DRC1_CTRL_2:
682 case RT5682_DRC1_CTRL_3:
683 case RT5682_DRC1_CTRL_4:
684 case RT5682_DRC1_CTRL_5:
685 case RT5682_DRC1_CTRL_6:
686 case RT5682_DRC1_HARD_LMT_CTRL_1:
687 case RT5682_DRC1_HARD_LMT_CTRL_2:
688 case RT5682_DRC1_PRIV_1:
689 case RT5682_DRC1_PRIV_2:
690 case RT5682_DRC1_PRIV_3:
691 case RT5682_DRC1_PRIV_4:
692 case RT5682_DRC1_PRIV_5:
693 case RT5682_DRC1_PRIV_6:
694 case RT5682_DRC1_PRIV_7:
695 case RT5682_DRC1_PRIV_8:
696 case RT5682_EQ_AUTO_RCV_CTRL1:
697 case RT5682_EQ_AUTO_RCV_CTRL2:
698 case RT5682_EQ_AUTO_RCV_CTRL3:
699 case RT5682_EQ_AUTO_RCV_CTRL4:
700 case RT5682_EQ_AUTO_RCV_CTRL5:
701 case RT5682_EQ_AUTO_RCV_CTRL6:
702 case RT5682_EQ_AUTO_RCV_CTRL7:
703 case RT5682_EQ_AUTO_RCV_CTRL8:
704 case RT5682_EQ_AUTO_RCV_CTRL9:
705 case RT5682_EQ_AUTO_RCV_CTRL10:
706 case RT5682_EQ_AUTO_RCV_CTRL11:
707 case RT5682_EQ_AUTO_RCV_CTRL12:
708 case RT5682_EQ_AUTO_RCV_CTRL13:
709 case RT5682_ADC_L_EQ_LPF1_A1:
710 case RT5682_R_EQ_LPF1_A1:
711 case RT5682_L_EQ_LPF1_H0:
712 case RT5682_R_EQ_LPF1_H0:
713 case RT5682_L_EQ_BPF1_A1:
714 case RT5682_R_EQ_BPF1_A1:
715 case RT5682_L_EQ_BPF1_A2:
716 case RT5682_R_EQ_BPF1_A2:
717 case RT5682_L_EQ_BPF1_H0:
718 case RT5682_R_EQ_BPF1_H0:
719 case RT5682_L_EQ_BPF2_A1:
720 case RT5682_R_EQ_BPF2_A1:
721 case RT5682_L_EQ_BPF2_A2:
722 case RT5682_R_EQ_BPF2_A2:
723 case RT5682_L_EQ_BPF2_H0:
724 case RT5682_R_EQ_BPF2_H0:
725 case RT5682_L_EQ_BPF3_A1:
726 case RT5682_R_EQ_BPF3_A1:
727 case RT5682_L_EQ_BPF3_A2:
728 case RT5682_R_EQ_BPF3_A2:
729 case RT5682_L_EQ_BPF3_H0:
730 case RT5682_R_EQ_BPF3_H0:
731 case RT5682_L_EQ_BPF4_A1:
732 case RT5682_R_EQ_BPF4_A1:
733 case RT5682_L_EQ_BPF4_A2:
734 case RT5682_R_EQ_BPF4_A2:
735 case RT5682_L_EQ_BPF4_H0:
736 case RT5682_R_EQ_BPF4_H0:
737 case RT5682_L_EQ_HPF1_A1:
738 case RT5682_R_EQ_HPF1_A1:
739 case RT5682_L_EQ_HPF1_H0:
740 case RT5682_R_EQ_HPF1_H0:
741 case RT5682_L_EQ_PRE_VOL:
742 case RT5682_R_EQ_PRE_VOL:
743 case RT5682_L_EQ_POST_VOL:
744 case RT5682_R_EQ_POST_VOL:
745 case RT5682_I2C_MODE:
752 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
753 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
754 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
755 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
757 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
758 static const DECLARE_TLV_DB_RANGE(bst_tlv,
759 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
760 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
761 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
762 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
763 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
764 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
765 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
768 /* Interface data select */
769 static const char * const rt5682_data_select[] = {
770 "L/R", "R/L", "L/L", "R/R"
773 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
774 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
776 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
777 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
779 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
780 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
788 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
789 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
791 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
794 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
795 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
797 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
798 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
800 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
801 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
803 static void rt5682_reset(struct regmap *regmap)
805 regmap_write(regmap, RT5682_RESET, 0);
806 regmap_write(regmap, RT5682_I2C_MODE, 1);
809 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
810 * @component: SoC audio component device.
811 * @filter_mask: mask of filters.
812 * @clk_src: clock source
814 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
815 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
816 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
817 * ASRC function will track i2s clock and generate a corresponding system clock
818 * for codec. This function provides an API to select the clock source for a
819 * set of filters specified by the mask. And the component driver will turn on
820 * ASRC for these filters if ASRC is selected as their clock source.
822 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
823 unsigned int filter_mask, unsigned int clk_src)
827 case RT5682_CLK_SEL_SYS:
828 case RT5682_CLK_SEL_I2S1_ASRC:
829 case RT5682_CLK_SEL_I2S2_ASRC:
836 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
837 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
838 RT5682_FILTER_CLK_SEL_MASK,
839 clk_src << RT5682_FILTER_CLK_SEL_SFT);
842 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
844 RT5682_FILTER_CLK_SEL_MASK,
845 clk_src << RT5682_FILTER_CLK_SEL_SFT);
850 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
852 static int rt5682_button_detect(struct snd_soc_component *component)
856 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
857 btn_type = val & 0xfff0;
858 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
859 pr_debug("%s btn_type=%x\n", __func__, btn_type);
860 snd_soc_component_update_bits(component,
861 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
866 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
870 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
871 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
872 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
873 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
874 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
875 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
876 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
877 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
878 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
879 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
881 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
882 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
883 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
884 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
885 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
886 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
887 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
888 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
890 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
895 * rt5682_headset_detect - Detect headset.
896 * @component: SoC audio component device.
897 * @jack_insert: Jack insert or not.
899 * Detect whether is headset or not when jack inserted.
901 * Returns detect status.
903 static int rt5682_headset_detect(struct snd_soc_component *component,
906 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
907 struct snd_soc_dapm_context *dapm =
908 snd_soc_component_get_dapm(component);
909 unsigned int val, count;
912 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
913 snd_soc_dapm_sync(dapm);
914 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
915 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
918 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
919 & RT5682_JACK_TYPE_MASK;
920 while (val == 0 && count < 50) {
921 usleep_range(10000, 15000);
922 val = snd_soc_component_read32(component,
923 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
930 rt5682->jack_type = SND_JACK_HEADSET;
931 rt5682_enable_push_button_irq(component, true);
934 rt5682->jack_type = SND_JACK_HEADPHONE;
938 rt5682_enable_push_button_irq(component, false);
939 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
940 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
941 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
942 snd_soc_dapm_sync(dapm);
944 rt5682->jack_type = 0;
947 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
948 return rt5682->jack_type;
951 static irqreturn_t rt5682_irq(int irq, void *data)
953 struct rt5682_priv *rt5682 = data;
955 mod_delayed_work(system_power_efficient_wq,
956 &rt5682->jack_detect_work, msecs_to_jiffies(250));
961 static void rt5682_jd_check_handler(struct work_struct *work)
963 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
966 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
967 & RT5682_JDH_RS_MASK) {
969 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
971 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
973 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
974 SND_JACK_BTN_2 | SND_JACK_BTN_3);
976 schedule_delayed_work(&rt5682->jd_check_work, 500);
980 static int rt5682_set_jack_detect(struct snd_soc_component *component,
981 struct snd_soc_jack *hs_jack, void *data)
983 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
985 switch (rt5682->pdata.jd_src) {
987 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
988 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
989 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
990 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
991 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
992 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
993 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
994 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
995 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
996 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
997 RT5682_POW_IRQ | RT5682_POW_JDH |
998 RT5682_POW_ANA, RT5682_POW_IRQ |
999 RT5682_POW_JDH | RT5682_POW_ANA);
1000 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1001 RT5682_PWR_JDH | RT5682_PWR_JDL,
1002 RT5682_PWR_JDH | RT5682_PWR_JDL);
1003 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1004 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1005 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1006 mod_delayed_work(system_power_efficient_wq,
1007 &rt5682->jack_detect_work, msecs_to_jiffies(250));
1010 case RT5682_JD_NULL:
1011 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1012 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1013 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1014 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1018 dev_warn(component->dev, "Wrong JD source\n");
1022 rt5682->hs_jack = hs_jack;
1027 static void rt5682_jack_detect_handler(struct work_struct *work)
1029 struct rt5682_priv *rt5682 =
1030 container_of(work, struct rt5682_priv, jack_detect_work.work);
1033 while (!rt5682->component)
1034 usleep_range(10000, 15000);
1036 while (!rt5682->component->card->instantiated)
1037 usleep_range(10000, 15000);
1039 mutex_lock(&rt5682->calibrate_mutex);
1041 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1042 & RT5682_JDH_RS_MASK;
1045 if (rt5682->jack_type == 0) {
1046 /* jack was out, report jack type */
1048 rt5682_headset_detect(rt5682->component, 1);
1050 /* jack is already in, report button event */
1051 rt5682->jack_type = SND_JACK_HEADSET;
1052 btn_type = rt5682_button_detect(rt5682->component);
1054 * rt5682 can report three kinds of button behavior,
1055 * one click, double click and hold. However,
1056 * currently we will report button pressed/released
1057 * event. So all the three button behaviors are
1058 * treated as button pressed.
1064 rt5682->jack_type |= SND_JACK_BTN_0;
1069 rt5682->jack_type |= SND_JACK_BTN_1;
1074 rt5682->jack_type |= SND_JACK_BTN_2;
1079 rt5682->jack_type |= SND_JACK_BTN_3;
1081 case 0x0000: /* unpressed */
1085 dev_err(rt5682->component->dev,
1086 "Unexpected button code 0x%04x\n",
1093 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1096 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1098 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1099 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1101 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1102 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1103 schedule_delayed_work(&rt5682->jd_check_work, 0);
1105 cancel_delayed_work_sync(&rt5682->jd_check_work);
1107 mutex_unlock(&rt5682->calibrate_mutex);
1110 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1111 /* Headphone Output Volume */
1112 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5682_HPL_GAIN,
1113 RT5682_HPR_GAIN, RT5682_G_HP_SFT, 15, 1, hp_vol_tlv),
1115 /* DAC Digital Volume */
1116 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1117 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1119 /* IN Boost Volume */
1120 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1121 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1123 /* ADC Digital Volume Control */
1124 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1125 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1126 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1127 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1129 /* ADC Boost Volume Control */
1130 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1131 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1136 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1137 int target, const int div[], int size)
1141 if (rt5682->sysclk < target) {
1142 pr_err("sysclk rate %d is too low\n",
1147 for (i = 0; i < size - 1; i++) {
1148 pr_info("div[%d]=%d\n", i, div[i]);
1149 if (target * div[i] == rt5682->sysclk)
1151 if (target * div[i + 1] > rt5682->sysclk) {
1152 pr_err("can't find div for sysclk %d\n",
1158 if (target * div[i] < rt5682->sysclk)
1159 pr_err("sysclk rate %d is too high\n",
1167 * set_dmic_clk - Set parameter of dmic.
1170 * @kcontrol: The kcontrol of this widget.
1173 * Choose dmic clock between 1MHz and 3MHz.
1174 * It is better for clock to approximate 3MHz.
1176 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1177 struct snd_kcontrol *kcontrol, int event)
1179 struct snd_soc_component *component =
1180 snd_soc_dapm_to_component(w->dapm);
1181 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1183 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1185 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1187 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1188 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1193 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1194 struct snd_kcontrol *kcontrol, int event)
1196 struct snd_soc_component *component =
1197 snd_soc_dapm_to_component(w->dapm);
1198 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1199 int ref, val, reg, sft, mask, idx = -EINVAL;
1200 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1201 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1203 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1204 RT5682_GP4_PIN_MASK;
1205 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1206 val == RT5682_GP4_PIN_ADCDAT2)
1207 ref = 256 * rt5682->lrck[RT5682_AIF2];
1209 ref = 256 * rt5682->lrck[RT5682_AIF1];
1211 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1213 if (w->shift == RT5682_PWR_ADC_S1F_BIT) {
1214 reg = RT5682_PLL_TRACK_3;
1215 sft = RT5682_ADC_OSR_SFT;
1216 mask = RT5682_ADC_OSR_MASK;
1218 reg = RT5682_PLL_TRACK_2;
1219 sft = RT5682_DAC_OSR_SFT;
1220 mask = RT5682_DAC_OSR_MASK;
1223 snd_soc_component_update_bits(component, reg,
1224 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1226 /* select over sample rate */
1227 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1228 if (rt5682->sysclk <= 12288000 * div_o[idx])
1232 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1238 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1239 struct snd_soc_dapm_widget *sink)
1242 struct snd_soc_component *component =
1243 snd_soc_dapm_to_component(w->dapm);
1245 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1246 val &= RT5682_SCLK_SRC_MASK;
1247 if (val == RT5682_SCLK_SRC_PLL1)
1253 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1254 struct snd_soc_dapm_widget *sink)
1256 unsigned int reg, shift, val;
1257 struct snd_soc_component *component =
1258 snd_soc_dapm_to_component(w->dapm);
1261 case RT5682_ADC_STO1_ASRC_SFT:
1262 reg = RT5682_PLL_TRACK_3;
1263 shift = RT5682_FILTER_CLK_SEL_SFT;
1265 case RT5682_DAC_STO1_ASRC_SFT:
1266 reg = RT5682_PLL_TRACK_2;
1267 shift = RT5682_FILTER_CLK_SEL_SFT;
1273 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1275 case RT5682_CLK_SEL_I2S1_ASRC:
1276 case RT5682_CLK_SEL_I2S2_ASRC:
1285 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1286 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1287 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1288 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1289 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1292 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1293 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1294 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1295 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1296 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1299 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1300 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1301 RT5682_M_ADCMIX_L_SFT, 1, 1),
1302 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1303 RT5682_M_DAC1_L_SFT, 1, 1),
1306 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1307 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1308 RT5682_M_ADCMIX_R_SFT, 1, 1),
1309 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1310 RT5682_M_DAC1_R_SFT, 1, 1),
1313 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1314 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1315 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1316 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1317 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1320 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1321 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1322 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1323 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1324 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1327 /* Analog Input Mixer */
1328 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1329 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1330 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1333 /* STO1 ADC1 Source */
1334 /* MX-26 [13] [5] */
1335 static const char * const rt5682_sto1_adc1_src[] = {
1339 static SOC_ENUM_SINGLE_DECL(
1340 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1341 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1343 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1344 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1346 static SOC_ENUM_SINGLE_DECL(
1347 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1348 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1350 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1351 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1353 /* STO1 ADC Source */
1354 /* MX-26 [11:10] [3:2] */
1355 static const char * const rt5682_sto1_adc_src[] = {
1359 static SOC_ENUM_SINGLE_DECL(
1360 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1361 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1363 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1364 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1366 static SOC_ENUM_SINGLE_DECL(
1367 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1368 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1370 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1371 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1373 /* STO1 ADC2 Source */
1374 /* MX-26 [12] [4] */
1375 static const char * const rt5682_sto1_adc2_src[] = {
1379 static SOC_ENUM_SINGLE_DECL(
1380 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1381 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1383 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1384 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1386 static SOC_ENUM_SINGLE_DECL(
1387 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1388 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1390 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1391 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1393 /* MX-79 [6:4] I2S1 ADC data location */
1394 static const unsigned int rt5682_if1_adc_slot_values[] = {
1401 static const char * const rt5682_if1_adc_slot_src[] = {
1402 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1405 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1406 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1407 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1409 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1410 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1412 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1413 /* MX-2B [4], MX-2B [0]*/
1414 static const char * const rt5682_alg_dac1_src[] = {
1415 "Stereo1 DAC Mixer", "DAC1"
1418 static SOC_ENUM_SINGLE_DECL(
1419 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1420 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1422 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1423 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1425 static SOC_ENUM_SINGLE_DECL(
1426 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1427 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1429 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1430 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1433 static const struct snd_kcontrol_new hpol_switch =
1434 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1435 RT5682_L_MUTE_SFT, 1, 1);
1436 static const struct snd_kcontrol_new hpor_switch =
1437 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1438 RT5682_R_MUTE_SFT, 1, 1);
1440 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w,
1441 struct snd_kcontrol *kcontrol, int event)
1443 struct snd_soc_component *component =
1444 snd_soc_dapm_to_component(w->dapm);
1447 case SND_SOC_DAPM_PRE_PMU:
1448 snd_soc_component_update_bits(component,
1449 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
1451 case SND_SOC_DAPM_POST_PMD:
1452 snd_soc_component_update_bits(component,
1453 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV);
1462 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1463 struct snd_kcontrol *kcontrol, int event)
1465 struct snd_soc_component *component =
1466 snd_soc_dapm_to_component(w->dapm);
1469 case SND_SOC_DAPM_PRE_PMU:
1470 snd_soc_component_write(component,
1471 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1472 snd_soc_component_write(component,
1473 RT5682_HP_CTRL_2, 0x6000);
1474 snd_soc_component_update_bits(component,
1475 RT5682_DEPOP_1, 0x60, 0x60);
1478 case SND_SOC_DAPM_POST_PMD:
1479 snd_soc_component_update_bits(component,
1480 RT5682_DEPOP_1, 0x60, 0x0);
1481 snd_soc_component_write(component,
1482 RT5682_HP_CTRL_2, 0x0000);
1493 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1494 struct snd_kcontrol *kcontrol, int event)
1497 case SND_SOC_DAPM_POST_PMU:
1498 /*Add delay to avoid pop noise*/
1509 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1510 struct snd_kcontrol *kcontrol, int event)
1512 struct snd_soc_component *component =
1513 snd_soc_dapm_to_component(w->dapm);
1516 case SND_SOC_DAPM_PRE_PMU:
1518 case RT5682_PWR_VREF1_BIT:
1519 snd_soc_component_update_bits(component,
1520 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1523 case RT5682_PWR_VREF2_BIT:
1524 snd_soc_component_update_bits(component,
1525 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1533 case SND_SOC_DAPM_POST_PMU:
1534 usleep_range(15000, 20000);
1536 case RT5682_PWR_VREF1_BIT:
1537 snd_soc_component_update_bits(component,
1538 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1542 case RT5682_PWR_VREF2_BIT:
1543 snd_soc_component_update_bits(component,
1544 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1560 static const unsigned int rt5682_adcdat_pin_values[] = {
1565 static const char * const rt5682_adcdat_pin_select[] = {
1570 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1571 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1572 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1574 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1575 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1577 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1578 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1580 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1582 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1584 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1586 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1587 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1588 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1589 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1592 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1593 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1594 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1595 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1596 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1597 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1598 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1599 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1600 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1601 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1604 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1606 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1610 SND_SOC_DAPM_INPUT("DMIC L1"),
1611 SND_SOC_DAPM_INPUT("DMIC R1"),
1613 SND_SOC_DAPM_INPUT("IN1P"),
1615 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1616 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1617 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1618 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1621 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1624 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3,
1625 RT5682_PWR_CBJ_BIT, 0, NULL, 0),
1628 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1629 ARRAY_SIZE(rt5682_rec1_l_mix)),
1630 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1631 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1634 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1635 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1637 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1638 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1639 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1640 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1641 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1642 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1645 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1646 &rt5682_sto1_adc1l_mux),
1647 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1648 &rt5682_sto1_adc1r_mux),
1649 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1650 &rt5682_sto1_adc2l_mux),
1651 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1652 &rt5682_sto1_adc2r_mux),
1653 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1654 &rt5682_sto1_adcl_mux),
1655 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1656 &rt5682_sto1_adcr_mux),
1657 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1658 &rt5682_if1_adc_slot_mux),
1661 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1662 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1663 SND_SOC_DAPM_PRE_PMU),
1664 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1665 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1666 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1667 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1668 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1669 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1670 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1674 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1676 /* Digital Interface */
1677 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1679 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1681 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1682 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1683 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1685 /* Digital Interface Select */
1686 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1687 &rt5682_if1_01_adc_swap_mux),
1688 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1689 &rt5682_if1_23_adc_swap_mux),
1690 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1691 &rt5682_if1_45_adc_swap_mux),
1692 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1693 &rt5682_if1_67_adc_swap_mux),
1694 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1695 &rt5682_if2_adc_swap_mux),
1697 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1698 &rt5682_adcdat_pin_ctrl),
1700 /* Audio Interface */
1701 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1702 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1703 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1704 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1705 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1708 /* DAC mixer before sound effect */
1709 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1710 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1711 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1712 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1714 /* DAC channel Mux */
1715 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1716 &rt5682_alg_dac_l1_mux),
1717 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1718 &rt5682_alg_dac_r1_mux),
1721 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1722 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1723 SND_SOC_DAPM_PRE_PMU),
1724 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1725 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1726 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1727 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1730 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1731 RT5682_PWR_DAC_L1_BIT, 0),
1732 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1733 RT5682_PWR_DAC_R1_BIT, 0),
1734 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1735 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1738 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1739 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1741 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1742 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1743 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1744 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1745 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1746 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event,
1747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1748 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1749 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1751 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1753 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1757 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1758 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1759 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1760 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1761 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1762 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1763 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1764 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1767 SND_SOC_DAPM_OUTPUT("HPOL"),
1768 SND_SOC_DAPM_OUTPUT("HPOR"),
1772 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1774 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1775 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1778 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1779 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1780 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1781 {"ADC STO1 ASRC", NULL, "CLKDET"},
1782 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1783 {"DAC STO1 ASRC", NULL, "CLKDET"},
1786 {"MICBIAS1", NULL, "Vref1"},
1787 {"MICBIAS1", NULL, "Vref2"},
1788 {"MICBIAS2", NULL, "Vref1"},
1789 {"MICBIAS2", NULL, "Vref2"},
1791 {"CLKDET SYS", NULL, "CLKDET"},
1793 {"IN1P", NULL, "LDO2"},
1795 {"BST1 CBJ", NULL, "IN1P"},
1796 {"BST1 CBJ", NULL, "CBJ Power"},
1797 {"CBJ Power", NULL, "Vref2"},
1799 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1800 {"RECMIX1L", NULL, "RECMIX1L Power"},
1802 {"ADC1 L", NULL, "RECMIX1L"},
1803 {"ADC1 L", NULL, "ADC1 L Power"},
1804 {"ADC1 L", NULL, "ADC1 clock"},
1806 {"DMIC L1", NULL, "DMIC CLK"},
1807 {"DMIC L1", NULL, "DMIC1 Power"},
1808 {"DMIC R1", NULL, "DMIC CLK"},
1809 {"DMIC R1", NULL, "DMIC1 Power"},
1810 {"DMIC CLK", NULL, "DMIC ASRC"},
1812 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1813 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1814 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1815 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1817 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1818 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1819 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1820 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1822 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1823 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1824 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1825 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1827 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1828 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1829 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1831 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1832 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1833 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1835 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1837 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1838 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1840 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1841 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1842 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1843 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1844 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1845 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1846 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1847 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1848 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1849 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1850 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1851 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1852 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1853 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1854 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1855 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1857 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1858 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1859 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1860 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1861 {"IF1_ADC Mux", NULL, "I2S1"},
1862 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1863 {"AIF1TX", NULL, "ADCDAT Mux"},
1864 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1865 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1866 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1867 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1868 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1869 {"AIF2TX", NULL, "ADCDAT Mux"},
1871 {"IF1 DAC1 L", NULL, "AIF1RX"},
1872 {"IF1 DAC1 L", NULL, "I2S1"},
1873 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1874 {"IF1 DAC1 R", NULL, "AIF1RX"},
1875 {"IF1 DAC1 R", NULL, "I2S1"},
1876 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1878 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1879 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1880 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1881 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1883 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1884 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1886 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1887 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1889 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1890 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1891 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1892 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1894 {"DAC L1", NULL, "DAC L1 Source"},
1895 {"DAC R1", NULL, "DAC R1 Source"},
1897 {"DAC L1", NULL, "DAC 1 Clock"},
1898 {"DAC R1", NULL, "DAC 1 Clock"},
1900 {"HP Amp", NULL, "DAC L1"},
1901 {"HP Amp", NULL, "DAC R1"},
1902 {"HP Amp", NULL, "HP Amp L"},
1903 {"HP Amp", NULL, "HP Amp R"},
1904 {"HP Amp", NULL, "Capless"},
1905 {"HP Amp", NULL, "Charge Pump"},
1906 {"HP Amp", NULL, "CLKDET SYS"},
1907 {"HP Amp", NULL, "CBJ Power"},
1908 {"HP Amp", NULL, "Vref1"},
1909 {"HP Amp", NULL, "Vref2"},
1910 {"HPOL Playback", "Switch", "HP Amp"},
1911 {"HPOR Playback", "Switch", "HP Amp"},
1912 {"HPOL", NULL, "HPOL Playback"},
1913 {"HPOR", NULL, "HPOR Playback"},
1916 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1917 unsigned int rx_mask, int slots, int slot_width)
1919 struct snd_soc_component *component = dai->component;
1920 unsigned int cl, val = 0;
1922 if (tx_mask || rx_mask)
1923 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1924 RT5682_TDM_EN, RT5682_TDM_EN);
1926 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1931 val |= RT5682_TDM_TX_CH_4;
1932 val |= RT5682_TDM_RX_CH_4;
1935 val |= RT5682_TDM_TX_CH_6;
1936 val |= RT5682_TDM_RX_CH_6;
1939 val |= RT5682_TDM_TX_CH_8;
1940 val |= RT5682_TDM_RX_CH_8;
1948 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1949 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1951 switch (slot_width) {
1953 if (tx_mask || rx_mask)
1955 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1958 val = RT5682_TDM_CL_16;
1959 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1962 val = RT5682_TDM_CL_20;
1963 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1966 val = RT5682_TDM_CL_24;
1967 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1970 val = RT5682_TDM_CL_32;
1971 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1977 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1978 RT5682_TDM_CL_MASK, val);
1979 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1980 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1986 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1987 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1989 struct snd_soc_component *component = dai->component;
1990 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1991 unsigned int len_1 = 0, len_2 = 0;
1992 int pre_div, frame_size;
1994 rt5682->lrck[dai->id] = params_rate(params);
1995 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
1997 frame_size = snd_soc_params_to_frame_size(params);
1998 if (frame_size < 0) {
1999 dev_err(component->dev, "Unsupported frame size: %d\n",
2004 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2005 rt5682->lrck[dai->id], pre_div, dai->id);
2007 switch (params_width(params)) {
2011 len_1 |= RT5682_I2S1_DL_20;
2012 len_2 |= RT5682_I2S2_DL_20;
2015 len_1 |= RT5682_I2S1_DL_24;
2016 len_2 |= RT5682_I2S2_DL_24;
2019 len_1 |= RT5682_I2S1_DL_32;
2020 len_2 |= RT5682_I2S2_DL_24;
2023 len_1 |= RT5682_I2S2_DL_8;
2024 len_2 |= RT5682_I2S2_DL_8;
2032 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2033 RT5682_I2S1_DL_MASK, len_1);
2034 if (rt5682->master[RT5682_AIF1]) {
2035 snd_soc_component_update_bits(component,
2036 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2037 pre_div << RT5682_I2S_M_DIV_SFT);
2039 if (params_channels(params) == 1) /* mono mode */
2040 snd_soc_component_update_bits(component,
2041 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2042 RT5682_I2S1_MONO_EN);
2044 snd_soc_component_update_bits(component,
2045 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2046 RT5682_I2S1_MONO_DIS);
2049 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2050 RT5682_I2S2_DL_MASK, len_2);
2051 if (rt5682->master[RT5682_AIF2]) {
2052 snd_soc_component_update_bits(component,
2053 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2054 pre_div << RT5682_I2S2_M_PD_SFT);
2056 if (params_channels(params) == 1) /* mono mode */
2057 snd_soc_component_update_bits(component,
2058 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2059 RT5682_I2S2_MONO_EN);
2061 snd_soc_component_update_bits(component,
2062 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2063 RT5682_I2S2_MONO_DIS);
2066 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2073 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2075 struct snd_soc_component *component = dai->component;
2076 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2077 unsigned int reg_val = 0, tdm_ctrl = 0;
2079 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2080 case SND_SOC_DAIFMT_CBM_CFM:
2081 rt5682->master[dai->id] = 1;
2083 case SND_SOC_DAIFMT_CBS_CFS:
2084 rt5682->master[dai->id] = 0;
2090 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2091 case SND_SOC_DAIFMT_NB_NF:
2093 case SND_SOC_DAIFMT_IB_NF:
2094 reg_val |= RT5682_I2S_BP_INV;
2095 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2097 case SND_SOC_DAIFMT_NB_IF:
2098 if (dai->id == RT5682_AIF1)
2099 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2103 case SND_SOC_DAIFMT_IB_IF:
2104 if (dai->id == RT5682_AIF1)
2105 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2106 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2114 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2115 case SND_SOC_DAIFMT_I2S:
2117 case SND_SOC_DAIFMT_LEFT_J:
2118 reg_val |= RT5682_I2S_DF_LEFT;
2119 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2121 case SND_SOC_DAIFMT_DSP_A:
2122 reg_val |= RT5682_I2S_DF_PCM_A;
2123 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2125 case SND_SOC_DAIFMT_DSP_B:
2126 reg_val |= RT5682_I2S_DF_PCM_B;
2127 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2135 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2136 RT5682_I2S_DF_MASK, reg_val);
2137 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2138 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2139 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2140 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2141 tdm_ctrl | rt5682->master[dai->id]);
2144 if (rt5682->master[dai->id] == 0)
2145 reg_val |= RT5682_I2S2_MS_S;
2146 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2147 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2148 RT5682_I2S_DF_MASK, reg_val);
2151 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2157 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2158 int clk_id, int source, unsigned int freq, int dir)
2160 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2161 unsigned int reg_val = 0, src = 0;
2163 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2167 case RT5682_SCLK_S_MCLK:
2168 reg_val |= RT5682_SCLK_SRC_MCLK;
2169 src = RT5682_CLK_SRC_MCLK;
2171 case RT5682_SCLK_S_PLL1:
2172 reg_val |= RT5682_SCLK_SRC_PLL1;
2173 src = RT5682_CLK_SRC_PLL1;
2175 case RT5682_SCLK_S_PLL2:
2176 reg_val |= RT5682_SCLK_SRC_PLL2;
2177 src = RT5682_CLK_SRC_PLL2;
2179 case RT5682_SCLK_S_RCCLK:
2180 reg_val |= RT5682_SCLK_SRC_RCCLK;
2181 src = RT5682_CLK_SRC_RCCLK;
2184 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2187 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2188 RT5682_SCLK_SRC_MASK, reg_val);
2190 if (rt5682->master[RT5682_AIF2]) {
2191 snd_soc_component_update_bits(component,
2192 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2193 src << RT5682_I2S2_SRC_SFT);
2196 rt5682->sysclk = freq;
2197 rt5682->sysclk_src = clk_id;
2199 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2205 static int rt5682_set_component_pll(struct snd_soc_component *component,
2206 int pll_id, int source, unsigned int freq_in,
2207 unsigned int freq_out)
2209 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2210 struct rl6231_pll_code pll_code;
2213 if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2214 freq_out == rt5682->pll_out)
2217 if (!freq_in || !freq_out) {
2218 dev_dbg(component->dev, "PLL disabled\n");
2221 rt5682->pll_out = 0;
2222 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2223 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2228 case RT5682_PLL1_S_MCLK:
2229 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2230 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2232 case RT5682_PLL1_S_BCLK1:
2233 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2234 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2237 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2241 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2243 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2247 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2248 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2249 pll_code.n_code, pll_code.k_code);
2251 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2252 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2253 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2254 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2255 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2257 rt5682->pll_in = freq_in;
2258 rt5682->pll_out = freq_out;
2259 rt5682->pll_src = source;
2264 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2266 struct snd_soc_component *component = dai->component;
2267 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2269 rt5682->bclk[dai->id] = ratio;
2273 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2274 RT5682_I2S2_BCLK_MS2_MASK,
2275 RT5682_I2S2_BCLK_MS2_64);
2278 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2279 RT5682_I2S2_BCLK_MS2_MASK,
2280 RT5682_I2S2_BCLK_MS2_32);
2283 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2290 static int rt5682_set_bias_level(struct snd_soc_component *component,
2291 enum snd_soc_bias_level level)
2293 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2296 case SND_SOC_BIAS_PREPARE:
2297 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2298 RT5682_PWR_MB | RT5682_PWR_BG,
2299 RT5682_PWR_MB | RT5682_PWR_BG);
2300 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2301 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2302 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2305 case SND_SOC_BIAS_STANDBY:
2306 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2307 RT5682_PWR_MB, RT5682_PWR_MB);
2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2309 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2311 case SND_SOC_BIAS_OFF:
2312 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2313 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2314 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2315 RT5682_PWR_MB | RT5682_PWR_BG, 0);
2325 static int rt5682_probe(struct snd_soc_component *component)
2327 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2329 rt5682->component = component;
2334 static void rt5682_remove(struct snd_soc_component *component)
2336 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2338 rt5682_reset(rt5682->regmap);
2342 static int rt5682_suspend(struct snd_soc_component *component)
2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2346 regcache_cache_only(rt5682->regmap, true);
2347 regcache_mark_dirty(rt5682->regmap);
2351 static int rt5682_resume(struct snd_soc_component *component)
2353 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2355 regcache_cache_only(rt5682->regmap, false);
2356 regcache_sync(rt5682->regmap);
2361 #define rt5682_suspend NULL
2362 #define rt5682_resume NULL
2365 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2366 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2367 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2369 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2370 .hw_params = rt5682_hw_params,
2371 .set_fmt = rt5682_set_dai_fmt,
2372 .set_tdm_slot = rt5682_set_tdm_slot,
2375 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2376 .hw_params = rt5682_hw_params,
2377 .set_fmt = rt5682_set_dai_fmt,
2378 .set_bclk_ratio = rt5682_set_bclk_ratio,
2381 static struct snd_soc_dai_driver rt5682_dai[] = {
2383 .name = "rt5682-aif1",
2386 .stream_name = "AIF1 Playback",
2389 .rates = RT5682_STEREO_RATES,
2390 .formats = RT5682_FORMATS,
2393 .stream_name = "AIF1 Capture",
2396 .rates = RT5682_STEREO_RATES,
2397 .formats = RT5682_FORMATS,
2399 .ops = &rt5682_aif1_dai_ops,
2402 .name = "rt5682-aif2",
2405 .stream_name = "AIF2 Capture",
2408 .rates = RT5682_STEREO_RATES,
2409 .formats = RT5682_FORMATS,
2411 .ops = &rt5682_aif2_dai_ops,
2415 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2416 .probe = rt5682_probe,
2417 .remove = rt5682_remove,
2418 .suspend = rt5682_suspend,
2419 .resume = rt5682_resume,
2420 .set_bias_level = rt5682_set_bias_level,
2421 .controls = rt5682_snd_controls,
2422 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2423 .dapm_widgets = rt5682_dapm_widgets,
2424 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2425 .dapm_routes = rt5682_dapm_routes,
2426 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2427 .set_sysclk = rt5682_set_component_sysclk,
2428 .set_pll = rt5682_set_component_pll,
2429 .set_jack = rt5682_set_jack_detect,
2430 .use_pmdown_time = 1,
2432 .non_legacy_dai_naming = 1,
2435 static const struct regmap_config rt5682_regmap = {
2438 .max_register = RT5682_I2C_MODE,
2439 .volatile_reg = rt5682_volatile_register,
2440 .readable_reg = rt5682_readable_register,
2441 .cache_type = REGCACHE_RBTREE,
2442 .reg_defaults = rt5682_reg,
2443 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2444 .use_single_rw = true,
2447 static const struct i2c_device_id rt5682_i2c_id[] = {
2451 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2453 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2456 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2457 &rt5682->pdata.dmic1_data_pin);
2458 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2459 &rt5682->pdata.dmic1_clk_pin);
2460 device_property_read_u32(dev, "realtek,jd-src",
2461 &rt5682->pdata.jd_src);
2463 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2464 "realtek,ldo1-en-gpios", 0);
2469 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2473 mutex_lock(&rt5682->calibrate_mutex);
2475 rt5682_reset(rt5682->regmap);
2476 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2bf);
2477 usleep_range(15000, 20000);
2478 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2bf);
2479 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2480 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2481 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2482 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2483 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2484 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2485 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2486 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2487 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2489 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2491 for (count = 0; count < 60; count++) {
2492 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2493 if (!(value & 0x8000))
2496 usleep_range(10000, 10005);
2500 pr_err("HP Calibration Failure\n");
2502 /* restore settings */
2503 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2504 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2506 mutex_unlock(&rt5682->calibrate_mutex);
2510 static int rt5682_i2c_probe(struct i2c_client *i2c,
2511 const struct i2c_device_id *id)
2513 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2514 struct rt5682_priv *rt5682;
2518 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2524 i2c_set_clientdata(i2c, rt5682);
2527 rt5682->pdata = *pdata;
2529 rt5682_parse_dt(rt5682, &i2c->dev);
2531 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2532 if (IS_ERR(rt5682->regmap)) {
2533 ret = PTR_ERR(rt5682->regmap);
2534 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2539 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2540 rt5682->supplies[i].supply = rt5682_supply_names[i];
2542 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2545 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2549 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2552 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2556 if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2557 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2558 GPIOF_OUT_INIT_HIGH, "rt5682"))
2559 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2562 /* Sleep for 300 ms miniumum */
2563 usleep_range(300000, 350000);
2565 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2566 usleep_range(10000, 15000);
2568 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2569 if (val != DEVICE_ID) {
2570 pr_err("Device with ID register %x is not rt5682\n", val);
2574 rt5682_reset(rt5682->regmap);
2576 rt5682_calibrate(rt5682);
2578 ret = regmap_register_patch(rt5682->regmap, patch_list,
2579 ARRAY_SIZE(patch_list));
2581 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2583 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2586 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2587 switch (rt5682->pdata.dmic1_data_pin) {
2588 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2589 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2590 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2591 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2592 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2595 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2596 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2597 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2598 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2599 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2603 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2607 switch (rt5682->pdata.dmic1_clk_pin) {
2608 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2609 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2610 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2613 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2614 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2615 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2619 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2624 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2625 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2626 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2627 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2628 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2629 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2630 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2631 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2632 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2633 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2634 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2635 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2637 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2638 rt5682_jack_detect_handler);
2639 INIT_DELAYED_WORK(&rt5682->jd_check_work,
2640 rt5682_jd_check_handler);
2642 mutex_init(&rt5682->calibrate_mutex);
2645 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2646 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2647 | IRQF_ONESHOT, "rt5682", rt5682);
2649 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2653 return devm_snd_soc_register_component(&i2c->dev,
2654 &soc_component_dev_rt5682,
2655 rt5682_dai, ARRAY_SIZE(rt5682_dai));
2658 static void rt5682_i2c_shutdown(struct i2c_client *client)
2660 struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2662 rt5682_reset(rt5682->regmap);
2666 static const struct of_device_id rt5682_of_match[] = {
2667 {.compatible = "realtek,rt5682i"},
2670 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2674 static const struct acpi_device_id rt5682_acpi_match[] = {
2678 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2681 static struct i2c_driver rt5682_i2c_driver = {
2684 .of_match_table = of_match_ptr(rt5682_of_match),
2685 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2687 .probe = rt5682_i2c_probe,
2688 .shutdown = rt5682_i2c_shutdown,
2689 .id_table = rt5682_i2c_id,
2691 module_i2c_driver(rt5682_i2c_driver);
2693 MODULE_DESCRIPTION("ASoC RT5682 driver");
2694 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2695 MODULE_LICENSE("GPL v2");
projects / platform / kernel / linux-starfive.git / blob