sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682.c  --  RT5682 ALSA SoC audio component driver
   4 //
   5 // Copyright 2018 Realtek Semiconductor Corp.
   6 // Author: Bard Liao <bardliao@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/mutex.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/jack.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/rt5682.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5682.h"
  33
  34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  35         "AVDD",
  36         "MICVDD",
  37         "VBAT",
  38 };
  39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
  40
  41 static const struct reg_sequence patch_list[] = {
  42         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  43         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  44         {RT5682_I2C_CTRL, 0x000f},
  45         {RT5682_PLL2_INTERNAL, 0x8266},
  46 };
  47
  48 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  49 {
  50         int ret;
  51
  52         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  53                                      ARRAY_SIZE(patch_list));
  54         if (ret)
  55                 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  56 }
  57 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  58
  59 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  60         {0x0002, 0x8080},
  61         {0x0003, 0x8000},
  62         {0x0005, 0x0000},
  63         {0x0006, 0x0000},
  64         {0x0008, 0x800f},
  65         {0x000b, 0x0000},
  66         {0x0010, 0x4040},
  67         {0x0011, 0x0000},
  68         {0x0012, 0x1404},
  69         {0x0013, 0x1000},
  70         {0x0014, 0xa00a},
  71         {0x0015, 0x0404},
  72         {0x0016, 0x0404},
  73         {0x0019, 0xafaf},
  74         {0x001c, 0x2f2f},
  75         {0x001f, 0x0000},
  76         {0x0022, 0x5757},
  77         {0x0023, 0x0039},
  78         {0x0024, 0x000b},
  79         {0x0026, 0xc0c4},
  80         {0x0029, 0x8080},
  81         {0x002a, 0xa0a0},
  82         {0x002b, 0x0300},
  83         {0x0030, 0x0000},
  84         {0x003c, 0x0080},
  85         {0x0044, 0x0c0c},
  86         {0x0049, 0x0000},
  87         {0x0061, 0x0000},
  88         {0x0062, 0x0000},
  89         {0x0063, 0x003f},
  90         {0x0064, 0x0000},
  91         {0x0065, 0x0000},
  92         {0x0066, 0x0030},
  93         {0x0067, 0x0000},
  94         {0x006b, 0x0000},
  95         {0x006c, 0x0000},
  96         {0x006d, 0x2200},
  97         {0x006e, 0x0a10},
  98         {0x0070, 0x8000},
  99         {0x0071, 0x8000},
 100         {0x0073, 0x0000},
 101         {0x0074, 0x0000},
 102         {0x0075, 0x0002},
 103         {0x0076, 0x0001},
 104         {0x0079, 0x0000},
 105         {0x007a, 0x0000},
 106         {0x007b, 0x0000},
 107         {0x007c, 0x0100},
 108         {0x007e, 0x0000},
 109         {0x0080, 0x0000},
 110         {0x0081, 0x0000},
 111         {0x0082, 0x0000},
 112         {0x0083, 0x0000},
 113         {0x0084, 0x0000},
 114         {0x0085, 0x0000},
 115         {0x0086, 0x0005},
 116         {0x0087, 0x0000},
 117         {0x0088, 0x0000},
 118         {0x008c, 0x0003},
 119         {0x008d, 0x0000},
 120         {0x008e, 0x0060},
 121         {0x008f, 0x1000},
 122         {0x0091, 0x0c26},
 123         {0x0092, 0x0073},
 124         {0x0093, 0x0000},
 125         {0x0094, 0x0080},
 126         {0x0098, 0x0000},
 127         {0x009a, 0x0000},
 128         {0x009b, 0x0000},
 129         {0x009c, 0x0000},
 130         {0x009d, 0x0000},
 131         {0x009e, 0x100c},
 132         {0x009f, 0x0000},
 133         {0x00a0, 0x0000},
 134         {0x00a3, 0x0002},
 135         {0x00a4, 0x0001},
 136         {0x00ae, 0x2040},
 137         {0x00af, 0x0000},
 138         {0x00b6, 0x0000},
 139         {0x00b7, 0x0000},
 140         {0x00b8, 0x0000},
 141         {0x00b9, 0x0002},
 142         {0x00be, 0x0000},
 143         {0x00c0, 0x0160},
 144         {0x00c1, 0x82a0},
 145         {0x00c2, 0x0000},
 146         {0x00d0, 0x0000},
 147         {0x00d1, 0x2244},
 148         {0x00d2, 0x3300},
 149         {0x00d3, 0x2200},
 150         {0x00d4, 0x0000},
 151         {0x00d9, 0x0009},
 152         {0x00da, 0x0000},
 153         {0x00db, 0x0000},
 154         {0x00dc, 0x00c0},
 155         {0x00dd, 0x2220},
 156         {0x00de, 0x3131},
 157         {0x00df, 0x3131},
 158         {0x00e0, 0x3131},
 159         {0x00e2, 0x0000},
 160         {0x00e3, 0x4000},
 161         {0x00e4, 0x0aa0},
 162         {0x00e5, 0x3131},
 163         {0x00e6, 0x3131},
 164         {0x00e7, 0x3131},
 165         {0x00e8, 0x3131},
 166         {0x00ea, 0xb320},
 167         {0x00eb, 0x0000},
 168         {0x00f0, 0x0000},
 169         {0x00f1, 0x00d0},
 170         {0x00f2, 0x00d0},
 171         {0x00f6, 0x0000},
 172         {0x00fa, 0x0000},
 173         {0x00fb, 0x0000},
 174         {0x00fc, 0x0000},
 175         {0x00fd, 0x0000},
 176         {0x00fe, 0x10ec},
 177         {0x00ff, 0x6530},
 178         {0x0100, 0xa0a0},
 179         {0x010b, 0x0000},
 180         {0x010c, 0xae00},
 181         {0x010d, 0xaaa0},
 182         {0x010e, 0x8aa2},
 183         {0x010f, 0x02a2},
 184         {0x0110, 0xc000},
 185         {0x0111, 0x04a2},
 186         {0x0112, 0x2800},
 187         {0x0113, 0x0000},
 188         {0x0117, 0x0100},
 189         {0x0125, 0x0410},
 190         {0x0132, 0x6026},
 191         {0x0136, 0x5555},
 192         {0x0138, 0x3700},
 193         {0x013a, 0x2000},
 194         {0x013b, 0x2000},
 195         {0x013c, 0x2005},
 196         {0x013f, 0x0000},
 197         {0x0142, 0x0000},
 198         {0x0145, 0x0002},
 199         {0x0146, 0x0000},
 200         {0x0147, 0x0000},
 201         {0x0148, 0x0000},
 202         {0x0149, 0x0000},
 203         {0x0150, 0x79a1},
 204         {0x0156, 0xaaaa},
 205         {0x0160, 0x4ec0},
 206         {0x0161, 0x0080},
 207         {0x0162, 0x0200},
 208         {0x0163, 0x0800},
 209         {0x0164, 0x0000},
 210         {0x0165, 0x0000},
 211         {0x0166, 0x0000},
 212         {0x0167, 0x000f},
 213         {0x0168, 0x000f},
 214         {0x0169, 0x0021},
 215         {0x0190, 0x413d},
 216         {0x0194, 0x0000},
 217         {0x0195, 0x0000},
 218         {0x0197, 0x0022},
 219         {0x0198, 0x0000},
 220         {0x0199, 0x0000},
 221         {0x01af, 0x0000},
 222         {0x01b0, 0x0400},
 223         {0x01b1, 0x0000},
 224         {0x01b2, 0x0000},
 225         {0x01b3, 0x0000},
 226         {0x01b4, 0x0000},
 227         {0x01b5, 0x0000},
 228         {0x01b6, 0x01c3},
 229         {0x01b7, 0x02a0},
 230         {0x01b8, 0x03e9},
 231         {0x01b9, 0x1389},
 232         {0x01ba, 0xc351},
 233         {0x01bb, 0x0009},
 234         {0x01bc, 0x0018},
 235         {0x01bd, 0x002a},
 236         {0x01be, 0x004c},
 237         {0x01bf, 0x0097},
 238         {0x01c0, 0x433d},
 239         {0x01c2, 0x0000},
 240         {0x01c3, 0x0000},
 241         {0x01c4, 0x0000},
 242         {0x01c5, 0x0000},
 243         {0x01c6, 0x0000},
 244         {0x01c7, 0x0000},
 245         {0x01c8, 0x40af},
 246         {0x01c9, 0x0702},
 247         {0x01ca, 0x0000},
 248         {0x01cb, 0x0000},
 249         {0x01cc, 0x5757},
 250         {0x01cd, 0x5757},
 251         {0x01ce, 0x5757},
 252         {0x01cf, 0x5757},
 253         {0x01d0, 0x5757},
 254         {0x01d1, 0x5757},
 255         {0x01d2, 0x5757},
 256         {0x01d3, 0x5757},
 257         {0x01d4, 0x5757},
 258         {0x01d5, 0x5757},
 259         {0x01d6, 0x0000},
 260         {0x01d7, 0x0008},
 261         {0x01d8, 0x0029},
 262         {0x01d9, 0x3333},
 263         {0x01da, 0x0000},
 264         {0x01db, 0x0004},
 265         {0x01dc, 0x0000},
 266         {0x01de, 0x7c00},
 267         {0x01df, 0x0320},
 268         {0x01e0, 0x06a1},
 269         {0x01e1, 0x0000},
 270         {0x01e2, 0x0000},
 271         {0x01e3, 0x0000},
 272         {0x01e4, 0x0000},
 273         {0x01e6, 0x0001},
 274         {0x01e7, 0x0000},
 275         {0x01e8, 0x0000},
 276         {0x01ea, 0x0000},
 277         {0x01eb, 0x0000},
 278         {0x01ec, 0x0000},
 279         {0x01ed, 0x0000},
 280         {0x01ee, 0x0000},
 281         {0x01ef, 0x0000},
 282         {0x01f0, 0x0000},
 283         {0x01f1, 0x0000},
 284         {0x01f2, 0x0000},
 285         {0x01f3, 0x0000},
 286         {0x01f4, 0x0000},
 287         {0x0210, 0x6297},
 288         {0x0211, 0xa005},
 289         {0x0212, 0x824c},
 290         {0x0213, 0xf7ff},
 291         {0x0214, 0xf24c},
 292         {0x0215, 0x0102},
 293         {0x0216, 0x00a3},
 294         {0x0217, 0x0048},
 295         {0x0218, 0xa2c0},
 296         {0x0219, 0x0400},
 297         {0x021a, 0x00c8},
 298         {0x021b, 0x00c0},
 299         {0x021c, 0x0000},
 300         {0x0250, 0x4500},
 301         {0x0251, 0x40b3},
 302         {0x0252, 0x0000},
 303         {0x0253, 0x0000},
 304         {0x0254, 0x0000},
 305         {0x0255, 0x0000},
 306         {0x0256, 0x0000},
 307         {0x0257, 0x0000},
 308         {0x0258, 0x0000},
 309         {0x0259, 0x0000},
 310         {0x025a, 0x0005},
 311         {0x0270, 0x0000},
 312         {0x02ff, 0x0110},
 313         {0x0300, 0x001f},
 314         {0x0301, 0x032c},
 315         {0x0302, 0x5f21},
 316         {0x0303, 0x4000},
 317         {0x0304, 0x4000},
 318         {0x0305, 0x06d5},
 319         {0x0306, 0x8000},
 320         {0x0307, 0x0700},
 321         {0x0310, 0x4560},
 322         {0x0311, 0xa4a8},
 323         {0x0312, 0x7418},
 324         {0x0313, 0x0000},
 325         {0x0314, 0x0006},
 326         {0x0315, 0xffff},
 327         {0x0316, 0xc400},
 328         {0x0317, 0x0000},
 329         {0x03c0, 0x7e00},
 330         {0x03c1, 0x8000},
 331         {0x03c2, 0x8000},
 332         {0x03c3, 0x8000},
 333         {0x03c4, 0x8000},
 334         {0x03c5, 0x8000},
 335         {0x03c6, 0x8000},
 336         {0x03c7, 0x8000},
 337         {0x03c8, 0x8000},
 338         {0x03c9, 0x8000},
 339         {0x03ca, 0x8000},
 340         {0x03cb, 0x8000},
 341         {0x03cc, 0x8000},
 342         {0x03d0, 0x0000},
 343         {0x03d1, 0x0000},
 344         {0x03d2, 0x0000},
 345         {0x03d3, 0x0000},
 346         {0x03d4, 0x2000},
 347         {0x03d5, 0x2000},
 348         {0x03d6, 0x0000},
 349         {0x03d7, 0x0000},
 350         {0x03d8, 0x2000},
 351         {0x03d9, 0x2000},
 352         {0x03da, 0x2000},
 353         {0x03db, 0x2000},
 354         {0x03dc, 0x0000},
 355         {0x03dd, 0x0000},
 356         {0x03de, 0x0000},
 357         {0x03df, 0x2000},
 358         {0x03e0, 0x0000},
 359         {0x03e1, 0x0000},
 360         {0x03e2, 0x0000},
 361         {0x03e3, 0x0000},
 362         {0x03e4, 0x0000},
 363         {0x03e5, 0x0000},
 364         {0x03e6, 0x0000},
 365         {0x03e7, 0x0000},
 366         {0x03e8, 0x0000},
 367         {0x03e9, 0x0000},
 368         {0x03ea, 0x0000},
 369         {0x03eb, 0x0000},
 370         {0x03ec, 0x0000},
 371         {0x03ed, 0x0000},
 372         {0x03ee, 0x0000},
 373         {0x03ef, 0x0000},
 374         {0x03f0, 0x0800},
 375         {0x03f1, 0x0800},
 376         {0x03f2, 0x0800},
 377         {0x03f3, 0x0800},
 378 };
 379 EXPORT_SYMBOL_GPL(rt5682_reg);
 380
 381 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 382 {
 383         switch (reg) {
 384         case RT5682_RESET:
 385         case RT5682_CBJ_CTRL_2:
 386         case RT5682_INT_ST_1:
 387         case RT5682_4BTN_IL_CMD_1:
 388         case RT5682_AJD1_CTRL:
 389         case RT5682_HP_CALIB_CTRL_1:
 390         case RT5682_DEVICE_ID:
 391         case RT5682_I2C_MODE:
 392         case RT5682_HP_CALIB_CTRL_10:
 393         case RT5682_EFUSE_CTRL_2:
 394         case RT5682_JD_TOP_VC_VTRL:
 395         case RT5682_HP_IMP_SENS_CTRL_19:
 396         case RT5682_IL_CMD_1:
 397         case RT5682_SAR_IL_CMD_2:
 398         case RT5682_SAR_IL_CMD_4:
 399         case RT5682_SAR_IL_CMD_10:
 400         case RT5682_SAR_IL_CMD_11:
 401         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 402         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 403                 return true;
 404         default:
 405                 return false;
 406         }
 407 }
 408 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
 409
 410 bool rt5682_readable_register(struct device *dev, unsigned int reg)
 411 {
 412         switch (reg) {
 413         case RT5682_RESET:
 414         case RT5682_VERSION_ID:
 415         case RT5682_VENDOR_ID:
 416         case RT5682_DEVICE_ID:
 417         case RT5682_HP_CTRL_1:
 418         case RT5682_HP_CTRL_2:
 419         case RT5682_HPL_GAIN:
 420         case RT5682_HPR_GAIN:
 421         case RT5682_I2C_CTRL:
 422         case RT5682_CBJ_BST_CTRL:
 423         case RT5682_CBJ_CTRL_1:
 424         case RT5682_CBJ_CTRL_2:
 425         case RT5682_CBJ_CTRL_3:
 426         case RT5682_CBJ_CTRL_4:
 427         case RT5682_CBJ_CTRL_5:
 428         case RT5682_CBJ_CTRL_6:
 429         case RT5682_CBJ_CTRL_7:
 430         case RT5682_DAC1_DIG_VOL:
 431         case RT5682_STO1_ADC_DIG_VOL:
 432         case RT5682_STO1_ADC_BOOST:
 433         case RT5682_HP_IMP_GAIN_1:
 434         case RT5682_HP_IMP_GAIN_2:
 435         case RT5682_SIDETONE_CTRL:
 436         case RT5682_STO1_ADC_MIXER:
 437         case RT5682_AD_DA_MIXER:
 438         case RT5682_STO1_DAC_MIXER:
 439         case RT5682_A_DAC1_MUX:
 440         case RT5682_DIG_INF2_DATA:
 441         case RT5682_REC_MIXER:
 442         case RT5682_CAL_REC:
 443         case RT5682_ALC_BACK_GAIN:
 444         case RT5682_PWR_DIG_1:
 445         case RT5682_PWR_DIG_2:
 446         case RT5682_PWR_ANLG_1:
 447         case RT5682_PWR_ANLG_2:
 448         case RT5682_PWR_ANLG_3:
 449         case RT5682_PWR_MIXER:
 450         case RT5682_PWR_VOL:
 451         case RT5682_CLK_DET:
 452         case RT5682_RESET_LPF_CTRL:
 453         case RT5682_RESET_HPF_CTRL:
 454         case RT5682_DMIC_CTRL_1:
 455         case RT5682_I2S1_SDP:
 456         case RT5682_I2S2_SDP:
 457         case RT5682_ADDA_CLK_1:
 458         case RT5682_ADDA_CLK_2:
 459         case RT5682_I2S1_F_DIV_CTRL_1:
 460         case RT5682_I2S1_F_DIV_CTRL_2:
 461         case RT5682_TDM_CTRL:
 462         case RT5682_TDM_ADDA_CTRL_1:
 463         case RT5682_TDM_ADDA_CTRL_2:
 464         case RT5682_DATA_SEL_CTRL_1:
 465         case RT5682_TDM_TCON_CTRL:
 466         case RT5682_GLB_CLK:
 467         case RT5682_PLL_CTRL_1:
 468         case RT5682_PLL_CTRL_2:
 469         case RT5682_PLL_TRACK_1:
 470         case RT5682_PLL_TRACK_2:
 471         case RT5682_PLL_TRACK_3:
 472         case RT5682_PLL_TRACK_4:
 473         case RT5682_PLL_TRACK_5:
 474         case RT5682_PLL_TRACK_6:
 475         case RT5682_PLL_TRACK_11:
 476         case RT5682_SDW_REF_CLK:
 477         case RT5682_DEPOP_1:
 478         case RT5682_DEPOP_2:
 479         case RT5682_HP_CHARGE_PUMP_1:
 480         case RT5682_HP_CHARGE_PUMP_2:
 481         case RT5682_MICBIAS_1:
 482         case RT5682_MICBIAS_2:
 483         case RT5682_PLL_TRACK_12:
 484         case RT5682_PLL_TRACK_14:
 485         case RT5682_PLL2_CTRL_1:
 486         case RT5682_PLL2_CTRL_2:
 487         case RT5682_PLL2_CTRL_3:
 488         case RT5682_PLL2_CTRL_4:
 489         case RT5682_RC_CLK_CTRL:
 490         case RT5682_I2S_M_CLK_CTRL_1:
 491         case RT5682_I2S2_F_DIV_CTRL_1:
 492         case RT5682_I2S2_F_DIV_CTRL_2:
 493         case RT5682_EQ_CTRL_1:
 494         case RT5682_EQ_CTRL_2:
 495         case RT5682_IRQ_CTRL_1:
 496         case RT5682_IRQ_CTRL_2:
 497         case RT5682_IRQ_CTRL_3:
 498         case RT5682_IRQ_CTRL_4:
 499         case RT5682_INT_ST_1:
 500         case RT5682_GPIO_CTRL_1:
 501         case RT5682_GPIO_CTRL_2:
 502         case RT5682_GPIO_CTRL_3:
 503         case RT5682_HP_AMP_DET_CTRL_1:
 504         case RT5682_HP_AMP_DET_CTRL_2:
 505         case RT5682_MID_HP_AMP_DET:
 506         case RT5682_LOW_HP_AMP_DET:
 507         case RT5682_DELAY_BUF_CTRL:
 508         case RT5682_SV_ZCD_1:
 509         case RT5682_SV_ZCD_2:
 510         case RT5682_IL_CMD_1:
 511         case RT5682_IL_CMD_2:
 512         case RT5682_IL_CMD_3:
 513         case RT5682_IL_CMD_4:
 514         case RT5682_IL_CMD_5:
 515         case RT5682_IL_CMD_6:
 516         case RT5682_4BTN_IL_CMD_1:
 517         case RT5682_4BTN_IL_CMD_2:
 518         case RT5682_4BTN_IL_CMD_3:
 519         case RT5682_4BTN_IL_CMD_4:
 520         case RT5682_4BTN_IL_CMD_5:
 521         case RT5682_4BTN_IL_CMD_6:
 522         case RT5682_4BTN_IL_CMD_7:
 523         case RT5682_ADC_STO1_HP_CTRL_1:
 524         case RT5682_ADC_STO1_HP_CTRL_2:
 525         case RT5682_AJD1_CTRL:
 526         case RT5682_JD1_THD:
 527         case RT5682_JD2_THD:
 528         case RT5682_JD_CTRL_1:
 529         case RT5682_DUMMY_1:
 530         case RT5682_DUMMY_2:
 531         case RT5682_DUMMY_3:
 532         case RT5682_DAC_ADC_DIG_VOL1:
 533         case RT5682_BIAS_CUR_CTRL_2:
 534         case RT5682_BIAS_CUR_CTRL_3:
 535         case RT5682_BIAS_CUR_CTRL_4:
 536         case RT5682_BIAS_CUR_CTRL_5:
 537         case RT5682_BIAS_CUR_CTRL_6:
 538         case RT5682_BIAS_CUR_CTRL_7:
 539         case RT5682_BIAS_CUR_CTRL_8:
 540         case RT5682_BIAS_CUR_CTRL_9:
 541         case RT5682_BIAS_CUR_CTRL_10:
 542         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 543         case RT5682_CHARGE_PUMP_1:
 544         case RT5682_DIG_IN_CTRL_1:
 545         case RT5682_PAD_DRIVING_CTRL:
 546         case RT5682_SOFT_RAMP_DEPOP:
 547         case RT5682_CHOP_DAC:
 548         case RT5682_CHOP_ADC:
 549         case RT5682_CALIB_ADC_CTRL:
 550         case RT5682_VOL_TEST:
 551         case RT5682_SPKVDD_DET_STA:
 552         case RT5682_TEST_MODE_CTRL_1:
 553         case RT5682_TEST_MODE_CTRL_2:
 554         case RT5682_TEST_MODE_CTRL_3:
 555         case RT5682_TEST_MODE_CTRL_4:
 556         case RT5682_TEST_MODE_CTRL_5:
 557         case RT5682_PLL1_INTERNAL:
 558         case RT5682_PLL2_INTERNAL:
 559         case RT5682_STO_NG2_CTRL_1:
 560         case RT5682_STO_NG2_CTRL_2:
 561         case RT5682_STO_NG2_CTRL_3:
 562         case RT5682_STO_NG2_CTRL_4:
 563         case RT5682_STO_NG2_CTRL_5:
 564         case RT5682_STO_NG2_CTRL_6:
 565         case RT5682_STO_NG2_CTRL_7:
 566         case RT5682_STO_NG2_CTRL_8:
 567         case RT5682_STO_NG2_CTRL_9:
 568         case RT5682_STO_NG2_CTRL_10:
 569         case RT5682_STO1_DAC_SIL_DET:
 570         case RT5682_SIL_PSV_CTRL1:
 571         case RT5682_SIL_PSV_CTRL2:
 572         case RT5682_SIL_PSV_CTRL3:
 573         case RT5682_SIL_PSV_CTRL4:
 574         case RT5682_SIL_PSV_CTRL5:
 575         case RT5682_HP_IMP_SENS_CTRL_01:
 576         case RT5682_HP_IMP_SENS_CTRL_02:
 577         case RT5682_HP_IMP_SENS_CTRL_03:
 578         case RT5682_HP_IMP_SENS_CTRL_04:
 579         case RT5682_HP_IMP_SENS_CTRL_05:
 580         case RT5682_HP_IMP_SENS_CTRL_06:
 581         case RT5682_HP_IMP_SENS_CTRL_07:
 582         case RT5682_HP_IMP_SENS_CTRL_08:
 583         case RT5682_HP_IMP_SENS_CTRL_09:
 584         case RT5682_HP_IMP_SENS_CTRL_10:
 585         case RT5682_HP_IMP_SENS_CTRL_11:
 586         case RT5682_HP_IMP_SENS_CTRL_12:
 587         case RT5682_HP_IMP_SENS_CTRL_13:
 588         case RT5682_HP_IMP_SENS_CTRL_14:
 589         case RT5682_HP_IMP_SENS_CTRL_15:
 590         case RT5682_HP_IMP_SENS_CTRL_16:
 591         case RT5682_HP_IMP_SENS_CTRL_17:
 592         case RT5682_HP_IMP_SENS_CTRL_18:
 593         case RT5682_HP_IMP_SENS_CTRL_19:
 594         case RT5682_HP_IMP_SENS_CTRL_20:
 595         case RT5682_HP_IMP_SENS_CTRL_21:
 596         case RT5682_HP_IMP_SENS_CTRL_22:
 597         case RT5682_HP_IMP_SENS_CTRL_23:
 598         case RT5682_HP_IMP_SENS_CTRL_24:
 599         case RT5682_HP_IMP_SENS_CTRL_25:
 600         case RT5682_HP_IMP_SENS_CTRL_26:
 601         case RT5682_HP_IMP_SENS_CTRL_27:
 602         case RT5682_HP_IMP_SENS_CTRL_28:
 603         case RT5682_HP_IMP_SENS_CTRL_29:
 604         case RT5682_HP_IMP_SENS_CTRL_30:
 605         case RT5682_HP_IMP_SENS_CTRL_31:
 606         case RT5682_HP_IMP_SENS_CTRL_32:
 607         case RT5682_HP_IMP_SENS_CTRL_33:
 608         case RT5682_HP_IMP_SENS_CTRL_34:
 609         case RT5682_HP_IMP_SENS_CTRL_35:
 610         case RT5682_HP_IMP_SENS_CTRL_36:
 611         case RT5682_HP_IMP_SENS_CTRL_37:
 612         case RT5682_HP_IMP_SENS_CTRL_38:
 613         case RT5682_HP_IMP_SENS_CTRL_39:
 614         case RT5682_HP_IMP_SENS_CTRL_40:
 615         case RT5682_HP_IMP_SENS_CTRL_41:
 616         case RT5682_HP_IMP_SENS_CTRL_42:
 617         case RT5682_HP_IMP_SENS_CTRL_43:
 618         case RT5682_HP_LOGIC_CTRL_1:
 619         case RT5682_HP_LOGIC_CTRL_2:
 620         case RT5682_HP_LOGIC_CTRL_3:
 621         case RT5682_HP_CALIB_CTRL_1:
 622         case RT5682_HP_CALIB_CTRL_2:
 623         case RT5682_HP_CALIB_CTRL_3:
 624         case RT5682_HP_CALIB_CTRL_4:
 625         case RT5682_HP_CALIB_CTRL_5:
 626         case RT5682_HP_CALIB_CTRL_6:
 627         case RT5682_HP_CALIB_CTRL_7:
 628         case RT5682_HP_CALIB_CTRL_9:
 629         case RT5682_HP_CALIB_CTRL_10:
 630         case RT5682_HP_CALIB_CTRL_11:
 631         case RT5682_HP_CALIB_STA_1:
 632         case RT5682_HP_CALIB_STA_2:
 633         case RT5682_HP_CALIB_STA_3:
 634         case RT5682_HP_CALIB_STA_4:
 635         case RT5682_HP_CALIB_STA_5:
 636         case RT5682_HP_CALIB_STA_6:
 637         case RT5682_HP_CALIB_STA_7:
 638         case RT5682_HP_CALIB_STA_8:
 639         case RT5682_HP_CALIB_STA_9:
 640         case RT5682_HP_CALIB_STA_10:
 641         case RT5682_HP_CALIB_STA_11:
 642         case RT5682_SAR_IL_CMD_1:
 643         case RT5682_SAR_IL_CMD_2:
 644         case RT5682_SAR_IL_CMD_3:
 645         case RT5682_SAR_IL_CMD_4:
 646         case RT5682_SAR_IL_CMD_5:
 647         case RT5682_SAR_IL_CMD_6:
 648         case RT5682_SAR_IL_CMD_7:
 649         case RT5682_SAR_IL_CMD_8:
 650         case RT5682_SAR_IL_CMD_9:
 651         case RT5682_SAR_IL_CMD_10:
 652         case RT5682_SAR_IL_CMD_11:
 653         case RT5682_SAR_IL_CMD_12:
 654         case RT5682_SAR_IL_CMD_13:
 655         case RT5682_EFUSE_CTRL_1:
 656         case RT5682_EFUSE_CTRL_2:
 657         case RT5682_EFUSE_CTRL_3:
 658         case RT5682_EFUSE_CTRL_4:
 659         case RT5682_EFUSE_CTRL_5:
 660         case RT5682_EFUSE_CTRL_6:
 661         case RT5682_EFUSE_CTRL_7:
 662         case RT5682_EFUSE_CTRL_8:
 663         case RT5682_EFUSE_CTRL_9:
 664         case RT5682_EFUSE_CTRL_10:
 665         case RT5682_EFUSE_CTRL_11:
 666         case RT5682_JD_TOP_VC_VTRL:
 667         case RT5682_DRC1_CTRL_0:
 668         case RT5682_DRC1_CTRL_1:
 669         case RT5682_DRC1_CTRL_2:
 670         case RT5682_DRC1_CTRL_3:
 671         case RT5682_DRC1_CTRL_4:
 672         case RT5682_DRC1_CTRL_5:
 673         case RT5682_DRC1_CTRL_6:
 674         case RT5682_DRC1_HARD_LMT_CTRL_1:
 675         case RT5682_DRC1_HARD_LMT_CTRL_2:
 676         case RT5682_DRC1_PRIV_1:
 677         case RT5682_DRC1_PRIV_2:
 678         case RT5682_DRC1_PRIV_3:
 679         case RT5682_DRC1_PRIV_4:
 680         case RT5682_DRC1_PRIV_5:
 681         case RT5682_DRC1_PRIV_6:
 682         case RT5682_DRC1_PRIV_7:
 683         case RT5682_DRC1_PRIV_8:
 684         case RT5682_EQ_AUTO_RCV_CTRL1:
 685         case RT5682_EQ_AUTO_RCV_CTRL2:
 686         case RT5682_EQ_AUTO_RCV_CTRL3:
 687         case RT5682_EQ_AUTO_RCV_CTRL4:
 688         case RT5682_EQ_AUTO_RCV_CTRL5:
 689         case RT5682_EQ_AUTO_RCV_CTRL6:
 690         case RT5682_EQ_AUTO_RCV_CTRL7:
 691         case RT5682_EQ_AUTO_RCV_CTRL8:
 692         case RT5682_EQ_AUTO_RCV_CTRL9:
 693         case RT5682_EQ_AUTO_RCV_CTRL10:
 694         case RT5682_EQ_AUTO_RCV_CTRL11:
 695         case RT5682_EQ_AUTO_RCV_CTRL12:
 696         case RT5682_EQ_AUTO_RCV_CTRL13:
 697         case RT5682_ADC_L_EQ_LPF1_A1:
 698         case RT5682_R_EQ_LPF1_A1:
 699         case RT5682_L_EQ_LPF1_H0:
 700         case RT5682_R_EQ_LPF1_H0:
 701         case RT5682_L_EQ_BPF1_A1:
 702         case RT5682_R_EQ_BPF1_A1:
 703         case RT5682_L_EQ_BPF1_A2:
 704         case RT5682_R_EQ_BPF1_A2:
 705         case RT5682_L_EQ_BPF1_H0:
 706         case RT5682_R_EQ_BPF1_H0:
 707         case RT5682_L_EQ_BPF2_A1:
 708         case RT5682_R_EQ_BPF2_A1:
 709         case RT5682_L_EQ_BPF2_A2:
 710         case RT5682_R_EQ_BPF2_A2:
 711         case RT5682_L_EQ_BPF2_H0:
 712         case RT5682_R_EQ_BPF2_H0:
 713         case RT5682_L_EQ_BPF3_A1:
 714         case RT5682_R_EQ_BPF3_A1:
 715         case RT5682_L_EQ_BPF3_A2:
 716         case RT5682_R_EQ_BPF3_A2:
 717         case RT5682_L_EQ_BPF3_H0:
 718         case RT5682_R_EQ_BPF3_H0:
 719         case RT5682_L_EQ_BPF4_A1:
 720         case RT5682_R_EQ_BPF4_A1:
 721         case RT5682_L_EQ_BPF4_A2:
 722         case RT5682_R_EQ_BPF4_A2:
 723         case RT5682_L_EQ_BPF4_H0:
 724         case RT5682_R_EQ_BPF4_H0:
 725         case RT5682_L_EQ_HPF1_A1:
 726         case RT5682_R_EQ_HPF1_A1:
 727         case RT5682_L_EQ_HPF1_H0:
 728         case RT5682_R_EQ_HPF1_H0:
 729         case RT5682_L_EQ_PRE_VOL:
 730         case RT5682_R_EQ_PRE_VOL:
 731         case RT5682_L_EQ_POST_VOL:
 732         case RT5682_R_EQ_POST_VOL:
 733         case RT5682_I2C_MODE:
 734                 return true;
 735         default:
 736                 return false;
 737         }
 738 }
 739 EXPORT_SYMBOL_GPL(rt5682_readable_register);
 740
 741 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 742 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 743 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 744
 745 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 746 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 747         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 748         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 749         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 750         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 751         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 752         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 753         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 754 );
 755
 756 /* Interface data select */
 757 static const char * const rt5682_data_select[] = {
 758         "L/R", "R/L", "L/L", "R/R"
 759 };
 760
 761 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 762         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 763
 764 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 765         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 766
 767 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 768         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 769
 770 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 771         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 772
 773 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 774         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 775
 776 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 777         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 778
 779 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 780         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 781
 782 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 783         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 784
 785 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 786         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 787
 788 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 789         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 790
 791 static const char * const rt5682_dac_select[] = {
 792         "IF1", "SOUND"
 793 };
 794
 795 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
 796         RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
 797
 798 static const struct snd_kcontrol_new rt5682_dac_l_mux =
 799         SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
 800
 801 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
 802         RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
 803
 804 static const struct snd_kcontrol_new rt5682_dac_r_mux =
 805         SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
 806
 807 void rt5682_reset(struct rt5682_priv *rt5682)
 808 {
 809         regmap_write(rt5682->regmap, RT5682_RESET, 0);
 810         if (!rt5682->is_sdw)
 811                 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
 812 }
 813 EXPORT_SYMBOL_GPL(rt5682_reset);
 814
 815 /**
 816  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 817  * @component: SoC audio component device.
 818  * @filter_mask: mask of filters.
 819  * @clk_src: clock source
 820  *
 821  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 822  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 823  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 824  * ASRC function will track i2s clock and generate a corresponding system clock
 825  * for codec. This function provides an API to select the clock source for a
 826  * set of filters specified by the mask. And the component driver will turn on
 827  * ASRC for these filters if ASRC is selected as their clock source.
 828  */
 829 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 830                 unsigned int filter_mask, unsigned int clk_src)
 831 {
 832         switch (clk_src) {
 833         case RT5682_CLK_SEL_SYS:
 834         case RT5682_CLK_SEL_I2S1_ASRC:
 835         case RT5682_CLK_SEL_I2S2_ASRC:
 836                 break;
 837
 838         default:
 839                 return -EINVAL;
 840         }
 841
 842         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 843                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 844                         RT5682_FILTER_CLK_SEL_MASK,
 845                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 846         }
 847
 848         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 849                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 850                         RT5682_FILTER_CLK_SEL_MASK,
 851                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 852         }
 853
 854         return 0;
 855 }
 856 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 857
 858 static int rt5682_button_detect(struct snd_soc_component *component)
 859 {
 860         int btn_type, val;
 861
 862         val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
 863         btn_type = val & 0xfff0;
 864         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 865         dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
 866         snd_soc_component_update_bits(component,
 867                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 868
 869         return btn_type;
 870 }
 871
 872 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 873                 bool enable)
 874 {
 875         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 876
 877         if (enable) {
 878                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 879                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 880                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 881                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 882                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 883                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 884                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 885                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 886                 if (rt5682->is_sdw)
 887                         snd_soc_component_update_bits(component,
 888                                 RT5682_IRQ_CTRL_3,
 889                                 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
 890                                 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
 891                 else
 892                         snd_soc_component_update_bits(component,
 893                                 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
 894                                 RT5682_IL_IRQ_EN);
 895         } else {
 896                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 897                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 898                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 899                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 900                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 901                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 902                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 903                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 904                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 905                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 906         }
 907 }
 908
 909 /**
 910  * rt5682_headset_detect - Detect headset.
 911  * @component: SoC audio component device.
 912  * @jack_insert: Jack insert or not.
 913  *
 914  * Detect whether is headset or not when jack inserted.
 915  *
 916  * Returns detect status.
 917  */
 918 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
 919 {
 920         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 921         struct snd_soc_dapm_context *dapm = &component->dapm;
 922         unsigned int val, count;
 923
 924         if (jack_insert) {
 925                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 926                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 927                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 928                 snd_soc_component_update_bits(component,
 929                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 930                 usleep_range(15000, 20000);
 931                 snd_soc_component_update_bits(component,
 932                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 933                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 934                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 935                 snd_soc_component_update_bits(component,
 936                         RT5682_HP_CHARGE_PUMP_1,
 937                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
 938                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 939                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 940
 941                 count = 0;
 942                 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
 943                         & RT5682_JACK_TYPE_MASK;
 944                 while (val == 0 && count < 50) {
 945                         usleep_range(10000, 15000);
 946                         val = snd_soc_component_read32(component,
 947                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 948                         count++;
 949                 }
 950
 951                 switch (val) {
 952                 case 0x1:
 953                 case 0x2:
 954                         rt5682->jack_type = SND_JACK_HEADSET;
 955                         rt5682_enable_push_button_irq(component, true);
 956                         break;
 957                 default:
 958                         rt5682->jack_type = SND_JACK_HEADPHONE;
 959                         break;
 960                 }
 961
 962                 snd_soc_component_update_bits(component,
 963                         RT5682_HP_CHARGE_PUMP_1,
 964                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
 965                         RT5682_OSW_L_EN | RT5682_OSW_R_EN);
 966         } else {
 967                 rt5682_enable_push_button_irq(component, false);
 968                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 969                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 970                 if (snd_soc_dapm_get_pin_status(dapm, "MICBIAS"))
 971                         snd_soc_component_update_bits(component,
 972                                 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
 973                 else
 974                         snd_soc_component_update_bits(component,
 975                                 RT5682_PWR_ANLG_1,
 976                                 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
 977                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 978                         RT5682_PWR_CBJ, 0);
 979
 980                 rt5682->jack_type = 0;
 981         }
 982
 983         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
 984         return rt5682->jack_type;
 985 }
 986 EXPORT_SYMBOL_GPL(rt5682_headset_detect);
 987
 988 static int rt5682_set_jack_detect(struct snd_soc_component *component,
 989                 struct snd_soc_jack *hs_jack, void *data)
 990 {
 991         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 992
 993         rt5682->hs_jack = hs_jack;
 994
 995         if (!rt5682->is_sdw) {
 996                 if (!hs_jack) {
 997                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
 998                                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
 999                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1000                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1001                         cancel_delayed_work_sync(&rt5682->jack_detect_work);
1002                         return 0;
1003                 }
1004
1005                 switch (rt5682->pdata.jd_src) {
1006                 case RT5682_JD1:
1007                         snd_soc_component_update_bits(component,
1008                                 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1009                                 RT5682_EXT_JD_SRC_MANUAL);
1010                         snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1011                                 0xd042);
1012                         snd_soc_component_update_bits(component,
1013                                 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1014                                 RT5682_CBJ_IN_BUF_EN);
1015                         snd_soc_component_update_bits(component,
1016                                 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1017                                 RT5682_SAR_POW_EN);
1018                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1019                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1020                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1021                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1022                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1023                                 RT5682_POW_JDH | RT5682_POW_ANA);
1024                         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1025                                 RT5682_PWR_JDH | RT5682_PWR_JDL,
1026                                 RT5682_PWR_JDH | RT5682_PWR_JDL);
1027                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1028                                 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1029                                 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1030                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1031                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1032                                 rt5682->pdata.btndet_delay));
1033                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1034                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1035                                 rt5682->pdata.btndet_delay));
1036                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1037                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1038                                 rt5682->pdata.btndet_delay));
1039                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1040                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1041                                 rt5682->pdata.btndet_delay));
1042                         mod_delayed_work(system_power_efficient_wq,
1043                                 &rt5682->jack_detect_work,
1044                                 msecs_to_jiffies(250));
1045                         break;
1046
1047                 case RT5682_JD_NULL:
1048                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1049                                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1050                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1051                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1052                         break;
1053
1054                 default:
1055                         dev_warn(component->dev, "Wrong JD source\n");
1056                         break;
1057                 }
1058         }
1059
1060         return 0;
1061 }
1062
1063 void rt5682_jack_detect_handler(struct work_struct *work)
1064 {
1065         struct rt5682_priv *rt5682 =
1066                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1067         int val, btn_type;
1068
1069         while (!rt5682->component)
1070                 usleep_range(10000, 15000);
1071
1072         while (!rt5682->component->card->instantiated)
1073                 usleep_range(10000, 15000);
1074
1075         mutex_lock(&rt5682->calibrate_mutex);
1076
1077         val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1078                 & RT5682_JDH_RS_MASK;
1079         if (!val) {
1080                 /* jack in */
1081                 if (rt5682->jack_type == 0) {
1082                         /* jack was out, report jack type */
1083                         rt5682->jack_type =
1084                                 rt5682_headset_detect(rt5682->component, 1);
1085                 } else {
1086                         /* jack is already in, report button event */
1087                         rt5682->jack_type = SND_JACK_HEADSET;
1088                         btn_type = rt5682_button_detect(rt5682->component);
1089                         /**
1090                          * rt5682 can report three kinds of button behavior,
1091                          * one click, double click and hold. However,
1092                          * currently we will report button pressed/released
1093                          * event. So all the three button behaviors are
1094                          * treated as button pressed.
1095                          */
1096                         switch (btn_type) {
1097                         case 0x8000:
1098                         case 0x4000:
1099                         case 0x2000:
1100                                 rt5682->jack_type |= SND_JACK_BTN_0;
1101                                 break;
1102                         case 0x1000:
1103                         case 0x0800:
1104                         case 0x0400:
1105                                 rt5682->jack_type |= SND_JACK_BTN_1;
1106                                 break;
1107                         case 0x0200:
1108                         case 0x0100:
1109                         case 0x0080:
1110                                 rt5682->jack_type |= SND_JACK_BTN_2;
1111                                 break;
1112                         case 0x0040:
1113                         case 0x0020:
1114                         case 0x0010:
1115                                 rt5682->jack_type |= SND_JACK_BTN_3;
1116                                 break;
1117                         case 0x0000: /* unpressed */
1118                                 break;
1119                         default:
1120                                 dev_err(rt5682->component->dev,
1121                                         "Unexpected button code 0x%04x\n",
1122                                         btn_type);
1123                                 break;
1124                         }
1125                 }
1126         } else {
1127                 /* jack out */
1128                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1129         }
1130
1131         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1132                 SND_JACK_HEADSET |
1133                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1134                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1135
1136         if (!rt5682->is_sdw) {
1137                 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1138                         SND_JACK_BTN_2 | SND_JACK_BTN_3))
1139                         schedule_delayed_work(&rt5682->jd_check_work, 0);
1140                 else
1141                         cancel_delayed_work_sync(&rt5682->jd_check_work);
1142         }
1143
1144         mutex_unlock(&rt5682->calibrate_mutex);
1145 }
1146 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1147
1148 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1149         /* DAC Digital Volume */
1150         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1151                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1152
1153         /* IN Boost Volume */
1154         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1155                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1156
1157         /* ADC Digital Volume Control */
1158         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1159                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1160         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1161                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1162
1163         /* ADC Boost Volume Control */
1164         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1165                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1166                 3, 0, adc_bst_tlv),
1167 };
1168
1169 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1170                 int target, const int div[], int size)
1171 {
1172         int i;
1173
1174         if (rt5682->sysclk < target) {
1175                 dev_err(rt5682->component->dev,
1176                         "sysclk rate %d is too low\n", rt5682->sysclk);
1177                 return 0;
1178         }
1179
1180         for (i = 0; i < size - 1; i++) {
1181                 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1182                 if (target * div[i] == rt5682->sysclk)
1183                         return i;
1184                 if (target * div[i + 1] > rt5682->sysclk) {
1185                         dev_dbg(rt5682->component->dev,
1186                                 "can't find div for sysclk %d\n",
1187                                 rt5682->sysclk);
1188                         return i;
1189                 }
1190         }
1191
1192         if (target * div[i] < rt5682->sysclk)
1193                 dev_err(rt5682->component->dev,
1194                         "sysclk rate %d is too high\n", rt5682->sysclk);
1195
1196         return size - 1;
1197 }
1198
1199 /**
1200  * set_dmic_clk - Set parameter of dmic.
1201  *
1202  * @w: DAPM widget.
1203  * @kcontrol: The kcontrol of this widget.
1204  * @event: Event id.
1205  *
1206  * Choose dmic clock between 1MHz and 3MHz.
1207  * It is better for clock to approximate 3MHz.
1208  */
1209 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1210                 struct snd_kcontrol *kcontrol, int event)
1211 {
1212         struct snd_soc_component *component =
1213                 snd_soc_dapm_to_component(w->dapm);
1214         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1215         int idx = -EINVAL, dmic_clk_rate = 3072000;
1216         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1217
1218         if (rt5682->pdata.dmic_clk_rate)
1219                 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1220
1221         idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1222
1223         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1224                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1225
1226         return 0;
1227 }
1228
1229 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1230                 struct snd_kcontrol *kcontrol, int event)
1231 {
1232         struct snd_soc_component *component =
1233                 snd_soc_dapm_to_component(w->dapm);
1234         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1235         int ref, val, reg, idx = -EINVAL;
1236         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1237         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1238
1239         if (rt5682->is_sdw)
1240                 return 0;
1241
1242         val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1243                 RT5682_GP4_PIN_MASK;
1244         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1245                 val == RT5682_GP4_PIN_ADCDAT2)
1246                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1247         else
1248                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1249
1250         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1251
1252         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1253                 reg = RT5682_PLL_TRACK_3;
1254         else
1255                 reg = RT5682_PLL_TRACK_2;
1256
1257         snd_soc_component_update_bits(component, reg,
1258                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1259
1260         /* select over sample rate */
1261         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1262                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1263                         break;
1264         }
1265
1266         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1267                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1268                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1269
1270         return 0;
1271 }
1272
1273 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1274                 struct snd_soc_dapm_widget *sink)
1275 {
1276         unsigned int val;
1277         struct snd_soc_component *component =
1278                 snd_soc_dapm_to_component(w->dapm);
1279
1280         val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1281         val &= RT5682_SCLK_SRC_MASK;
1282         if (val == RT5682_SCLK_SRC_PLL1)
1283                 return 1;
1284         else
1285                 return 0;
1286 }
1287
1288 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1289                 struct snd_soc_dapm_widget *sink)
1290 {
1291         unsigned int val;
1292         struct snd_soc_component *component =
1293                 snd_soc_dapm_to_component(w->dapm);
1294
1295         val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1296         val &= RT5682_SCLK_SRC_MASK;
1297         if (val == RT5682_SCLK_SRC_PLL2)
1298                 return 1;
1299         else
1300                 return 0;
1301 }
1302
1303 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1304                 struct snd_soc_dapm_widget *sink)
1305 {
1306         unsigned int reg, shift, val;
1307         struct snd_soc_component *component =
1308                 snd_soc_dapm_to_component(w->dapm);
1309
1310         switch (w->shift) {
1311         case RT5682_ADC_STO1_ASRC_SFT:
1312                 reg = RT5682_PLL_TRACK_3;
1313                 shift = RT5682_FILTER_CLK_SEL_SFT;
1314                 break;
1315         case RT5682_DAC_STO1_ASRC_SFT:
1316                 reg = RT5682_PLL_TRACK_2;
1317                 shift = RT5682_FILTER_CLK_SEL_SFT;
1318                 break;
1319         default:
1320                 return 0;
1321         }
1322
1323         val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1324         switch (val) {
1325         case RT5682_CLK_SEL_I2S1_ASRC:
1326         case RT5682_CLK_SEL_I2S2_ASRC:
1327                 return 1;
1328         default:
1329                 return 0;
1330         }
1331 }
1332
1333 /* Digital Mixer */
1334 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1335         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1336                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1337         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1338                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1339 };
1340
1341 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1342         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1343                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1344         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1345                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1346 };
1347
1348 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1349         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1350                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1351         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1352                         RT5682_M_DAC1_L_SFT, 1, 1),
1353 };
1354
1355 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1356         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1357                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1358         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1359                         RT5682_M_DAC1_R_SFT, 1, 1),
1360 };
1361
1362 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1363         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1364                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1365         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1366                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1367 };
1368
1369 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1370         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1371                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1372         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1373                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1374 };
1375
1376 /* Analog Input Mixer */
1377 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1378         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1379                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1380 };
1381
1382 /* STO1 ADC1 Source */
1383 /* MX-26 [13] [5] */
1384 static const char * const rt5682_sto1_adc1_src[] = {
1385         "DAC MIX", "ADC"
1386 };
1387
1388 static SOC_ENUM_SINGLE_DECL(
1389         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1390         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1391
1392 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1393         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1394
1395 static SOC_ENUM_SINGLE_DECL(
1396         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1397         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1398
1399 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1400         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1401
1402 /* STO1 ADC Source */
1403 /* MX-26 [11:10] [3:2] */
1404 static const char * const rt5682_sto1_adc_src[] = {
1405         "ADC1 L", "ADC1 R"
1406 };
1407
1408 static SOC_ENUM_SINGLE_DECL(
1409         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1410         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1411
1412 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1413         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1414
1415 static SOC_ENUM_SINGLE_DECL(
1416         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1417         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1418
1419 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1420         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1421
1422 /* STO1 ADC2 Source */
1423 /* MX-26 [12] [4] */
1424 static const char * const rt5682_sto1_adc2_src[] = {
1425         "DAC MIX", "DMIC"
1426 };
1427
1428 static SOC_ENUM_SINGLE_DECL(
1429         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1430         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1431
1432 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1433         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1434
1435 static SOC_ENUM_SINGLE_DECL(
1436         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1437         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1438
1439 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1440         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1441
1442 /* MX-79 [6:4] I2S1 ADC data location */
1443 static const unsigned int rt5682_if1_adc_slot_values[] = {
1444         0,
1445         2,
1446         4,
1447         6,
1448 };
1449
1450 static const char * const rt5682_if1_adc_slot_src[] = {
1451         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1452 };
1453
1454 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1455         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1456         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1457
1458 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1459         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1460
1461 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1462 /* MX-2B [4], MX-2B [0]*/
1463 static const char * const rt5682_alg_dac1_src[] = {
1464         "Stereo1 DAC Mixer", "DAC1"
1465 };
1466
1467 static SOC_ENUM_SINGLE_DECL(
1468         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1469         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1470
1471 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1472         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1473
1474 static SOC_ENUM_SINGLE_DECL(
1475         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1476         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1477
1478 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1479         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1480
1481 /* Out Switch */
1482 static const struct snd_kcontrol_new hpol_switch =
1483         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1484                 RT5682_L_MUTE_SFT, 1, 1);
1485 static const struct snd_kcontrol_new hpor_switch =
1486         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1487                 RT5682_R_MUTE_SFT, 1, 1);
1488
1489 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1490                 struct snd_kcontrol *kcontrol, int event)
1491 {
1492         struct snd_soc_component *component =
1493                 snd_soc_dapm_to_component(w->dapm);
1494
1495         switch (event) {
1496         case SND_SOC_DAPM_PRE_PMU:
1497                 snd_soc_component_write(component,
1498                         RT5682_HP_LOGIC_CTRL_2, 0x0012);
1499                 snd_soc_component_write(component,
1500                         RT5682_HP_CTRL_2, 0x6000);
1501                 snd_soc_component_update_bits(component,
1502                         RT5682_DEPOP_1, 0x60, 0x60);
1503                 snd_soc_component_update_bits(component,
1504                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1505                 break;
1506
1507         case SND_SOC_DAPM_POST_PMD:
1508                 snd_soc_component_update_bits(component,
1509                         RT5682_DEPOP_1, 0x60, 0x0);
1510                 snd_soc_component_write(component,
1511                         RT5682_HP_CTRL_2, 0x0000);
1512                 snd_soc_component_update_bits(component,
1513                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1514                 break;
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1521                 struct snd_kcontrol *kcontrol, int event)
1522 {
1523         struct snd_soc_component *component =
1524                 snd_soc_dapm_to_component(w->dapm);
1525         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1526         unsigned int delay = 50;
1527
1528         if (rt5682->pdata.dmic_delay)
1529                 delay = rt5682->pdata.dmic_delay;
1530
1531         switch (event) {
1532         case SND_SOC_DAPM_POST_PMU:
1533                 /*Add delay to avoid pop noise*/
1534                 msleep(delay);
1535                 break;
1536         }
1537
1538         return 0;
1539 }
1540
1541 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1542                 struct snd_kcontrol *kcontrol, int event)
1543 {
1544         struct snd_soc_component *component =
1545                 snd_soc_dapm_to_component(w->dapm);
1546
1547         switch (event) {
1548         case SND_SOC_DAPM_PRE_PMU:
1549                 switch (w->shift) {
1550                 case RT5682_PWR_VREF1_BIT:
1551                         snd_soc_component_update_bits(component,
1552                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1553                         break;
1554
1555                 case RT5682_PWR_VREF2_BIT:
1556                         snd_soc_component_update_bits(component,
1557                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1558                         break;
1559                 }
1560                 break;
1561
1562         case SND_SOC_DAPM_POST_PMU:
1563                 usleep_range(15000, 20000);
1564                 switch (w->shift) {
1565                 case RT5682_PWR_VREF1_BIT:
1566                         snd_soc_component_update_bits(component,
1567                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1568                                 RT5682_PWR_FV1);
1569                         break;
1570
1571                 case RT5682_PWR_VREF2_BIT:
1572                         snd_soc_component_update_bits(component,
1573                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1574                                 RT5682_PWR_FV2);
1575                         break;
1576                 }
1577                 break;
1578         }
1579
1580         return 0;
1581 }
1582
1583 static const unsigned int rt5682_adcdat_pin_values[] = {
1584         1,
1585         3,
1586 };
1587
1588 static const char * const rt5682_adcdat_pin_select[] = {
1589         "ADCDAT1",
1590         "ADCDAT2",
1591 };
1592
1593 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1594         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1595         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1596
1597 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1598         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1599
1600 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1601         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1602                 0, NULL, 0),
1603         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1604                 0, NULL, 0),
1605         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1606                 0, NULL, 0),
1607         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1608                 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1609         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1610                 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1611         SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1612                 NULL, 0),
1613         SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1614
1615         /* ASRC */
1616         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1617                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1618         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1619                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1620         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1621                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1622         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1623                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1624         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1625                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1626
1627         /* Input Side */
1628         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1629                 0, NULL, 0),
1630         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1631                 0, NULL, 0),
1632
1633         /* Input Lines */
1634         SND_SOC_DAPM_INPUT("DMIC L1"),
1635         SND_SOC_DAPM_INPUT("DMIC R1"),
1636
1637         SND_SOC_DAPM_INPUT("IN1P"),
1638
1639         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1640                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1641         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1642                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1643
1644         /* Boost */
1645         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1646                 0, 0, NULL, 0),
1647
1648         /* REC Mixer */
1649         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1650                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1651         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1652                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1653
1654         /* ADCs */
1655         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1656         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1657
1658         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1659                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1660         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1661                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1662         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1663                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1664
1665         /* ADC Mux */
1666         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1667                 &rt5682_sto1_adc1l_mux),
1668         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1669                 &rt5682_sto1_adc1r_mux),
1670         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1671                 &rt5682_sto1_adc2l_mux),
1672         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1673                 &rt5682_sto1_adc2r_mux),
1674         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1675                 &rt5682_sto1_adcl_mux),
1676         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1677                 &rt5682_sto1_adcr_mux),
1678         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1679                 &rt5682_if1_adc_slot_mux),
1680
1681         /* ADC Mixer */
1682         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1683                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1684                 SND_SOC_DAPM_PRE_PMU),
1685         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1686                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1687                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1688         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1689                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1690                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1691         SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1692                 14, 1, NULL, 0),
1693
1694         /* ADC PGA */
1695         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1696
1697         /* Digital Interface */
1698         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1699                 0, NULL, 0),
1700         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1701                 0, NULL, 0),
1702         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1703         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1704         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1705         SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1706         SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1707
1708         /* Digital Interface Select */
1709         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1710                 &rt5682_if1_01_adc_swap_mux),
1711         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1712                 &rt5682_if1_23_adc_swap_mux),
1713         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1714                 &rt5682_if1_45_adc_swap_mux),
1715         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1716                 &rt5682_if1_67_adc_swap_mux),
1717         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1718                 &rt5682_if2_adc_swap_mux),
1719
1720         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1721                 &rt5682_adcdat_pin_ctrl),
1722
1723         SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1724                 &rt5682_dac_l_mux),
1725         SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1726                 &rt5682_dac_r_mux),
1727
1728         /* Audio Interface */
1729         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1730                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1731         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1732                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1733         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1734         SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1735         SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1736
1737         /* Output Side */
1738         /* DAC mixer before sound effect  */
1739         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1740                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1741         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1742                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1743
1744         /* DAC channel Mux */
1745         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1746                 &rt5682_alg_dac_l1_mux),
1747         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1748                 &rt5682_alg_dac_r1_mux),
1749
1750         /* DAC Mixer */
1751         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1752                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1753                 SND_SOC_DAPM_PRE_PMU),
1754         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1755                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1756         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1757                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1758
1759         /* DACs */
1760         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1761                 RT5682_PWR_DAC_L1_BIT, 0),
1762         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1763                 RT5682_PWR_DAC_R1_BIT, 0),
1764         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1765                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1766
1767         /* HPO */
1768         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1769                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1770
1771         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1772                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1773         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1774                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1775         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1776                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1777         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1778                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1779
1780         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1781                 &hpol_switch),
1782         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1783                 &hpor_switch),
1784
1785         /* CLK DET */
1786         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1787                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1788         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1789                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1790         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1791                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1792         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1793                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1794
1795         /* Output Lines */
1796         SND_SOC_DAPM_OUTPUT("HPOL"),
1797         SND_SOC_DAPM_OUTPUT("HPOR"),
1798 };
1799
1800 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1801         /*PLL*/
1802         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1803         {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1804         {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1805         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1806         {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1807         {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1808
1809         /*ASRC*/
1810         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1811         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1812         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1813         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1814         {"ADC STO1 ASRC", NULL, "CLKDET"},
1815         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1816         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1817         {"DAC STO1 ASRC", NULL, "CLKDET"},
1818
1819         /*Vref*/
1820         {"MICBIAS1", NULL, "Vref1"},
1821         {"MICBIAS2", NULL, "Vref1"},
1822
1823         {"CLKDET SYS", NULL, "CLKDET"},
1824
1825         {"IN1P", NULL, "LDO2"},
1826
1827         {"BST1 CBJ", NULL, "IN1P"},
1828
1829         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1830         {"RECMIX1L", NULL, "RECMIX1L Power"},
1831
1832         {"ADC1 L", NULL, "RECMIX1L"},
1833         {"ADC1 L", NULL, "ADC1 L Power"},
1834         {"ADC1 L", NULL, "ADC1 clock"},
1835
1836         {"DMIC L1", NULL, "DMIC CLK"},
1837         {"DMIC L1", NULL, "DMIC1 Power"},
1838         {"DMIC R1", NULL, "DMIC CLK"},
1839         {"DMIC R1", NULL, "DMIC1 Power"},
1840         {"DMIC CLK", NULL, "DMIC ASRC"},
1841
1842         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1843         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1844         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1845         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1846
1847         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1848         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1849         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1850         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1851
1852         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1853         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1854         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1855         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1856
1857         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1858         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1859         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1860
1861         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1862         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1863         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1864
1865         {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1866
1867         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1868         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1869
1870         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1871         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1872         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1873         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1874         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1875         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1876         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1877         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1878         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1879         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1880         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1881         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1882         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1883         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1884         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1885         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1886
1887         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1888         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1889         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1890         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1891         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1892         {"AIF1TX", NULL, "I2S1"},
1893         {"AIF1TX", NULL, "ADCDAT Mux"},
1894         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1895         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1896         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1897         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1898         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1899         {"AIF2TX", NULL, "ADCDAT Mux"},
1900
1901         {"SDWTX", NULL, "PLL2B"},
1902         {"SDWTX", NULL, "PLL2F"},
1903         {"SDWTX", NULL, "ADCDAT Mux"},
1904
1905         {"IF1 DAC1 L", NULL, "AIF1RX"},
1906         {"IF1 DAC1 L", NULL, "I2S1"},
1907         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1908         {"IF1 DAC1 R", NULL, "AIF1RX"},
1909         {"IF1 DAC1 R", NULL, "I2S1"},
1910         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1911
1912         {"SOUND DAC L", NULL, "SDWRX"},
1913         {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1914         {"SOUND DAC L", NULL, "PLL2B"},
1915         {"SOUND DAC L", NULL, "PLL2F"},
1916         {"SOUND DAC R", NULL, "SDWRX"},
1917         {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1918         {"SOUND DAC R", NULL, "PLL2B"},
1919         {"SOUND DAC R", NULL, "PLL2F"},
1920
1921         {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1922         {"DAC L Mux", "SOUND", "SOUND DAC L"},
1923         {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1924         {"DAC R Mux", "SOUND", "SOUND DAC R"},
1925
1926         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1927         {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1928         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1929         {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1930
1931         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1932         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1933
1934         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1935         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1936
1937         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1938         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1939         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1940         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1941
1942         {"DAC L1", NULL, "DAC L1 Source"},
1943         {"DAC R1", NULL, "DAC R1 Source"},
1944
1945         {"DAC L1", NULL, "DAC 1 Clock"},
1946         {"DAC R1", NULL, "DAC 1 Clock"},
1947
1948         {"HP Amp", NULL, "DAC L1"},
1949         {"HP Amp", NULL, "DAC R1"},
1950         {"HP Amp", NULL, "HP Amp L"},
1951         {"HP Amp", NULL, "HP Amp R"},
1952         {"HP Amp", NULL, "Capless"},
1953         {"HP Amp", NULL, "Charge Pump"},
1954         {"HP Amp", NULL, "CLKDET SYS"},
1955         {"HP Amp", NULL, "Vref1"},
1956         {"HPOL Playback", "Switch", "HP Amp"},
1957         {"HPOR Playback", "Switch", "HP Amp"},
1958         {"HPOL", NULL, "HPOL Playback"},
1959         {"HPOR", NULL, "HPOR Playback"},
1960 };
1961
1962 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1963                 unsigned int rx_mask, int slots, int slot_width)
1964 {
1965         struct snd_soc_component *component = dai->component;
1966         unsigned int cl, val = 0;
1967
1968         if (tx_mask || rx_mask)
1969                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1970                         RT5682_TDM_EN, RT5682_TDM_EN);
1971         else
1972                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1973                         RT5682_TDM_EN, 0);
1974
1975         switch (slots) {
1976         case 4:
1977                 val |= RT5682_TDM_TX_CH_4;
1978                 val |= RT5682_TDM_RX_CH_4;
1979                 break;
1980         case 6:
1981                 val |= RT5682_TDM_TX_CH_6;
1982                 val |= RT5682_TDM_RX_CH_6;
1983                 break;
1984         case 8:
1985                 val |= RT5682_TDM_TX_CH_8;
1986                 val |= RT5682_TDM_RX_CH_8;
1987                 break;
1988         case 2:
1989                 break;
1990         default:
1991                 return -EINVAL;
1992         }
1993
1994         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1995                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1996
1997         switch (slot_width) {
1998         case 8:
1999                 if (tx_mask || rx_mask)
2000                         return -EINVAL;
2001                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2002                 break;
2003         case 16:
2004                 val = RT5682_TDM_CL_16;
2005                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2006                 break;
2007         case 20:
2008                 val = RT5682_TDM_CL_20;
2009                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2010                 break;
2011         case 24:
2012                 val = RT5682_TDM_CL_24;
2013                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2014                 break;
2015         case 32:
2016                 val = RT5682_TDM_CL_32;
2017                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2018                 break;
2019         default:
2020                 return -EINVAL;
2021         }
2022
2023         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2024                 RT5682_TDM_CL_MASK, val);
2025         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2026                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2027
2028         return 0;
2029 }
2030
2031 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2032                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2033 {
2034         struct snd_soc_component *component = dai->component;
2035         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2036         unsigned int len_1 = 0, len_2 = 0;
2037         int pre_div, frame_size;
2038
2039         rt5682->lrck[dai->id] = params_rate(params);
2040         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2041
2042         frame_size = snd_soc_params_to_frame_size(params);
2043         if (frame_size < 0) {
2044                 dev_err(component->dev, "Unsupported frame size: %d\n",
2045                         frame_size);
2046                 return -EINVAL;
2047         }
2048
2049         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2050                 rt5682->lrck[dai->id], pre_div, dai->id);
2051
2052         switch (params_width(params)) {
2053         case 16:
2054                 break;
2055         case 20:
2056                 len_1 |= RT5682_I2S1_DL_20;
2057                 len_2 |= RT5682_I2S2_DL_20;
2058                 break;
2059         case 24:
2060                 len_1 |= RT5682_I2S1_DL_24;
2061                 len_2 |= RT5682_I2S2_DL_24;
2062                 break;
2063         case 32:
2064                 len_1 |= RT5682_I2S1_DL_32;
2065                 len_2 |= RT5682_I2S2_DL_24;
2066                 break;
2067         case 8:
2068                 len_1 |= RT5682_I2S2_DL_8;
2069                 len_2 |= RT5682_I2S2_DL_8;
2070                 break;
2071         default:
2072                 return -EINVAL;
2073         }
2074
2075         switch (dai->id) {
2076         case RT5682_AIF1:
2077                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2078                         RT5682_I2S1_DL_MASK, len_1);
2079                 if (rt5682->master[RT5682_AIF1]) {
2080                         snd_soc_component_update_bits(component,
2081                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2082                                 RT5682_I2S_CLK_SRC_MASK,
2083                                 pre_div << RT5682_I2S_M_DIV_SFT |
2084                                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2085                 }
2086                 if (params_channels(params) == 1) /* mono mode */
2087                         snd_soc_component_update_bits(component,
2088                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2089                                 RT5682_I2S1_MONO_EN);
2090                 else
2091                         snd_soc_component_update_bits(component,
2092                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2093                                 RT5682_I2S1_MONO_DIS);
2094                 break;
2095         case RT5682_AIF2:
2096                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2097                         RT5682_I2S2_DL_MASK, len_2);
2098                 if (rt5682->master[RT5682_AIF2]) {
2099                         snd_soc_component_update_bits(component,
2100                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2101                                 pre_div << RT5682_I2S2_M_PD_SFT);
2102                 }
2103                 if (params_channels(params) == 1) /* mono mode */
2104                         snd_soc_component_update_bits(component,
2105                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2106                                 RT5682_I2S2_MONO_EN);
2107                 else
2108                         snd_soc_component_update_bits(component,
2109                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2110                                 RT5682_I2S2_MONO_DIS);
2111                 break;
2112         default:
2113                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2114                 return -EINVAL;
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2121 {
2122         struct snd_soc_component *component = dai->component;
2123         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2124         unsigned int reg_val = 0, tdm_ctrl = 0;
2125
2126         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2127         case SND_SOC_DAIFMT_CBM_CFM:
2128                 rt5682->master[dai->id] = 1;
2129                 break;
2130         case SND_SOC_DAIFMT_CBS_CFS:
2131                 rt5682->master[dai->id] = 0;
2132                 break;
2133         default:
2134                 return -EINVAL;
2135         }
2136
2137         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2138         case SND_SOC_DAIFMT_NB_NF:
2139                 break;
2140         case SND_SOC_DAIFMT_IB_NF:
2141                 reg_val |= RT5682_I2S_BP_INV;
2142                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2143                 break;
2144         case SND_SOC_DAIFMT_NB_IF:
2145                 if (dai->id == RT5682_AIF1)
2146                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2147                 else
2148                         return -EINVAL;
2149                 break;
2150         case SND_SOC_DAIFMT_IB_IF:
2151                 if (dai->id == RT5682_AIF1)
2152                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2153                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2154                 else
2155                         return -EINVAL;
2156                 break;
2157         default:
2158                 return -EINVAL;
2159         }
2160
2161         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2162         case SND_SOC_DAIFMT_I2S:
2163                 break;
2164         case SND_SOC_DAIFMT_LEFT_J:
2165                 reg_val |= RT5682_I2S_DF_LEFT;
2166                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2167                 break;
2168         case SND_SOC_DAIFMT_DSP_A:
2169                 reg_val |= RT5682_I2S_DF_PCM_A;
2170                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2171                 break;
2172         case SND_SOC_DAIFMT_DSP_B:
2173                 reg_val |= RT5682_I2S_DF_PCM_B;
2174                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2175                 break;
2176         default:
2177                 return -EINVAL;
2178         }
2179
2180         switch (dai->id) {
2181         case RT5682_AIF1:
2182                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2183                         RT5682_I2S_DF_MASK, reg_val);
2184                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2185                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2186                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2187                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2188                         tdm_ctrl | rt5682->master[dai->id]);
2189                 break;
2190         case RT5682_AIF2:
2191                 if (rt5682->master[dai->id] == 0)
2192                         reg_val |= RT5682_I2S2_MS_S;
2193                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2194                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2195                         RT5682_I2S_DF_MASK, reg_val);
2196                 break;
2197         default:
2198                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2199                 return -EINVAL;
2200         }
2201         return 0;
2202 }
2203
2204 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2205                 int clk_id, int source, unsigned int freq, int dir)
2206 {
2207         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2208         unsigned int reg_val = 0, src = 0;
2209
2210         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2211                 return 0;
2212
2213         switch (clk_id) {
2214         case RT5682_SCLK_S_MCLK:
2215                 reg_val |= RT5682_SCLK_SRC_MCLK;
2216                 src = RT5682_CLK_SRC_MCLK;
2217                 break;
2218         case RT5682_SCLK_S_PLL1:
2219                 reg_val |= RT5682_SCLK_SRC_PLL1;
2220                 src = RT5682_CLK_SRC_PLL1;
2221                 break;
2222         case RT5682_SCLK_S_PLL2:
2223                 reg_val |= RT5682_SCLK_SRC_PLL2;
2224                 src = RT5682_CLK_SRC_PLL2;
2225                 break;
2226         case RT5682_SCLK_S_RCCLK:
2227                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2228                 src = RT5682_CLK_SRC_RCCLK;
2229                 break;
2230         default:
2231                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2232                 return -EINVAL;
2233         }
2234         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2235                 RT5682_SCLK_SRC_MASK, reg_val);
2236
2237         if (rt5682->master[RT5682_AIF2]) {
2238                 snd_soc_component_update_bits(component,
2239                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2240                         src << RT5682_I2S2_SRC_SFT);
2241         }
2242
2243         rt5682->sysclk = freq;
2244         rt5682->sysclk_src = clk_id;
2245
2246         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2247                 freq, clk_id);
2248
2249         return 0;
2250 }
2251
2252 static int rt5682_set_component_pll(struct snd_soc_component *component,
2253                 int pll_id, int source, unsigned int freq_in,
2254                 unsigned int freq_out)
2255 {
2256         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2257         struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2258         unsigned int pll2_fout1;
2259         int ret;
2260
2261         if (source == rt5682->pll_src[pll_id] &&
2262             freq_in == rt5682->pll_in[pll_id] &&
2263             freq_out == rt5682->pll_out[pll_id])
2264                 return 0;
2265
2266         if (!freq_in || !freq_out) {
2267                 dev_dbg(component->dev, "PLL disabled\n");
2268
2269                 rt5682->pll_in[pll_id] = 0;
2270                 rt5682->pll_out[pll_id] = 0;
2271                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2272                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2273                 return 0;
2274         }
2275
2276         if (pll_id == RT5682_PLL2) {
2277                 switch (source) {
2278                 case RT5682_PLL2_S_MCLK:
2279                         snd_soc_component_update_bits(component,
2280                                 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2281                                 RT5682_PLL2_SRC_MCLK);
2282                         break;
2283                 default:
2284                         dev_err(component->dev, "Unknown PLL2 Source %d\n",
2285                                 source);
2286                         return -EINVAL;
2287                 }
2288
2289                 /**
2290                  * PLL2 concatenates 2 PLL units.
2291                  * We suggest the Fout of the front PLL is 3.84MHz.
2292                  */
2293                 pll2_fout1 = 3840000;
2294                 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2295                 if (ret < 0) {
2296                         dev_err(component->dev, "Unsupport input clock %d\n",
2297                                 freq_in);
2298                         return ret;
2299                 }
2300                 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2301                         freq_in, pll2_fout1,
2302                         pll2f_code.m_bp,
2303                         (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2304                         pll2f_code.n_code, pll2f_code.k_code);
2305
2306                 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2307                 if (ret < 0) {
2308                         dev_err(component->dev, "Unsupport input clock %d\n",
2309                                 pll2_fout1);
2310                         return ret;
2311                 }
2312                 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2313                         pll2_fout1, freq_out,
2314                         pll2b_code.m_bp,
2315                         (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2316                         pll2b_code.n_code, pll2b_code.k_code);
2317
2318                 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2319                         pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2320                         pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2321                         pll2b_code.m_code);
2322                 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2323                         pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2324                         pll2b_code.n_code);
2325                 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2326                         pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2327                 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2328                         RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2329                         (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2330                         (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2331                         0xf);
2332         } else {
2333                 switch (source) {
2334                 case RT5682_PLL1_S_MCLK:
2335                         snd_soc_component_update_bits(component,
2336                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2337                                 RT5682_PLL1_SRC_MCLK);
2338                         break;
2339                 case RT5682_PLL1_S_BCLK1:
2340                         snd_soc_component_update_bits(component,
2341                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2342                                 RT5682_PLL1_SRC_BCLK1);
2343                         break;
2344                 default:
2345                         dev_err(component->dev, "Unknown PLL1 Source %d\n",
2346                                 source);
2347                         return -EINVAL;
2348                 }
2349
2350                 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2351                 if (ret < 0) {
2352                         dev_err(component->dev, "Unsupport input clock %d\n",
2353                                 freq_in);
2354                         return ret;
2355                 }
2356
2357                 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2358                         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2359                         pll_code.n_code, pll_code.k_code);
2360
2361                 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2362                         pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2363                 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2364                     (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2365                     pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2366         }
2367
2368         rt5682->pll_in[pll_id] = freq_in;
2369         rt5682->pll_out[pll_id] = freq_out;
2370         rt5682->pll_src[pll_id] = source;
2371
2372         return 0;
2373 }
2374
2375 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2376 {
2377         struct snd_soc_component *component = dai->component;
2378         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2379
2380         rt5682->bclk[dai->id] = ratio;
2381
2382         switch (ratio) {
2383         case 256:
2384                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2385                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2386                 break;
2387         case 128:
2388                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2389                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2390                 break;
2391         case 64:
2392                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2393                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2394                 break;
2395         case 32:
2396                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2397                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2398                 break;
2399         default:
2400                 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2401                 return -EINVAL;
2402         }
2403
2404         return 0;
2405 }
2406
2407 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2408 {
2409         struct snd_soc_component *component = dai->component;
2410         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2411
2412         rt5682->bclk[dai->id] = ratio;
2413
2414         switch (ratio) {
2415         case 64:
2416                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2417                         RT5682_I2S2_BCLK_MS2_MASK,
2418                         RT5682_I2S2_BCLK_MS2_64);
2419                 break;
2420         case 32:
2421                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2422                         RT5682_I2S2_BCLK_MS2_MASK,
2423                         RT5682_I2S2_BCLK_MS2_32);
2424                 break;
2425         default:
2426                 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2427                 return -EINVAL;
2428         }
2429
2430         return 0;
2431 }
2432
2433 static int rt5682_set_bias_level(struct snd_soc_component *component,
2434                 enum snd_soc_bias_level level)
2435 {
2436         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2437
2438         switch (level) {
2439         case SND_SOC_BIAS_PREPARE:
2440                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2441                         RT5682_PWR_BG, RT5682_PWR_BG);
2442                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2443                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2444                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2445                 break;
2446
2447         case SND_SOC_BIAS_STANDBY:
2448                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2449                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2450                 break;
2451         case SND_SOC_BIAS_OFF:
2452                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2453                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2454                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2455                         RT5682_PWR_BG, 0);
2456                 break;
2457         case SND_SOC_BIAS_ON:
2458                 break;
2459         }
2460
2461         return 0;
2462 }
2463
2464 #ifdef CONFIG_COMMON_CLK
2465 #define CLK_PLL2_FIN 48000000
2466 #define CLK_PLL2_FOUT 24576000
2467 #define CLK_48 48000
2468
2469 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2470 {
2471         if (!rt5682->master[RT5682_AIF1]) {
2472                 dev_err(rt5682->component->dev, "sysclk/dai not set correctly\n");
2473                 return false;
2474         }
2475         return true;
2476 }
2477
2478 static int rt5682_wclk_prepare(struct clk_hw *hw)
2479 {
2480         struct rt5682_priv *rt5682 =
2481                 container_of(hw, struct rt5682_priv,
2482                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2483         struct snd_soc_component *component = rt5682->component;
2484         struct snd_soc_dapm_context *dapm =
2485                         snd_soc_component_get_dapm(component);
2486
2487         if (!rt5682_clk_check(rt5682))
2488                 return -EINVAL;
2489
2490         snd_soc_dapm_mutex_lock(dapm);
2491
2492         snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2493         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2494                                 RT5682_PWR_MB, RT5682_PWR_MB);
2495         snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2496         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2497         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2498         snd_soc_dapm_sync_unlocked(dapm);
2499
2500         snd_soc_dapm_mutex_unlock(dapm);
2501
2502         return 0;
2503 }
2504
2505 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2506 {
2507         struct rt5682_priv *rt5682 =
2508                 container_of(hw, struct rt5682_priv,
2509                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2510         struct snd_soc_component *component = rt5682->component;
2511         struct snd_soc_dapm_context *dapm =
2512                         snd_soc_component_get_dapm(component);
2513
2514         if (!rt5682_clk_check(rt5682))
2515                 return;
2516
2517         snd_soc_dapm_mutex_lock(dapm);
2518
2519         snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2520         if (!rt5682->jack_type)
2521                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2522                                 RT5682_PWR_MB, 0);
2523         snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2524         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2525         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2526         snd_soc_dapm_sync_unlocked(dapm);
2527
2528         snd_soc_dapm_mutex_unlock(dapm);
2529 }
2530
2531 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2532                                              unsigned long parent_rate)
2533 {
2534         struct rt5682_priv *rt5682 =
2535                 container_of(hw, struct rt5682_priv,
2536                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2537
2538         if (!rt5682_clk_check(rt5682))
2539                 return 0;
2540         /*
2541          * Only accept to set wclk rate to 48kHz temporarily.
2542          */
2543         return CLK_48;
2544 }
2545
2546 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2547                                    unsigned long *parent_rate)
2548 {
2549         struct rt5682_priv *rt5682 =
2550                 container_of(hw, struct rt5682_priv,
2551                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2552
2553         if (!rt5682_clk_check(rt5682))
2554                 return -EINVAL;
2555         /*
2556          * Only accept to set wclk rate to 48kHz temporarily.
2557          */
2558         return CLK_48;
2559 }
2560
2561 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2562                                 unsigned long parent_rate)
2563 {
2564         struct rt5682_priv *rt5682 =
2565                 container_of(hw, struct rt5682_priv,
2566                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2567         struct snd_soc_component *component = rt5682->component;
2568         struct clk *parent_clk;
2569         const char * const clk_name = __clk_get_name(hw->clk);
2570         int pre_div;
2571
2572         if (!rt5682_clk_check(rt5682))
2573                 return -EINVAL;
2574
2575         /*
2576          * Whether the wclk's parent clk (mclk) exists or not, please ensure
2577          * it is fixed or set to 48MHz before setting wclk rate. It's a
2578          * temporary limitation. Only accept 48MHz clk as the clk provider.
2579          *
2580          * It will set the codec anyway by assuming mclk is 48MHz.
2581          */
2582         parent_clk = clk_get_parent(hw->clk);
2583         if (!parent_clk)
2584                 dev_warn(component->dev,
2585                         "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2586                         CLK_PLL2_FIN);
2587
2588         if (parent_rate != CLK_PLL2_FIN)
2589                 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2590                         clk_name, CLK_PLL2_FIN);
2591
2592         /*
2593          * It's a temporary limitation. Only accept to set wclk rate to 48kHz.
2594          * It will force wclk to 48kHz even it's not.
2595          */
2596         if (rate != CLK_48) {
2597                 dev_warn(component->dev, "clk %s only support %d Hz output\n",
2598                         clk_name, CLK_48);
2599                 rate = CLK_48;
2600         }
2601
2602         /*
2603          * To achieve the rate conversion from 48MHz to 48kHz, PLL2 is needed.
2604          */
2605         rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2606                 CLK_PLL2_FIN, CLK_PLL2_FOUT);
2607
2608         rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2609                 CLK_PLL2_FOUT, SND_SOC_CLOCK_IN);
2610
2611         pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2612
2613         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2614                 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2615                 pre_div << RT5682_I2S_M_DIV_SFT |
2616                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2617
2618         return 0;
2619 }
2620
2621 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2622                                              unsigned long parent_rate)
2623 {
2624         struct rt5682_priv *rt5682 =
2625                 container_of(hw, struct rt5682_priv,
2626                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2627         struct snd_soc_component *component = rt5682->component;
2628         unsigned int bclks_per_wclk;
2629
2630         snd_soc_component_read(component, RT5682_TDM_TCON_CTRL,
2631                 &bclks_per_wclk);
2632
2633         switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2634         case RT5682_TDM_BCLK_MS1_256:
2635                 return parent_rate * 256;
2636         case RT5682_TDM_BCLK_MS1_128:
2637                 return parent_rate * 128;
2638         case RT5682_TDM_BCLK_MS1_64:
2639                 return parent_rate * 64;
2640         case RT5682_TDM_BCLK_MS1_32:
2641                 return parent_rate * 32;
2642         default:
2643                 return 0;
2644         }
2645 }
2646
2647 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2648                                             unsigned long parent_rate)
2649 {
2650         unsigned long factor;
2651
2652         factor = rate / parent_rate;
2653         if (factor < 64)
2654                 return 32;
2655         else if (factor < 128)
2656                 return 64;
2657         else if (factor < 256)
2658                 return 128;
2659         else
2660                 return 256;
2661 }
2662
2663 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2664                                    unsigned long *parent_rate)
2665 {
2666         struct rt5682_priv *rt5682 =
2667                 container_of(hw, struct rt5682_priv,
2668                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2669         unsigned long factor;
2670
2671         if (!*parent_rate || !rt5682_clk_check(rt5682))
2672                 return -EINVAL;
2673
2674         /*
2675          * BCLK rates are set as a multiplier of WCLK in HW.
2676          * We don't allow changing the parent WCLK. We just do
2677          * some rounding down based on the parent WCLK rate
2678          * and find the appropriate multiplier of BCLK to
2679          * get the rounded down BCLK value.
2680          */
2681         factor = rt5682_bclk_get_factor(rate, *parent_rate);
2682
2683         return *parent_rate * factor;
2684 }
2685
2686 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2687                                 unsigned long parent_rate)
2688 {
2689         struct rt5682_priv *rt5682 =
2690                 container_of(hw, struct rt5682_priv,
2691                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2692         struct snd_soc_component *component = rt5682->component;
2693         struct snd_soc_dai *dai = NULL;
2694         unsigned long factor;
2695
2696         if (!rt5682_clk_check(rt5682))
2697                 return -EINVAL;
2698
2699         factor = rt5682_bclk_get_factor(rate, parent_rate);
2700
2701         for_each_component_dais(component, dai)
2702                 if (dai->id == RT5682_AIF1)
2703                         break;
2704         if (!dai) {
2705                 dev_err(component->dev, "dai %d not found in component\n",
2706                         RT5682_AIF1);
2707                 return -ENODEV;
2708         }
2709
2710         return rt5682_set_bclk1_ratio(dai, factor);
2711 }
2712
2713 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2714         [RT5682_DAI_WCLK_IDX] = {
2715                 .prepare = rt5682_wclk_prepare,
2716                 .unprepare = rt5682_wclk_unprepare,
2717                 .recalc_rate = rt5682_wclk_recalc_rate,
2718                 .round_rate = rt5682_wclk_round_rate,
2719                 .set_rate = rt5682_wclk_set_rate,
2720         },
2721         [RT5682_DAI_BCLK_IDX] = {
2722                 .recalc_rate = rt5682_bclk_recalc_rate,
2723                 .round_rate = rt5682_bclk_round_rate,
2724                 .set_rate = rt5682_bclk_set_rate,
2725         },
2726 };
2727
2728 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2729 {
2730         struct device *dev = component->dev;
2731         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2732         struct rt5682_platform_data *pdata = &rt5682->pdata;
2733         struct clk_init_data init;
2734         struct clk *dai_clk;
2735         struct clk_lookup *dai_clk_lookup;
2736         struct clk_hw *dai_clk_hw;
2737         const char *parent_name;
2738         int i, ret;
2739
2740         for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2741                 dai_clk_hw = &rt5682->dai_clks_hw[i];
2742
2743                 switch (i) {
2744                 case RT5682_DAI_WCLK_IDX:
2745                         /* Make MCLK the parent of WCLK */
2746                         if (rt5682->mclk) {
2747                                 parent_name = __clk_get_name(rt5682->mclk);
2748                                 init.parent_names = &parent_name;
2749                                 init.num_parents = 1;
2750                         } else {
2751                                 init.parent_names = NULL;
2752                                 init.num_parents = 0;
2753                         }
2754                         break;
2755                 case RT5682_DAI_BCLK_IDX:
2756                         /* Make WCLK the parent of BCLK */
2757                         parent_name = __clk_get_name(
2758                                 rt5682->dai_clks[RT5682_DAI_WCLK_IDX]);
2759                         init.parent_names = &parent_name;
2760                         init.num_parents = 1;
2761                         break;
2762                 default:
2763                         dev_err(dev, "Invalid clock index\n");
2764                         ret = -EINVAL;
2765                         goto err;
2766                 }
2767
2768                 init.name = pdata->dai_clk_names[i];
2769                 init.ops = &rt5682_dai_clk_ops[i];
2770                 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2771                 dai_clk_hw->init = &init;
2772
2773                 dai_clk = devm_clk_register(dev, dai_clk_hw);
2774                 if (IS_ERR(dai_clk)) {
2775                         dev_warn(dev, "Failed to register %s: %ld\n",
2776                                  init.name, PTR_ERR(dai_clk));
2777                         ret = PTR_ERR(dai_clk);
2778                         goto err;
2779                 }
2780                 rt5682->dai_clks[i] = dai_clk;
2781
2782                 if (dev->of_node) {
2783                         devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2784                                                     dai_clk_hw);
2785                 } else {
2786                         dai_clk_lookup = clkdev_create(dai_clk, init.name,
2787                                                        "%s", dev_name(dev));
2788                         if (!dai_clk_lookup) {
2789                                 ret = -ENOMEM;
2790                                 goto err;
2791                         } else {
2792                                 rt5682->dai_clks_lookup[i] = dai_clk_lookup;
2793                         }
2794                 }
2795         }
2796
2797         return 0;
2798
2799 err:
2800         do {
2801                 if (rt5682->dai_clks_lookup[i])
2802                         clkdev_drop(rt5682->dai_clks_lookup[i]);
2803         } while (i-- > 0);
2804
2805         return ret;
2806 }
2807 #endif /* CONFIG_COMMON_CLK */
2808
2809 static int rt5682_probe(struct snd_soc_component *component)
2810 {
2811         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2812         struct sdw_slave *slave;
2813         unsigned long time;
2814
2815 #ifdef CONFIG_COMMON_CLK
2816         int ret;
2817 #endif
2818         rt5682->component = component;
2819
2820         if (rt5682->is_sdw) {
2821                 slave = rt5682->slave;
2822                 time = wait_for_completion_timeout(
2823                         &slave->initialization_complete,
2824                         msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2825                 if (!time) {
2826                         dev_err(&slave->dev, "Initialization not complete, timed out\n");
2827                         return -ETIMEDOUT;
2828                 }
2829         } else {
2830 #ifdef CONFIG_COMMON_CLK
2831                 /* Check if MCLK provided */
2832                 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2833                 if (IS_ERR(rt5682->mclk)) {
2834                         if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2835                                 ret = PTR_ERR(rt5682->mclk);
2836                                 return ret;
2837                         }
2838                         rt5682->mclk = NULL;
2839                 }
2840
2841                 /* Register CCF DAI clock control */
2842                 ret = rt5682_register_dai_clks(component);
2843                 if (ret)
2844                         return ret;
2845
2846                 /* Initial setup for CCF */
2847                 rt5682->lrck[RT5682_AIF1] = CLK_48;
2848 #endif
2849         }
2850
2851         return 0;
2852 }
2853
2854 static void rt5682_remove(struct snd_soc_component *component)
2855 {
2856         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2857
2858 #ifdef CONFIG_COMMON_CLK
2859         int i;
2860
2861         for (i = RT5682_DAI_NUM_CLKS - 1; i >= 0; --i) {
2862                 if (rt5682->dai_clks_lookup[i])
2863                         clkdev_drop(rt5682->dai_clks_lookup[i]);
2864         }
2865 #endif
2866
2867         rt5682_reset(rt5682);
2868 }
2869
2870 #ifdef CONFIG_PM
2871 static int rt5682_suspend(struct snd_soc_component *component)
2872 {
2873         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2874
2875         regcache_cache_only(rt5682->regmap, true);
2876         regcache_mark_dirty(rt5682->regmap);
2877         return 0;
2878 }
2879
2880 static int rt5682_resume(struct snd_soc_component *component)
2881 {
2882         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2883
2884         regcache_cache_only(rt5682->regmap, false);
2885         regcache_sync(rt5682->regmap);
2886
2887         mod_delayed_work(system_power_efficient_wq,
2888                 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2889
2890         return 0;
2891 }
2892 #else
2893 #define rt5682_suspend NULL
2894 #define rt5682_resume NULL
2895 #endif
2896
2897 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2898         .hw_params = rt5682_hw_params,
2899         .set_fmt = rt5682_set_dai_fmt,
2900         .set_tdm_slot = rt5682_set_tdm_slot,
2901         .set_bclk_ratio = rt5682_set_bclk1_ratio,
2902 };
2903 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2904
2905 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2906         .hw_params = rt5682_hw_params,
2907         .set_fmt = rt5682_set_dai_fmt,
2908         .set_bclk_ratio = rt5682_set_bclk2_ratio,
2909 };
2910 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2911
2912 const struct snd_soc_component_driver rt5682_soc_component_dev = {
2913         .probe = rt5682_probe,
2914         .remove = rt5682_remove,
2915         .suspend = rt5682_suspend,
2916         .resume = rt5682_resume,
2917         .set_bias_level = rt5682_set_bias_level,
2918         .controls = rt5682_snd_controls,
2919         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2920         .dapm_widgets = rt5682_dapm_widgets,
2921         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2922         .dapm_routes = rt5682_dapm_routes,
2923         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2924         .set_sysclk = rt5682_set_component_sysclk,
2925         .set_pll = rt5682_set_component_pll,
2926         .set_jack = rt5682_set_jack_detect,
2927         .use_pmdown_time        = 1,
2928         .endianness             = 1,
2929         .non_legacy_dai_naming  = 1,
2930 };
2931 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2932
2933 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2934 {
2935
2936         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2937                 &rt5682->pdata.dmic1_data_pin);
2938         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2939                 &rt5682->pdata.dmic1_clk_pin);
2940         device_property_read_u32(dev, "realtek,jd-src",
2941                 &rt5682->pdata.jd_src);
2942         device_property_read_u32(dev, "realtek,btndet-delay",
2943                 &rt5682->pdata.btndet_delay);
2944         device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2945                 &rt5682->pdata.dmic_clk_rate);
2946         device_property_read_u32(dev, "realtek,dmic-delay-ms",
2947                 &rt5682->pdata.dmic_delay);
2948
2949         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2950                 "realtek,ldo1-en-gpios", 0);
2951
2952         if (device_property_read_string_array(dev, "clock-output-names",
2953                                               rt5682->pdata.dai_clk_names,
2954                                               RT5682_DAI_NUM_CLKS) < 0)
2955                 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2956                          rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
2957                          rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
2958
2959         return 0;
2960 }
2961 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
2962
2963 void rt5682_calibrate(struct rt5682_priv *rt5682)
2964 {
2965         int value, count;
2966
2967         mutex_lock(&rt5682->calibrate_mutex);
2968
2969         rt5682_reset(rt5682);
2970         regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
2971         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2972         usleep_range(15000, 20000);
2973         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
2974         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2975         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2976         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2977         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2978         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2979         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2980         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2981         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2982         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2983         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2984         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2985         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2986         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2987         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2988
2989         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2990
2991         for (count = 0; count < 60; count++) {
2992                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2993                 if (!(value & 0x8000))
2994                         break;
2995
2996                 usleep_range(10000, 10005);
2997         }
2998
2999         if (count >= 60)
3000                 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3001
3002         /* restore settings */
3003         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
3004         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3005         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3006         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3007         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3008         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3009         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3010
3011         mutex_unlock(&rt5682->calibrate_mutex);
3012 }
3013 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3014
3015 MODULE_DESCRIPTION("ASoC RT5682 driver");
3016 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3017 MODULE_LICENSE("GPL v2");