sound/soc/codecs/rt5514.c

   1 /*
   2  * rt5514.c  --  RT5514 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2015 Realtek Semiconductor Corp.
   5  * Author: Oder Chiou <oder_chiou@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/acpi.h>
  13 #include <linux/fs.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/regmap.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/firmware.h>
  23 #include <linux/gpio.h>
  24 #include <sound/core.h>
  25 #include <sound/pcm.h>
  26 #include <sound/pcm_params.h>
  27 #include <sound/soc.h>
  28 #include <sound/soc-dapm.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31
  32 #include "rl6231.h"
  33 #include "rt5514.h"
  34 #if defined(CONFIG_SND_SOC_RT5514_SPI)
  35 #include "rt5514-spi.h"
  36 #endif
  37
  38 static const struct reg_sequence rt5514_i2c_patch[] = {
  39         {0x1800101c, 0x00000000},
  40         {0x18001100, 0x0000031f},
  41         {0x18001104, 0x00000007},
  42         {0x18001108, 0x00000000},
  43         {0x1800110c, 0x00000000},
  44         {0x18001110, 0x00000000},
  45         {0x18001114, 0x00000001},
  46         {0x18001118, 0x00000000},
  47         {0x18002f08, 0x00000006},
  48         {0x18002f00, 0x00055149},
  49         {0x18002f00, 0x0005514b},
  50         {0x18002f00, 0x00055149},
  51         {0xfafafafa, 0x00000001},
  52         {0x18002f10, 0x00000001},
  53         {0x18002f10, 0x00000000},
  54         {0x18002f10, 0x00000001},
  55         {0xfafafafa, 0x00000001},
  56         {0x18002000, 0x000010ec},
  57         {0xfafafafa, 0x00000000},
  58 };
  59
  60 static const struct reg_sequence rt5514_patch[] = {
  61         {RT5514_DIG_IO_CTRL,            0x00000040},
  62         {RT5514_CLK_CTRL1,              0x38020041},
  63         {RT5514_SRC_CTRL,               0x44000eee},
  64         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  65         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
  66 };
  67
  68 static const struct reg_default rt5514_reg[] = {
  69         {RT5514_RESET,                  0x00000000},
  70         {RT5514_PWR_ANA1,               0x00808880},
  71         {RT5514_PWR_ANA2,               0x00220000},
  72         {RT5514_I2S_CTRL1,              0x00000330},
  73         {RT5514_I2S_CTRL2,              0x20000000},
  74         {RT5514_VAD_CTRL6,              0xc00007d2},
  75         {RT5514_EXT_VAD_CTRL,           0x80000080},
  76         {RT5514_DIG_IO_CTRL,            0x00000040},
  77         {RT5514_PAD_CTRL1,              0x00804000},
  78         {RT5514_DMIC_DATA_CTRL,         0x00000005},
  79         {RT5514_DIG_SOURCE_CTRL,        0x00000002},
  80         {RT5514_SRC_CTRL,               0x44000eee},
  81         {RT5514_DOWNFILTER2_CTRL1,      0x0000882f},
  82         {RT5514_PLL_SOURCE_CTRL,        0x00000004},
  83         {RT5514_CLK_CTRL1,              0x38020041},
  84         {RT5514_CLK_CTRL2,              0x00000000},
  85         {RT5514_PLL3_CALIB_CTRL1,       0x00400200},
  86         {RT5514_PLL3_CALIB_CTRL5,       0x40220012},
  87         {RT5514_DELAY_BUF_CTRL1,        0x7fff006a},
  88         {RT5514_DELAY_BUF_CTRL3,        0x00000000},
  89         {RT5514_DOWNFILTER0_CTRL1,      0x00020c2f},
  90         {RT5514_DOWNFILTER0_CTRL2,      0x00020c2f},
  91         {RT5514_DOWNFILTER0_CTRL3,      0x00000362},
  92         {RT5514_DOWNFILTER1_CTRL1,      0x00020c2f},
  93         {RT5514_DOWNFILTER1_CTRL2,      0x00020c2f},
  94         {RT5514_DOWNFILTER1_CTRL3,      0x00000362},
  95         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  96         {RT5514_ANA_CTRL_LDO18_16,      0x02000345},
  97         {RT5514_ANA_CTRL_ADC12,         0x0000a2a8},
  98         {RT5514_ANA_CTRL_ADC21,         0x00001180},
  99         {RT5514_ANA_CTRL_ADC22,         0x0000aaa8},
 100         {RT5514_ANA_CTRL_ADC23,         0x00151427},
 101         {RT5514_ANA_CTRL_MICBST,        0x00002000},
 102         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
 103         {RT5514_ANA_CTRL_INBUF,         0x00000143},
 104         {RT5514_ANA_CTRL_VREF,          0x00008d50},
 105         {RT5514_ANA_CTRL_PLL3,          0x0000000e},
 106         {RT5514_ANA_CTRL_PLL1_1,        0x00000000},
 107         {RT5514_ANA_CTRL_PLL1_2,        0x00030220},
 108         {RT5514_DMIC_LP_CTRL,           0x00000000},
 109         {RT5514_MISC_CTRL_DSP,          0x00000000},
 110         {RT5514_DSP_CTRL1,              0x00055149},
 111         {RT5514_DSP_CTRL3,              0x00000006},
 112         {RT5514_DSP_CTRL4,              0x00000001},
 113         {RT5514_VENDOR_ID1,             0x00000001},
 114         {RT5514_VENDOR_ID2,             0x10ec5514},
 115 };
 116
 117 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
 118 {
 119         /* Reset */
 120         regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
 121         /* LDO_I_limit */
 122         regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
 123         /* I2C bypass enable */
 124         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
 125         /* mini-core reset */
 126         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
 127         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
 128         /* I2C bypass disable */
 129         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
 130         /* PIN config */
 131         regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
 132         /* PLL3(QN)=RCOSC*(10+2) */
 133         regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
 134         /* PLL3 source=RCOSC, fsi=rt_clk */
 135         regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
 136         /* Power on RCOSC, pll3 */
 137         regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
 138         /* DSP clk source = pll3, ENABLE DSP clk */
 139         regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
 140         /* Enable DSP clk auto switch */
 141         regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
 142         /* Reduce DSP power */
 143         regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
 144 }
 145
 146 static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
 147 {
 148         switch (reg) {
 149         case RT5514_VENDOR_ID1:
 150         case RT5514_VENDOR_ID2:
 151                 return true;
 152
 153         default:
 154                 return false;
 155         }
 156 }
 157
 158 static bool rt5514_readable_register(struct device *dev, unsigned int reg)
 159 {
 160         switch (reg) {
 161         case RT5514_RESET:
 162         case RT5514_PWR_ANA1:
 163         case RT5514_PWR_ANA2:
 164         case RT5514_I2S_CTRL1:
 165         case RT5514_I2S_CTRL2:
 166         case RT5514_VAD_CTRL6:
 167         case RT5514_EXT_VAD_CTRL:
 168         case RT5514_DIG_IO_CTRL:
 169         case RT5514_PAD_CTRL1:
 170         case RT5514_DMIC_DATA_CTRL:
 171         case RT5514_DIG_SOURCE_CTRL:
 172         case RT5514_SRC_CTRL:
 173         case RT5514_DOWNFILTER2_CTRL1:
 174         case RT5514_PLL_SOURCE_CTRL:
 175         case RT5514_CLK_CTRL1:
 176         case RT5514_CLK_CTRL2:
 177         case RT5514_PLL3_CALIB_CTRL1:
 178         case RT5514_PLL3_CALIB_CTRL5:
 179         case RT5514_DELAY_BUF_CTRL1:
 180         case RT5514_DELAY_BUF_CTRL3:
 181         case RT5514_DOWNFILTER0_CTRL1:
 182         case RT5514_DOWNFILTER0_CTRL2:
 183         case RT5514_DOWNFILTER0_CTRL3:
 184         case RT5514_DOWNFILTER1_CTRL1:
 185         case RT5514_DOWNFILTER1_CTRL2:
 186         case RT5514_DOWNFILTER1_CTRL3:
 187         case RT5514_ANA_CTRL_LDO10:
 188         case RT5514_ANA_CTRL_LDO18_16:
 189         case RT5514_ANA_CTRL_ADC12:
 190         case RT5514_ANA_CTRL_ADC21:
 191         case RT5514_ANA_CTRL_ADC22:
 192         case RT5514_ANA_CTRL_ADC23:
 193         case RT5514_ANA_CTRL_MICBST:
 194         case RT5514_ANA_CTRL_ADCFED:
 195         case RT5514_ANA_CTRL_INBUF:
 196         case RT5514_ANA_CTRL_VREF:
 197         case RT5514_ANA_CTRL_PLL3:
 198         case RT5514_ANA_CTRL_PLL1_1:
 199         case RT5514_ANA_CTRL_PLL1_2:
 200         case RT5514_DMIC_LP_CTRL:
 201         case RT5514_MISC_CTRL_DSP:
 202         case RT5514_DSP_CTRL1:
 203         case RT5514_DSP_CTRL3:
 204         case RT5514_DSP_CTRL4:
 205         case RT5514_VENDOR_ID1:
 206         case RT5514_VENDOR_ID2:
 207                 return true;
 208
 209         default:
 210                 return false;
 211         }
 212 }
 213
 214 static bool rt5514_i2c_readable_register(struct device *dev,
 215         unsigned int reg)
 216 {
 217         switch (reg) {
 218         case RT5514_DSP_MAPPING | RT5514_RESET:
 219         case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
 220         case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
 221         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
 222         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
 223         case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
 224         case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
 225         case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
 226         case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
 227         case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
 228         case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
 229         case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
 230         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
 231         case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
 232         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
 233         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
 234         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
 235         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
 236         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
 237         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
 238         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
 239         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
 240         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
 241         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
 242         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
 243         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
 244         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
 245         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
 246         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
 247         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
 248         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
 249         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
 250         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
 251         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
 252         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
 253         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
 254         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
 255         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
 256         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
 257         case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
 258         case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
 259         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
 260         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
 261         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
 262         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
 263         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
 264                 return true;
 265
 266         default:
 267                 return false;
 268         }
 269 }
 270
 271 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
 272 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 273         0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
 274         3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
 275         4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
 276         5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
 277         6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
 278         7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
 279         8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
 280 );
 281
 282 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 283
 284 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
 285                 struct snd_ctl_elem_value *ucontrol)
 286 {
 287         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 288         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 289
 290         ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
 291
 292         return 0;
 293 }
 294
 295 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
 296                 struct snd_ctl_elem_value *ucontrol)
 297 {
 298         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 299         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 300         struct snd_soc_codec *codec = rt5514->codec;
 301         const struct firmware *fw = NULL;
 302
 303         if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
 304                 return 0;
 305
 306         if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 307                 rt5514->dsp_enabled = ucontrol->value.integer.value[0];
 308
 309                 if (rt5514->dsp_enabled) {
 310                         rt5514_enable_dsp_prepare(rt5514);
 311
 312                         request_firmware(&fw, RT5514_FIRMWARE1, codec->dev);
 313                         if (fw) {
 314 #if defined(CONFIG_SND_SOC_RT5514_SPI)
 315                                 rt5514_spi_burst_write(0x4ff60000, fw->data,
 316                                         ((fw->size/8)+1)*8);
 317 #else
 318                                 dev_err(codec->dev, "There is no SPI driver for"
 319                                         " loading the firmware\n");
 320 #endif
 321                                 release_firmware(fw);
 322                                 fw = NULL;
 323                         }
 324
 325                         request_firmware(&fw, RT5514_FIRMWARE2, codec->dev);
 326                         if (fw) {
 327 #if defined(CONFIG_SND_SOC_RT5514_SPI)
 328                                 rt5514_spi_burst_write(0x4ffc0000, fw->data,
 329                                         ((fw->size/8)+1)*8);
 330 #else
 331                                 dev_err(codec->dev, "There is no SPI driver for"
 332                                         " loading the firmware\n");
 333 #endif
 334                                 release_firmware(fw);
 335                                 fw = NULL;
 336                         }
 337
 338                         /* DSP run */
 339                         regmap_write(rt5514->i2c_regmap, 0x18002f00,
 340                                 0x00055148);
 341                 } else {
 342                         regmap_multi_reg_write(rt5514->i2c_regmap,
 343                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 344                         regcache_mark_dirty(rt5514->regmap);
 345                         regcache_sync(rt5514->regmap);
 346                 }
 347         }
 348
 349         return 0;
 350 }
 351
 352 static const struct snd_kcontrol_new rt5514_snd_controls[] = {
 353         SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
 354                 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
 355         SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
 356                 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 357                 adc_vol_tlv),
 358         SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
 359                 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 360                 adc_vol_tlv),
 361         SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
 362                 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
 363 };
 364
 365 /* ADC Mixer*/
 366 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
 367         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
 368                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 369         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
 370                 RT5514_AD_AD_MIX_BIT, 1, 1),
 371 };
 372
 373 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
 374         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
 375                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 376         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
 377                 RT5514_AD_AD_MIX_BIT, 1, 1),
 378 };
 379
 380 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
 381         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
 382                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 383         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
 384                 RT5514_AD_AD_MIX_BIT, 1, 1),
 385 };
 386
 387 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
 388         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
 389                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 390         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
 391                 RT5514_AD_AD_MIX_BIT, 1, 1),
 392 };
 393
 394 /* DMIC Source */
 395 static const char * const rt5514_dmic_src[] = {
 396         "DMIC1", "DMIC2"
 397 };
 398
 399 static SOC_ENUM_SINGLE_DECL(
 400         rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 401         RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 402
 403 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
 404         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
 405
 406 static SOC_ENUM_SINGLE_DECL(
 407         rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 408         RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 409
 410 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
 411         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
 412
 413 /**
 414  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
 415  *
 416  * @rate: base clock rate.
 417  *
 418  * Choose divider parameter that gives the highest possible DMIC frequency in
 419  * 1MHz - 3MHz range.
 420  */
 421 static int rt5514_calc_dmic_clk(struct snd_soc_codec *codec, int rate)
 422 {
 423         int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
 424         int i;
 425
 426         if (rate < 1000000 * div[0]) {
 427                 pr_warn("Base clock rate %d is too low\n", rate);
 428                 return -EINVAL;
 429         }
 430
 431         for (i = 0; i < ARRAY_SIZE(div); i++) {
 432                 /* find divider that gives DMIC frequency below 3.072MHz */
 433                 if (3072000 * div[i] >= rate)
 434                         return i;
 435         }
 436
 437         dev_warn(codec->dev, "Base clock rate %d is too high\n", rate);
 438         return -EINVAL;
 439 }
 440
 441 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
 442         struct snd_kcontrol *kcontrol, int event)
 443 {
 444         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 445         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 446         int idx;
 447
 448         idx = rt5514_calc_dmic_clk(codec, rt5514->sysclk);
 449         if (idx < 0)
 450                 dev_err(codec->dev, "Failed to set DMIC clock\n");
 451         else
 452                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 453                         RT5514_CLK_DMIC_OUT_SEL_MASK,
 454                         idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
 455
 456         if (rt5514->pdata.dmic_init_delay)
 457                 msleep(rt5514->pdata.dmic_init_delay);
 458
 459         return idx;
 460 }
 461
 462 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 463                          struct snd_soc_dapm_widget *sink)
 464 {
 465         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 466         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 467
 468         if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
 469                 return 1;
 470         else
 471                 return 0;
 472 }
 473
 474 static int rt5514_pre_event(struct snd_soc_dapm_widget *w,
 475         struct snd_kcontrol *kcontrol, int event)
 476 {
 477         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 478         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 479
 480         switch (event) {
 481         case SND_SOC_DAPM_PRE_PMU:
 482                 /**
 483                  * If the DSP is enabled in start of recording, the DSP
 484                  * should be disabled, and sync back to normal recording
 485                  * settings to make sure recording properly.
 486                 */
 487                 if (rt5514->dsp_enabled) {
 488                         rt5514->dsp_enabled = 0;
 489                         regmap_multi_reg_write(rt5514->i2c_regmap,
 490                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 491                         regcache_mark_dirty(rt5514->regmap);
 492                         regcache_sync(rt5514->regmap);
 493                 }
 494                 break;
 495
 496         default:
 497                 return 0;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
 504         /* Input Lines */
 505         SND_SOC_DAPM_INPUT("DMIC1L"),
 506         SND_SOC_DAPM_INPUT("DMIC1R"),
 507         SND_SOC_DAPM_INPUT("DMIC2L"),
 508         SND_SOC_DAPM_INPUT("DMIC2R"),
 509
 510         SND_SOC_DAPM_INPUT("AMICL"),
 511         SND_SOC_DAPM_INPUT("AMICR"),
 512
 513         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 514         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 515
 516         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
 517                 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
 518
 519         SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
 520                 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
 521
 522         SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
 523                 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
 524         SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
 525                 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
 526         SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
 527                 NULL, 0),
 528         SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
 529                 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
 530         SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
 531                 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
 532         SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
 533                 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
 534         SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
 535                 NULL, 0),
 536         SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
 537                 NULL, 0),
 538         SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
 539                 NULL, 0),
 540         SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 541
 542
 543         SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
 544                 NULL, 0),
 545         SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
 546                 NULL, 0),
 547         SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
 548                 NULL, 0),
 549         SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
 550                 NULL, 0),
 551         SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
 552                 0, NULL, 0),
 553         SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 554
 555         SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
 556                 NULL, 0),
 557         SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
 558                 NULL, 0),
 559         SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
 560                 NULL, 0),
 561         SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
 562                 NULL, 0),
 563         SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
 564                 0, NULL, 0),
 565         SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 566
 567         SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
 568                 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
 569         SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
 570                 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
 571         SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
 572                 NULL, 0),
 573
 574         /* ADC Mux */
 575         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
 576                                 &rt5514_sto1_dmic_mux),
 577         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
 578                                 &rt5514_sto2_dmic_mux),
 579
 580         /* ADC Mixer */
 581         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
 582                 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
 583         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
 584                 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
 585
 586         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
 587                 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
 588         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
 589                 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
 590         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
 591                 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
 592         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
 593                 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
 594
 595         SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
 596                 RT5514_AD_AD_MUTE_BIT, 1),
 597         SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
 598                 RT5514_AD_AD_MUTE_BIT, 1),
 599         SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
 600                 RT5514_AD_AD_MUTE_BIT, 1),
 601         SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
 602                 RT5514_AD_AD_MUTE_BIT, 1),
 603
 604         /* ADC PGA */
 605         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 606         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 607
 608         /* Audio Interface */
 609         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 610
 611         SND_SOC_DAPM_PRE("DAPM Pre", rt5514_pre_event),
 612 };
 613
 614 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
 615         { "DMIC1", NULL, "DMIC1L" },
 616         { "DMIC1", NULL, "DMIC1R" },
 617         { "DMIC2", NULL, "DMIC2L" },
 618         { "DMIC2", NULL, "DMIC2R" },
 619
 620         { "DMIC1L", NULL, "DMIC CLK" },
 621         { "DMIC1R", NULL, "DMIC CLK" },
 622         { "DMIC2L", NULL, "DMIC CLK" },
 623         { "DMIC2R", NULL, "DMIC CLK" },
 624
 625         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
 626         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
 627
 628         { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
 629         { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
 630         { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
 631         { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
 632
 633         { "ADC Power", NULL, "LDO18 IN" },
 634         { "ADC Power", NULL, "LDO18 ADC" },
 635         { "ADC Power", NULL, "LDO21" },
 636         { "ADC Power", NULL, "BG LDO18 IN" },
 637         { "ADC Power", NULL, "BG LDO21" },
 638         { "ADC Power", NULL, "BG MBIAS" },
 639         { "ADC Power", NULL, "MBIAS" },
 640         { "ADC Power", NULL, "VREF2" },
 641         { "ADC Power", NULL, "VREF1" },
 642
 643         { "ADCL Power", NULL, "LDO16L" },
 644         { "ADCL Power", NULL, "ADC1L" },
 645         { "ADCL Power", NULL, "BSTL2" },
 646         { "ADCL Power", NULL, "BSTL" },
 647         { "ADCL Power", NULL, "ADCFEDL" },
 648
 649         { "ADCR Power", NULL, "LDO16R" },
 650         { "ADCR Power", NULL, "ADC1R" },
 651         { "ADCR Power", NULL, "BSTR2" },
 652         { "ADCR Power", NULL, "BSTR" },
 653         { "ADCR Power", NULL, "ADCFEDR" },
 654
 655         { "AMICL", NULL, "ADC CLK" },
 656         { "AMICL", NULL, "ADC Power" },
 657         { "AMICL", NULL, "ADCL Power" },
 658         { "AMICR", NULL, "ADC CLK" },
 659         { "AMICR", NULL, "ADC Power" },
 660         { "AMICR", NULL, "ADCR Power" },
 661
 662         { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
 663         { "PLL1", NULL, "PLL1 LDO" },
 664
 665         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
 666         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
 667
 668         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
 669         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
 670         { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
 671         { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 672
 673         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
 674         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
 675
 676         { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
 677         { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
 678         { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
 679         { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
 680
 681         { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
 682         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
 683
 684         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
 685         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
 686         { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
 687         { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 688
 689         { "AIF1TX", NULL, "Stereo1 ADC MIX"},
 690         { "AIF1TX", NULL, "Stereo2 ADC MIX"},
 691 };
 692
 693 static int rt5514_hw_params(struct snd_pcm_substream *substream,
 694         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 695 {
 696         struct snd_soc_codec *codec = dai->codec;
 697         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 698         int pre_div, bclk_ms, frame_size;
 699         unsigned int val_len = 0;
 700
 701         rt5514->lrck = params_rate(params);
 702         pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
 703         if (pre_div < 0) {
 704                 dev_err(codec->dev, "Unsupported clock setting\n");
 705                 return -EINVAL;
 706         }
 707
 708         frame_size = snd_soc_params_to_frame_size(params);
 709         if (frame_size < 0) {
 710                 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
 711                 return -EINVAL;
 712         }
 713
 714         bclk_ms = frame_size > 32;
 715         rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
 716
 717         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
 718                 rt5514->bclk, rt5514->lrck);
 719         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 720                                 bclk_ms, pre_div, dai->id);
 721
 722         switch (params_format(params)) {
 723         case SNDRV_PCM_FORMAT_S16_LE:
 724                 break;
 725         case SNDRV_PCM_FORMAT_S20_3LE:
 726                 val_len = RT5514_I2S_DL_20;
 727                 break;
 728         case SNDRV_PCM_FORMAT_S24_LE:
 729                 val_len = RT5514_I2S_DL_24;
 730                 break;
 731         case SNDRV_PCM_FORMAT_S8:
 732                 val_len = RT5514_I2S_DL_8;
 733                 break;
 734         default:
 735                 return -EINVAL;
 736         }
 737
 738         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
 739                 val_len);
 740         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 741                 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
 742                 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
 743                 pre_div << RT5514_SEL_ADC_OSR_SFT);
 744
 745         return 0;
 746 }
 747
 748 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 749 {
 750         struct snd_soc_codec *codec = dai->codec;
 751         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 752         unsigned int reg_val = 0;
 753
 754         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 755         case SND_SOC_DAIFMT_NB_NF:
 756                 break;
 757
 758         case SND_SOC_DAIFMT_NB_IF:
 759                 reg_val |= RT5514_I2S_LR_INV;
 760                 break;
 761
 762         case SND_SOC_DAIFMT_IB_NF:
 763                 reg_val |= RT5514_I2S_BP_INV;
 764                 break;
 765
 766         case SND_SOC_DAIFMT_IB_IF:
 767                 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
 768                 break;
 769
 770         default:
 771                 return -EINVAL;
 772         }
 773
 774         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 775         case SND_SOC_DAIFMT_I2S:
 776                 break;
 777
 778         case SND_SOC_DAIFMT_LEFT_J:
 779                 reg_val |= RT5514_I2S_DF_LEFT;
 780                 break;
 781
 782         case SND_SOC_DAIFMT_DSP_A:
 783                 reg_val |= RT5514_I2S_DF_PCM_A;
 784                 break;
 785
 786         case SND_SOC_DAIFMT_DSP_B:
 787                 reg_val |= RT5514_I2S_DF_PCM_B;
 788                 break;
 789
 790         default:
 791                 return -EINVAL;
 792         }
 793
 794         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
 795                 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
 796                 reg_val);
 797
 798         return 0;
 799 }
 800
 801 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
 802                 int clk_id, unsigned int freq, int dir)
 803 {
 804         struct snd_soc_codec *codec = dai->codec;
 805         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 806         unsigned int reg_val = 0;
 807
 808         if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
 809                 return 0;
 810
 811         switch (clk_id) {
 812         case RT5514_SCLK_S_MCLK:
 813                 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
 814                 break;
 815
 816         case RT5514_SCLK_S_PLL1:
 817                 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
 818                 break;
 819
 820         default:
 821                 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
 822                 return -EINVAL;
 823         }
 824
 825         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 826                 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
 827
 828         rt5514->sysclk = freq;
 829         rt5514->sysclk_src = clk_id;
 830
 831         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
 832
 833         return 0;
 834 }
 835
 836 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
 837                         unsigned int freq_in, unsigned int freq_out)
 838 {
 839         struct snd_soc_codec *codec = dai->codec;
 840         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 841         struct rl6231_pll_code pll_code;
 842         int ret;
 843
 844         if (!freq_in || !freq_out) {
 845                 dev_dbg(codec->dev, "PLL disabled\n");
 846
 847                 rt5514->pll_in = 0;
 848                 rt5514->pll_out = 0;
 849                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 850                         RT5514_CLK_SYS_PRE_SEL_MASK,
 851                         RT5514_CLK_SYS_PRE_SEL_MCLK);
 852
 853                 return 0;
 854         }
 855
 856         if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
 857             freq_out == rt5514->pll_out)
 858                 return 0;
 859
 860         switch (source) {
 861         case RT5514_PLL1_S_MCLK:
 862                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 863                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
 864                 break;
 865
 866         case RT5514_PLL1_S_BCLK:
 867                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 868                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
 869                 break;
 870
 871         default:
 872                 dev_err(codec->dev, "Unknown PLL source %d\n", source);
 873                 return -EINVAL;
 874         }
 875
 876         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 877         if (ret < 0) {
 878                 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
 879                 return ret;
 880         }
 881
 882         dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
 883                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 884                 pll_code.n_code, pll_code.k_code);
 885
 886         regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
 887                 pll_code.k_code << RT5514_PLL_K_SFT |
 888                 pll_code.n_code << RT5514_PLL_N_SFT |
 889                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
 890         regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
 891                 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
 892
 893         rt5514->pll_in = freq_in;
 894         rt5514->pll_out = freq_out;
 895         rt5514->pll_src = source;
 896
 897         return 0;
 898 }
 899
 900 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 901                         unsigned int rx_mask, int slots, int slot_width)
 902 {
 903         struct snd_soc_codec *codec = dai->codec;
 904         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 905         unsigned int val = 0;
 906
 907         if (rx_mask || tx_mask)
 908                 val |= RT5514_TDM_MODE;
 909
 910         switch (slots) {
 911         case 4:
 912                 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
 913                 break;
 914
 915         case 6:
 916                 val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
 917                 break;
 918
 919         case 8:
 920                 val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
 921                 break;
 922
 923         case 2:
 924         default:
 925                 break;
 926         }
 927
 928         switch (slot_width) {
 929         case 20:
 930                 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
 931                 break;
 932
 933         case 24:
 934                 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
 935                 break;
 936
 937         case 25:
 938                 val |= RT5514_TDM_MODE2;
 939                 break;
 940
 941         case 32:
 942                 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
 943                 break;
 944
 945         case 16:
 946         default:
 947                 break;
 948         }
 949
 950         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
 951                 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
 952                 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
 953                 RT5514_TDM_MODE2, val);
 954
 955         return 0;
 956 }
 957
 958 static int rt5514_set_bias_level(struct snd_soc_codec *codec,
 959                         enum snd_soc_bias_level level)
 960 {
 961         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 962         int ret;
 963
 964         switch (level) {
 965         case SND_SOC_BIAS_PREPARE:
 966                 if (IS_ERR(rt5514->mclk))
 967                         break;
 968
 969                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
 970                         clk_disable_unprepare(rt5514->mclk);
 971                 } else {
 972                         ret = clk_prepare_enable(rt5514->mclk);
 973                         if (ret)
 974                                 return ret;
 975                 }
 976                 break;
 977
 978         default:
 979                 break;
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int rt5514_probe(struct snd_soc_codec *codec)
 986 {
 987         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 988
 989         rt5514->mclk = devm_clk_get(codec->dev, "mclk");
 990         if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
 991                 return -EPROBE_DEFER;
 992
 993         rt5514->codec = codec;
 994
 995         return 0;
 996 }
 997
 998 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
 999 {
1000         struct i2c_client *client = context;
1001         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1002
1003         regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1004
1005         return 0;
1006 }
1007
1008 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
1009 {
1010         struct i2c_client *client = context;
1011         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1012
1013         regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1014
1015         return 0;
1016 }
1017
1018 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1019 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1020                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1021
1022 struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1023         .hw_params = rt5514_hw_params,
1024         .set_fmt = rt5514_set_dai_fmt,
1025         .set_sysclk = rt5514_set_dai_sysclk,
1026         .set_pll = rt5514_set_dai_pll,
1027         .set_tdm_slot = rt5514_set_tdm_slot,
1028 };
1029
1030 struct snd_soc_dai_driver rt5514_dai[] = {
1031         {
1032                 .name = "rt5514-aif1",
1033                 .id = 0,
1034                 .capture = {
1035                         .stream_name = "AIF1 Capture",
1036                         .channels_min = 1,
1037                         .channels_max = 4,
1038                         .rates = RT5514_STEREO_RATES,
1039                         .formats = RT5514_FORMATS,
1040                 },
1041                 .ops = &rt5514_aif_dai_ops,
1042         }
1043 };
1044
1045 static struct snd_soc_codec_driver soc_codec_dev_rt5514 = {
1046         .probe = rt5514_probe,
1047         .idle_bias_off = true,
1048         .set_bias_level = rt5514_set_bias_level,
1049         .component_driver = {
1050                 .controls               = rt5514_snd_controls,
1051                 .num_controls           = ARRAY_SIZE(rt5514_snd_controls),
1052                 .dapm_widgets           = rt5514_dapm_widgets,
1053                 .num_dapm_widgets       = ARRAY_SIZE(rt5514_dapm_widgets),
1054                 .dapm_routes            = rt5514_dapm_routes,
1055                 .num_dapm_routes        = ARRAY_SIZE(rt5514_dapm_routes),
1056         },
1057 };
1058
1059 static const struct regmap_config rt5514_i2c_regmap = {
1060         .name = "i2c",
1061         .reg_bits = 32,
1062         .val_bits = 32,
1063
1064         .readable_reg = rt5514_i2c_readable_register,
1065
1066         .cache_type = REGCACHE_NONE,
1067 };
1068
1069 static const struct regmap_config rt5514_regmap = {
1070         .reg_bits = 16,
1071         .val_bits = 32,
1072
1073         .max_register = RT5514_VENDOR_ID2,
1074         .volatile_reg = rt5514_volatile_register,
1075         .readable_reg = rt5514_readable_register,
1076         .reg_read = rt5514_i2c_read,
1077         .reg_write = rt5514_i2c_write,
1078
1079         .cache_type = REGCACHE_RBTREE,
1080         .reg_defaults = rt5514_reg,
1081         .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1082         .use_single_rw = true,
1083 };
1084
1085 static const struct i2c_device_id rt5514_i2c_id[] = {
1086         { "rt5514", 0 },
1087         { }
1088 };
1089 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1090
1091 #if defined(CONFIG_OF)
1092 static const struct of_device_id rt5514_of_match[] = {
1093         { .compatible = "realtek,rt5514", },
1094         {},
1095 };
1096 MODULE_DEVICE_TABLE(of, rt5514_of_match);
1097 #endif
1098
1099 #ifdef CONFIG_ACPI
1100 static struct acpi_device_id rt5514_acpi_match[] = {
1101         { "10EC5514", 0},
1102         {},
1103 };
1104 MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
1105 #endif
1106
1107 static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev)
1108 {
1109         device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
1110                 &rt5514->pdata.dmic_init_delay);
1111
1112         return 0;
1113 }
1114
1115 static __maybe_unused int rt5514_i2c_resume(struct device *dev)
1116 {
1117         struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
1118         unsigned int val;
1119
1120         /*
1121          * Add a bogus read to avoid rt5514's confusion after s2r in case it
1122          * saw glitches on the i2c lines and thought the other side sent a
1123          * start bit.
1124          */
1125         regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1126
1127         return 0;
1128 }
1129
1130 static int rt5514_i2c_probe(struct i2c_client *i2c,
1131                     const struct i2c_device_id *id)
1132 {
1133         struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
1134         struct rt5514_priv *rt5514;
1135         int ret;
1136         unsigned int val = ~0;
1137
1138         rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1139                                 GFP_KERNEL);
1140         if (rt5514 == NULL)
1141                 return -ENOMEM;
1142
1143         i2c_set_clientdata(i2c, rt5514);
1144
1145         if (pdata)
1146                 rt5514->pdata = *pdata;
1147         else if (i2c->dev.of_node)
1148                 rt5514_parse_dt(rt5514, &i2c->dev);
1149
1150         rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1151         if (IS_ERR(rt5514->i2c_regmap)) {
1152                 ret = PTR_ERR(rt5514->i2c_regmap);
1153                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1154                         ret);
1155                 return ret;
1156         }
1157
1158         rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1159         if (IS_ERR(rt5514->regmap)) {
1160                 ret = PTR_ERR(rt5514->regmap);
1161                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1162                         ret);
1163                 return ret;
1164         }
1165
1166         /*
1167          * The rt5514 can get confused if the i2c lines glitch together, as
1168          * can happen at bootup as regulators are turned off and on.  If it's
1169          * in this glitched state the first i2c read will fail, so we'll give
1170          * it one change to retry.
1171          */
1172         ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1173         if (ret || val != RT5514_DEVICE_ID)
1174                 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1175         if (ret || val != RT5514_DEVICE_ID) {
1176                 dev_err(&i2c->dev,
1177                         "Device with ID register %x is not rt5514\n", val);
1178                 return -ENODEV;
1179         }
1180
1181         ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1182                                     ARRAY_SIZE(rt5514_i2c_patch));
1183         if (ret != 0)
1184                 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1185                         ret);
1186
1187         ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1188                                     ARRAY_SIZE(rt5514_patch));
1189         if (ret != 0)
1190                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1191
1192         return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5514,
1193                         rt5514_dai, ARRAY_SIZE(rt5514_dai));
1194 }
1195
1196 static int rt5514_i2c_remove(struct i2c_client *i2c)
1197 {
1198         snd_soc_unregister_codec(&i2c->dev);
1199
1200         return 0;
1201 }
1202
1203 static const struct dev_pm_ops rt5514_i2_pm_ops = {
1204         SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
1205 };
1206
1207 static struct i2c_driver rt5514_i2c_driver = {
1208         .driver = {
1209                 .name = "rt5514",
1210                 .acpi_match_table = ACPI_PTR(rt5514_acpi_match),
1211                 .of_match_table = of_match_ptr(rt5514_of_match),
1212                 .pm = &rt5514_i2_pm_ops,
1213         },
1214         .probe = rt5514_i2c_probe,
1215         .remove   = rt5514_i2c_remove,
1216         .id_table = rt5514_i2c_id,
1217 };
1218 module_i2c_driver(rt5514_i2c_driver);
1219
1220 MODULE_DESCRIPTION("ASoC RT5514 driver");
1221 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1222 MODULE_LICENSE("GPL v2");