1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver
5 // Copyright 2019 Realtek Semiconductor Corp.
7 // Author: Jack Yu <jack.yu@realtek.com>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/regmap.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/gpio.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 static const struct reg_default rt1015_reg[] = {
187 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
194 case RT1015_VENDOR_ID:
195 case RT1015_DEVICE_ID:
198 case RT1015_VBAT_TEST_OUT1:
199 case RT1015_VBAT_TEST_OUT2:
200 case RT1015_VBAT_PROT_ATT:
201 case RT1015_VBAT_DET_CODE:
202 case RT1015_SMART_BST_CTRL1:
203 case RT1015_SPK_DC_DETECT1:
204 case RT1015_SPK_DC_DETECT4:
205 case RT1015_SPK_DC_DETECT5:
206 case RT1015_DC_CALIB_CLSD1:
207 case RT1015_DC_CALIB_CLSD5:
208 case RT1015_DC_CALIB_CLSD6:
209 case RT1015_DC_CALIB_CLSD7:
210 case RT1015_DC_CALIB_CLSD8:
211 case RT1015_S_BST_TIMING_INTER1:
219 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
229 case RT1015_CUSTOMER_ID:
230 case RT1015_PCODE_FWVER:
232 case RT1015_VENDOR_ID:
233 case RT1015_DEVICE_ID:
234 case RT1015_PAD_DRV1:
235 case RT1015_PAD_DRV2:
236 case RT1015_GAT_BOOST:
244 case RT1015_TDM_MASTER:
245 case RT1015_TDM_TCON:
253 case RT1015_ANA_PROTECT1:
254 case RT1015_ANA_CTRL_SEQ1:
255 case RT1015_ANA_CTRL_SEQ2:
256 case RT1015_VBAT_DET_DEB:
257 case RT1015_VBAT_VOLT_DET1:
258 case RT1015_VBAT_VOLT_DET2:
259 case RT1015_VBAT_TEST_OUT1:
260 case RT1015_VBAT_TEST_OUT2:
261 case RT1015_VBAT_PROT_ATT:
262 case RT1015_VBAT_DET_CODE:
270 case RT1015_CLASSD_SEQ:
271 case RT1015_SMART_BST_CTRL1:
272 case RT1015_SMART_BST_CTRL2:
273 case RT1015_ANA_CTRL1:
274 case RT1015_ANA_CTRL2:
276 case RT1015_SHORT_DETTOP1:
277 case RT1015_SHORT_DETTOP2:
278 case RT1015_SPK_DC_DETECT1:
279 case RT1015_SPK_DC_DETECT2:
280 case RT1015_SPK_DC_DETECT3:
281 case RT1015_SPK_DC_DETECT4:
282 case RT1015_SPK_DC_DETECT5:
283 case RT1015_BAT_RPO_STEP1:
284 case RT1015_BAT_RPO_STEP2:
285 case RT1015_BAT_RPO_STEP3:
286 case RT1015_BAT_RPO_STEP4:
287 case RT1015_BAT_RPO_STEP5:
288 case RT1015_BAT_RPO_STEP6:
289 case RT1015_BAT_RPO_STEP7:
290 case RT1015_BAT_RPO_STEP8:
291 case RT1015_BAT_RPO_STEP9:
292 case RT1015_BAT_RPO_STEP10:
293 case RT1015_BAT_RPO_STEP11:
294 case RT1015_BAT_RPO_STEP12:
295 case RT1015_SPREAD_SPEC1:
296 case RT1015_SPREAD_SPEC2:
297 case RT1015_PAD_STATUS:
298 case RT1015_PADS_PULLING_CTRL1:
299 case RT1015_PADS_DRIVING:
300 case RT1015_SYS_RST1:
301 case RT1015_SYS_RST2:
302 case RT1015_SYS_GATING1:
303 case RT1015_TEST_MODE1:
304 case RT1015_TEST_MODE2:
305 case RT1015_TIMING_CTRL1:
307 case RT1015_TEST_OUT1:
308 case RT1015_DC_CALIB_CLSD1:
309 case RT1015_DC_CALIB_CLSD2:
310 case RT1015_DC_CALIB_CLSD3:
311 case RT1015_DC_CALIB_CLSD4:
312 case RT1015_DC_CALIB_CLSD5:
313 case RT1015_DC_CALIB_CLSD6:
314 case RT1015_DC_CALIB_CLSD7:
315 case RT1015_DC_CALIB_CLSD8:
316 case RT1015_DC_CALIB_CLSD9:
317 case RT1015_DC_CALIB_CLSD10:
318 case RT1015_CLSD_INTERNAL1:
319 case RT1015_CLSD_INTERNAL2:
320 case RT1015_CLSD_INTERNAL3:
321 case RT1015_CLSD_INTERNAL4:
322 case RT1015_CLSD_INTERNAL5:
323 case RT1015_CLSD_INTERNAL6:
324 case RT1015_CLSD_INTERNAL7:
325 case RT1015_CLSD_INTERNAL8:
326 case RT1015_CLSD_INTERNAL9:
327 case RT1015_CLSD_OCP_CTRL:
333 case RT1015_VREF_LV1:
334 case RT1015_S_BST_TIMING_INTER1:
335 case RT1015_S_BST_TIMING_INTER2:
336 case RT1015_S_BST_TIMING_INTER3:
337 case RT1015_S_BST_TIMING_INTER4:
338 case RT1015_S_BST_TIMING_INTER5:
339 case RT1015_S_BST_TIMING_INTER6:
340 case RT1015_S_BST_TIMING_INTER7:
341 case RT1015_S_BST_TIMING_INTER8:
342 case RT1015_S_BST_TIMING_INTER9:
343 case RT1015_S_BST_TIMING_INTER10:
344 case RT1015_S_BST_TIMING_INTER11:
345 case RT1015_S_BST_TIMING_INTER12:
346 case RT1015_S_BST_TIMING_INTER13:
347 case RT1015_S_BST_TIMING_INTER14:
348 case RT1015_S_BST_TIMING_INTER15:
349 case RT1015_S_BST_TIMING_INTER16:
350 case RT1015_S_BST_TIMING_INTER17:
351 case RT1015_S_BST_TIMING_INTER18:
352 case RT1015_S_BST_TIMING_INTER19:
353 case RT1015_S_BST_TIMING_INTER20:
354 case RT1015_S_BST_TIMING_INTER21:
355 case RT1015_S_BST_TIMING_INTER22:
356 case RT1015_S_BST_TIMING_INTER23:
357 case RT1015_S_BST_TIMING_INTER24:
358 case RT1015_S_BST_TIMING_INTER25:
359 case RT1015_S_BST_TIMING_INTER26:
360 case RT1015_S_BST_TIMING_INTER27:
361 case RT1015_S_BST_TIMING_INTER28:
362 case RT1015_S_BST_TIMING_INTER29:
363 case RT1015_S_BST_TIMING_INTER30:
364 case RT1015_S_BST_TIMING_INTER31:
365 case RT1015_S_BST_TIMING_INTER32:
366 case RT1015_S_BST_TIMING_INTER33:
367 case RT1015_S_BST_TIMING_INTER34:
368 case RT1015_S_BST_TIMING_INTER35:
369 case RT1015_S_BST_TIMING_INTER36:
377 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
379 static const char * const rt1015_din_source_select[] = {
382 "Left + Right average",
385 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
386 rt1015_din_source_select);
388 static const char * const rt1015_boost_mode[] = {
389 "Bypass", "Adaptive", "Fixed Adaptive"
392 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
395 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
396 struct snd_ctl_elem_value *ucontrol)
398 struct snd_soc_component *component =
399 snd_soc_kcontrol_component(kcontrol);
400 struct rt1015_priv *rt1015 =
401 snd_soc_component_get_drvdata(component);
403 ucontrol->value.integer.value[0] = rt1015->boost_mode;
408 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
409 struct snd_ctl_elem_value *ucontrol)
411 struct snd_soc_component *component =
412 snd_soc_kcontrol_component(kcontrol);
413 struct rt1015_priv *rt1015 =
414 snd_soc_component_get_drvdata(component);
416 rt1015->boost_mode = ucontrol->value.integer.value[0];
418 switch (rt1015->boost_mode) {
420 snd_soc_component_update_bits(component,
421 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
422 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
423 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
424 RT1015_BYPASS_SWRREG_BYPASS);
427 snd_soc_component_update_bits(component,
428 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
429 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
430 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
431 RT1015_BYPASS_SWRREG_PASS);
434 snd_soc_component_update_bits(component,
435 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
436 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
437 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
438 RT1015_BYPASS_SWRREG_PASS);
441 dev_err(component->dev, "Unknown boost control.\n");
447 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
450 struct snd_soc_component *component =
451 snd_soc_kcontrol_component(kcontrol);
452 struct rt1015_priv *rt1015 =
453 snd_soc_component_get_drvdata(component);
455 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
460 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
461 struct snd_ctl_elem_value *ucontrol)
463 struct snd_soc_component *component =
464 snd_soc_kcontrol_component(kcontrol);
465 struct rt1015_priv *rt1015 =
466 snd_soc_component_get_drvdata(component);
468 if (!rt1015->dac_is_used) {
469 rt1015->bypass_boost = ucontrol->value.integer.value[0];
470 if (rt1015->bypass_boost == 1) {
471 snd_soc_component_write(component,
472 RT1015_PWR4, 0x00b2);
473 snd_soc_component_write(component,
474 RT1015_CLSD_INTERNAL8, 0x2008);
475 snd_soc_component_write(component,
476 RT1015_CLSD_INTERNAL9, 0x0140);
477 snd_soc_component_write(component,
478 RT1015_GAT_BOOST, 0x0efe);
479 snd_soc_component_write(component,
480 RT1015_PWR_STATE_CTRL, 0x000d);
482 snd_soc_component_write(component,
483 RT1015_PWR_STATE_CTRL, 0x000e);
486 dev_err(component->dev, "DAC is being used!\n");
491 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
492 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
493 127, 0, dac_vol_tlv),
494 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
495 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
496 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
497 rt1015_boost_mode_get, rt1015_boost_mode_put),
498 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
499 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
500 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
503 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
504 struct snd_soc_dapm_widget *sink)
506 struct snd_soc_component *component =
507 snd_soc_dapm_to_component(source->dapm);
508 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
510 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
516 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
517 struct snd_kcontrol *kcontrol, int event)
519 struct snd_soc_component *component =
520 snd_soc_dapm_to_component(w->dapm);
521 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
524 case SND_SOC_DAPM_PRE_PMU:
525 rt1015->dac_is_used = 1;
526 if (rt1015->bypass_boost == 0) {
527 snd_soc_component_write(component,
528 RT1015_SYS_RST1, 0x05f7);
529 snd_soc_component_write(component,
530 RT1015_GAT_BOOST, 0xacfe);
531 snd_soc_component_write(component,
532 RT1015_PWR9, 0xaa00);
533 snd_soc_component_write(component,
534 RT1015_GAT_BOOST, 0xecfe);
536 snd_soc_component_write(component,
537 RT1015_SYS_RST1, 0x05f7);
538 snd_soc_component_write(component,
539 RT1015_PWR_STATE_CTRL, 0x026e);
543 case SND_SOC_DAPM_POST_PMD:
544 if (rt1015->bypass_boost == 0) {
545 snd_soc_component_write(component,
546 RT1015_PWR9, 0xa800);
547 snd_soc_component_write(component,
548 RT1015_SYS_RST1, 0x05f5);
550 snd_soc_component_write(component,
551 RT1015_PWR_STATE_CTRL, 0x0268);
552 snd_soc_component_write(component,
553 RT1015_SYS_RST1, 0x05f5);
555 rt1015->dac_is_used = 0;
564 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
565 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0,
567 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT,
569 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0,
571 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0,
573 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
575 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0,
577 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0,
579 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL,
581 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0,
583 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL,
585 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0,
587 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL,
589 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0,
592 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
593 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0,
594 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
596 SND_SOC_DAPM_OUTPUT("SPO"),
599 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
600 { "DAC", NULL, "AIFRX" },
601 { "DAC", NULL, "LDO2" },
602 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
603 { "DAC", NULL, "INT RC CLK" },
604 { "DAC", NULL, "ISENSE" },
605 { "DAC", NULL, "VSENSE" },
606 { "DAC", NULL, "BG1 BG2" },
607 { "DAC", NULL, "MBIAS BG" },
608 { "DAC", NULL, "VBAT" },
609 { "DAC", NULL, "MBIAS" },
610 { "DAC", NULL, "ADCV" },
611 { "DAC", NULL, "MIXERV" },
612 { "DAC", NULL, "SUMV" },
613 { "DAC", NULL, "VREFLV" },
614 { "SPO", NULL, "DAC" },
617 static int rt1015_hw_params(struct snd_pcm_substream *substream,
618 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
620 struct snd_soc_component *component = dai->component;
621 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
622 int pre_div, bclk_ms, frame_size;
623 unsigned int val_len = 0;
625 rt1015->lrck = params_rate(params);
626 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck);
628 dev_err(component->dev, "Unsupported clock rate\n");
632 frame_size = snd_soc_params_to_frame_size(params);
633 if (frame_size < 0) {
634 dev_err(component->dev, "Unsupported frame size: %d\n",
639 bclk_ms = frame_size > 32;
640 rt1015->bclk = rt1015->lrck * (32 << bclk_ms);
642 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
643 bclk_ms, pre_div, dai->id);
645 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
646 rt1015->lrck, pre_div, dai->id);
648 switch (params_width(params)) {
652 val_len = RT1015_I2S_DL_20;
655 val_len = RT1015_I2S_DL_24;
658 val_len = RT1015_I2S_DL_8;
664 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
665 RT1015_I2S_DL_MASK, val_len);
666 snd_soc_component_update_bits(component, RT1015_CLK2,
667 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
672 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
674 struct snd_soc_component *component = dai->component;
675 unsigned int reg_val = 0, reg_val2 = 0;
677 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
678 case SND_SOC_DAIFMT_CBM_CFM:
679 reg_val |= RT1015_TCON_TDM_MS_M;
681 case SND_SOC_DAIFMT_CBS_CFS:
682 reg_val |= RT1015_TCON_TDM_MS_S;
688 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
689 case SND_SOC_DAIFMT_NB_NF:
691 case SND_SOC_DAIFMT_IB_NF:
692 reg_val2 |= RT1015_TDM_INV_BCLK;
698 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
699 case SND_SOC_DAIFMT_I2S:
702 case SND_SOC_DAIFMT_LEFT_J:
703 reg_val |= RT1015_I2S_M_DF_LEFT;
706 case SND_SOC_DAIFMT_DSP_A:
707 reg_val |= RT1015_I2S_M_DF_PCM_A;
710 case SND_SOC_DAIFMT_DSP_B:
711 reg_val |= RT1015_I2S_M_DF_PCM_B;
718 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
719 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
721 snd_soc_component_update_bits(component, RT1015_TDM1_1,
722 RT1015_TDM_INV_BCLK_MASK, reg_val2);
727 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
728 int clk_id, int source, unsigned int freq, int dir)
730 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
731 unsigned int reg_val = 0;
733 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
737 case RT1015_SCLK_S_MCLK:
738 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
741 case RT1015_SCLK_S_PLL:
742 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
746 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
750 rt1015->sysclk = freq;
751 rt1015->sysclk_src = clk_id;
753 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
756 snd_soc_component_update_bits(component, RT1015_CLK2,
757 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
762 static int rt1015_set_component_pll(struct snd_soc_component *component,
763 int pll_id, int source, unsigned int freq_in,
764 unsigned int freq_out)
766 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
767 struct rl6231_pll_code pll_code;
770 if (!freq_in || !freq_out) {
771 dev_dbg(component->dev, "PLL disabled\n");
779 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
780 freq_out == rt1015->pll_out)
783 if (source == RT1015_PLL_S_BCLK) {
784 if (rt1015->bclk_ratio == 0) {
785 dev_err(component->dev,
786 "Can not support bclk ratio as 0.\n");
792 case RT1015_PLL_S_MCLK:
793 snd_soc_component_update_bits(component, RT1015_CLK2,
794 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
797 case RT1015_PLL_S_BCLK:
798 snd_soc_component_update_bits(component, RT1015_CLK2,
799 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
803 dev_err(component->dev, "Unknown PLL Source %d\n", source);
807 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
809 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
813 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
814 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
815 pll_code.n_code, pll_code.k_code);
817 snd_soc_component_write(component, RT1015_PLL1,
818 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
819 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
820 snd_soc_component_write(component, RT1015_PLL2,
823 rt1015->pll_in = freq_in;
824 rt1015->pll_out = freq_out;
825 rt1015->pll_src = source;
830 static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
832 struct snd_soc_component *component = dai->component;
833 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
835 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
837 rt1015->bclk_ratio = ratio;
840 dev_dbg(component->dev, "Unsupport bclk ratio\n");
847 static int rt1015_probe(struct snd_soc_component *component)
849 struct rt1015_priv *rt1015 =
850 snd_soc_component_get_drvdata(component);
852 rt1015->component = component;
853 rt1015->bclk_ratio = 0;
854 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c);
859 static void rt1015_remove(struct snd_soc_component *component)
861 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
863 regmap_write(rt1015->regmap, RT1015_RESET, 0);
866 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
867 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
868 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
870 static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
871 .hw_params = rt1015_hw_params,
872 .set_fmt = rt1015_set_dai_fmt,
873 .set_bclk_ratio = rt1015_set_bclk_ratio,
876 static struct snd_soc_dai_driver rt1015_dai[] = {
878 .name = "rt1015-aif",
881 .stream_name = "AIF Playback",
884 .rates = RT1015_STEREO_RATES,
885 .formats = RT1015_FORMATS,
887 .ops = &rt1015_aif_dai_ops,
892 static int rt1015_suspend(struct snd_soc_component *component)
894 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
896 regcache_cache_only(rt1015->regmap, true);
897 regcache_mark_dirty(rt1015->regmap);
902 static int rt1015_resume(struct snd_soc_component *component)
904 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
906 regcache_cache_only(rt1015->regmap, false);
907 regcache_sync(rt1015->regmap);
911 #define rt1015_suspend NULL
912 #define rt1015_resume NULL
915 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
916 .probe = rt1015_probe,
917 .remove = rt1015_remove,
918 .suspend = rt1015_suspend,
919 .resume = rt1015_resume,
920 .controls = rt1015_snd_controls,
921 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
922 .dapm_widgets = rt1015_dapm_widgets,
923 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
924 .dapm_routes = rt1015_dapm_routes,
925 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
926 .set_sysclk = rt1015_set_component_sysclk,
927 .set_pll = rt1015_set_component_pll,
928 .use_pmdown_time = 1,
930 .non_legacy_dai_naming = 1,
933 static const struct regmap_config rt1015_regmap = {
936 .max_register = RT1015_S_BST_TIMING_INTER36,
937 .volatile_reg = rt1015_volatile_register,
938 .readable_reg = rt1015_readable_register,
939 .cache_type = REGCACHE_RBTREE,
940 .reg_defaults = rt1015_reg,
941 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
944 static const struct i2c_device_id rt1015_i2c_id[] = {
948 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
950 #if defined(CONFIG_OF)
951 static const struct of_device_id rt1015_of_match[] = {
952 { .compatible = "realtek,rt1015", },
955 MODULE_DEVICE_TABLE(of, rt1015_of_match);
959 static struct acpi_device_id rt1015_acpi_match[] = {
963 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
966 static int rt1015_i2c_probe(struct i2c_client *i2c,
967 const struct i2c_device_id *id)
969 struct rt1015_priv *rt1015;
973 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv),
978 i2c_set_clientdata(i2c, rt1015);
980 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
981 if (IS_ERR(rt1015->regmap)) {
982 ret = PTR_ERR(rt1015->regmap);
983 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
988 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
989 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) {
991 "Device with ID register %x is not rt1015\n", val);
995 return devm_snd_soc_register_component(&i2c->dev,
996 &soc_component_dev_rt1015,
997 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1000 static void rt1015_i2c_shutdown(struct i2c_client *client)
1002 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1004 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1007 static struct i2c_driver rt1015_i2c_driver = {
1010 .of_match_table = of_match_ptr(rt1015_of_match),
1011 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1013 .probe = rt1015_i2c_probe,
1014 .shutdown = rt1015_i2c_shutdown,
1015 .id_table = rt1015_i2c_id,
1017 module_i2c_driver(rt1015_i2c_driver);
1019 MODULE_DESCRIPTION("ASoC RT1015 driver");
1020 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1021 MODULE_LICENSE("GPL v2");