1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver
5 // Copyright 2019 Realtek Semiconductor Corp.
7 // Author: Jack Yu <jack.yu@realtek.com>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/regmap.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/gpio.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 static const struct reg_default rt1015_reg[] = {
196 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
203 case RT1015_VENDOR_ID:
204 case RT1015_DEVICE_ID:
207 case RT1015_VBAT_TEST_OUT1:
208 case RT1015_VBAT_TEST_OUT2:
209 case RT1015_VBAT_PROT_ATT:
210 case RT1015_VBAT_DET_CODE:
211 case RT1015_SMART_BST_CTRL1:
212 case RT1015_SPK_DC_DETECT1:
213 case RT1015_SPK_DC_DETECT4:
214 case RT1015_SPK_DC_DETECT5:
215 case RT1015_DC_CALIB_CLSD1:
216 case RT1015_DC_CALIB_CLSD5:
217 case RT1015_DC_CALIB_CLSD6:
218 case RT1015_DC_CALIB_CLSD7:
219 case RT1015_DC_CALIB_CLSD8:
220 case RT1015_S_BST_TIMING_INTER1:
221 case RT1015_OSCK_STA:
222 case RT1015_MONO_DYNA_CTRL1:
223 case RT1015_MONO_DYNA_CTRL5:
231 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
247 case RT1015_CUSTOMER_ID:
248 case RT1015_PCODE_FWVER:
250 case RT1015_VENDOR_ID:
251 case RT1015_DEVICE_ID:
252 case RT1015_PAD_DRV1:
253 case RT1015_PAD_DRV2:
254 case RT1015_GAT_BOOST:
256 case RT1015_OSCK_STA:
263 case RT1015_TDM_MASTER:
264 case RT1015_TDM_TCON:
272 case RT1015_ANA_PROTECT1:
273 case RT1015_ANA_CTRL_SEQ1:
274 case RT1015_ANA_CTRL_SEQ2:
275 case RT1015_VBAT_DET_DEB:
276 case RT1015_VBAT_VOLT_DET1:
277 case RT1015_VBAT_VOLT_DET2:
278 case RT1015_VBAT_TEST_OUT1:
279 case RT1015_VBAT_TEST_OUT2:
280 case RT1015_VBAT_PROT_ATT:
281 case RT1015_VBAT_DET_CODE:
289 case RT1015_CLASSD_SEQ:
290 case RT1015_SMART_BST_CTRL1:
291 case RT1015_SMART_BST_CTRL2:
292 case RT1015_ANA_CTRL1:
293 case RT1015_ANA_CTRL2:
294 case RT1015_PWR_STATE_CTRL:
295 case RT1015_MONO_DYNA_CTRL:
296 case RT1015_MONO_DYNA_CTRL1:
297 case RT1015_MONO_DYNA_CTRL2:
298 case RT1015_MONO_DYNA_CTRL3:
299 case RT1015_MONO_DYNA_CTRL4:
300 case RT1015_MONO_DYNA_CTRL5:
302 case RT1015_SHORT_DETTOP1:
303 case RT1015_SHORT_DETTOP2:
304 case RT1015_SPK_DC_DETECT1:
305 case RT1015_SPK_DC_DETECT2:
306 case RT1015_SPK_DC_DETECT3:
307 case RT1015_SPK_DC_DETECT4:
308 case RT1015_SPK_DC_DETECT5:
309 case RT1015_BAT_RPO_STEP1:
310 case RT1015_BAT_RPO_STEP2:
311 case RT1015_BAT_RPO_STEP3:
312 case RT1015_BAT_RPO_STEP4:
313 case RT1015_BAT_RPO_STEP5:
314 case RT1015_BAT_RPO_STEP6:
315 case RT1015_BAT_RPO_STEP7:
316 case RT1015_BAT_RPO_STEP8:
317 case RT1015_BAT_RPO_STEP9:
318 case RT1015_BAT_RPO_STEP10:
319 case RT1015_BAT_RPO_STEP11:
320 case RT1015_BAT_RPO_STEP12:
321 case RT1015_SPREAD_SPEC1:
322 case RT1015_SPREAD_SPEC2:
323 case RT1015_PAD_STATUS:
324 case RT1015_PADS_PULLING_CTRL1:
325 case RT1015_PADS_DRIVING:
326 case RT1015_SYS_RST1:
327 case RT1015_SYS_RST2:
328 case RT1015_SYS_GATING1:
329 case RT1015_TEST_MODE1:
330 case RT1015_TEST_MODE2:
331 case RT1015_TIMING_CTRL1:
333 case RT1015_TEST_OUT1:
334 case RT1015_DC_CALIB_CLSD1:
335 case RT1015_DC_CALIB_CLSD2:
336 case RT1015_DC_CALIB_CLSD3:
337 case RT1015_DC_CALIB_CLSD4:
338 case RT1015_DC_CALIB_CLSD5:
339 case RT1015_DC_CALIB_CLSD6:
340 case RT1015_DC_CALIB_CLSD7:
341 case RT1015_DC_CALIB_CLSD8:
342 case RT1015_DC_CALIB_CLSD9:
343 case RT1015_DC_CALIB_CLSD10:
344 case RT1015_CLSD_INTERNAL1:
345 case RT1015_CLSD_INTERNAL2:
346 case RT1015_CLSD_INTERNAL3:
347 case RT1015_CLSD_INTERNAL4:
348 case RT1015_CLSD_INTERNAL5:
349 case RT1015_CLSD_INTERNAL6:
350 case RT1015_CLSD_INTERNAL7:
351 case RT1015_CLSD_INTERNAL8:
352 case RT1015_CLSD_INTERNAL9:
353 case RT1015_CLSD_OCP_CTRL:
359 case RT1015_VREF_LV1:
360 case RT1015_S_BST_TIMING_INTER1:
361 case RT1015_S_BST_TIMING_INTER2:
362 case RT1015_S_BST_TIMING_INTER3:
363 case RT1015_S_BST_TIMING_INTER4:
364 case RT1015_S_BST_TIMING_INTER5:
365 case RT1015_S_BST_TIMING_INTER6:
366 case RT1015_S_BST_TIMING_INTER7:
367 case RT1015_S_BST_TIMING_INTER8:
368 case RT1015_S_BST_TIMING_INTER9:
369 case RT1015_S_BST_TIMING_INTER10:
370 case RT1015_S_BST_TIMING_INTER11:
371 case RT1015_S_BST_TIMING_INTER12:
372 case RT1015_S_BST_TIMING_INTER13:
373 case RT1015_S_BST_TIMING_INTER14:
374 case RT1015_S_BST_TIMING_INTER15:
375 case RT1015_S_BST_TIMING_INTER16:
376 case RT1015_S_BST_TIMING_INTER17:
377 case RT1015_S_BST_TIMING_INTER18:
378 case RT1015_S_BST_TIMING_INTER19:
379 case RT1015_S_BST_TIMING_INTER20:
380 case RT1015_S_BST_TIMING_INTER21:
381 case RT1015_S_BST_TIMING_INTER22:
382 case RT1015_S_BST_TIMING_INTER23:
383 case RT1015_S_BST_TIMING_INTER24:
384 case RT1015_S_BST_TIMING_INTER25:
385 case RT1015_S_BST_TIMING_INTER26:
386 case RT1015_S_BST_TIMING_INTER27:
387 case RT1015_S_BST_TIMING_INTER28:
388 case RT1015_S_BST_TIMING_INTER29:
389 case RT1015_S_BST_TIMING_INTER30:
390 case RT1015_S_BST_TIMING_INTER31:
391 case RT1015_S_BST_TIMING_INTER32:
392 case RT1015_S_BST_TIMING_INTER33:
393 case RT1015_S_BST_TIMING_INTER34:
394 case RT1015_S_BST_TIMING_INTER35:
395 case RT1015_S_BST_TIMING_INTER36:
403 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
405 static const char * const rt1015_din_source_select[] = {
408 "Left + Right average",
411 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
412 rt1015_din_source_select);
414 static const char * const rt1015_boost_mode[] = {
415 "Bypass", "Adaptive", "Fixed Adaptive"
418 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
421 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
424 struct snd_soc_component *component =
425 snd_soc_kcontrol_component(kcontrol);
426 struct rt1015_priv *rt1015 =
427 snd_soc_component_get_drvdata(component);
429 ucontrol->value.integer.value[0] = rt1015->boost_mode;
434 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
435 struct snd_ctl_elem_value *ucontrol)
437 struct snd_soc_component *component =
438 snd_soc_kcontrol_component(kcontrol);
439 struct rt1015_priv *rt1015 =
440 snd_soc_component_get_drvdata(component);
442 rt1015->boost_mode = ucontrol->value.integer.value[0];
444 switch (rt1015->boost_mode) {
446 snd_soc_component_update_bits(component,
447 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
448 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
449 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
450 RT1015_BYPASS_SWRREG_BYPASS);
453 snd_soc_component_update_bits(component,
454 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
455 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
456 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
457 RT1015_BYPASS_SWRREG_PASS);
460 snd_soc_component_update_bits(component,
461 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
462 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
463 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
464 RT1015_BYPASS_SWRREG_PASS);
467 dev_err(component->dev, "Unknown boost control.\n");
473 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
474 struct snd_ctl_elem_value *ucontrol)
476 struct snd_soc_component *component =
477 snd_soc_kcontrol_component(kcontrol);
478 struct rt1015_priv *rt1015 =
479 snd_soc_component_get_drvdata(component);
481 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
486 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
487 struct snd_ctl_elem_value *ucontrol)
489 struct snd_soc_component *component =
490 snd_soc_kcontrol_component(kcontrol);
491 struct rt1015_priv *rt1015 =
492 snd_soc_component_get_drvdata(component);
494 if (!rt1015->dac_is_used) {
495 rt1015->bypass_boost = ucontrol->value.integer.value[0];
496 if (rt1015->bypass_boost == 1) {
497 snd_soc_component_write(component,
498 RT1015_PWR4, 0x00b2);
499 snd_soc_component_write(component,
500 RT1015_CLSD_INTERNAL8, 0x2008);
501 snd_soc_component_write(component,
502 RT1015_CLSD_INTERNAL9, 0x0140);
503 snd_soc_component_write(component,
504 RT1015_GAT_BOOST, 0x0efe);
505 snd_soc_component_write(component,
506 RT1015_PWR_STATE_CTRL, 0x000d);
508 snd_soc_component_write(component,
509 RT1015_PWR_STATE_CTRL, 0x000e);
512 dev_err(component->dev, "DAC is being used!\n");
517 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
518 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
519 127, 0, dac_vol_tlv),
520 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
521 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
522 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
523 rt1015_boost_mode_get, rt1015_boost_mode_put),
524 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
525 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
526 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
529 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
530 struct snd_soc_dapm_widget *sink)
532 struct snd_soc_component *component =
533 snd_soc_dapm_to_component(source->dapm);
534 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
536 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
542 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
543 struct snd_kcontrol *kcontrol, int event)
545 struct snd_soc_component *component =
546 snd_soc_dapm_to_component(w->dapm);
547 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
550 case SND_SOC_DAPM_PRE_PMU:
551 rt1015->dac_is_used = 1;
552 if (rt1015->bypass_boost == 0) {
553 snd_soc_component_write(component,
554 RT1015_SYS_RST1, 0x05f7);
555 snd_soc_component_write(component,
556 RT1015_GAT_BOOST, 0xacfe);
557 snd_soc_component_write(component,
558 RT1015_PWR9, 0xaa00);
559 snd_soc_component_write(component,
560 RT1015_GAT_BOOST, 0xecfe);
562 snd_soc_component_write(component,
563 RT1015_SYS_RST1, 0x05f7);
564 snd_soc_component_write(component,
565 RT1015_PWR_STATE_CTRL, 0x026e);
569 case SND_SOC_DAPM_POST_PMD:
570 if (rt1015->bypass_boost == 0) {
571 snd_soc_component_write(component,
572 RT1015_PWR9, 0xa800);
573 snd_soc_component_write(component,
574 RT1015_SYS_RST1, 0x05f5);
576 snd_soc_component_write(component,
577 RT1015_PWR_STATE_CTRL, 0x0268);
578 snd_soc_component_write(component,
579 RT1015_SYS_RST1, 0x05f5);
581 rt1015->dac_is_used = 0;
590 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
591 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0,
593 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT,
595 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0,
597 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0,
599 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
601 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0,
603 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0,
605 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL,
607 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0,
609 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL,
611 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0,
613 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL,
615 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0,
618 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
619 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0,
620 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
622 SND_SOC_DAPM_OUTPUT("SPO"),
625 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
626 { "DAC", NULL, "AIFRX" },
627 { "DAC", NULL, "LDO2" },
628 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
629 { "DAC", NULL, "INT RC CLK" },
630 { "DAC", NULL, "ISENSE" },
631 { "DAC", NULL, "VSENSE" },
632 { "DAC", NULL, "BG1 BG2" },
633 { "DAC", NULL, "MBIAS BG" },
634 { "DAC", NULL, "VBAT" },
635 { "DAC", NULL, "MBIAS" },
636 { "DAC", NULL, "ADCV" },
637 { "DAC", NULL, "MIXERV" },
638 { "DAC", NULL, "SUMV" },
639 { "DAC", NULL, "VREFLV" },
640 { "SPO", NULL, "DAC" },
643 static int rt1015_hw_params(struct snd_pcm_substream *substream,
644 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
646 struct snd_soc_component *component = dai->component;
647 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
648 int pre_div, bclk_ms, frame_size;
649 unsigned int val_len = 0;
651 rt1015->lrck = params_rate(params);
652 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck);
654 dev_err(component->dev, "Unsupported clock rate\n");
658 frame_size = snd_soc_params_to_frame_size(params);
659 if (frame_size < 0) {
660 dev_err(component->dev, "Unsupported frame size: %d\n",
665 bclk_ms = frame_size > 32;
666 rt1015->bclk = rt1015->lrck * (32 << bclk_ms);
668 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
669 bclk_ms, pre_div, dai->id);
671 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
672 rt1015->lrck, pre_div, dai->id);
674 switch (params_width(params)) {
678 val_len = RT1015_I2S_DL_20;
681 val_len = RT1015_I2S_DL_24;
684 val_len = RT1015_I2S_DL_8;
690 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
691 RT1015_I2S_DL_MASK, val_len);
692 snd_soc_component_update_bits(component, RT1015_CLK2,
693 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
698 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
700 struct snd_soc_component *component = dai->component;
701 unsigned int reg_val = 0, reg_val2 = 0;
703 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
704 case SND_SOC_DAIFMT_CBM_CFM:
705 reg_val |= RT1015_TCON_TDM_MS_M;
707 case SND_SOC_DAIFMT_CBS_CFS:
708 reg_val |= RT1015_TCON_TDM_MS_S;
714 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
715 case SND_SOC_DAIFMT_NB_NF:
717 case SND_SOC_DAIFMT_IB_NF:
718 reg_val2 |= RT1015_TDM_INV_BCLK;
724 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
725 case SND_SOC_DAIFMT_I2S:
728 case SND_SOC_DAIFMT_LEFT_J:
729 reg_val |= RT1015_I2S_M_DF_LEFT;
732 case SND_SOC_DAIFMT_DSP_A:
733 reg_val |= RT1015_I2S_M_DF_PCM_A;
736 case SND_SOC_DAIFMT_DSP_B:
737 reg_val |= RT1015_I2S_M_DF_PCM_B;
744 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
745 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
747 snd_soc_component_update_bits(component, RT1015_TDM1_1,
748 RT1015_TDM_INV_BCLK_MASK, reg_val2);
753 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
754 int clk_id, int source, unsigned int freq, int dir)
756 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
757 unsigned int reg_val = 0;
759 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
763 case RT1015_SCLK_S_MCLK:
764 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
767 case RT1015_SCLK_S_PLL:
768 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
772 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
776 rt1015->sysclk = freq;
777 rt1015->sysclk_src = clk_id;
779 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
782 snd_soc_component_update_bits(component, RT1015_CLK2,
783 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
788 static int rt1015_set_component_pll(struct snd_soc_component *component,
789 int pll_id, int source, unsigned int freq_in,
790 unsigned int freq_out)
792 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
793 struct rl6231_pll_code pll_code;
796 if (!freq_in || !freq_out) {
797 dev_dbg(component->dev, "PLL disabled\n");
805 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
806 freq_out == rt1015->pll_out)
809 if (source == RT1015_PLL_S_BCLK) {
810 if (rt1015->bclk_ratio == 0) {
811 dev_err(component->dev,
812 "Can not support bclk ratio as 0.\n");
818 case RT1015_PLL_S_MCLK:
819 snd_soc_component_update_bits(component, RT1015_CLK2,
820 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
823 case RT1015_PLL_S_BCLK:
824 snd_soc_component_update_bits(component, RT1015_CLK2,
825 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
829 dev_err(component->dev, "Unknown PLL Source %d\n", source);
833 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
835 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
839 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
840 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
841 pll_code.n_code, pll_code.k_code);
843 snd_soc_component_write(component, RT1015_PLL1,
844 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
845 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
846 snd_soc_component_write(component, RT1015_PLL2,
849 rt1015->pll_in = freq_in;
850 rt1015->pll_out = freq_out;
851 rt1015->pll_src = source;
856 static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
858 struct snd_soc_component *component = dai->component;
859 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
861 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
863 rt1015->bclk_ratio = ratio;
866 dev_dbg(component->dev, "Unsupport bclk ratio\n");
873 static int rt1015_probe(struct snd_soc_component *component)
875 struct rt1015_priv *rt1015 =
876 snd_soc_component_get_drvdata(component);
878 rt1015->component = component;
879 rt1015->bclk_ratio = 0;
880 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c);
885 static void rt1015_remove(struct snd_soc_component *component)
887 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
889 regmap_write(rt1015->regmap, RT1015_RESET, 0);
892 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
893 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
894 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
896 static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
897 .hw_params = rt1015_hw_params,
898 .set_fmt = rt1015_set_dai_fmt,
899 .set_bclk_ratio = rt1015_set_bclk_ratio,
902 static struct snd_soc_dai_driver rt1015_dai[] = {
904 .name = "rt1015-aif",
907 .stream_name = "AIF Playback",
910 .rates = RT1015_STEREO_RATES,
911 .formats = RT1015_FORMATS,
913 .ops = &rt1015_aif_dai_ops,
918 static int rt1015_suspend(struct snd_soc_component *component)
920 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
922 regcache_cache_only(rt1015->regmap, true);
923 regcache_mark_dirty(rt1015->regmap);
928 static int rt1015_resume(struct snd_soc_component *component)
930 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
932 regcache_cache_only(rt1015->regmap, false);
933 regcache_sync(rt1015->regmap);
937 #define rt1015_suspend NULL
938 #define rt1015_resume NULL
941 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
942 .probe = rt1015_probe,
943 .remove = rt1015_remove,
944 .suspend = rt1015_suspend,
945 .resume = rt1015_resume,
946 .controls = rt1015_snd_controls,
947 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
948 .dapm_widgets = rt1015_dapm_widgets,
949 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
950 .dapm_routes = rt1015_dapm_routes,
951 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
952 .set_sysclk = rt1015_set_component_sysclk,
953 .set_pll = rt1015_set_component_pll,
954 .use_pmdown_time = 1,
956 .non_legacy_dai_naming = 1,
959 static const struct regmap_config rt1015_regmap = {
962 .max_register = RT1015_S_BST_TIMING_INTER36,
963 .volatile_reg = rt1015_volatile_register,
964 .readable_reg = rt1015_readable_register,
965 .cache_type = REGCACHE_RBTREE,
966 .reg_defaults = rt1015_reg,
967 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
970 static const struct i2c_device_id rt1015_i2c_id[] = {
974 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
976 #if defined(CONFIG_OF)
977 static const struct of_device_id rt1015_of_match[] = {
978 { .compatible = "realtek,rt1015", },
981 MODULE_DEVICE_TABLE(of, rt1015_of_match);
985 static struct acpi_device_id rt1015_acpi_match[] = {
989 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
992 static int rt1015_i2c_probe(struct i2c_client *i2c,
993 const struct i2c_device_id *id)
995 struct rt1015_priv *rt1015;
999 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv),
1004 i2c_set_clientdata(i2c, rt1015);
1006 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1007 if (IS_ERR(rt1015->regmap)) {
1008 ret = PTR_ERR(rt1015->regmap);
1009 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1014 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1015 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) {
1017 "Device with ID register %x is not rt1015\n", val);
1021 return devm_snd_soc_register_component(&i2c->dev,
1022 &soc_component_dev_rt1015,
1023 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1026 static void rt1015_i2c_shutdown(struct i2c_client *client)
1028 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1030 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1033 static struct i2c_driver rt1015_i2c_driver = {
1036 .of_match_table = of_match_ptr(rt1015_of_match),
1037 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1039 .probe = rt1015_i2c_probe,
1040 .shutdown = rt1015_i2c_shutdown,
1041 .id_table = rt1015_i2c_id,
1043 module_i2c_driver(rt1015_i2c_driver);
1045 MODULE_DESCRIPTION("ASoC RT1015 driver");
1046 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1047 MODULE_LICENSE("GPL v2");