sound/soc/codecs/max98373-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2020, Maxim Integrated
   3
   4 #include <linux/acpi.h>
   5 #include <linux/delay.h>
   6 #include <linux/module.h>
   7 #include <linux/mod_devicetable.h>
   8 #include <linux/pm_runtime.h>
   9 #include <linux/regmap.h>
  10 #include <linux/slab.h>
  11 #include <sound/pcm.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc.h>
  14 #include <sound/tlv.h>
  15 #include <linux/of.h>
  16 #include <linux/soundwire/sdw.h>
  17 #include <linux/soundwire/sdw_type.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include "max98373.h"
  20 #include "max98373-sdw.h"
  21
  22 struct sdw_stream_data {
  23         struct sdw_stream_runtime *sdw_stream;
  24 };
  25
  26 static const u32 max98373_sdw_cache_reg[] = {
  27         MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
  28         MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
  29         MAX98373_R20B6_BDE_CUR_STATE_READBACK,
  30 };
  31
  32 static struct reg_default max98373_reg[] = {
  33         {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
  34         {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
  35         {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
  36         {MAX98373_R0044_SCP_CTRL, 0x00},
  37         {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
  38         {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
  39         {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
  40         {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
  41         {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
  42         {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
  43         {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
  44         {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
  45         {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
  46         {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
  47         {MAX98373_R0100_DP1_INIT_STAT, 0x00},
  48         {MAX98373_R0101_DP1_INIT_MASK, 0x00},
  49         {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
  50         {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
  51         {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
  52         {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
  53         {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
  54         {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
  55         {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
  56         {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
  57         {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
  58         {MAX98373_R0126_DP1_HCTRL, 0x00},
  59         {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
  60         {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
  61         {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
  62         {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
  63         {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
  64         {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
  65         {MAX98373_R0136_DP1_HCTRL, 0x0136},
  66         {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
  67         {MAX98373_R0300_DP3_INIT_STAT, 0x00},
  68         {MAX98373_R0301_DP3_INIT_MASK, 0x00},
  69         {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
  70         {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
  71         {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
  72         {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
  73         {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
  74         {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
  75         {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
  76         {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
  77         {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
  78         {MAX98373_R0326_DP3_HCTRL, 0x00},
  79         {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
  80         {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
  81         {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
  82         {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
  83         {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
  84         {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
  85         {MAX98373_R0336_DP3_HCTRL, 0x00},
  86         {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
  87         {MAX98373_R2000_SW_RESET, 0x00},
  88         {MAX98373_R2001_INT_RAW1, 0x00},
  89         {MAX98373_R2002_INT_RAW2, 0x00},
  90         {MAX98373_R2003_INT_RAW3, 0x00},
  91         {MAX98373_R2004_INT_STATE1, 0x00},
  92         {MAX98373_R2005_INT_STATE2, 0x00},
  93         {MAX98373_R2006_INT_STATE3, 0x00},
  94         {MAX98373_R2007_INT_FLAG1, 0x00},
  95         {MAX98373_R2008_INT_FLAG2, 0x00},
  96         {MAX98373_R2009_INT_FLAG3, 0x00},
  97         {MAX98373_R200A_INT_EN1, 0x00},
  98         {MAX98373_R200B_INT_EN2, 0x00},
  99         {MAX98373_R200C_INT_EN3, 0x00},
 100         {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
 101         {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
 102         {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
 103         {MAX98373_R2010_IRQ_CTRL, 0x00},
 104         {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
 105         {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
 106         {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
 107         {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
 108         {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
 109         {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
 110         {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
 111         {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
 112         {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
 113         {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
 114         {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
 115         {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
 116         {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
 117         {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
 118         {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
 119         {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
 120         {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
 121         {MAX98373_R202B_PCM_RX_EN, 0x00},
 122         {MAX98373_R202C_PCM_TX_EN, 0x00},
 123         {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
 124         {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
 125         {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
 126         {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
 127         {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
 128         {MAX98373_R2034_ICC_TX_CNTL, 0x00},
 129         {MAX98373_R2035_ICC_TX_EN, 0x00},
 130         {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
 131         {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
 132         {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
 133         {MAX98373_R203F_AMP_DSP_CFG, 0x02},
 134         {MAX98373_R2040_TONE_GEN_CFG, 0x00},
 135         {MAX98373_R2041_AMP_CFG, 0x03},
 136         {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
 137         {MAX98373_R2043_AMP_EN, 0x00},
 138         {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
 139         {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
 140         {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
 141         {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
 142         {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
 143         {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
 144         {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
 145         {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
 146         {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
 147         {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
 148         {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
 149         {MAX98373_R2097_BDE_L1_THRESH, 0x00},
 150         {MAX98373_R2098_BDE_L2_THRESH, 0x00},
 151         {MAX98373_R2099_BDE_L3_THRESH, 0x00},
 152         {MAX98373_R209A_BDE_L4_THRESH, 0x00},
 153         {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
 154         {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
 155         {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
 156         {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
 157         {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
 158         {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
 159         {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
 160         {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
 161         {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
 162         {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
 163         {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
 164         {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
 165         {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
 166         {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
 167         {MAX98373_R20B5_BDE_EN, 0x00},
 168         {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
 169         {MAX98373_R20D1_DHT_CFG, 0x01},
 170         {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
 171         {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
 172         {MAX98373_R20D4_DHT_EN, 0x00},
 173         {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
 174         {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
 175         {MAX98373_R20E2_LIMITER_EN, 0x00},
 176         {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
 177         {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
 178         {MAX98373_R21FF_REV_ID, 0x42},
 179 };
 180
 181 static bool max98373_readable_register(struct device *dev, unsigned int reg)
 182 {
 183         switch (reg) {
 184         case MAX98373_R21FF_REV_ID:
 185         case MAX98373_R2010_IRQ_CTRL:
 186         /* SoundWire Control Port Registers */
 187         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 188         /* Soundwire Data Port 1 Registers */
 189         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 190         /* Soundwire Data Port 3 Registers */
 191         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 192         case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
 193         case MAX98373_R2014_THERM_WARN_THRESH
 194                 ... MAX98373_R2018_THERM_FOLDBACK_EN:
 195         case MAX98373_R201E_PIN_DRIVE_STRENGTH
 196                 ... MAX98373_R2036_SOUNDWIRE_CTRL:
 197         case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
 198         case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
 199                 ... MAX98373_R2047_IV_SENSE_ADC_EN:
 200         case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
 201                 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
 202         case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
 203         case MAX98373_R2097_BDE_L1_THRESH
 204                 ... MAX98373_R209B_BDE_THRESH_HYST:
 205         case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
 206         case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 207         case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
 208         case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
 209         case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
 210                 ... MAX98373_R20FF_GLOBAL_SHDN:
 211                 return true;
 212         default:
 213                 return false;
 214         }
 215 };
 216
 217 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
 218 {
 219         switch (reg) {
 220         case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
 221         case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
 222         case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 223         case MAX98373_R21FF_REV_ID:
 224         /* SoundWire Control Port Registers */
 225         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 226         /* Soundwire Data Port 1 Registers */
 227         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 228         /* Soundwire Data Port 3 Registers */
 229         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 230         case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
 231                 return true;
 232         default:
 233                 return false;
 234         }
 235 }
 236
 237 static const struct regmap_config max98373_sdw_regmap = {
 238         .reg_bits = 32,
 239         .val_bits = 8,
 240         .max_register = MAX98373_R21FF_REV_ID,
 241         .reg_defaults  = max98373_reg,
 242         .num_reg_defaults = ARRAY_SIZE(max98373_reg),
 243         .readable_reg = max98373_readable_register,
 244         .volatile_reg = max98373_volatile_reg,
 245         .cache_type = REGCACHE_RBTREE,
 246         .use_single_read = true,
 247         .use_single_write = true,
 248 };
 249
 250 /* Power management functions and structure */
 251 static __maybe_unused int max98373_suspend(struct device *dev)
 252 {
 253         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 254         int i;
 255
 256         /* cache feedback register values before suspend */
 257         for (i = 0; i < max98373->cache_num; i++)
 258                 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
 259
 260         regcache_cache_only(max98373->regmap, true);
 261
 262         return 0;
 263 }
 264
 265 static __maybe_unused int max98373_resume(struct device *dev)
 266 {
 267         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 268         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 269         unsigned long time;
 270
 271         if (!max98373->hw_init)
 272                 return 0;
 273
 274         if (!slave->unattach_request)
 275                 goto regmap_sync;
 276
 277         time = wait_for_completion_timeout(&slave->initialization_complete,
 278                                            msecs_to_jiffies(2000));
 279         if (!time) {
 280                 dev_err(dev, "Initialization not complete, timed out\n");
 281                 return -ETIMEDOUT;
 282         }
 283
 284 regmap_sync:
 285         slave->unattach_request = 0;
 286         regcache_cache_only(max98373->regmap, false);
 287         regcache_sync(max98373->regmap);
 288
 289         return 0;
 290 }
 291
 292 static const struct dev_pm_ops max98373_pm = {
 293         SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
 294         SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
 295 };
 296
 297 static int max98373_read_prop(struct sdw_slave *slave)
 298 {
 299         struct sdw_slave_prop *prop = &slave->prop;
 300         int nval, i;
 301         u32 bit;
 302         unsigned long addr;
 303         struct sdw_dpn_prop *dpn;
 304
 305         prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
 306
 307         /* BITMAP: 00001000  Dataport 3 is active */
 308         prop->source_ports = BIT(3);
 309         /* BITMAP: 00000010  Dataport 1 is active */
 310         prop->sink_ports = BIT(1);
 311         prop->paging_support = true;
 312         prop->clk_stop_timeout = 20;
 313
 314         nval = hweight32(prop->source_ports);
 315         prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
 316                                           sizeof(*prop->src_dpn_prop),
 317                                           GFP_KERNEL);
 318         if (!prop->src_dpn_prop)
 319                 return -ENOMEM;
 320
 321         i = 0;
 322         dpn = prop->src_dpn_prop;
 323         addr = prop->source_ports;
 324         for_each_set_bit(bit, &addr, 32) {
 325                 dpn[i].num = bit;
 326                 dpn[i].type = SDW_DPN_FULL;
 327                 dpn[i].simple_ch_prep_sm = true;
 328                 dpn[i].ch_prep_timeout = 10;
 329                 i++;
 330         }
 331
 332         /* do this again for sink now */
 333         nval = hweight32(prop->sink_ports);
 334         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 335                                            sizeof(*prop->sink_dpn_prop),
 336                                            GFP_KERNEL);
 337         if (!prop->sink_dpn_prop)
 338                 return -ENOMEM;
 339
 340         i = 0;
 341         dpn = prop->sink_dpn_prop;
 342         addr = prop->sink_ports;
 343         for_each_set_bit(bit, &addr, 32) {
 344                 dpn[i].num = bit;
 345                 dpn[i].type = SDW_DPN_FULL;
 346                 dpn[i].simple_ch_prep_sm = true;
 347                 dpn[i].ch_prep_timeout = 10;
 348                 i++;
 349         }
 350
 351         /* set the timeout values */
 352         prop->clk_stop_timeout = 20;
 353
 354         return 0;
 355 }
 356
 357 static int max98373_io_init(struct sdw_slave *slave)
 358 {
 359         struct device *dev = &slave->dev;
 360         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 361
 362         if (max98373->pm_init_once) {
 363                 regcache_cache_only(max98373->regmap, false);
 364                 regcache_cache_bypass(max98373->regmap, true);
 365         }
 366
 367         /*
 368          * PM runtime is only enabled when a Slave reports as Attached
 369          */
 370         if (!max98373->pm_init_once) {
 371                 /* set autosuspend parameters */
 372                 pm_runtime_set_autosuspend_delay(dev, 3000);
 373                 pm_runtime_use_autosuspend(dev);
 374
 375                 /* update count of parent 'active' children */
 376                 pm_runtime_set_active(dev);
 377
 378                 /* make sure the device does not suspend immediately */
 379                 pm_runtime_mark_last_busy(dev);
 380
 381                 pm_runtime_enable(dev);
 382         }
 383
 384         pm_runtime_get_noresume(dev);
 385
 386         /* Software Reset */
 387         max98373_reset(max98373, dev);
 388
 389         /* Set soundwire mode */
 390         regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
 391         /* Enable ADC */
 392         regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
 393         /* Set default Soundwire clock */
 394         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
 395         /* Set default sampling rate for speaker and IVDAC */
 396         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 397         /* IV default slot configuration */
 398         regmap_write(max98373->regmap,
 399                      MAX98373_R2020_PCM_TX_HIZ_EN_1,
 400                      0xFF);
 401         regmap_write(max98373->regmap,
 402                      MAX98373_R2021_PCM_TX_HIZ_EN_2,
 403                      0xFF);
 404         /* L/R mix configuration */
 405         regmap_write(max98373->regmap,
 406                      MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 407                      0x80);
 408         regmap_write(max98373->regmap,
 409                      MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 410                      0x1);
 411         /* Enable DC blocker */
 412         regmap_write(max98373->regmap,
 413                      MAX98373_R203F_AMP_DSP_CFG,
 414                      0x3);
 415         /* Enable IMON VMON DC blocker */
 416         regmap_write(max98373->regmap,
 417                      MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
 418                      0x7);
 419         /* voltage, current slot configuration */
 420         regmap_write(max98373->regmap,
 421                      MAX98373_R2022_PCM_TX_SRC_1,
 422                      (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
 423                      max98373->v_slot) & 0xFF);
 424         if (max98373->v_slot < 8)
 425                 regmap_update_bits(max98373->regmap,
 426                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 427                                    1 << max98373->v_slot, 0);
 428         else
 429                 regmap_update_bits(max98373->regmap,
 430                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 431                                    1 << (max98373->v_slot - 8), 0);
 432
 433         if (max98373->i_slot < 8)
 434                 regmap_update_bits(max98373->regmap,
 435                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 436                                    1 << max98373->i_slot, 0);
 437         else
 438                 regmap_update_bits(max98373->regmap,
 439                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 440                                    1 << (max98373->i_slot - 8), 0);
 441
 442         /* speaker feedback slot configuration */
 443         regmap_write(max98373->regmap,
 444                      MAX98373_R2023_PCM_TX_SRC_2,
 445                      max98373->spkfb_slot & 0xFF);
 446
 447         /* Set interleave mode */
 448         if (max98373->interleave_mode)
 449                 regmap_update_bits(max98373->regmap,
 450                                    MAX98373_R2024_PCM_DATA_FMT_CFG,
 451                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
 452                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
 453
 454         /* Speaker enable */
 455         regmap_update_bits(max98373->regmap,
 456                            MAX98373_R2043_AMP_EN,
 457                            MAX98373_SPK_EN_MASK, 1);
 458
 459         regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
 460         regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
 461
 462         if (max98373->pm_init_once) {
 463                 regcache_cache_bypass(max98373->regmap, false);
 464                 regcache_mark_dirty(max98373->regmap);
 465         }
 466
 467         max98373->pm_init_once = true;
 468         max98373->hw_init = true;
 469
 470         pm_runtime_mark_last_busy(dev);
 471         pm_runtime_put_autosuspend(dev);
 472
 473         return 0;
 474 }
 475
 476 static int max98373_clock_calculate(struct sdw_slave *slave,
 477                                     unsigned int clk_freq)
 478 {
 479         int x, y;
 480         static const int max98373_clk_family[] = {
 481                 7680000, 8400000, 9600000, 11289600,
 482                 12000000, 12288000, 13000000
 483         };
 484
 485         for (x = 0; x < 4; x++)
 486                 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
 487                         if (clk_freq == (max98373_clk_family[y] >> x))
 488                                 return (x << 3) + y;
 489
 490         /* Set default clock (12.288 Mhz) if the value is not in the list */
 491         dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
 492                 clk_freq);
 493         return 0x5;
 494 }
 495
 496 static int max98373_clock_config(struct sdw_slave *slave,
 497                                  struct sdw_bus_params *params)
 498 {
 499         struct device *dev = &slave->dev;
 500         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 501         unsigned int clk_freq, value;
 502
 503         clk_freq = (params->curr_dr_freq >> 1);
 504
 505         /*
 506          *      Select the proper value for the register based on the
 507          *      requested clock. If the value is not in the list,
 508          *      use reasonable default - 12.288 Mhz
 509          */
 510         value = max98373_clock_calculate(slave, clk_freq);
 511
 512         /* SWCLK */
 513         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
 514
 515         /* The default Sampling Rate value for IV is 48KHz*/
 516         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 517
 518         return 0;
 519 }
 520
 521 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
 522 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
 523
 524 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
 525                                       struct snd_pcm_hw_params *params,
 526                                       struct snd_soc_dai *dai)
 527 {
 528         struct snd_soc_component *component = dai->component;
 529         struct max98373_priv *max98373 =
 530                 snd_soc_component_get_drvdata(component);
 531
 532         struct sdw_stream_config stream_config;
 533         struct sdw_port_config port_config;
 534         enum sdw_data_direction direction;
 535         struct sdw_stream_data *stream;
 536         int ret, chan_sz, sampling_rate;
 537
 538         stream = snd_soc_dai_get_dma_data(dai, substream);
 539
 540         if (!stream)
 541                 return -EINVAL;
 542
 543         if (!max98373->slave)
 544                 return -EINVAL;
 545
 546         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 547                 direction = SDW_DATA_DIR_RX;
 548                 port_config.num = 1;
 549         } else {
 550                 direction = SDW_DATA_DIR_TX;
 551                 port_config.num = 3;
 552         }
 553
 554         stream_config.frame_rate = params_rate(params);
 555         stream_config.bps = snd_pcm_format_width(params_format(params));
 556         stream_config.direction = direction;
 557
 558         if (max98373->slot && direction == SDW_DATA_DIR_RX) {
 559                 stream_config.ch_count = max98373->slot;
 560                 port_config.ch_mask = max98373->rx_mask;
 561         } else {
 562                 /* only IV are supported by capture */
 563                 if (direction == SDW_DATA_DIR_TX)
 564                         stream_config.ch_count = 2;
 565                 else
 566                         stream_config.ch_count = params_channels(params);
 567
 568                 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
 569         }
 570
 571         ret = sdw_stream_add_slave(max98373->slave, &stream_config,
 572                                    &port_config, 1, stream->sdw_stream);
 573         if (ret) {
 574                 dev_err(dai->dev, "Unable to configure port\n");
 575                 return ret;
 576         }
 577
 578         if (params_channels(params) > 16) {
 579                 dev_err(component->dev, "Unsupported channels %d\n",
 580                         params_channels(params));
 581                 return -EINVAL;
 582         }
 583
 584         /* Channel size configuration */
 585         switch (snd_pcm_format_width(params_format(params))) {
 586         case 16:
 587                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 588                 break;
 589         case 24:
 590                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 591                 break;
 592         case 32:
 593                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 594                 break;
 595         default:
 596                 dev_err(component->dev, "Channel size unsupported %d\n",
 597                         params_format(params));
 598                 return -EINVAL;
 599         }
 600
 601         max98373->ch_size = snd_pcm_format_width(params_format(params));
 602
 603         regmap_update_bits(max98373->regmap,
 604                            MAX98373_R2024_PCM_DATA_FMT_CFG,
 605                            MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 606
 607         dev_dbg(component->dev, "Format supported %d", params_format(params));
 608
 609         /* Sampling rate configuration */
 610         switch (params_rate(params)) {
 611         case 8000:
 612                 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
 613                 break;
 614         case 11025:
 615                 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
 616                 break;
 617         case 12000:
 618                 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
 619                 break;
 620         case 16000:
 621                 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
 622                 break;
 623         case 22050:
 624                 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
 625                 break;
 626         case 24000:
 627                 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
 628                 break;
 629         case 32000:
 630                 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
 631                 break;
 632         case 44100:
 633                 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
 634                 break;
 635         case 48000:
 636                 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
 637                 break;
 638         case 88200:
 639                 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
 640                 break;
 641         case 96000:
 642                 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
 643                 break;
 644         default:
 645                 dev_err(component->dev, "Rate %d is not supported\n",
 646                         params_rate(params));
 647                 return -EINVAL;
 648         }
 649
 650         /* set correct sampling frequency */
 651         regmap_update_bits(max98373->regmap,
 652                            MAX98373_R2028_PCM_SR_SETUP_2,
 653                            MAX98373_PCM_SR_SET2_SR_MASK,
 654                            sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
 655
 656         /* set sampling rate of IV */
 657         regmap_update_bits(max98373->regmap,
 658                            MAX98373_R2028_PCM_SR_SETUP_2,
 659                            MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 660                            sampling_rate);
 661
 662         return 0;
 663 }
 664
 665 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
 666                                 struct snd_soc_dai *dai)
 667 {
 668         struct snd_soc_component *component = dai->component;
 669         struct max98373_priv *max98373 =
 670                 snd_soc_component_get_drvdata(component);
 671         struct sdw_stream_data *stream =
 672                 snd_soc_dai_get_dma_data(dai, substream);
 673
 674         if (!max98373->slave)
 675                 return -EINVAL;
 676
 677         sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
 678         return 0;
 679 }
 680
 681 static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
 682                                    void *sdw_stream, int direction)
 683 {
 684         struct sdw_stream_data *stream;
 685
 686         if (!sdw_stream)
 687                 return 0;
 688
 689         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 690         if (!stream)
 691                 return -ENOMEM;
 692
 693         stream->sdw_stream = sdw_stream;
 694
 695         /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
 696         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 697                 dai->playback_dma_data = stream;
 698         else
 699                 dai->capture_dma_data = stream;
 700
 701         return 0;
 702 }
 703
 704 static void max98373_shutdown(struct snd_pcm_substream *substream,
 705                               struct snd_soc_dai *dai)
 706 {
 707         struct sdw_stream_data *stream;
 708
 709         stream = snd_soc_dai_get_dma_data(dai, substream);
 710         snd_soc_dai_set_dma_data(dai, substream, NULL);
 711         kfree(stream);
 712 }
 713
 714 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
 715                                      unsigned int tx_mask,
 716                                      unsigned int rx_mask,
 717                                      int slots, int slot_width)
 718 {
 719         struct snd_soc_component *component = dai->component;
 720         struct max98373_priv *max98373 =
 721                 snd_soc_component_get_drvdata(component);
 722
 723         /* tx_mask is unused since it's irrelevant for I/V feedback */
 724         if (tx_mask)
 725                 return -EINVAL;
 726
 727         if (!rx_mask && !slots && !slot_width)
 728                 max98373->tdm_mode = false;
 729         else
 730                 max98373->tdm_mode = true;
 731
 732         max98373->rx_mask = rx_mask;
 733         max98373->slot = slots;
 734
 735         return 0;
 736 }
 737
 738 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
 739         .hw_params = max98373_sdw_dai_hw_params,
 740         .hw_free = max98373_pcm_hw_free,
 741         .set_sdw_stream = max98373_set_sdw_stream,
 742         .shutdown = max98373_shutdown,
 743         .set_tdm_slot = max98373_sdw_set_tdm_slot,
 744 };
 745
 746 static struct snd_soc_dai_driver max98373_sdw_dai[] = {
 747         {
 748                 .name = "max98373-aif1",
 749                 .playback = {
 750                         .stream_name = "HiFi Playback",
 751                         .channels_min = 1,
 752                         .channels_max = 2,
 753                         .rates = MAX98373_RATES,
 754                         .formats = MAX98373_FORMATS,
 755                 },
 756                 .capture = {
 757                         .stream_name = "HiFi Capture",
 758                         .channels_min = 1,
 759                         .channels_max = 2,
 760                         .rates = MAX98373_RATES,
 761                         .formats = MAX98373_FORMATS,
 762                 },
 763                 .ops = &max98373_dai_sdw_ops,
 764         }
 765 };
 766
 767 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
 768 {
 769         struct max98373_priv *max98373;
 770         int ret;
 771         int i;
 772         struct device *dev = &slave->dev;
 773
 774         /*  Allocate and assign private driver data structure  */
 775         max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
 776         if (!max98373)
 777                 return -ENOMEM;
 778
 779         dev_set_drvdata(dev, max98373);
 780         max98373->regmap = regmap;
 781         max98373->slave = slave;
 782
 783         max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg);
 784         max98373->cache = devm_kcalloc(dev, max98373->cache_num,
 785                                        sizeof(*max98373->cache),
 786                                        GFP_KERNEL);
 787
 788         for (i = 0; i < max98373->cache_num; i++)
 789                 max98373->cache[i].reg = max98373_sdw_cache_reg[i];
 790
 791         /* Read voltage and slot configuration */
 792         max98373_slot_config(dev, max98373);
 793
 794         max98373->hw_init = false;
 795         max98373->pm_init_once = false;
 796
 797         /* codec registration  */
 798         ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
 799                                               max98373_sdw_dai,
 800                                               ARRAY_SIZE(max98373_sdw_dai));
 801         if (ret < 0)
 802                 dev_err(dev, "Failed to register codec: %d\n", ret);
 803
 804         return ret;
 805 }
 806
 807 static int max98373_update_status(struct sdw_slave *slave,
 808                                   enum sdw_slave_status status)
 809 {
 810         struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
 811
 812         if (status == SDW_SLAVE_UNATTACHED)
 813                 max98373->hw_init = false;
 814
 815         /*
 816          * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
 817          */
 818         if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
 819                 return 0;
 820
 821         /* perform I/O transfers required for Slave initialization */
 822         return max98373_io_init(slave);
 823 }
 824
 825 static int max98373_bus_config(struct sdw_slave *slave,
 826                                struct sdw_bus_params *params)
 827 {
 828         int ret;
 829
 830         ret = max98373_clock_config(slave, params);
 831         if (ret < 0)
 832                 dev_err(&slave->dev, "Invalid clk config");
 833
 834         return ret;
 835 }
 836
 837 /*
 838  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
 839  * port_prep are not defined for now
 840  */
 841 static struct sdw_slave_ops max98373_slave_ops = {
 842         .read_prop = max98373_read_prop,
 843         .update_status = max98373_update_status,
 844         .bus_config = max98373_bus_config,
 845 };
 846
 847 static int max98373_sdw_probe(struct sdw_slave *slave,
 848                               const struct sdw_device_id *id)
 849 {
 850         struct regmap *regmap;
 851
 852         /* Regmap Initialization */
 853         regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
 854         if (IS_ERR(regmap))
 855                 return PTR_ERR(regmap);
 856
 857         return max98373_init(slave, regmap);
 858 }
 859
 860 #if defined(CONFIG_OF)
 861 static const struct of_device_id max98373_of_match[] = {
 862         { .compatible = "maxim,max98373", },
 863         {},
 864 };
 865 MODULE_DEVICE_TABLE(of, max98373_of_match);
 866 #endif
 867
 868 #ifdef CONFIG_ACPI
 869 static const struct acpi_device_id max98373_acpi_match[] = {
 870         { "MX98373", 0 },
 871         {},
 872 };
 873 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
 874 #endif
 875
 876 static const struct sdw_device_id max98373_id[] = {
 877         SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
 878         {},
 879 };
 880 MODULE_DEVICE_TABLE(sdw, max98373_id);
 881
 882 static struct sdw_driver max98373_sdw_driver = {
 883         .driver = {
 884                 .name = "max98373",
 885                 .owner = THIS_MODULE,
 886                 .of_match_table = of_match_ptr(max98373_of_match),
 887                 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
 888                 .pm = &max98373_pm,
 889         },
 890         .probe = max98373_sdw_probe,
 891         .remove = NULL,
 892         .ops = &max98373_slave_ops,
 893         .id_table = max98373_id,
 894 };
 895
 896 module_sdw_driver(max98373_sdw_driver);
 897
 898 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
 899 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
 900 MODULE_LICENSE("GPL v2");