1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
5 #include <linux/clk-provider.h>
6 #include <linux/init.h>
8 #include <linux/module.h>
9 #include <linux/of_clk.h>
10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/regulator/consumer.h>
14 #include <sound/soc.h>
15 #include <sound/soc-dapm.h>
16 #include <sound/tlv.h>
18 /* VA macro registers */
19 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
20 #define CDC_VA_MCLK_CONTROL_EN BIT(0)
21 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
22 #define CDC_VA_FS_CONTROL_EN BIT(0)
23 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008)
24 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080)
25 #define CDC_VA_FS_BROADCAST_EN BIT(1)
26 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084)
27 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088)
28 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C)
29 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090)
30 #define CDC_VA_DMIC_EN_MASK BIT(0)
31 #define CDC_VA_DMIC_ENABLE BIT(0)
32 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1)
33 #define CDC_VA_DMIC_CLK_SEL_SHFT 1
34 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0
35 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2
36 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4
37 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6
38 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8
39 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa
40 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094)
41 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7)
42 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7)
43 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0
44 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3)
45 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3)
46 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2)
47 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2)
48 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1)
49 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1)
50 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0)
51 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0)
52 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0
53 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C)
54 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0)
55 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4)
56 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8)
57 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC)
58 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0)
59 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4)
60 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8)
61 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC)
62 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0)
63 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4)
64 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8)
65 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC)
66 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100)
67 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104)
68 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108)
69 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C)
70 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110)
71 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114)
72 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118)
73 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C)
74 #define CDC_VA_TX0_TX_PATH_CTL (0x0400)
75 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5)
76 #define CDC_VA_TX_PATH_CLK_EN BIT(5)
77 #define CDC_VA_TX_PATH_CLK_DISABLE 0
78 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4)
79 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4)
80 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0
81 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404)
82 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1)
83 #define CDC_VA_ADC_MODE_SHIFT 1
84 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5)
85 #define CF_MIN_3DB_4HZ 0x0
86 #define CF_MIN_3DB_75HZ 0x1
87 #define CF_MIN_3DB_150HZ 0x2
88 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408)
89 #define CDC_VA_TX0_TX_VOL_CTL (0x040C)
90 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410)
91 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414)
92 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418)
93 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1)
94 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1)
95 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0)
96 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0)
97 #define CDC_VA_TX_HPF_ZERO_GATE 0
98 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C)
99 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420)
100 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424)
101 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428)
102 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C)
103 #define CDC_VA_TX1_TX_PATH_CTL (0x0480)
104 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484)
105 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488)
106 #define CDC_VA_TX1_TX_VOL_CTL (0x048C)
107 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490)
108 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494)
109 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498)
110 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C)
111 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0)
112 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4)
113 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8)
114 #define CDC_VA_TX2_TX_PATH_CTL (0x0500)
115 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504)
116 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508)
117 #define CDC_VA_TX2_TX_VOL_CTL (0x050C)
118 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510)
119 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514)
120 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518)
121 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C)
122 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520)
123 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524)
124 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528)
125 #define CDC_VA_TX3_TX_PATH_CTL (0x0580)
126 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584)
127 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7)
128 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7)
129 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0
130 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588)
131 #define CDC_VA_TX3_TX_VOL_CTL (0x058C)
132 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590)
133 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594)
134 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598)
135 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C)
136 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0)
137 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4)
138 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8)
140 #define VA_MAX_OFFSET (0x07A8)
142 #define VA_MACRO_NUM_DECIMATORS 4
143 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
144 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
145 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
146 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
147 SNDRV_PCM_FMTBIT_S24_LE |\
148 SNDRV_PCM_FMTBIT_S24_3LE)
150 #define VA_MACRO_MCLK_FREQ 9600000
151 #define VA_MACRO_TX_PATH_OFFSET 0x80
152 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
153 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
155 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
158 VA_MACRO_AIF_INVALID = 0,
186 #define VA_NUM_CLKS_MAX 3
190 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
191 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
194 int dec_mode[VA_MACRO_NUM_DECIMATORS];
195 struct regmap *regmap;
196 struct clk_bulk_data clks[VA_NUM_CLKS_MAX];
199 s32 dmic_0_1_clk_cnt;
200 s32 dmic_2_3_clk_cnt;
201 s32 dmic_4_5_clk_cnt;
202 s32 dmic_6_7_clk_cnt;
209 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
211 static bool va_is_volatile_register(struct device *dev, unsigned int reg)
214 case CDC_VA_TOP_CSR_CORE_ID_0:
215 case CDC_VA_TOP_CSR_CORE_ID_1:
216 case CDC_VA_TOP_CSR_CORE_ID_2:
217 case CDC_VA_TOP_CSR_CORE_ID_3:
218 case CDC_VA_TOP_CSR_DMIC0_CTL:
219 case CDC_VA_TOP_CSR_DMIC1_CTL:
220 case CDC_VA_TOP_CSR_DMIC2_CTL:
221 case CDC_VA_TOP_CSR_DMIC3_CTL:
227 static const struct reg_default va_defaults[] = {
229 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
230 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
231 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
232 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
233 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
234 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
235 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
236 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
237 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
238 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
239 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
240 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
241 { CDC_VA_TOP_CSR_I2S_CLK, 0x00},
242 { CDC_VA_TOP_CSR_I2S_RESET, 0x00},
243 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
244 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
245 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
246 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
247 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
248 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
249 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
250 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
253 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
254 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
255 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
256 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
257 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
258 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
259 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
260 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
261 { CDC_VA_TX0_TX_PATH_CTL, 0x04},
262 { CDC_VA_TX0_TX_PATH_CFG0, 0x10},
263 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
264 { CDC_VA_TX0_TX_VOL_CTL, 0x00},
265 { CDC_VA_TX0_TX_PATH_SEC0, 0x00},
266 { CDC_VA_TX0_TX_PATH_SEC1, 0x00},
267 { CDC_VA_TX0_TX_PATH_SEC2, 0x01},
268 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
269 { CDC_VA_TX0_TX_PATH_SEC4, 0x20},
270 { CDC_VA_TX0_TX_PATH_SEC5, 0x00},
271 { CDC_VA_TX0_TX_PATH_SEC6, 0x00},
272 { CDC_VA_TX0_TX_PATH_SEC7, 0x25},
273 { CDC_VA_TX1_TX_PATH_CTL, 0x04},
274 { CDC_VA_TX1_TX_PATH_CFG0, 0x10},
275 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
276 { CDC_VA_TX1_TX_VOL_CTL, 0x00},
277 { CDC_VA_TX1_TX_PATH_SEC0, 0x00},
278 { CDC_VA_TX1_TX_PATH_SEC1, 0x00},
279 { CDC_VA_TX1_TX_PATH_SEC2, 0x01},
280 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
281 { CDC_VA_TX1_TX_PATH_SEC4, 0x20},
282 { CDC_VA_TX1_TX_PATH_SEC5, 0x00},
283 { CDC_VA_TX1_TX_PATH_SEC6, 0x00},
284 { CDC_VA_TX2_TX_PATH_CTL, 0x04},
285 { CDC_VA_TX2_TX_PATH_CFG0, 0x10},
286 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
287 { CDC_VA_TX2_TX_VOL_CTL, 0x00},
288 { CDC_VA_TX2_TX_PATH_SEC0, 0x00},
289 { CDC_VA_TX2_TX_PATH_SEC1, 0x00},
290 { CDC_VA_TX2_TX_PATH_SEC2, 0x01},
291 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
292 { CDC_VA_TX2_TX_PATH_SEC4, 0x20},
293 { CDC_VA_TX2_TX_PATH_SEC5, 0x00},
294 { CDC_VA_TX2_TX_PATH_SEC6, 0x00},
295 { CDC_VA_TX3_TX_PATH_CTL, 0x04},
296 { CDC_VA_TX3_TX_PATH_CFG0, 0x10},
297 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
298 { CDC_VA_TX3_TX_VOL_CTL, 0x00},
299 { CDC_VA_TX3_TX_PATH_SEC0, 0x00},
300 { CDC_VA_TX3_TX_PATH_SEC1, 0x00},
301 { CDC_VA_TX3_TX_PATH_SEC2, 0x01},
302 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
303 { CDC_VA_TX3_TX_PATH_SEC4, 0x20},
304 { CDC_VA_TX3_TX_PATH_SEC5, 0x00},
305 { CDC_VA_TX3_TX_PATH_SEC6, 0x00},
308 static bool va_is_rw_register(struct device *dev, unsigned int reg)
311 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL:
312 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL:
313 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL:
314 case CDC_VA_TOP_CSR_TOP_CFG0:
315 case CDC_VA_TOP_CSR_DMIC0_CTL:
316 case CDC_VA_TOP_CSR_DMIC1_CTL:
317 case CDC_VA_TOP_CSR_DMIC2_CTL:
318 case CDC_VA_TOP_CSR_DMIC3_CTL:
319 case CDC_VA_TOP_CSR_DMIC_CFG:
320 case CDC_VA_TOP_CSR_DEBUG_BUS:
321 case CDC_VA_TOP_CSR_DEBUG_EN:
322 case CDC_VA_TOP_CSR_TX_I2S_CTL:
323 case CDC_VA_TOP_CSR_I2S_CLK:
324 case CDC_VA_TOP_CSR_I2S_RESET:
325 case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
326 case CDC_VA_INP_MUX_ADC_MUX0_CFG1:
327 case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
328 case CDC_VA_INP_MUX_ADC_MUX1_CFG1:
329 case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
330 case CDC_VA_INP_MUX_ADC_MUX2_CFG1:
331 case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
332 case CDC_VA_INP_MUX_ADC_MUX3_CFG1:
333 case CDC_VA_TX0_TX_PATH_CTL:
334 case CDC_VA_TX0_TX_PATH_CFG0:
335 case CDC_VA_TX0_TX_PATH_CFG1:
336 case CDC_VA_TX0_TX_VOL_CTL:
337 case CDC_VA_TX0_TX_PATH_SEC0:
338 case CDC_VA_TX0_TX_PATH_SEC1:
339 case CDC_VA_TX0_TX_PATH_SEC2:
340 case CDC_VA_TX0_TX_PATH_SEC3:
341 case CDC_VA_TX0_TX_PATH_SEC4:
342 case CDC_VA_TX0_TX_PATH_SEC5:
343 case CDC_VA_TX0_TX_PATH_SEC6:
344 case CDC_VA_TX0_TX_PATH_SEC7:
345 case CDC_VA_TX1_TX_PATH_CTL:
346 case CDC_VA_TX1_TX_PATH_CFG0:
347 case CDC_VA_TX1_TX_PATH_CFG1:
348 case CDC_VA_TX1_TX_VOL_CTL:
349 case CDC_VA_TX1_TX_PATH_SEC0:
350 case CDC_VA_TX1_TX_PATH_SEC1:
351 case CDC_VA_TX1_TX_PATH_SEC2:
352 case CDC_VA_TX1_TX_PATH_SEC3:
353 case CDC_VA_TX1_TX_PATH_SEC4:
354 case CDC_VA_TX1_TX_PATH_SEC5:
355 case CDC_VA_TX1_TX_PATH_SEC6:
356 case CDC_VA_TX2_TX_PATH_CTL:
357 case CDC_VA_TX2_TX_PATH_CFG0:
358 case CDC_VA_TX2_TX_PATH_CFG1:
359 case CDC_VA_TX2_TX_VOL_CTL:
360 case CDC_VA_TX2_TX_PATH_SEC0:
361 case CDC_VA_TX2_TX_PATH_SEC1:
362 case CDC_VA_TX2_TX_PATH_SEC2:
363 case CDC_VA_TX2_TX_PATH_SEC3:
364 case CDC_VA_TX2_TX_PATH_SEC4:
365 case CDC_VA_TX2_TX_PATH_SEC5:
366 case CDC_VA_TX2_TX_PATH_SEC6:
367 case CDC_VA_TX3_TX_PATH_CTL:
368 case CDC_VA_TX3_TX_PATH_CFG0:
369 case CDC_VA_TX3_TX_PATH_CFG1:
370 case CDC_VA_TX3_TX_VOL_CTL:
371 case CDC_VA_TX3_TX_PATH_SEC0:
372 case CDC_VA_TX3_TX_PATH_SEC1:
373 case CDC_VA_TX3_TX_PATH_SEC2:
374 case CDC_VA_TX3_TX_PATH_SEC3:
375 case CDC_VA_TX3_TX_PATH_SEC4:
376 case CDC_VA_TX3_TX_PATH_SEC5:
377 case CDC_VA_TX3_TX_PATH_SEC6:
384 static bool va_is_readable_register(struct device *dev, unsigned int reg)
387 case CDC_VA_TOP_CSR_CORE_ID_0:
388 case CDC_VA_TOP_CSR_CORE_ID_1:
389 case CDC_VA_TOP_CSR_CORE_ID_2:
390 case CDC_VA_TOP_CSR_CORE_ID_3:
394 return va_is_rw_register(dev, reg);
397 static const struct regmap_config va_regmap_config = {
402 .cache_type = REGCACHE_FLAT,
403 .reg_defaults = va_defaults,
404 .num_reg_defaults = ARRAY_SIZE(va_defaults),
405 .max_register = VA_MAX_OFFSET,
406 .volatile_reg = va_is_volatile_register,
407 .readable_reg = va_is_readable_register,
408 .writeable_reg = va_is_rw_register,
411 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
413 struct regmap *regmap = va->regmap;
416 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
417 CDC_VA_MCLK_CONTROL_EN,
418 CDC_VA_MCLK_CONTROL_EN);
420 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
421 CDC_VA_FS_CONTROL_EN,
422 CDC_VA_FS_CONTROL_EN);
424 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
425 CDC_VA_FS_BROADCAST_EN,
426 CDC_VA_FS_BROADCAST_EN);
428 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
429 CDC_VA_MCLK_CONTROL_EN, 0x0);
431 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
432 CDC_VA_FS_CONTROL_EN, 0x0);
434 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
435 CDC_VA_FS_BROADCAST_EN, 0x0);
441 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
443 struct regmap *regmap = va->regmap;
446 va_clk_rsc_fs_gen_request(va, true);
447 regcache_mark_dirty(regmap);
448 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET);
450 va_clk_rsc_fs_gen_request(va, false);
456 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
457 struct snd_kcontrol *kcontrol, int event)
459 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
460 struct va_macro *va = snd_soc_component_get_drvdata(comp);
463 case SND_SOC_DAPM_PRE_PMU:
464 return va_macro_mclk_enable(va, true);
465 case SND_SOC_DAPM_POST_PMD:
466 return va_macro_mclk_enable(va, false);
472 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
473 struct snd_ctl_elem_value *ucontrol)
475 struct snd_soc_dapm_widget *widget =
476 snd_soc_dapm_kcontrol_widget(kcontrol);
477 struct snd_soc_component *component =
478 snd_soc_dapm_to_component(widget->dapm);
479 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
483 val = ucontrol->value.enumerated.item[0];
486 case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
487 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
489 case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
490 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
492 case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
493 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
495 case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
496 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
499 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
505 snd_soc_component_update_bits(component, mic_sel_reg,
506 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
507 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
509 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
512 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
513 struct snd_ctl_elem_value *ucontrol)
515 struct snd_soc_dapm_widget *widget =
516 snd_soc_dapm_kcontrol_widget(kcontrol);
517 struct snd_soc_component *component =
518 snd_soc_dapm_to_component(widget->dapm);
519 struct soc_mixer_control *mc =
520 (struct soc_mixer_control *)kcontrol->private_value;
521 u32 dai_id = widget->shift;
522 u32 dec_id = mc->shift;
523 struct va_macro *va = snd_soc_component_get_drvdata(component);
525 if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
526 ucontrol->value.integer.value[0] = 1;
528 ucontrol->value.integer.value[0] = 0;
533 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
534 struct snd_ctl_elem_value *ucontrol)
536 struct snd_soc_dapm_widget *widget =
537 snd_soc_dapm_kcontrol_widget(kcontrol);
538 struct snd_soc_component *component =
539 snd_soc_dapm_to_component(widget->dapm);
540 struct snd_soc_dapm_update *update = NULL;
541 struct soc_mixer_control *mc =
542 (struct soc_mixer_control *)kcontrol->private_value;
543 u32 dai_id = widget->shift;
544 u32 dec_id = mc->shift;
545 u32 enable = ucontrol->value.integer.value[0];
546 struct va_macro *va = snd_soc_component_get_drvdata(component);
549 set_bit(dec_id, &va->active_ch_mask[dai_id]);
550 va->active_ch_cnt[dai_id]++;
552 clear_bit(dec_id, &va->active_ch_mask[dai_id]);
553 va->active_ch_cnt[dai_id]--;
556 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
561 static int va_dmic_clk_enable(struct snd_soc_component *component,
562 u32 dmic, bool enable)
564 struct va_macro *va = snd_soc_component_get_drvdata(component);
574 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
575 dmic_clk_div = &(va->dmic_0_1_clk_div);
576 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL;
577 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK;
581 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
582 dmic_clk_div = &(va->dmic_2_3_clk_div);
583 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL;
584 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK;
588 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
589 dmic_clk_div = &(va->dmic_4_5_clk_div);
590 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL;
591 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK;
595 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
596 dmic_clk_div = &(va->dmic_6_7_clk_div);
597 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL;
598 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK;
601 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
607 clk_div = va->dmic_clk_div;
609 if (*dmic_clk_cnt == 1) {
610 snd_soc_component_update_bits(component,
611 CDC_VA_TOP_CSR_DMIC_CFG,
612 CDC_VA_RESET_ALL_DMICS_MASK,
613 CDC_VA_RESET_ALL_DMICS_DISABLE);
614 snd_soc_component_update_bits(component, dmic_clk_reg,
615 CDC_VA_DMIC_CLK_SEL_MASK,
616 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
617 snd_soc_component_update_bits(component, dmic_clk_reg,
621 if (*dmic_clk_div > clk_div) {
622 snd_soc_component_update_bits(component,
623 CDC_VA_TOP_CSR_DMIC_CFG,
626 snd_soc_component_update_bits(component, dmic_clk_reg,
627 CDC_VA_DMIC_CLK_SEL_MASK,
628 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
629 snd_soc_component_update_bits(component,
630 CDC_VA_TOP_CSR_DMIC_CFG,
632 CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
634 clk_div = *dmic_clk_div;
637 *dmic_clk_div = clk_div;
640 if (*dmic_clk_cnt == 0) {
641 snd_soc_component_update_bits(component, dmic_clk_reg,
642 CDC_VA_DMIC_EN_MASK, 0);
644 snd_soc_component_update_bits(component, dmic_clk_reg,
645 CDC_VA_DMIC_CLK_SEL_MASK,
646 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
648 clk_div = va->dmic_clk_div;
649 if (*dmic_clk_div > clk_div) {
650 clk_div = va->dmic_clk_div;
651 snd_soc_component_update_bits(component,
652 CDC_VA_TOP_CSR_DMIC_CFG,
655 snd_soc_component_update_bits(component, dmic_clk_reg,
656 CDC_VA_DMIC_CLK_SEL_MASK,
657 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
658 snd_soc_component_update_bits(component,
659 CDC_VA_TOP_CSR_DMIC_CFG,
661 CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
663 clk_div = *dmic_clk_div;
666 *dmic_clk_div = clk_div;
672 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
673 struct snd_kcontrol *kcontrol, int event)
675 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
676 unsigned int dmic = w->shift;
679 case SND_SOC_DAPM_PRE_PMU:
680 va_dmic_clk_enable(comp, dmic, true);
682 case SND_SOC_DAPM_POST_PMD:
683 va_dmic_clk_enable(comp, dmic, false);
690 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
691 struct snd_kcontrol *kcontrol, int event)
693 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
694 unsigned int decimator;
695 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
699 struct va_macro *va = snd_soc_component_get_drvdata(comp);
701 decimator = w->shift;
703 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
704 VA_MACRO_TX_PATH_OFFSET * decimator;
705 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 +
706 VA_MACRO_TX_PATH_OFFSET * decimator;
707 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 +
708 VA_MACRO_TX_PATH_OFFSET * decimator;
709 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL +
710 VA_MACRO_TX_PATH_OFFSET * decimator;
713 case SND_SOC_DAPM_PRE_PMU:
714 snd_soc_component_update_bits(comp,
715 dec_cfg_reg, CDC_VA_ADC_MODE_MASK,
716 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
717 /* Enable TX PGA Mute */
719 case SND_SOC_DAPM_POST_PMU:
721 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
722 CDC_VA_TX_PATH_CLK_EN_MASK,
723 CDC_VA_TX_PATH_CLK_EN);
724 snd_soc_component_update_bits(comp, hpf_gate_reg,
725 CDC_VA_TX_HPF_ZERO_GATE_MASK,
726 CDC_VA_TX_HPF_ZERO_GATE);
728 usleep_range(1000, 1010);
729 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
730 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
732 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
733 snd_soc_component_update_bits(comp, dec_cfg_reg,
734 TX_HPF_CUT_OFF_FREQ_MASK,
735 CF_MIN_3DB_150HZ << 5);
737 snd_soc_component_update_bits(comp, hpf_gate_reg,
738 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
739 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ);
742 * Minimum 1 clk cycle delay is required as per HW spec
744 usleep_range(1000, 1010);
746 snd_soc_component_update_bits(comp,
748 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
753 usleep_range(1000, 1010);
754 snd_soc_component_update_bits(comp, hpf_gate_reg,
755 CDC_VA_TX_HPF_ZERO_GATE_MASK,
756 CDC_VA_TX_HPF_ZERO_NO_GATE);
758 * 6ms delay is required as per HW spec
760 usleep_range(6000, 6010);
761 /* apply gain after decimator is enabled */
762 snd_soc_component_write(comp, tx_gain_ctl_reg,
763 snd_soc_component_read(comp, tx_gain_ctl_reg));
765 case SND_SOC_DAPM_POST_PMD:
767 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
768 CDC_VA_TX_PATH_CLK_EN_MASK,
769 CDC_VA_TX_PATH_CLK_DISABLE);
775 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
776 struct snd_ctl_elem_value *ucontrol)
778 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
779 struct va_macro *va = snd_soc_component_get_drvdata(comp);
780 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
781 int path = e->shift_l;
783 ucontrol->value.integer.value[0] = va->dec_mode[path];
788 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
789 struct snd_ctl_elem_value *ucontrol)
791 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
792 int value = ucontrol->value.integer.value[0];
793 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
794 int path = e->shift_l;
795 struct va_macro *va = snd_soc_component_get_drvdata(comp);
797 va->dec_mode[path] = value;
802 static int va_macro_hw_params(struct snd_pcm_substream *substream,
803 struct snd_pcm_hw_params *params,
804 struct snd_soc_dai *dai)
807 struct snd_soc_component *component = dai->component;
808 u32 decimator, sample_rate;
810 struct device *va_dev = component->dev;
811 struct va_macro *va = snd_soc_component_get_drvdata(component);
813 sample_rate = params_rate(params);
814 switch (sample_rate) {
837 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
838 __func__, params_rate(params));
842 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
844 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL +
845 VA_MACRO_TX_PATH_OFFSET * decimator;
846 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F,
852 static int va_macro_get_channel_map(struct snd_soc_dai *dai,
853 unsigned int *tx_num, unsigned int *tx_slot,
854 unsigned int *rx_num, unsigned int *rx_slot)
856 struct snd_soc_component *component = dai->component;
857 struct device *va_dev = component->dev;
858 struct va_macro *va = snd_soc_component_get_drvdata(component);
861 case VA_MACRO_AIF1_CAP:
862 case VA_MACRO_AIF2_CAP:
863 case VA_MACRO_AIF3_CAP:
864 *tx_slot = va->active_ch_mask[dai->id];
865 *tx_num = va->active_ch_cnt[dai->id];
868 dev_err(va_dev, "%s: Invalid AIF\n", __func__);
874 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
876 struct snd_soc_component *component = dai->component;
877 struct va_macro *va = snd_soc_component_get_drvdata(component);
878 u16 tx_vol_ctl_reg, decimator;
880 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
882 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
883 VA_MACRO_TX_PATH_OFFSET * decimator;
885 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
886 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
887 CDC_VA_TX_PATH_PGA_MUTE_EN);
889 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
890 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
891 CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
897 static struct snd_soc_dai_ops va_macro_dai_ops = {
898 .hw_params = va_macro_hw_params,
899 .get_channel_map = va_macro_get_channel_map,
900 .mute_stream = va_macro_digital_mute,
903 static struct snd_soc_dai_driver va_macro_dais[] = {
905 .name = "va_macro_tx1",
906 .id = VA_MACRO_AIF1_CAP,
908 .stream_name = "VA_AIF1 Capture",
909 .rates = VA_MACRO_RATES,
910 .formats = VA_MACRO_FORMATS,
916 .ops = &va_macro_dai_ops,
919 .name = "va_macro_tx2",
920 .id = VA_MACRO_AIF2_CAP,
922 .stream_name = "VA_AIF2 Capture",
923 .rates = VA_MACRO_RATES,
924 .formats = VA_MACRO_FORMATS,
930 .ops = &va_macro_dai_ops,
933 .name = "va_macro_tx3",
934 .id = VA_MACRO_AIF3_CAP,
936 .stream_name = "VA_AIF3 Capture",
937 .rates = VA_MACRO_RATES,
938 .formats = VA_MACRO_FORMATS,
944 .ops = &va_macro_dai_ops,
948 static const char * const adc_mux_text[] = {
952 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1,
954 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1,
956 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1,
958 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1,
961 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0",
963 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1",
965 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2",
967 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3",
970 static const char * const dmic_mux_text[] = {
971 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
972 "DMIC4", "DMIC5", "DMIC6", "DMIC7"
975 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0,
978 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0,
981 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0,
984 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0,
987 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0",
988 va_dmic0_enum, snd_soc_dapm_get_enum_double,
989 va_macro_put_dec_enum);
991 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1",
992 va_dmic1_enum, snd_soc_dapm_get_enum_double,
993 va_macro_put_dec_enum);
995 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2",
996 va_dmic2_enum, snd_soc_dapm_get_enum_double,
997 va_macro_put_dec_enum);
999 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3",
1000 va_dmic3_enum, snd_soc_dapm_get_enum_double,
1001 va_macro_put_dec_enum);
1003 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
1004 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1005 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1006 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1007 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1008 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1009 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1010 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1011 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1012 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1013 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1014 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1015 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1016 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1017 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1018 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1019 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1022 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
1023 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1024 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1025 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1026 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1027 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1028 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1029 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1030 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1031 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1032 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1033 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1034 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1035 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1036 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1037 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1038 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1041 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
1042 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1043 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1044 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1045 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1046 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1047 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1048 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1049 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1050 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1051 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1052 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1053 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1054 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1055 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1056 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1057 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1060 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = {
1061 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
1062 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0),
1064 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
1065 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0),
1067 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
1068 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0),
1070 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
1071 VA_MACRO_AIF1_CAP, 0,
1072 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
1074 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
1075 VA_MACRO_AIF2_CAP, 0,
1076 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
1078 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
1079 VA_MACRO_AIF3_CAP, 0,
1080 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
1082 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
1083 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
1084 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
1085 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
1087 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1088 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
1089 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
1090 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
1091 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
1092 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
1093 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
1094 SND_SOC_DAPM_INPUT("DMIC6 Pin"),
1095 SND_SOC_DAPM_INPUT("DMIC7 Pin"),
1097 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
1098 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1099 SND_SOC_DAPM_POST_PMD),
1101 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
1102 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1103 SND_SOC_DAPM_POST_PMD),
1105 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
1106 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1107 SND_SOC_DAPM_POST_PMD),
1109 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
1110 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1111 SND_SOC_DAPM_POST_PMD),
1113 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
1114 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1115 SND_SOC_DAPM_POST_PMD),
1117 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
1118 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1119 SND_SOC_DAPM_POST_PMD),
1121 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
1122 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1123 SND_SOC_DAPM_POST_PMD),
1125 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
1126 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1127 SND_SOC_DAPM_POST_PMD),
1129 SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
1130 SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
1131 SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
1132 SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
1133 SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
1134 SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
1135 SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
1136 SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
1137 SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
1138 SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
1139 SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
1140 SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
1142 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1143 &va_dec0_mux, va_macro_enable_dec,
1144 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1145 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1147 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1148 &va_dec1_mux, va_macro_enable_dec,
1149 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1150 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1152 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1153 &va_dec2_mux, va_macro_enable_dec,
1154 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1155 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1157 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1158 &va_dec3_mux, va_macro_enable_dec,
1159 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1160 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1162 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1163 va_macro_mclk_event,
1164 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1167 static const struct snd_soc_dapm_route va_audio_map[] = {
1168 {"VA_AIF1 CAP", NULL, "VA_MCLK"},
1169 {"VA_AIF2 CAP", NULL, "VA_MCLK"},
1170 {"VA_AIF3 CAP", NULL, "VA_MCLK"},
1172 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
1173 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
1174 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
1176 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1177 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1178 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1179 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1181 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1182 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1183 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1184 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1186 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1187 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1188 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1189 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1191 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1192 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
1193 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
1194 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
1195 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
1196 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
1197 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
1198 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
1199 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
1201 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1202 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
1203 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
1204 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
1205 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
1206 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
1207 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
1208 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
1209 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
1211 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1212 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
1213 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
1214 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
1215 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
1216 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
1217 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
1218 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
1219 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
1221 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1222 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
1223 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
1224 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
1225 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
1226 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
1227 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
1228 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
1229 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
1231 { "VA DMIC0", NULL, "DMIC0 Pin" },
1232 { "VA DMIC1", NULL, "DMIC1 Pin" },
1233 { "VA DMIC2", NULL, "DMIC2 Pin" },
1234 { "VA DMIC3", NULL, "DMIC3 Pin" },
1235 { "VA DMIC4", NULL, "DMIC4 Pin" },
1236 { "VA DMIC5", NULL, "DMIC5 Pin" },
1237 { "VA DMIC6", NULL, "DMIC6 Pin" },
1238 { "VA DMIC7", NULL, "DMIC7 Pin" },
1241 static const char * const dec_mode_mux_text[] = {
1242 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1245 static const struct soc_enum dec_mode_mux_enum[] = {
1246 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1248 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1250 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1252 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1256 static const struct snd_kcontrol_new va_macro_snd_controls[] = {
1257 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL,
1258 -84, 40, digital_gain),
1259 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL,
1260 -84, 40, digital_gain),
1261 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL,
1262 -84, 40, digital_gain),
1263 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL,
1264 -84, 40, digital_gain),
1266 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0],
1267 va_macro_dec_mode_get, va_macro_dec_mode_put),
1268 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1],
1269 va_macro_dec_mode_get, va_macro_dec_mode_put),
1270 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2],
1271 va_macro_dec_mode_get, va_macro_dec_mode_put),
1272 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3],
1273 va_macro_dec_mode_get, va_macro_dec_mode_put),
1276 static int va_macro_component_probe(struct snd_soc_component *component)
1278 struct va_macro *va = snd_soc_component_get_drvdata(component);
1280 snd_soc_component_init_regmap(component, va->regmap);
1285 static const struct snd_soc_component_driver va_macro_component_drv = {
1287 .probe = va_macro_component_probe,
1288 .controls = va_macro_snd_controls,
1289 .num_controls = ARRAY_SIZE(va_macro_snd_controls),
1290 .dapm_widgets = va_macro_dapm_widgets,
1291 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets),
1292 .dapm_routes = va_audio_map,
1293 .num_dapm_routes = ARRAY_SIZE(va_audio_map),
1296 static int fsgen_gate_enable(struct clk_hw *hw)
1298 return va_macro_mclk_enable(to_va_macro(hw), true);
1301 static void fsgen_gate_disable(struct clk_hw *hw)
1303 va_macro_mclk_enable(to_va_macro(hw), false);
1306 static int fsgen_gate_is_enabled(struct clk_hw *hw)
1308 struct va_macro *va = to_va_macro(hw);
1311 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1313 return !!(val & CDC_VA_FS_BROADCAST_EN);
1316 static const struct clk_ops fsgen_gate_ops = {
1317 .prepare = fsgen_gate_enable,
1318 .unprepare = fsgen_gate_disable,
1319 .is_enabled = fsgen_gate_is_enabled,
1322 static int va_macro_register_fsgen_output(struct va_macro *va)
1324 struct clk *parent = va->clks[2].clk;
1325 struct device *dev = va->dev;
1326 struct device_node *np = dev->of_node;
1327 const char *parent_clk_name;
1328 const char *clk_name = "fsgen";
1329 struct clk_init_data init;
1332 parent_clk_name = __clk_get_name(parent);
1334 of_property_read_string(np, "clock-output-names", &clk_name);
1336 init.name = clk_name;
1337 init.ops = &fsgen_gate_ops;
1339 init.parent_names = &parent_clk_name;
1340 init.num_parents = 1;
1341 va->hw.init = &init;
1342 ret = devm_clk_hw_register(va->dev, &va->hw);
1346 return of_clk_add_provider(np, of_clk_src_simple_get, va->hw.clk);
1349 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
1350 struct va_macro *va)
1353 u32 mclk_rate = VA_MACRO_MCLK_FREQ;
1355 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0)
1356 goto undefined_rate;
1358 div_factor = mclk_rate / dmic_sample_rate;
1360 switch (div_factor) {
1362 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1365 va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1368 va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1371 va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1374 va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1377 va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1380 /* Any other DIV factor is invalid */
1381 goto undefined_rate;
1384 return dmic_sample_rate;
1387 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1388 __func__, dmic_sample_rate, mclk_rate);
1389 dmic_sample_rate = 0;
1391 return dmic_sample_rate;
1394 static int va_macro_probe(struct platform_device *pdev)
1396 struct device *dev = &pdev->dev;
1397 struct va_macro *va;
1399 u32 sample_rate = 0;
1402 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
1407 va->clks[0].id = "macro";
1408 va->clks[1].id = "dcodec";
1409 va->clks[2].id = "mclk";
1411 ret = devm_clk_bulk_get(dev, VA_NUM_CLKS_MAX, va->clks);
1413 dev_err(dev, "Error getting VA Clocks (%d)\n", ret);
1417 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
1420 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
1421 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1423 ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
1429 clk_set_rate(va->clks[1].clk, VA_MACRO_MCLK_FREQ);
1430 ret = clk_bulk_prepare_enable(VA_NUM_CLKS_MAX, va->clks);
1434 base = devm_platform_ioremap_resource(pdev, 0);
1436 ret = PTR_ERR(base);
1440 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config);
1441 if (IS_ERR(va->regmap)) {
1446 dev_set_drvdata(dev, va);
1447 ret = va_macro_register_fsgen_output(va);
1451 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
1453 ARRAY_SIZE(va_macro_dais));
1460 of_clk_del_provider(pdev->dev.of_node);
1462 clk_bulk_disable_unprepare(VA_NUM_CLKS_MAX, va->clks);
1467 static int va_macro_remove(struct platform_device *pdev)
1469 struct va_macro *va = dev_get_drvdata(&pdev->dev);
1471 of_clk_del_provider(pdev->dev.of_node);
1472 clk_bulk_disable_unprepare(VA_NUM_CLKS_MAX, va->clks);
1477 static const struct of_device_id va_macro_dt_match[] = {
1478 { .compatible = "qcom,sm8250-lpass-va-macro" },
1481 MODULE_DEVICE_TABLE(of, va_macro_dt_match);
1483 static struct platform_driver va_macro_driver = {
1486 .of_match_table = va_macro_dt_match,
1487 .suppress_bind_attrs = true,
1489 .probe = va_macro_probe,
1490 .remove = va_macro_remove,
1493 module_platform_driver(va_macro_driver);
1494 MODULE_DESCRIPTION("VA macro driver");
1495 MODULE_LICENSE("GPL");