sound/soc/codecs/lpass-rx-macro.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/module.h>
   5 #include <linux/init.h>
   6 #include <linux/io.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/clk.h>
   9 #include <sound/soc.h>
  10 #include <sound/pcm.h>
  11 #include <sound/pcm_params.h>
  12 #include <sound/soc-dapm.h>
  13 #include <sound/tlv.h>
  14 #include <linux/of_clk.h>
  15 #include <linux/clk-provider.h>
  16
  17 #define CDC_RX_TOP_TOP_CFG0             (0x0000)
  18 #define CDC_RX_TOP_SWR_CTRL             (0x0008)
  19 #define CDC_RX_TOP_DEBUG                (0x000C)
  20 #define CDC_RX_TOP_DEBUG_BUS            (0x0010)
  21 #define CDC_RX_TOP_DEBUG_EN0            (0x0014)
  22 #define CDC_RX_TOP_DEBUG_EN1            (0x0018)
  23 #define CDC_RX_TOP_DEBUG_EN2            (0x001C)
  24 #define CDC_RX_TOP_HPHL_COMP_WR_LSB     (0x0020)
  25 #define CDC_RX_TOP_HPHL_COMP_WR_MSB     (0x0024)
  26 #define CDC_RX_TOP_HPHL_COMP_LUT        (0x0028)
  27 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK  BIT(7)
  28 #define CDC_RX_TOP_HPHL_COMP_RD_LSB     (0x002C)
  29 #define CDC_RX_TOP_HPHL_COMP_RD_MSB     (0x0030)
  30 #define CDC_RX_TOP_HPHR_COMP_WR_LSB     (0x0034)
  31 #define CDC_RX_TOP_HPHR_COMP_WR_MSB     (0x0038)
  32 #define CDC_RX_TOP_HPHR_COMP_LUT        (0x003C)
  33 #define CDC_RX_TOP_HPHR_COMP_RD_LSB     (0x0040)
  34 #define CDC_RX_TOP_HPHR_COMP_RD_MSB     (0x0044)
  35 #define CDC_RX_TOP_DSD0_DEBUG_CFG0      (0x0070)
  36 #define CDC_RX_TOP_DSD0_DEBUG_CFG1      (0x0074)
  37 #define CDC_RX_TOP_DSD0_DEBUG_CFG2      (0x0078)
  38 #define CDC_RX_TOP_DSD0_DEBUG_CFG3      (0x007C)
  39 #define CDC_RX_TOP_DSD1_DEBUG_CFG0      (0x0080)
  40 #define CDC_RX_TOP_DSD1_DEBUG_CFG1      (0x0084)
  41 #define CDC_RX_TOP_DSD1_DEBUG_CFG2      (0x0088)
  42 #define CDC_RX_TOP_DSD1_DEBUG_CFG3      (0x008C)
  43 #define CDC_RX_TOP_RX_I2S_CTL           (0x0090)
  44 #define CDC_RX_TOP_TX_I2S2_CTL          (0x0094)
  45 #define CDC_RX_TOP_I2S_CLK              (0x0098)
  46 #define CDC_RX_TOP_I2S_RESET            (0x009C)
  47 #define CDC_RX_TOP_I2S_MUX              (0x00A0)
  48 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL        (0x0100)
  49 #define CDC_RX_CLK_MCLK_EN_MASK         BIT(0)
  50 #define CDC_RX_CLK_MCLK_ENABLE          BIT(0)
  51 #define CDC_RX_CLK_MCLK2_EN_MASK        BIT(1)
  52 #define CDC_RX_CLK_MCLK2_ENABLE         BIT(1)
  53 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL      (0x0104)
  54 #define CDC_RX_FS_MCLK_CNT_EN_MASK      BIT(0)
  55 #define CDC_RX_FS_MCLK_CNT_ENABLE       BIT(0)
  56 #define CDC_RX_FS_MCLK_CNT_CLR_MASK     BIT(1)
  57 #define CDC_RX_FS_MCLK_CNT_CLR          BIT(1)
  58 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)
  59 #define CDC_RX_SWR_CLK_EN_MASK          BIT(0)
  60 #define CDC_RX_SWR_RESET_MASK           BIT(1)
  61 #define CDC_RX_SWR_RESET                BIT(1)
  62 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)
  63 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL  (0x0110)
  64 #define CDC_RX_SOFTCLIP_CRC             (0x0140)
  65 #define CDC_RX_SOFTCLIP_CLK_EN_MASK     BIT(0)
  66 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL   (0x0144)
  67 #define CDC_RX_SOFTCLIP_EN_MASK         BIT(0)
  68 #define CDC_RX_INP_MUX_RX_INT0_CFG0     (0x0180)
  69 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)
  70 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)
  71 #define CDC_RX_INP_MUX_RX_INT0_CFG1     (0x0184)
  72 #define CDC_RX_INTX_2_SEL_MASK          GENMASK(3, 0)
  73 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)
  74 #define CDC_RX_INP_MUX_RX_INT1_CFG0     (0x0188)
  75 #define CDC_RX_INP_MUX_RX_INT1_CFG1     (0x018C)
  76 #define CDC_RX_INP_MUX_RX_INT2_CFG0     (0x0190)
  77 #define CDC_RX_INP_MUX_RX_INT2_CFG1     (0x0194)
  78 #define CDC_RX_INP_MUX_RX_MIX_CFG4      (0x0198)
  79 #define CDC_RX_INP_MUX_RX_MIX_CFG5      (0x019C)
  80 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0        (0x01A0)
  81 #define CDC_RX_CLSH_CRC                 (0x0200)
  82 #define CDC_RX_CLSH_CLK_EN_MASK         BIT(0)
  83 #define CDC_RX_CLSH_DLY_CTRL            (0x0204)
  84 #define CDC_RX_CLSH_DECAY_CTRL          (0x0208)
  85 #define CDC_RX_CLSH_DECAY_RATE_MASK     GENMASK(2, 0)
  86 #define CDC_RX_CLSH_HPH_V_PA            (0x020C)
  87 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK   GENMASK(5, 0)
  88 #define CDC_RX_CLSH_EAR_V_PA            (0x0210)
  89 #define CDC_RX_CLSH_HPH_V_HD            (0x0214)
  90 #define CDC_RX_CLSH_EAR_V_HD            (0x0218)
  91 #define CDC_RX_CLSH_K1_MSB              (0x021C)
  92 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK   GENMASK(3, 0)
  93 #define CDC_RX_CLSH_K1_LSB              (0x0220)
  94 #define CDC_RX_CLSH_K2_MSB              (0x0224)
  95 #define CDC_RX_CLSH_K2_LSB              (0x0228)
  96 #define CDC_RX_CLSH_IDLE_CTRL           (0x022C)
  97 #define CDC_RX_CLSH_IDLE_HPH            (0x0230)
  98 #define CDC_RX_CLSH_IDLE_EAR            (0x0234)
  99 #define CDC_RX_CLSH_TEST0               (0x0238)
 100 #define CDC_RX_CLSH_TEST1               (0x023C)
 101 #define CDC_RX_CLSH_OVR_VREF            (0x0240)
 102 #define CDC_RX_CLSH_CLSG_CTL            (0x0244)
 103 #define CDC_RX_CLSH_CLSG_CFG1           (0x0248)
 104 #define CDC_RX_CLSH_CLSG_CFG2           (0x024C)
 105 #define CDC_RX_BCL_VBAT_PATH_CTL        (0x0280)
 106 #define CDC_RX_BCL_VBAT_CFG             (0x0284)
 107 #define CDC_RX_BCL_VBAT_ADC_CAL1        (0x0288)
 108 #define CDC_RX_BCL_VBAT_ADC_CAL2        (0x028C)
 109 #define CDC_RX_BCL_VBAT_ADC_CAL3        (0x0290)
 110 #define CDC_RX_BCL_VBAT_PK_EST1         (0x0294)
 111 #define CDC_RX_BCL_VBAT_PK_EST2         (0x0298)
 112 #define CDC_RX_BCL_VBAT_PK_EST3         (0x029C)
 113 #define CDC_RX_BCL_VBAT_RF_PROC1        (0x02A0)
 114 #define CDC_RX_BCL_VBAT_RF_PROC2        (0x02A4)
 115 #define CDC_RX_BCL_VBAT_TAC1            (0x02A8)
 116 #define CDC_RX_BCL_VBAT_TAC2            (0x02AC)
 117 #define CDC_RX_BCL_VBAT_TAC3            (0x02B0)
 118 #define CDC_RX_BCL_VBAT_TAC4            (0x02B4)
 119 #define CDC_RX_BCL_VBAT_GAIN_UPD1       (0x02B8)
 120 #define CDC_RX_BCL_VBAT_GAIN_UPD2       (0x02BC)
 121 #define CDC_RX_BCL_VBAT_GAIN_UPD3       (0x02C0)
 122 #define CDC_RX_BCL_VBAT_GAIN_UPD4       (0x02C4)
 123 #define CDC_RX_BCL_VBAT_GAIN_UPD5       (0x02C8)
 124 #define CDC_RX_BCL_VBAT_DEBUG1          (0x02CC)
 125 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON    (0x02D0)
 126 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL    (0x02D4)
 127 #define CDC_RX_BCL_VBAT_BAN             (0x02D8)
 128 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1   (0x02DC)
 129 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2   (0x02E0)
 130 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3   (0x02E4)
 131 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4   (0x02E8)
 132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5   (0x02EC)
 133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6   (0x02F0)
 134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7   (0x02F4)
 135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8   (0x02F8)
 136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9   (0x02FC)
 137 #define CDC_RX_BCL_VBAT_ATTN1           (0x0300)
 138 #define CDC_RX_BCL_VBAT_ATTN2           (0x0304)
 139 #define CDC_RX_BCL_VBAT_ATTN3           (0x0308)
 140 #define CDC_RX_BCL_VBAT_DECODE_CTL1     (0x030C)
 141 #define CDC_RX_BCL_VBAT_DECODE_CTL2     (0x0310)
 142 #define CDC_RX_BCL_VBAT_DECODE_CFG1     (0x0314)
 143 #define CDC_RX_BCL_VBAT_DECODE_CFG2     (0x0318)
 144 #define CDC_RX_BCL_VBAT_DECODE_CFG3     (0x031C)
 145 #define CDC_RX_BCL_VBAT_DECODE_CFG4     (0x0320)
 146 #define CDC_RX_BCL_VBAT_DECODE_ST       (0x0324)
 147 #define CDC_RX_INTR_CTRL_CFG            (0x0340)
 148 #define CDC_RX_INTR_CTRL_CLR_COMMIT     (0x0344)
 149 #define CDC_RX_INTR_CTRL_PIN1_MASK0     (0x0360)
 150 #define CDC_RX_INTR_CTRL_PIN1_STATUS0   (0x0368)
 151 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0    (0x0370)
 152 #define CDC_RX_INTR_CTRL_PIN2_MASK0     (0x0380)
 153 #define CDC_RX_INTR_CTRL_PIN2_STATUS0   (0x0388)
 154 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0    (0x0390)
 155 #define CDC_RX_INTR_CTRL_LEVEL0         (0x03C0)
 156 #define CDC_RX_INTR_CTRL_BYPASS0        (0x03C8)
 157 #define CDC_RX_INTR_CTRL_SET0           (0x03D0)
 158 #define CDC_RX_RXn_RX_PATH_CTL(n)       (0x0400 + 0x80 * n)
 159 #define CDC_RX_RX0_RX_PATH_CTL          (0x0400)
 160 #define CDC_RX_PATH_RESET_EN_MASK       BIT(6)
 161 #define CDC_RX_PATH_CLK_EN_MASK         BIT(5)
 162 #define CDC_RX_PATH_CLK_ENABLE          BIT(5)
 163 #define CDC_RX_PATH_PGA_MUTE_MASK       BIT(4)
 164 #define CDC_RX_PATH_PGA_MUTE_ENABLE     BIT(4)
 165 #define CDC_RX_PATH_PCM_RATE_MASK       GENMASK(3, 0)
 166 #define CDC_RX_RXn_RX_PATH_CFG0(n)      (0x0404 + 0x80 * n)
 167 #define CDC_RX_RXn_COMP_EN_MASK         BIT(1)
 168 #define CDC_RX_RX0_RX_PATH_CFG0         (0x0404)
 169 #define CDC_RX_RXn_CLSH_EN_MASK         BIT(6)
 170 #define CDC_RX_DLY_ZN_EN_MASK           BIT(3)
 171 #define CDC_RX_DLY_ZN_ENABLE            BIT(3)
 172 #define CDC_RX_RXn_HD2_EN_MASK          BIT(2)
 173 #define CDC_RX_RXn_RX_PATH_CFG1(n)      (0x0408 + 0x80 * n)
 174 #define CDC_RX_RXn_SIDETONE_EN_MASK     BIT(4)
 175 #define CDC_RX_RX0_RX_PATH_CFG1         (0x0408)
 176 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK   BIT(1)
 177 #define CDC_RX_RXn_RX_PATH_CFG2(n)      (0x040C + 0x80 * n)
 178 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK    GENMASK(1, 0)
 179 #define CDC_RX_RX0_RX_PATH_CFG2         (0x040C)
 180 #define CDC_RX_RXn_RX_PATH_CFG3(n)      (0x0410 + 0x80 * n)
 181 #define CDC_RX_RX0_RX_PATH_CFG3         (0x0410)
 182 #define CDC_RX_DC_COEFF_SEL_MASK        GENMASK(1, 0)
 183 #define CDC_RX_DC_COEFF_SEL_TWO         0x2
 184 #define CDC_RX_RXn_RX_VOL_CTL(n)        (0x0414 + 0x80 * n)
 185 #define CDC_RX_RX0_RX_VOL_CTL           (0x0414)
 186 #define CDC_RX_RXn_RX_PATH_MIX_CTL(n)   (0x0418 + 0x80 * n)
 187 #define CDC_RX_RXn_MIX_PCM_RATE_MASK    GENMASK(3, 0)
 188 #define CDC_RX_RXn_MIX_RESET_MASK       BIT(6)
 189 #define CDC_RX_RXn_MIX_RESET            BIT(6)
 190 #define CDC_RX_RXn_MIX_CLK_EN_MASK      BIT(5)
 191 #define CDC_RX_RX0_RX_PATH_MIX_CTL      (0x0418)
 192 #define CDC_RX_RX0_RX_PATH_MIX_CFG      (0x041C)
 193 #define CDC_RX_RXn_RX_VOL_MIX_CTL(n)    (0x0420 + 0x80 * n)
 194 #define CDC_RX_RX0_RX_VOL_MIX_CTL       (0x0420)
 195 #define CDC_RX_RX0_RX_PATH_SEC1         (0x0424)
 196 #define CDC_RX_RX0_RX_PATH_SEC2         (0x0428)
 197 #define CDC_RX_RX0_RX_PATH_SEC3         (0x042C)
 198 #define CDC_RX_RX0_RX_PATH_SEC4         (0x0430)
 199 #define CDC_RX_RX0_RX_PATH_SEC7         (0x0434)
 200 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK   GENMASK(2, 0)
 201 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
 202 #define CDC_RX_RX0_RX_PATH_MIX_SEC0     (0x0438)
 203 #define CDC_RX_RX0_RX_PATH_MIX_SEC1     (0x043C)
 204 #define CDC_RX_RXn_RX_PATH_DSM_CTL(n)   (0x0440 + 0x80 * n)
 205 #define CDC_RX_RXn_DSM_CLK_EN_MASK      BIT(0)
 206 #define CDC_RX_RX0_RX_PATH_DSM_CTL      (0x0440)
 207 #define CDC_RX_RX0_RX_PATH_DSM_DATA1    (0x0444)
 208 #define CDC_RX_RX0_RX_PATH_DSM_DATA2    (0x0448)
 209 #define CDC_RX_RX0_RX_PATH_DSM_DATA3    (0x044C)
 210 #define CDC_RX_RX0_RX_PATH_DSM_DATA4    (0x0450)
 211 #define CDC_RX_RX0_RX_PATH_DSM_DATA5    (0x0454)
 212 #define CDC_RX_RX0_RX_PATH_DSM_DATA6    (0x0458)
 213 #define CDC_RX_RX1_RX_PATH_CTL          (0x0480)
 214 #define CDC_RX_RX1_RX_PATH_CFG0         (0x0484)
 215 #define CDC_RX_RX1_RX_PATH_CFG1         (0x0488)
 216 #define CDC_RX_RX1_RX_PATH_CFG2         (0x048C)
 217 #define CDC_RX_RX1_RX_PATH_CFG3         (0x0490)
 218 #define CDC_RX_RX1_RX_VOL_CTL           (0x0494)
 219 #define CDC_RX_RX1_RX_PATH_MIX_CTL      (0x0498)
 220 #define CDC_RX_RX1_RX_PATH_MIX_CFG      (0x049C)
 221 #define CDC_RX_RX1_RX_VOL_MIX_CTL       (0x04A0)
 222 #define CDC_RX_RX1_RX_PATH_SEC1         (0x04A4)
 223 #define CDC_RX_RX1_RX_PATH_SEC2         (0x04A8)
 224 #define CDC_RX_RX1_RX_PATH_SEC3         (0x04AC)
 225 #define CDC_RX_RXn_HD2_ALPHA_MASK       GENMASK(5, 2)
 226 #define CDC_RX_RX1_RX_PATH_SEC4         (0x04B0)
 227 #define CDC_RX_RX1_RX_PATH_SEC7         (0x04B4)
 228 #define CDC_RX_RX1_RX_PATH_MIX_SEC0     (0x04B8)
 229 #define CDC_RX_RX1_RX_PATH_MIX_SEC1     (0x04BC)
 230 #define CDC_RX_RX1_RX_PATH_DSM_CTL      (0x04C0)
 231 #define CDC_RX_RX1_RX_PATH_DSM_DATA1    (0x04C4)
 232 #define CDC_RX_RX1_RX_PATH_DSM_DATA2    (0x04C8)
 233 #define CDC_RX_RX1_RX_PATH_DSM_DATA3    (0x04CC)
 234 #define CDC_RX_RX1_RX_PATH_DSM_DATA4    (0x04D0)
 235 #define CDC_RX_RX1_RX_PATH_DSM_DATA5    (0x04D4)
 236 #define CDC_RX_RX1_RX_PATH_DSM_DATA6    (0x04D8)
 237 #define CDC_RX_RX2_RX_PATH_CTL          (0x0500)
 238 #define CDC_RX_RX2_RX_PATH_CFG0         (0x0504)
 239 #define CDC_RX_RX2_CLSH_EN_MASK         BIT(4)
 240 #define CDC_RX_RX2_DLY_Z_EN_MASK        BIT(3)
 241 #define CDC_RX_RX2_RX_PATH_CFG1         (0x0508)
 242 #define CDC_RX_RX2_RX_PATH_CFG2         (0x050C)
 243 #define CDC_RX_RX2_RX_PATH_CFG3         (0x0510)
 244 #define CDC_RX_RX2_RX_VOL_CTL           (0x0514)
 245 #define CDC_RX_RX2_RX_PATH_MIX_CTL      (0x0518)
 246 #define CDC_RX_RX2_RX_PATH_MIX_CFG      (0x051C)
 247 #define CDC_RX_RX2_RX_VOL_MIX_CTL       (0x0520)
 248 #define CDC_RX_RX2_RX_PATH_SEC0         (0x0524)
 249 #define CDC_RX_RX2_RX_PATH_SEC1         (0x0528)
 250 #define CDC_RX_RX2_RX_PATH_SEC2         (0x052C)
 251 #define CDC_RX_RX2_RX_PATH_SEC3         (0x0530)
 252 #define CDC_RX_RX2_RX_PATH_SEC4         (0x0534)
 253 #define CDC_RX_RX2_RX_PATH_SEC5         (0x0538)
 254 #define CDC_RX_RX2_RX_PATH_SEC6         (0x053C)
 255 #define CDC_RX_RX2_RX_PATH_SEC7         (0x0540)
 256 #define CDC_RX_RX2_RX_PATH_MIX_SEC0     (0x0544)
 257 #define CDC_RX_RX2_RX_PATH_MIX_SEC1     (0x0548)
 258 #define CDC_RX_RX2_RX_PATH_DSM_CTL      (0x054C)
 259 #define CDC_RX_IDLE_DETECT_PATH_CTL     (0x0780)
 260 #define CDC_RX_IDLE_DETECT_CFG0         (0x0784)
 261 #define CDC_RX_IDLE_DETECT_CFG1         (0x0788)
 262 #define CDC_RX_IDLE_DETECT_CFG2         (0x078C)
 263 #define CDC_RX_IDLE_DETECT_CFG3         (0x0790)
 264 #define CDC_RX_COMPANDERn_CTL0(n)       (0x0800 + 0x40 * n)
 265 #define CDC_RX_COMPANDERn_CLK_EN_MASK   BIT(0)
 266 #define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1)
 267 #define CDC_RX_COMPANDERn_HALT_MASK     BIT(2)
 268 #define CDC_RX_COMPANDER0_CTL0          (0x0800)
 269 #define CDC_RX_COMPANDER0_CTL1          (0x0804)
 270 #define CDC_RX_COMPANDER0_CTL2          (0x0808)
 271 #define CDC_RX_COMPANDER0_CTL3          (0x080C)
 272 #define CDC_RX_COMPANDER0_CTL4          (0x0810)
 273 #define CDC_RX_COMPANDER0_CTL5          (0x0814)
 274 #define CDC_RX_COMPANDER0_CTL6          (0x0818)
 275 #define CDC_RX_COMPANDER0_CTL7          (0x081C)
 276 #define CDC_RX_COMPANDER1_CTL0          (0x0840)
 277 #define CDC_RX_COMPANDER1_CTL1          (0x0844)
 278 #define CDC_RX_COMPANDER1_CTL2          (0x0848)
 279 #define CDC_RX_COMPANDER1_CTL3          (0x084C)
 280 #define CDC_RX_COMPANDER1_CTL4          (0x0850)
 281 #define CDC_RX_COMPANDER1_CTL5          (0x0854)
 282 #define CDC_RX_COMPANDER1_CTL6          (0x0858)
 283 #define CDC_RX_COMPANDER1_CTL7          (0x085C)
 284 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5)
 285 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL       (0x0A00)
 286 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL    (0x0A04)
 287 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL    (0x0A08)
 288 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL    (0x0A0C)
 289 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL    (0x0A10)
 290 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL    (0x0A14)
 291 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL    (0x0A18)
 292 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL    (0x0A1C)
 293 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL    (0x0A20)
 294 #define CDC_RX_SIDETONE_IIR0_IIR_CTL            (0x0A24)
 295 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)
 296 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL    (0x0A2C)
 297 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL    (0x0A30)
 298 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL       (0x0A80)
 299 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL    (0x0A84)
 300 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL    (0x0A88)
 301 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL    (0x0A8C)
 302 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL    (0x0A90)
 303 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL    (0x0A94)
 304 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL    (0x0A98)
 305 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL    (0x0A9C)
 306 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL    (0x0AA0)
 307 #define CDC_RX_SIDETONE_IIR1_IIR_CTL            (0x0AA4)
 308 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)
 309 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL    (0x0AAC)
 310 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL    (0x0AB0)
 311 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0        (0x0B00)
 312 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1        (0x0B04)
 313 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2        (0x0B08)
 314 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3        (0x0B0C)
 315 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0        (0x0B10)
 316 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1        (0x0B14)
 317 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2        (0x0B18)
 318 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3        (0x0B1C)
 319 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL    (0x0B40)
 320 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1   (0x0B44)
 321 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL    (0x0B50)
 322 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1   (0x0B54)
 323 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL    (0x0C00)
 324 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0        (0x0C04)
 325 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL    (0x0C40)
 326 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0        (0x0C44)
 327 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL    (0x0C80)
 328 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0        (0x0C84)
 329 #define CDC_RX_EC_ASRC0_CLK_RST_CTL             (0x0D00)
 330 #define CDC_RX_EC_ASRC0_CTL0                    (0x0D04)
 331 #define CDC_RX_EC_ASRC0_CTL1                    (0x0D08)
 332 #define CDC_RX_EC_ASRC0_FIFO_CTL                (0x0D0C)
 333 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB    (0x0D10)
 334 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB    (0x0D14)
 335 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB    (0x0D18)
 336 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB    (0x0D1C)
 337 #define CDC_RX_EC_ASRC0_STATUS_FIFO             (0x0D20)
 338 #define CDC_RX_EC_ASRC1_CLK_RST_CTL             (0x0D40)
 339 #define CDC_RX_EC_ASRC1_CTL0                    (0x0D44)
 340 #define CDC_RX_EC_ASRC1_CTL1                    (0x0D48)
 341 #define CDC_RX_EC_ASRC1_FIFO_CTL                (0x0D4C)
 342 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB    (0x0D50)
 343 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB    (0x0D54)
 344 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB    (0x0D58)
 345 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB    (0x0D5C)
 346 #define CDC_RX_EC_ASRC1_STATUS_FIFO             (0x0D60)
 347 #define CDC_RX_EC_ASRC2_CLK_RST_CTL             (0x0D80)
 348 #define CDC_RX_EC_ASRC2_CTL0                    (0x0D84)
 349 #define CDC_RX_EC_ASRC2_CTL1                    (0x0D88)
 350 #define CDC_RX_EC_ASRC2_FIFO_CTL                (0x0D8C)
 351 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB    (0x0D90)
 352 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB    (0x0D94)
 353 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB    (0x0D98)
 354 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB    (0x0D9C)
 355 #define CDC_RX_EC_ASRC2_STATUS_FIFO             (0x0DA0)
 356 #define CDC_RX_DSD0_PATH_CTL                    (0x0F00)
 357 #define CDC_RX_DSD0_CFG0                        (0x0F04)
 358 #define CDC_RX_DSD0_CFG1                        (0x0F08)
 359 #define CDC_RX_DSD0_CFG2                        (0x0F0C)
 360 #define CDC_RX_DSD1_PATH_CTL                    (0x0F80)
 361 #define CDC_RX_DSD1_CFG0                        (0x0F84)
 362 #define CDC_RX_DSD1_CFG1                        (0x0F88)
 363 #define CDC_RX_DSD1_CFG2                        (0x0F8C)
 364 #define RX_MAX_OFFSET                           (0x0F8C)
 365
 366 #define MCLK_FREQ               9600000
 367
 368 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 369                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
 370                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 371                         SNDRV_PCM_RATE_384000)
 372 /* Fractional Rates */
 373 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
 374                                 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
 375
 376 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 377                 SNDRV_PCM_FMTBIT_S24_LE |\
 378                 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 379
 380 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 381                         SNDRV_PCM_RATE_48000)
 382 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 383                 SNDRV_PCM_FMTBIT_S24_LE |\
 384                 SNDRV_PCM_FMTBIT_S24_3LE)
 385
 386 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2
 387
 388 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0
 389 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f
 390 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f
 391
 392 #define COMP_MAX_COEFF 25
 393 #define RX_NUM_CLKS_MAX 5
 394
 395 struct comp_coeff_val {
 396         u8 lsb;
 397         u8 msb;
 398 };
 399
 400 enum {
 401         HPH_ULP,
 402         HPH_LOHIFI,
 403         HPH_MODE_MAX,
 404 };
 405
 406 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {
 407         {
 408                 {0x40, 0x00},
 409                 {0x4C, 0x00},
 410                 {0x5A, 0x00},
 411                 {0x6B, 0x00},
 412                 {0x7F, 0x00},
 413                 {0x97, 0x00},
 414                 {0xB3, 0x00},
 415                 {0xD5, 0x00},
 416                 {0xFD, 0x00},
 417                 {0x2D, 0x01},
 418                 {0x66, 0x01},
 419                 {0xA7, 0x01},
 420                 {0xF8, 0x01},
 421                 {0x57, 0x02},
 422                 {0xC7, 0x02},
 423                 {0x4B, 0x03},
 424                 {0xE9, 0x03},
 425                 {0xA3, 0x04},
 426                 {0x7D, 0x05},
 427                 {0x90, 0x06},
 428                 {0xD1, 0x07},
 429                 {0x49, 0x09},
 430                 {0x00, 0x0B},
 431                 {0x01, 0x0D},
 432                 {0x59, 0x0F},
 433         },
 434         {
 435                 {0x40, 0x00},
 436                 {0x4C, 0x00},
 437                 {0x5A, 0x00},
 438                 {0x6B, 0x00},
 439                 {0x80, 0x00},
 440                 {0x98, 0x00},
 441                 {0xB4, 0x00},
 442                 {0xD5, 0x00},
 443                 {0xFE, 0x00},
 444                 {0x2E, 0x01},
 445                 {0x66, 0x01},
 446                 {0xA9, 0x01},
 447                 {0xF8, 0x01},
 448                 {0x56, 0x02},
 449                 {0xC4, 0x02},
 450                 {0x4F, 0x03},
 451                 {0xF0, 0x03},
 452                 {0xAE, 0x04},
 453                 {0x8B, 0x05},
 454                 {0x8E, 0x06},
 455                 {0xBC, 0x07},
 456                 {0x56, 0x09},
 457                 {0x0F, 0x0B},
 458                 {0x13, 0x0D},
 459                 {0x6F, 0x0F},
 460         },
 461 };
 462
 463 struct rx_macro_reg_mask_val {
 464         u16 reg;
 465         u8 mask;
 466         u8 val;
 467 };
 468
 469 enum {
 470         INTERP_HPHL,
 471         INTERP_HPHR,
 472         INTERP_AUX,
 473         INTERP_MAX
 474 };
 475
 476 enum {
 477         RX_MACRO_RX0,
 478         RX_MACRO_RX1,
 479         RX_MACRO_RX2,
 480         RX_MACRO_RX3,
 481         RX_MACRO_RX4,
 482         RX_MACRO_RX5,
 483         RX_MACRO_PORTS_MAX
 484 };
 485
 486 enum {
 487         RX_MACRO_COMP1, /* HPH_L */
 488         RX_MACRO_COMP2, /* HPH_R */
 489         RX_MACRO_COMP_MAX
 490 };
 491
 492 enum {
 493         RX_MACRO_EC0_MUX = 0,
 494         RX_MACRO_EC1_MUX,
 495         RX_MACRO_EC2_MUX,
 496         RX_MACRO_EC_MUX_MAX,
 497 };
 498
 499 enum {
 500         INTn_1_INP_SEL_ZERO = 0,
 501         INTn_1_INP_SEL_DEC0,
 502         INTn_1_INP_SEL_DEC1,
 503         INTn_1_INP_SEL_IIR0,
 504         INTn_1_INP_SEL_IIR1,
 505         INTn_1_INP_SEL_RX0,
 506         INTn_1_INP_SEL_RX1,
 507         INTn_1_INP_SEL_RX2,
 508         INTn_1_INP_SEL_RX3,
 509         INTn_1_INP_SEL_RX4,
 510         INTn_1_INP_SEL_RX5,
 511 };
 512
 513 enum {
 514         INTn_2_INP_SEL_ZERO = 0,
 515         INTn_2_INP_SEL_RX0,
 516         INTn_2_INP_SEL_RX1,
 517         INTn_2_INP_SEL_RX2,
 518         INTn_2_INP_SEL_RX3,
 519         INTn_2_INP_SEL_RX4,
 520         INTn_2_INP_SEL_RX5,
 521 };
 522
 523 enum {
 524         INTERP_MAIN_PATH,
 525         INTERP_MIX_PATH,
 526 };
 527
 528 /* Codec supports 2 IIR filters */
 529 enum {
 530         IIR0 = 0,
 531         IIR1,
 532         IIR_MAX,
 533 };
 534
 535 /* Each IIR has 5 Filter Stages */
 536 enum {
 537         BAND1 = 0,
 538         BAND2,
 539         BAND3,
 540         BAND4,
 541         BAND5,
 542         BAND_MAX,
 543 };
 544
 545 #define RX_MACRO_IIR_FILTER_SIZE        (sizeof(u32) * BAND_MAX)
 546
 547 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
 548 { \
 549         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 550         .info = rx_macro_iir_filter_info, \
 551         .get = rx_macro_get_iir_band_audio_mixer, \
 552         .put = rx_macro_put_iir_band_audio_mixer, \
 553         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 554                 .iir_idx = iidx, \
 555                 .band_idx = bidx, \
 556                 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
 557         } \
 558 }
 559
 560 struct interp_sample_rate {
 561         int sample_rate;
 562         int rate_val;
 563 };
 564
 565 static struct interp_sample_rate sr_val_tbl[] = {
 566         {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
 567         {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
 568         {176400, 0xB}, {352800, 0xC},
 569 };
 570
 571 enum {
 572         RX_MACRO_AIF_INVALID = 0,
 573         RX_MACRO_AIF1_PB,
 574         RX_MACRO_AIF2_PB,
 575         RX_MACRO_AIF3_PB,
 576         RX_MACRO_AIF4_PB,
 577         RX_MACRO_AIF_ECHO,
 578         RX_MACRO_MAX_DAIS,
 579 };
 580
 581 enum {
 582         RX_MACRO_AIF1_CAP = 0,
 583         RX_MACRO_AIF2_CAP,
 584         RX_MACRO_AIF3_CAP,
 585         RX_MACRO_MAX_AIF_CAP_DAIS
 586 };
 587
 588 struct rx_macro {
 589         struct device *dev;
 590         int comp_enabled[RX_MACRO_COMP_MAX];
 591         /* Main path clock users count */
 592         int main_clk_users[INTERP_MAX];
 593         int rx_port_value[RX_MACRO_PORTS_MAX];
 594         u16 prim_int_users[INTERP_MAX];
 595         int rx_mclk_users;
 596         bool reset_swr;
 597         int clsh_users;
 598         int rx_mclk_cnt;
 599         bool is_ear_mode_on;
 600         bool hph_pwr_mode;
 601         bool hph_hd2_mode;
 602         struct snd_soc_component *component;
 603         unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];
 604         unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];
 605         u16 bit_width[RX_MACRO_MAX_DAIS];
 606         int is_softclip_on;
 607         int is_aux_hpf_on;
 608         int softclip_clk_users;
 609
 610         struct regmap *regmap;
 611         struct clk *mclk;
 612         struct clk *npl;
 613         struct clk *macro;
 614         struct clk *dcodec;
 615         struct clk *fsgen;
 616         struct clk_hw hw;
 617 };
 618 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
 619
 620 struct wcd_iir_filter_ctl {
 621         unsigned int iir_idx;
 622         unsigned int band_idx;
 623         struct soc_bytes_ext bytes_ext;
 624 };
 625
 626 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 627
 628 static const char * const rx_int_mix_mux_text[] = {
 629         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
 630 };
 631
 632 static const char * const rx_prim_mix_text[] = {
 633         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 634         "RX3", "RX4", "RX5"
 635 };
 636
 637 static const char * const rx_sidetone_mix_text[] = {
 638         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 639 };
 640
 641 static const char * const iir_inp_mux_text[] = {
 642         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3",
 643         "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
 644 };
 645
 646 static const char * const rx_int_dem_inp_mux_text[] = {
 647         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 648 };
 649
 650 static const char * const rx_int0_1_interp_mux_text[] = {
 651         "ZERO", "RX INT0_1 MIX1",
 652 };
 653
 654 static const char * const rx_int1_1_interp_mux_text[] = {
 655         "ZERO", "RX INT1_1 MIX1",
 656 };
 657
 658 static const char * const rx_int2_1_interp_mux_text[] = {
 659         "ZERO", "RX INT2_1 MIX1",
 660 };
 661
 662 static const char * const rx_int0_2_interp_mux_text[] = {
 663         "ZERO", "RX INT0_2 MUX",
 664 };
 665
 666 static const char * const rx_int1_2_interp_mux_text[] = {
 667         "ZERO", "RX INT1_2 MUX",
 668 };
 669
 670 static const char * const rx_int2_2_interp_mux_text[] = {
 671         "ZERO", "RX INT2_2 MUX",
 672 };
 673
 674 static const char *const rx_macro_mux_text[] = {
 675         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB"
 676 };
 677
 678 static const char *const rx_macro_hph_pwr_mode_text[] = {
 679         "ULP", "LOHIFI"
 680 };
 681
 682 static const char * const rx_echo_mux_text[] = {
 683         "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2"
 684 };
 685
 686 static const struct soc_enum rx_macro_hph_pwr_mode_enum =
 687                 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text);
 688 static const struct soc_enum rx_mix_tx2_mux_enum =
 689                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
 690 static const struct soc_enum rx_mix_tx1_mux_enum =
 691                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
 692 static const struct soc_enum rx_mix_tx0_mux_enum =
 693                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text);
 694
 695 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
 696                             rx_int_mix_mux_text);
 697 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
 698                             rx_int_mix_mux_text);
 699 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
 700                             rx_int_mix_mux_text);
 701
 702 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
 703                             rx_prim_mix_text);
 704 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,
 705                             rx_prim_mix_text);
 706 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,
 707                             rx_prim_mix_text);
 708 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
 709                             rx_prim_mix_text);
 710 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,
 711                             rx_prim_mix_text);
 712 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,
 713                             rx_prim_mix_text);
 714 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
 715                             rx_prim_mix_text);
 716 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,
 717                             rx_prim_mix_text);
 718 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,
 719                             rx_prim_mix_text);
 720
 721 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,
 722                             rx_sidetone_mix_text);
 723 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,
 724                             rx_sidetone_mix_text);
 725 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,
 726                             rx_sidetone_mix_text);
 727 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
 728                             iir_inp_mux_text);
 729 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
 730                             iir_inp_mux_text);
 731 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
 732                             iir_inp_mux_text);
 733 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
 734                             iir_inp_mux_text);
 735 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
 736                             iir_inp_mux_text);
 737 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
 738                             iir_inp_mux_text);
 739 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
 740                             iir_inp_mux_text);
 741 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
 742                             iir_inp_mux_text);
 743
 744 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
 745                             rx_int0_1_interp_mux_text);
 746 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
 747                             rx_int1_1_interp_mux_text);
 748 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
 749                             rx_int2_1_interp_mux_text);
 750 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
 751                             rx_int0_2_interp_mux_text);
 752 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
 753                             rx_int1_2_interp_mux_text);
 754 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
 755                             rx_int2_2_interp_mux_text);
 756 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
 757                             rx_int_dem_inp_mux_text);
 758 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
 759                             rx_int_dem_inp_mux_text);
 760
 761 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 762 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 763 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 764 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 765 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 766 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 767
 768 static const struct snd_kcontrol_new rx_mix_tx1_mux =
 769                 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
 770 static const struct snd_kcontrol_new rx_mix_tx2_mux =
 771                 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
 772 static const struct snd_kcontrol_new rx_int0_2_mux =
 773                 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum);
 774 static const struct snd_kcontrol_new rx_int1_2_mux =
 775                 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum);
 776 static const struct snd_kcontrol_new rx_int2_2_mux =
 777                 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum);
 778 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
 779                 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum);
 780 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
 781                 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum);
 782 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
 783                 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum);
 784 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
 785                 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum);
 786 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
 787                 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum);
 788 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
 789                 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum);
 790 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
 791                 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum);
 792 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
 793                 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum);
 794 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
 795                 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum);
 796 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
 797                 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum);
 798 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
 799                 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum);
 800 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
 801                 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum);
 802 static const struct snd_kcontrol_new iir0_inp0_mux =
 803                 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum);
 804 static const struct snd_kcontrol_new iir0_inp1_mux =
 805                 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum);
 806 static const struct snd_kcontrol_new iir0_inp2_mux =
 807                 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum);
 808 static const struct snd_kcontrol_new iir0_inp3_mux =
 809                 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum);
 810 static const struct snd_kcontrol_new iir1_inp0_mux =
 811                 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum);
 812 static const struct snd_kcontrol_new iir1_inp1_mux =
 813                 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum);
 814 static const struct snd_kcontrol_new iir1_inp2_mux =
 815                 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum);
 816 static const struct snd_kcontrol_new iir1_inp3_mux =
 817                 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum);
 818 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
 819                 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum);
 820 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
 821                 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum);
 822 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
 823                 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum);
 824 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
 825                 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum);
 826 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
 827                 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum);
 828 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
 829                 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum);
 830 static const struct snd_kcontrol_new rx_mix_tx0_mux =
 831                 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
 832
 833 static const struct reg_default rx_defaults[] = {
 834         /* RX Macro */
 835         { CDC_RX_TOP_TOP_CFG0, 0x00 },
 836         { CDC_RX_TOP_SWR_CTRL, 0x00 },
 837         { CDC_RX_TOP_DEBUG, 0x00 },
 838         { CDC_RX_TOP_DEBUG_BUS, 0x00 },
 839         { CDC_RX_TOP_DEBUG_EN0, 0x00 },
 840         { CDC_RX_TOP_DEBUG_EN1, 0x00 },
 841         { CDC_RX_TOP_DEBUG_EN2, 0x00 },
 842         { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
 843         { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
 844         { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
 845         { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
 846         { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
 847         { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
 848         { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
 849         { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
 850         { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
 851         { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
 852         { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
 853         { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
 854         { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
 855         { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
 856         { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
 857         { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
 858         { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
 859         { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
 860         { CDC_RX_TOP_RX_I2S_CTL, 0x0C },
 861         { CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
 862         { CDC_RX_TOP_I2S_CLK, 0x0C },
 863         { CDC_RX_TOP_I2S_RESET, 0x00 },
 864         { CDC_RX_TOP_I2S_MUX, 0x00 },
 865         { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
 866         { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
 867         { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
 868         { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
 869         { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
 870         { CDC_RX_SOFTCLIP_CRC, 0x00 },
 871         { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
 872         { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
 873         { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
 874         { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
 875         { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
 876         { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
 877         { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
 878         { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
 879         { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
 880         { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
 881         { CDC_RX_CLSH_CRC, 0x00 },
 882         { CDC_RX_CLSH_DLY_CTRL, 0x03 },
 883         { CDC_RX_CLSH_DECAY_CTRL, 0x02 },
 884         { CDC_RX_CLSH_HPH_V_PA, 0x1C },
 885         { CDC_RX_CLSH_EAR_V_PA, 0x39 },
 886         { CDC_RX_CLSH_HPH_V_HD, 0x0C },
 887         { CDC_RX_CLSH_EAR_V_HD, 0x0C },
 888         { CDC_RX_CLSH_K1_MSB, 0x01 },
 889         { CDC_RX_CLSH_K1_LSB, 0x00 },
 890         { CDC_RX_CLSH_K2_MSB, 0x00 },
 891         { CDC_RX_CLSH_K2_LSB, 0x80 },
 892         { CDC_RX_CLSH_IDLE_CTRL, 0x00 },
 893         { CDC_RX_CLSH_IDLE_HPH, 0x00 },
 894         { CDC_RX_CLSH_IDLE_EAR, 0x00 },
 895         { CDC_RX_CLSH_TEST0, 0x07 },
 896         { CDC_RX_CLSH_TEST1, 0x00 },
 897         { CDC_RX_CLSH_OVR_VREF, 0x00 },
 898         { CDC_RX_CLSH_CLSG_CTL, 0x02 },
 899         { CDC_RX_CLSH_CLSG_CFG1, 0x9A },
 900         { CDC_RX_CLSH_CLSG_CFG2, 0x10 },
 901         { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
 902         { CDC_RX_BCL_VBAT_CFG, 0x10 },
 903         { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
 904         { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
 905         { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
 906         { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
 907         { CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
 908         { CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
 909         { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
 910         { CDC_RX_BCL_VBAT_RF_PROC1, 0x00 },
 911         { CDC_RX_BCL_VBAT_TAC1, 0x00 },
 912         { CDC_RX_BCL_VBAT_TAC2, 0x18 },
 913         { CDC_RX_BCL_VBAT_TAC3, 0x18 },
 914         { CDC_RX_BCL_VBAT_TAC4, 0x03 },
 915         { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
 916         { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
 917         { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
 918         { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
 919         { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
 920         { CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
 921         { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
 922         { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
 923         { CDC_RX_BCL_VBAT_BAN, 0x0C },
 924         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
 925         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
 926         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
 927         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
 928         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
 929         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
 930         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
 931         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
 932         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
 933         { CDC_RX_BCL_VBAT_ATTN1, 0x04 },
 934         { CDC_RX_BCL_VBAT_ATTN2, 0x08 },
 935         { CDC_RX_BCL_VBAT_ATTN3, 0x0C },
 936         { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
 937         { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
 938         { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
 939         { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
 940         { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
 941         { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
 942         { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
 943         { CDC_RX_INTR_CTRL_CFG, 0x00 },
 944         { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
 945         { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
 946         { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
 947         { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
 948         { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
 949         { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
 950         { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
 951         { CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
 952         { CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
 953         { CDC_RX_INTR_CTRL_SET0, 0x00 },
 954         { CDC_RX_RX0_RX_PATH_CTL, 0x04 },
 955         { CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
 956         { CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
 957         { CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
 958         { CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
 959         { CDC_RX_RX0_RX_VOL_CTL, 0x00 },
 960         { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
 961         { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
 962         { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
 963         { CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
 964         { CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
 965         { CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
 966         { CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
 967         { CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
 968         { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
 969         { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
 970         { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
 971         { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
 972         { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
 973         { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
 974         { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
 975         { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
 976         { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
 977         { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
 978         { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
 979         { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
 980         { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
 981         { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
 982         { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
 983         { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
 984         { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
 985         { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
 986         { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
 987         { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
 988         { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
 989         { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
 990         { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
 991         { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
 992         { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
 993         { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
 994         { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
 995         { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
 996         { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
 997         { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
 998         { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
 999         { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1000         { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
1001         { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
1002         { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
1003         { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
1004         { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
1005         { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
1006         { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1007         { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1008         { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1009         { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
1010         { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
1011         { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
1012         { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
1013         { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
1014         { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
1015         { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
1016         { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
1017         { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1018         { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1019         { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1020         { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
1021         { CDC_RX_IDLE_DETECT_CFG0, 0x07 },
1022         { CDC_RX_IDLE_DETECT_CFG1, 0x3C },
1023         { CDC_RX_IDLE_DETECT_CFG2, 0x00 },
1024         { CDC_RX_IDLE_DETECT_CFG3, 0x00 },
1025         { CDC_RX_COMPANDER0_CTL0, 0x60 },
1026         { CDC_RX_COMPANDER0_CTL1, 0xDB },
1027         { CDC_RX_COMPANDER0_CTL2, 0xFF },
1028         { CDC_RX_COMPANDER0_CTL3, 0x35 },
1029         { CDC_RX_COMPANDER0_CTL4, 0xFF },
1030         { CDC_RX_COMPANDER0_CTL5, 0x00 },
1031         { CDC_RX_COMPANDER0_CTL6, 0x01 },
1032         { CDC_RX_COMPANDER0_CTL7, 0x28 },
1033         { CDC_RX_COMPANDER1_CTL0, 0x60 },
1034         { CDC_RX_COMPANDER1_CTL1, 0xDB },
1035         { CDC_RX_COMPANDER1_CTL2, 0xFF },
1036         { CDC_RX_COMPANDER1_CTL3, 0x35 },
1037         { CDC_RX_COMPANDER1_CTL4, 0xFF },
1038         { CDC_RX_COMPANDER1_CTL5, 0x00 },
1039         { CDC_RX_COMPANDER1_CTL6, 0x01 },
1040         { CDC_RX_COMPANDER1_CTL7, 0x28 },
1041         { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
1042         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
1043         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
1044         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
1045         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
1046         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
1047         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
1048         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
1049         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
1050         { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
1051         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
1052         { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
1053         { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
1054         { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
1055         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
1056         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
1057         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
1058         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
1059         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
1060         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
1061         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
1062         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
1063         { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
1064         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
1065         { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
1066         { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
1067         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
1068         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
1069         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
1070         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
1071         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
1072         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
1073         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
1074         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
1075         { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
1076         { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
1077         { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
1078         { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
1079         { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
1080         { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
1081         { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
1082         { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
1083         { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
1084         { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
1085         { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
1086         { CDC_RX_EC_ASRC0_CTL0, 0x00 },
1087         { CDC_RX_EC_ASRC0_CTL1, 0x00 },
1088         { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
1089         { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
1090         { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
1091         { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
1092         { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
1093         { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
1094         { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
1095         { CDC_RX_EC_ASRC1_CTL0, 0x00 },
1096         { CDC_RX_EC_ASRC1_CTL1, 0x00 },
1097         { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
1098         { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
1099         { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
1100         { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
1101         { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
1102         { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
1103         { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
1104         { CDC_RX_EC_ASRC2_CTL0, 0x00 },
1105         { CDC_RX_EC_ASRC2_CTL1, 0x00 },
1106         { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
1107         { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
1108         { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
1109         { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
1110         { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
1111         { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
1112         { CDC_RX_DSD0_PATH_CTL, 0x00 },
1113         { CDC_RX_DSD0_CFG0, 0x00 },
1114         { CDC_RX_DSD0_CFG1, 0x62 },
1115         { CDC_RX_DSD0_CFG2, 0x96 },
1116         { CDC_RX_DSD1_PATH_CTL, 0x00 },
1117         { CDC_RX_DSD1_CFG0, 0x00 },
1118         { CDC_RX_DSD1_CFG1, 0x62 },
1119         { CDC_RX_DSD1_CFG2, 0x96 },
1120 };
1121
1122 static bool rx_is_wronly_register(struct device *dev,
1123                                         unsigned int reg)
1124 {
1125         switch (reg) {
1126         case CDC_RX_BCL_VBAT_GAIN_UPD_MON:
1127         case CDC_RX_INTR_CTRL_CLR_COMMIT:
1128         case CDC_RX_INTR_CTRL_PIN1_CLEAR0:
1129         case CDC_RX_INTR_CTRL_PIN2_CLEAR0:
1130                 return true;
1131         }
1132
1133         return false;
1134 }
1135
1136 static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
1137 {
1138         /* Update volatile list for rx/tx macros */
1139         switch (reg) {
1140         case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1141         case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1142         case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1143         case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1144         case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1145         case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1146         case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1147         case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1148         case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1149         case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1150         case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1151         case CDC_RX_BCL_VBAT_DECODE_ST:
1152         case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1153         case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1154         case CDC_RX_COMPANDER0_CTL6:
1155         case CDC_RX_COMPANDER1_CTL6:
1156         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1157         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1158         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1159         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1160         case CDC_RX_EC_ASRC0_STATUS_FIFO:
1161         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1162         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1163         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1164         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1165         case CDC_RX_EC_ASRC1_STATUS_FIFO:
1166         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1167         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1168         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1169         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1170         case CDC_RX_EC_ASRC2_STATUS_FIFO:
1171                 return true;
1172         }
1173         return false;
1174 }
1175
1176 static bool rx_is_rw_register(struct device *dev, unsigned int reg)
1177 {
1178         switch (reg) {
1179         case CDC_RX_TOP_TOP_CFG0:
1180         case CDC_RX_TOP_SWR_CTRL:
1181         case CDC_RX_TOP_DEBUG:
1182         case CDC_RX_TOP_DEBUG_BUS:
1183         case CDC_RX_TOP_DEBUG_EN0:
1184         case CDC_RX_TOP_DEBUG_EN1:
1185         case CDC_RX_TOP_DEBUG_EN2:
1186         case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1187         case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1188         case CDC_RX_TOP_HPHL_COMP_LUT:
1189         case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1190         case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1191         case CDC_RX_TOP_HPHR_COMP_LUT:
1192         case CDC_RX_TOP_DSD0_DEBUG_CFG0:
1193         case CDC_RX_TOP_DSD0_DEBUG_CFG1:
1194         case CDC_RX_TOP_DSD0_DEBUG_CFG3:
1195         case CDC_RX_TOP_DSD1_DEBUG_CFG0:
1196         case CDC_RX_TOP_DSD1_DEBUG_CFG1:
1197         case CDC_RX_TOP_DSD1_DEBUG_CFG3:
1198         case CDC_RX_TOP_RX_I2S_CTL:
1199         case CDC_RX_TOP_TX_I2S2_CTL:
1200         case CDC_RX_TOP_I2S_CLK:
1201         case CDC_RX_TOP_I2S_RESET:
1202         case CDC_RX_TOP_I2S_MUX:
1203         case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:
1204         case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:
1205         case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:
1206         case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:
1207         case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:
1208         case CDC_RX_SOFTCLIP_CRC:
1209         case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:
1210         case CDC_RX_INP_MUX_RX_INT0_CFG0:
1211         case CDC_RX_INP_MUX_RX_INT0_CFG1:
1212         case CDC_RX_INP_MUX_RX_INT1_CFG0:
1213         case CDC_RX_INP_MUX_RX_INT1_CFG1:
1214         case CDC_RX_INP_MUX_RX_INT2_CFG0:
1215         case CDC_RX_INP_MUX_RX_INT2_CFG1:
1216         case CDC_RX_INP_MUX_RX_MIX_CFG4:
1217         case CDC_RX_INP_MUX_RX_MIX_CFG5:
1218         case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:
1219         case CDC_RX_CLSH_CRC:
1220         case CDC_RX_CLSH_DLY_CTRL:
1221         case CDC_RX_CLSH_DECAY_CTRL:
1222         case CDC_RX_CLSH_HPH_V_PA:
1223         case CDC_RX_CLSH_EAR_V_PA:
1224         case CDC_RX_CLSH_HPH_V_HD:
1225         case CDC_RX_CLSH_EAR_V_HD:
1226         case CDC_RX_CLSH_K1_MSB:
1227         case CDC_RX_CLSH_K1_LSB:
1228         case CDC_RX_CLSH_K2_MSB:
1229         case CDC_RX_CLSH_K2_LSB:
1230         case CDC_RX_CLSH_IDLE_CTRL:
1231         case CDC_RX_CLSH_IDLE_HPH:
1232         case CDC_RX_CLSH_IDLE_EAR:
1233         case CDC_RX_CLSH_TEST0:
1234         case CDC_RX_CLSH_TEST1:
1235         case CDC_RX_CLSH_OVR_VREF:
1236         case CDC_RX_CLSH_CLSG_CTL:
1237         case CDC_RX_CLSH_CLSG_CFG1:
1238         case CDC_RX_CLSH_CLSG_CFG2:
1239         case CDC_RX_BCL_VBAT_PATH_CTL:
1240         case CDC_RX_BCL_VBAT_CFG:
1241         case CDC_RX_BCL_VBAT_ADC_CAL1:
1242         case CDC_RX_BCL_VBAT_ADC_CAL2:
1243         case CDC_RX_BCL_VBAT_ADC_CAL3:
1244         case CDC_RX_BCL_VBAT_PK_EST1:
1245         case CDC_RX_BCL_VBAT_PK_EST2:
1246         case CDC_RX_BCL_VBAT_PK_EST3:
1247         case CDC_RX_BCL_VBAT_RF_PROC1:
1248         case CDC_RX_BCL_VBAT_RF_PROC2:
1249         case CDC_RX_BCL_VBAT_TAC1:
1250         case CDC_RX_BCL_VBAT_TAC2:
1251         case CDC_RX_BCL_VBAT_TAC3:
1252         case CDC_RX_BCL_VBAT_TAC4:
1253         case CDC_RX_BCL_VBAT_GAIN_UPD1:
1254         case CDC_RX_BCL_VBAT_GAIN_UPD2:
1255         case CDC_RX_BCL_VBAT_GAIN_UPD3:
1256         case CDC_RX_BCL_VBAT_GAIN_UPD4:
1257         case CDC_RX_BCL_VBAT_GAIN_UPD5:
1258         case CDC_RX_BCL_VBAT_DEBUG1:
1259         case CDC_RX_BCL_VBAT_BAN:
1260         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:
1261         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:
1262         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:
1263         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:
1264         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:
1265         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:
1266         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:
1267         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:
1268         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:
1269         case CDC_RX_BCL_VBAT_ATTN1:
1270         case CDC_RX_BCL_VBAT_ATTN2:
1271         case CDC_RX_BCL_VBAT_ATTN3:
1272         case CDC_RX_BCL_VBAT_DECODE_CTL1:
1273         case CDC_RX_BCL_VBAT_DECODE_CTL2:
1274         case CDC_RX_BCL_VBAT_DECODE_CFG1:
1275         case CDC_RX_BCL_VBAT_DECODE_CFG2:
1276         case CDC_RX_BCL_VBAT_DECODE_CFG3:
1277         case CDC_RX_BCL_VBAT_DECODE_CFG4:
1278         case CDC_RX_INTR_CTRL_CFG:
1279         case CDC_RX_INTR_CTRL_PIN1_MASK0:
1280         case CDC_RX_INTR_CTRL_PIN2_MASK0:
1281         case CDC_RX_INTR_CTRL_LEVEL0:
1282         case CDC_RX_INTR_CTRL_BYPASS0:
1283         case CDC_RX_INTR_CTRL_SET0:
1284         case CDC_RX_RX0_RX_PATH_CTL:
1285         case CDC_RX_RX0_RX_PATH_CFG0:
1286         case CDC_RX_RX0_RX_PATH_CFG1:
1287         case CDC_RX_RX0_RX_PATH_CFG2:
1288         case CDC_RX_RX0_RX_PATH_CFG3:
1289         case CDC_RX_RX0_RX_VOL_CTL:
1290         case CDC_RX_RX0_RX_PATH_MIX_CTL:
1291         case CDC_RX_RX0_RX_PATH_MIX_CFG:
1292         case CDC_RX_RX0_RX_VOL_MIX_CTL:
1293         case CDC_RX_RX0_RX_PATH_SEC1:
1294         case CDC_RX_RX0_RX_PATH_SEC2:
1295         case CDC_RX_RX0_RX_PATH_SEC3:
1296         case CDC_RX_RX0_RX_PATH_SEC4:
1297         case CDC_RX_RX0_RX_PATH_SEC7:
1298         case CDC_RX_RX0_RX_PATH_MIX_SEC0:
1299         case CDC_RX_RX0_RX_PATH_MIX_SEC1:
1300         case CDC_RX_RX0_RX_PATH_DSM_CTL:
1301         case CDC_RX_RX0_RX_PATH_DSM_DATA1:
1302         case CDC_RX_RX0_RX_PATH_DSM_DATA2:
1303         case CDC_RX_RX0_RX_PATH_DSM_DATA3:
1304         case CDC_RX_RX0_RX_PATH_DSM_DATA4:
1305         case CDC_RX_RX0_RX_PATH_DSM_DATA5:
1306         case CDC_RX_RX0_RX_PATH_DSM_DATA6:
1307         case CDC_RX_RX1_RX_PATH_CTL:
1308         case CDC_RX_RX1_RX_PATH_CFG0:
1309         case CDC_RX_RX1_RX_PATH_CFG1:
1310         case CDC_RX_RX1_RX_PATH_CFG2:
1311         case CDC_RX_RX1_RX_PATH_CFG3:
1312         case CDC_RX_RX1_RX_VOL_CTL:
1313         case CDC_RX_RX1_RX_PATH_MIX_CTL:
1314         case CDC_RX_RX1_RX_PATH_MIX_CFG:
1315         case CDC_RX_RX1_RX_VOL_MIX_CTL:
1316         case CDC_RX_RX1_RX_PATH_SEC1:
1317         case CDC_RX_RX1_RX_PATH_SEC2:
1318         case CDC_RX_RX1_RX_PATH_SEC3:
1319         case CDC_RX_RX1_RX_PATH_SEC4:
1320         case CDC_RX_RX1_RX_PATH_SEC7:
1321         case CDC_RX_RX1_RX_PATH_MIX_SEC0:
1322         case CDC_RX_RX1_RX_PATH_MIX_SEC1:
1323         case CDC_RX_RX1_RX_PATH_DSM_CTL:
1324         case CDC_RX_RX1_RX_PATH_DSM_DATA1:
1325         case CDC_RX_RX1_RX_PATH_DSM_DATA2:
1326         case CDC_RX_RX1_RX_PATH_DSM_DATA3:
1327         case CDC_RX_RX1_RX_PATH_DSM_DATA4:
1328         case CDC_RX_RX1_RX_PATH_DSM_DATA5:
1329         case CDC_RX_RX1_RX_PATH_DSM_DATA6:
1330         case CDC_RX_RX2_RX_PATH_CTL:
1331         case CDC_RX_RX2_RX_PATH_CFG0:
1332         case CDC_RX_RX2_RX_PATH_CFG1:
1333         case CDC_RX_RX2_RX_PATH_CFG2:
1334         case CDC_RX_RX2_RX_PATH_CFG3:
1335         case CDC_RX_RX2_RX_VOL_CTL:
1336         case CDC_RX_RX2_RX_PATH_MIX_CTL:
1337         case CDC_RX_RX2_RX_PATH_MIX_CFG:
1338         case CDC_RX_RX2_RX_VOL_MIX_CTL:
1339         case CDC_RX_RX2_RX_PATH_SEC0:
1340         case CDC_RX_RX2_RX_PATH_SEC1:
1341         case CDC_RX_RX2_RX_PATH_SEC2:
1342         case CDC_RX_RX2_RX_PATH_SEC3:
1343         case CDC_RX_RX2_RX_PATH_SEC4:
1344         case CDC_RX_RX2_RX_PATH_SEC5:
1345         case CDC_RX_RX2_RX_PATH_SEC6:
1346         case CDC_RX_RX2_RX_PATH_SEC7:
1347         case CDC_RX_RX2_RX_PATH_MIX_SEC0:
1348         case CDC_RX_RX2_RX_PATH_MIX_SEC1:
1349         case CDC_RX_RX2_RX_PATH_DSM_CTL:
1350         case CDC_RX_IDLE_DETECT_PATH_CTL:
1351         case CDC_RX_IDLE_DETECT_CFG0:
1352         case CDC_RX_IDLE_DETECT_CFG1:
1353         case CDC_RX_IDLE_DETECT_CFG2:
1354         case CDC_RX_IDLE_DETECT_CFG3:
1355         case CDC_RX_COMPANDER0_CTL0:
1356         case CDC_RX_COMPANDER0_CTL1:
1357         case CDC_RX_COMPANDER0_CTL2:
1358         case CDC_RX_COMPANDER0_CTL3:
1359         case CDC_RX_COMPANDER0_CTL4:
1360         case CDC_RX_COMPANDER0_CTL5:
1361         case CDC_RX_COMPANDER0_CTL7:
1362         case CDC_RX_COMPANDER1_CTL0:
1363         case CDC_RX_COMPANDER1_CTL1:
1364         case CDC_RX_COMPANDER1_CTL2:
1365         case CDC_RX_COMPANDER1_CTL3:
1366         case CDC_RX_COMPANDER1_CTL4:
1367         case CDC_RX_COMPANDER1_CTL5:
1368         case CDC_RX_COMPANDER1_CTL7:
1369         case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:
1370         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:
1371         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:
1372         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:
1373         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:
1374         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:
1375         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:
1376         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:
1377         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:
1378         case CDC_RX_SIDETONE_IIR0_IIR_CTL:
1379         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:
1380         case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
1381         case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
1382         case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:
1383         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:
1384         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:
1385         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:
1386         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:
1387         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:
1388         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:
1389         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:
1390         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:
1391         case CDC_RX_SIDETONE_IIR1_IIR_CTL:
1392         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:
1393         case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
1394         case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
1395         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:
1396         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:
1397         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:
1398         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:
1399         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:
1400         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:
1401         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:
1402         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:
1403         case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:
1404         case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:
1405         case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:
1406         case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:
1407         case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:
1408         case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:
1409         case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:
1410         case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:
1411         case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:
1412         case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:
1413         case CDC_RX_EC_ASRC0_CLK_RST_CTL:
1414         case CDC_RX_EC_ASRC0_CTL0:
1415         case CDC_RX_EC_ASRC0_CTL1:
1416         case CDC_RX_EC_ASRC0_FIFO_CTL:
1417         case CDC_RX_EC_ASRC1_CLK_RST_CTL:
1418         case CDC_RX_EC_ASRC1_CTL0:
1419         case CDC_RX_EC_ASRC1_CTL1:
1420         case CDC_RX_EC_ASRC1_FIFO_CTL:
1421         case CDC_RX_EC_ASRC2_CLK_RST_CTL:
1422         case CDC_RX_EC_ASRC2_CTL0:
1423         case CDC_RX_EC_ASRC2_CTL1:
1424         case CDC_RX_EC_ASRC2_FIFO_CTL:
1425         case CDC_RX_DSD0_PATH_CTL:
1426         case CDC_RX_DSD0_CFG0:
1427         case CDC_RX_DSD0_CFG1:
1428         case CDC_RX_DSD0_CFG2:
1429         case CDC_RX_DSD1_PATH_CTL:
1430         case CDC_RX_DSD1_CFG0:
1431         case CDC_RX_DSD1_CFG1:
1432         case CDC_RX_DSD1_CFG2:
1433                 return true;
1434         }
1435
1436         return false;
1437 }
1438
1439 static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
1440 {
1441         bool ret;
1442
1443         ret = rx_is_rw_register(dev, reg);
1444         if (!ret)
1445                 return rx_is_wronly_register(dev, reg);
1446
1447         return ret;
1448 }
1449
1450 static bool rx_is_readable_register(struct device *dev, unsigned int reg)
1451 {
1452         switch (reg) {
1453         case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1454         case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1455         case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1456         case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1457         case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1458         case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1459         case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1460         case CDC_RX_BCL_VBAT_DECODE_ST:
1461         case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1462         case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1463         case CDC_RX_COMPANDER0_CTL6:
1464         case CDC_RX_COMPANDER1_CTL6:
1465         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1466         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1467         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1468         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1469         case CDC_RX_EC_ASRC0_STATUS_FIFO:
1470         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1471         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1472         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1473         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1474         case CDC_RX_EC_ASRC1_STATUS_FIFO:
1475         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1476         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1477         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1478         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1479         case CDC_RX_EC_ASRC2_STATUS_FIFO:
1480                 return true;
1481         }
1482
1483         return rx_is_rw_register(dev, reg);
1484 }
1485
1486 static const struct regmap_config rx_regmap_config = {
1487         .name = "rx_macro",
1488         .reg_bits = 16,
1489         .val_bits = 32, /* 8 but with 32 bit read/write */
1490         .reg_stride = 4,
1491         .cache_type = REGCACHE_FLAT,
1492         .reg_defaults = rx_defaults,
1493         .num_reg_defaults = ARRAY_SIZE(rx_defaults),
1494         .max_register = RX_MAX_OFFSET,
1495         .writeable_reg = rx_is_writeable_register,
1496         .volatile_reg = rx_is_volatile_register,
1497         .readable_reg = rx_is_readable_register,
1498 };
1499
1500 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
1501                                         struct snd_ctl_elem_value *ucontrol)
1502 {
1503         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1504         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1505         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1506         unsigned short look_ahead_dly_reg;
1507         unsigned int val;
1508
1509         val = ucontrol->value.enumerated.item[0];
1510
1511         if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
1512                 look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
1513         else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
1514                 look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
1515
1516         /* Set Look Ahead Delay */
1517         if (val)
1518                 snd_soc_component_update_bits(component, look_ahead_dly_reg,
1519                                               CDC_RX_DLY_ZN_EN_MASK,
1520                                               CDC_RX_DLY_ZN_ENABLE);
1521         else
1522                 snd_soc_component_update_bits(component, look_ahead_dly_reg,
1523                                               CDC_RX_DLY_ZN_EN_MASK, 0);
1524         /* Set DEM INP Select */
1525         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1526 }
1527
1528 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1529                 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum,
1530                   snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1531 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1532                 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
1533                   snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1534
1535 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1536                                                int rate_reg_val, u32 sample_rate)
1537 {
1538
1539         u8 int_1_mix1_inp;
1540         u32 j, port;
1541         u16 int_mux_cfg0, int_mux_cfg1;
1542         u16 int_fs_reg;
1543         u8 inp0_sel, inp1_sel, inp2_sel;
1544         struct snd_soc_component *component = dai->component;
1545         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1546
1547         for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1548                 int_1_mix1_inp = port;
1549                 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0;
1550                 /*
1551                  * Loop through all interpolator MUX inputs and find out
1552                  * to which interpolator input, the rx port
1553                  * is connected
1554                  */
1555                 for (j = 0; j < INTERP_MAX; j++) {
1556                         int_mux_cfg1 = int_mux_cfg0 + 4;
1557
1558                         inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1559                                                                 CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1560                         inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1561                                                                 CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1562                         inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
1563                                                                 CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1564
1565                         if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1566                             (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1567                             (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1568                                 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
1569                                 /* sample_rate is in Hz */
1570                                 snd_soc_component_update_bits(component, int_fs_reg,
1571                                                               CDC_RX_PATH_PCM_RATE_MASK,
1572                                                               rate_reg_val);
1573                         }
1574                         int_mux_cfg0 += 8;
1575                 }
1576         }
1577
1578         return 0;
1579 }
1580
1581 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1582                                               int rate_reg_val, u32 sample_rate)
1583 {
1584
1585         u8 int_2_inp;
1586         u32 j, port;
1587         u16 int_mux_cfg1, int_fs_reg;
1588         u8 int_mux_cfg1_val;
1589         struct snd_soc_component *component = dai->component;
1590         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1591
1592         for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1593                 int_2_inp = port;
1594
1595                 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1;
1596                 for (j = 0; j < INTERP_MAX; j++) {
1597                         int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
1598                                                                         CDC_RX_INTX_2_SEL_MASK);
1599
1600                         if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1601                                 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1602                                 snd_soc_component_update_bits(component, int_fs_reg,
1603                                                               CDC_RX_RXn_MIX_PCM_RATE_MASK,
1604                                                               rate_reg_val);
1605                         }
1606                         int_mux_cfg1 += 8;
1607                 }
1608         }
1609         return 0;
1610 }
1611
1612 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1613                                           u32 sample_rate)
1614 {
1615         int rate_val = 0;
1616         int i, ret;
1617
1618         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)
1619                 if (sample_rate == sr_val_tbl[i].sample_rate)
1620                         rate_val = sr_val_tbl[i].rate_val;
1621
1622         ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate);
1623         if (ret)
1624                 return ret;
1625
1626         ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate);
1627
1628         return ret;
1629 }
1630
1631 static int rx_macro_hw_params(struct snd_pcm_substream *substream,
1632                               struct snd_pcm_hw_params *params,
1633                               struct snd_soc_dai *dai)
1634 {
1635         struct snd_soc_component *component = dai->component;
1636         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1637         int ret;
1638
1639         switch (substream->stream) {
1640         case SNDRV_PCM_STREAM_PLAYBACK:
1641                 ret = rx_macro_set_interpolator_rate(dai, params_rate(params));
1642                 if (ret) {
1643                         dev_err(component->dev, "%s: cannot set sample rate: %u\n",
1644                                 __func__, params_rate(params));
1645                         return ret;
1646                 }
1647                 rx->bit_width[dai->id] = params_width(params);
1648                 break;
1649         default:
1650                 break;
1651         }
1652         return 0;
1653 }
1654
1655 static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
1656                                     unsigned int *tx_num, unsigned int *tx_slot,
1657                                     unsigned int *rx_num, unsigned int *rx_slot)
1658 {
1659         struct snd_soc_component *component = dai->component;
1660         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1661         u16 val, mask = 0, cnt = 0, temp;
1662
1663         switch (dai->id) {
1664         case RX_MACRO_AIF1_PB:
1665         case RX_MACRO_AIF2_PB:
1666         case RX_MACRO_AIF3_PB:
1667         case RX_MACRO_AIF4_PB:
1668                 for_each_set_bit(temp, &rx->active_ch_mask[dai->id],
1669                          RX_MACRO_PORTS_MAX) {
1670                         mask |= (1 << temp);
1671                         if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT)
1672                                 break;
1673                 }
1674                 /*
1675                  * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3
1676                  * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3
1677                  * CDC_DMA_RX_2 port drives RX4     -- ch_mask 0x1
1678                  * CDC_DMA_RX_3 port drives RX5     -- ch_mask 0x1
1679                  * AIFn can pair to any CDC_DMA_RX_n port.
1680                  * In general, below convention is used::
1681                  * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/
1682                  * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4)
1683                  */
1684                 if (mask & 0x0C)
1685                         mask = mask >> 2;
1686                 if ((mask & 0x10) || (mask & 0x20))
1687                         mask = 0x1;
1688                 *rx_slot = mask;
1689                 *rx_num = rx->active_ch_cnt[dai->id];
1690                 break;
1691         case RX_MACRO_AIF_ECHO:
1692                 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4);
1693                 if (val & RX_MACRO_EC_MIX_TX0_MASK) {
1694                         mask |= 0x1;
1695                         cnt++;
1696                 }
1697                 if (val & RX_MACRO_EC_MIX_TX1_MASK) {
1698                         mask |= 0x2;
1699                         cnt++;
1700                 }
1701                 val = snd_soc_component_read(component,
1702                         CDC_RX_INP_MUX_RX_MIX_CFG5);
1703                 if (val & RX_MACRO_EC_MIX_TX2_MASK) {
1704                         mask |= 0x4;
1705                         cnt++;
1706                 }
1707                 *tx_slot = mask;
1708                 *tx_num = cnt;
1709                 break;
1710         default:
1711                 dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1712                 break;
1713         }
1714         return 0;
1715 }
1716
1717 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1718 {
1719         struct snd_soc_component *component = dai->component;
1720         uint16_t j, reg, mix_reg, dsm_reg;
1721         u16 int_mux_cfg0, int_mux_cfg1;
1722         u8 int_mux_cfg0_val, int_mux_cfg1_val;
1723
1724         switch (dai->id) {
1725         case RX_MACRO_AIF1_PB:
1726         case RX_MACRO_AIF2_PB:
1727         case RX_MACRO_AIF3_PB:
1728         case RX_MACRO_AIF4_PB:
1729                 for (j = 0; j < INTERP_MAX; j++) {
1730                         reg = CDC_RX_RXn_RX_PATH_CTL(j);
1731                         mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1732                         dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
1733
1734                         if (mute) {
1735                                 snd_soc_component_update_bits(component, reg,
1736                                                               CDC_RX_PATH_PGA_MUTE_MASK,
1737                                                               CDC_RX_PATH_PGA_MUTE_ENABLE);
1738                                 snd_soc_component_update_bits(component, mix_reg,
1739                                                               CDC_RX_PATH_PGA_MUTE_MASK,
1740                                                               CDC_RX_PATH_PGA_MUTE_ENABLE);
1741                         } else {
1742                                 snd_soc_component_update_bits(component, reg,
1743                                                               CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1744                                 snd_soc_component_update_bits(component, mix_reg,
1745                                                               CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1746                         }
1747
1748                         if (j == INTERP_AUX)
1749                                 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
1750
1751                         int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
1752                         int_mux_cfg1 = int_mux_cfg0 + 4;
1753                         int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
1754                         int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
1755
1756                         if (snd_soc_component_read(component, dsm_reg) & 0x01) {
1757                                 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
1758                                         snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1759                                 if (int_mux_cfg1_val & 0x0F) {
1760                                         snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1761                                         snd_soc_component_update_bits(component, mix_reg, 0x20,
1762                                                                       0x20);
1763                                 }
1764                         }
1765                 }
1766                 break;
1767         default:
1768                 break;
1769         }
1770         return 0;
1771 }
1772
1773 static const struct snd_soc_dai_ops rx_macro_dai_ops = {
1774         .hw_params = rx_macro_hw_params,
1775         .get_channel_map = rx_macro_get_channel_map,
1776         .mute_stream = rx_macro_digital_mute,
1777 };
1778
1779 static struct snd_soc_dai_driver rx_macro_dai[] = {
1780         {
1781                 .name = "rx_macro_rx1",
1782                 .id = RX_MACRO_AIF1_PB,
1783                 .playback = {
1784                         .stream_name = "RX_MACRO_AIF1 Playback",
1785                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1786                         .formats = RX_MACRO_FORMATS,
1787                         .rate_max = 384000,
1788                         .rate_min = 8000,
1789                         .channels_min = 1,
1790                         .channels_max = 2,
1791                 },
1792                 .ops = &rx_macro_dai_ops,
1793         },
1794         {
1795                 .name = "rx_macro_rx2",
1796                 .id = RX_MACRO_AIF2_PB,
1797                 .playback = {
1798                         .stream_name = "RX_MACRO_AIF2 Playback",
1799                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1800                         .formats = RX_MACRO_FORMATS,
1801                         .rate_max = 384000,
1802                         .rate_min = 8000,
1803                         .channels_min = 1,
1804                         .channels_max = 2,
1805                 },
1806                 .ops = &rx_macro_dai_ops,
1807         },
1808         {
1809                 .name = "rx_macro_rx3",
1810                 .id = RX_MACRO_AIF3_PB,
1811                 .playback = {
1812                         .stream_name = "RX_MACRO_AIF3 Playback",
1813                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1814                         .formats = RX_MACRO_FORMATS,
1815                         .rate_max = 384000,
1816                         .rate_min = 8000,
1817                         .channels_min = 1,
1818                         .channels_max = 2,
1819                 },
1820                 .ops = &rx_macro_dai_ops,
1821         },
1822         {
1823                 .name = "rx_macro_rx4",
1824                 .id = RX_MACRO_AIF4_PB,
1825                 .playback = {
1826                         .stream_name = "RX_MACRO_AIF4 Playback",
1827                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1828                         .formats = RX_MACRO_FORMATS,
1829                         .rate_max = 384000,
1830                         .rate_min = 8000,
1831                         .channels_min = 1,
1832                         .channels_max = 2,
1833                 },
1834                 .ops = &rx_macro_dai_ops,
1835         },
1836         {
1837                 .name = "rx_macro_echo",
1838                 .id = RX_MACRO_AIF_ECHO,
1839                 .capture = {
1840                         .stream_name = "RX_AIF_ECHO Capture",
1841                         .rates = RX_MACRO_ECHO_RATES,
1842                         .formats = RX_MACRO_ECHO_FORMATS,
1843                         .rate_max = 48000,
1844                         .rate_min = 8000,
1845                         .channels_min = 1,
1846                         .channels_max = 3,
1847                 },
1848                 .ops = &rx_macro_dai_ops,
1849         },
1850 };
1851
1852 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
1853 {
1854         struct regmap *regmap = rx->regmap;
1855
1856         if (mclk_enable) {
1857                 if (rx->rx_mclk_users == 0) {
1858                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1859                                            CDC_RX_CLK_MCLK_EN_MASK |
1860                                            CDC_RX_CLK_MCLK2_EN_MASK,
1861                                            CDC_RX_CLK_MCLK_ENABLE |
1862                                            CDC_RX_CLK_MCLK2_ENABLE);
1863                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1864                                            CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00);
1865                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1866                                            CDC_RX_FS_MCLK_CNT_EN_MASK,
1867                                            CDC_RX_FS_MCLK_CNT_ENABLE);
1868                         regcache_mark_dirty(regmap);
1869                         regcache_sync(regmap);
1870                 }
1871                 rx->rx_mclk_users++;
1872         } else {
1873                 if (rx->rx_mclk_users <= 0) {
1874                         dev_err(rx->dev, "%s: clock already disabled\n", __func__);
1875                         rx->rx_mclk_users = 0;
1876                         return;
1877                 }
1878                 rx->rx_mclk_users--;
1879                 if (rx->rx_mclk_users == 0) {
1880                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1881                                            CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0);
1882                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1883                                            CDC_RX_FS_MCLK_CNT_CLR_MASK,
1884                                            CDC_RX_FS_MCLK_CNT_CLR);
1885                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1886                                            CDC_RX_CLK_MCLK_EN_MASK |
1887                                            CDC_RX_CLK_MCLK2_EN_MASK, 0x0);
1888                 }
1889         }
1890 }
1891
1892 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w,
1893                                struct snd_kcontrol *kcontrol, int event)
1894 {
1895         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1896         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1897         int ret = 0;
1898
1899         switch (event) {
1900         case SND_SOC_DAPM_PRE_PMU:
1901                 rx_macro_mclk_enable(rx, true);
1902                 break;
1903         case SND_SOC_DAPM_POST_PMD:
1904                 rx_macro_mclk_enable(rx, false);
1905                 break;
1906         default:
1907                 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event);
1908                 ret = -EINVAL;
1909         }
1910         return ret;
1911 }
1912
1913 static bool rx_macro_adie_lb(struct snd_soc_component *component,
1914                              int interp_idx)
1915 {
1916         u16 int_mux_cfg0, int_mux_cfg1;
1917         u8 int_n_inp0, int_n_inp1, int_n_inp2;
1918
1919         int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1920         int_mux_cfg1 = int_mux_cfg0 + 4;
1921
1922         int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
1923                                                   CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1924         int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
1925                                                   CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1926         int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
1927                                                   CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1928
1929         if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1930                 int_n_inp0 == INTn_1_INP_SEL_DEC1 ||
1931                 int_n_inp0 == INTn_1_INP_SEL_IIR0 ||
1932                 int_n_inp0 == INTn_1_INP_SEL_IIR1)
1933                 return true;
1934
1935         if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1936                 int_n_inp1 == INTn_1_INP_SEL_DEC1 ||
1937                 int_n_inp1 == INTn_1_INP_SEL_IIR0 ||
1938                 int_n_inp1 == INTn_1_INP_SEL_IIR1)
1939                 return true;
1940
1941         if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1942                 int_n_inp2 == INTn_1_INP_SEL_DEC1 ||
1943                 int_n_inp2 == INTn_1_INP_SEL_IIR0 ||
1944                 int_n_inp2 == INTn_1_INP_SEL_IIR1)
1945                 return true;
1946
1947         return false;
1948 }
1949
1950 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
1951                                       int event, int interp_idx);
1952 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1953                                         struct snd_kcontrol *kcontrol,
1954                                         int event)
1955 {
1956         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1957         u16 gain_reg, reg;
1958
1959         reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
1960         gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
1961
1962         switch (event) {
1963         case SND_SOC_DAPM_PRE_PMU:
1964                 rx_macro_enable_interp_clk(component, event, w->shift);
1965                 if (rx_macro_adie_lb(component, w->shift))
1966                         snd_soc_component_update_bits(component, reg,
1967                                                       CDC_RX_PATH_CLK_EN_MASK,
1968                                                       CDC_RX_PATH_CLK_ENABLE);
1969                 break;
1970         case SND_SOC_DAPM_POST_PMU:
1971                 snd_soc_component_write(component, gain_reg,
1972                         snd_soc_component_read(component, gain_reg));
1973                 break;
1974         case SND_SOC_DAPM_POST_PMD:
1975                 rx_macro_enable_interp_clk(component, event, w->shift);
1976                 break;
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int rx_macro_config_compander(struct snd_soc_component *component,
1983                                 struct rx_macro *rx,
1984                                 int comp, int event)
1985 {
1986         u8 pcm_rate, val;
1987
1988         /* AUX does not have compander */
1989         if (comp == INTERP_AUX)
1990                 return 0;
1991
1992         pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
1993         if (pcm_rate < 0x06)
1994                 val = 0x03;
1995         else if (pcm_rate < 0x08)
1996                 val = 0x01;
1997         else if (pcm_rate < 0x0B)
1998                 val = 0x02;
1999         else
2000                 val = 0x00;
2001
2002         if (SND_SOC_DAPM_EVENT_ON(event))
2003                 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2004                                               CDC_RX_DC_COEFF_SEL_MASK, val);
2005
2006         if (SND_SOC_DAPM_EVENT_OFF(event))
2007                 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2008                                               CDC_RX_DC_COEFF_SEL_MASK, 0x3);
2009         if (!rx->comp_enabled[comp])
2010                 return 0;
2011
2012         if (SND_SOC_DAPM_EVENT_ON(event)) {
2013                 /* Enable Compander Clock */
2014                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2015                                               CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1);
2016                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2017                                               CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
2018                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2019                                               CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
2020                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2021                                               CDC_RX_RXn_COMP_EN_MASK, 0x1);
2022         }
2023
2024         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2025                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2026                                               CDC_RX_COMPANDERn_HALT_MASK, 0x1);
2027                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2028                                               CDC_RX_RXn_COMP_EN_MASK, 0x0);
2029                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2030                                               CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
2031                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2032                                               CDC_RX_COMPANDERn_HALT_MASK, 0x0);
2033         }
2034
2035         return 0;
2036 }
2037
2038 static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
2039                                          struct rx_macro *rx,
2040                                          int comp, int event)
2041 {
2042         u16 comp_coeff_lsb_reg, comp_coeff_msb_reg;
2043         int i;
2044         int hph_pwr_mode;
2045
2046         if (!rx->comp_enabled[comp])
2047                 return 0;
2048
2049         if (comp == INTERP_HPHL) {
2050                 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB;
2051                 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB;
2052         } else if (comp == INTERP_HPHR) {
2053                 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB;
2054                 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB;
2055         } else {
2056                 /* compander coefficients are loaded only for hph path */
2057                 return 0;
2058         }
2059
2060         hph_pwr_mode = rx->hph_pwr_mode;
2061
2062         if (SND_SOC_DAPM_EVENT_ON(event)) {
2063                 /* Load Compander Coeff */
2064                 for (i = 0; i < COMP_MAX_COEFF; i++) {
2065                         snd_soc_component_write(component, comp_coeff_lsb_reg,
2066                                         comp_coeff_table[hph_pwr_mode][i].lsb);
2067                         snd_soc_component_write(component, comp_coeff_msb_reg,
2068                                         comp_coeff_table[hph_pwr_mode][i].msb);
2069                 }
2070         }
2071
2072         return 0;
2073 }
2074
2075 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
2076                                          struct rx_macro *rx, bool enable)
2077 {
2078         if (enable) {
2079                 if (rx->softclip_clk_users == 0)
2080                         snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2081                                                       CDC_RX_SOFTCLIP_CLK_EN_MASK, 1);
2082                 rx->softclip_clk_users++;
2083         } else {
2084                 rx->softclip_clk_users--;
2085                 if (rx->softclip_clk_users == 0)
2086                         snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2087                                                       CDC_RX_SOFTCLIP_CLK_EN_MASK, 0);
2088         }
2089 }
2090
2091 static int rx_macro_config_softclip(struct snd_soc_component *component,
2092                                     struct rx_macro *rx, int event)
2093 {
2094
2095         if (!rx->is_softclip_on)
2096                 return 0;
2097
2098         if (SND_SOC_DAPM_EVENT_ON(event)) {
2099                 /* Enable Softclip clock */
2100                 rx_macro_enable_softclip_clk(component, rx, true);
2101                 /* Enable Softclip control */
2102                 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2103                                              CDC_RX_SOFTCLIP_EN_MASK, 0x01);
2104         }
2105
2106         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2107                 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2108                                              CDC_RX_SOFTCLIP_EN_MASK, 0x0);
2109                 rx_macro_enable_softclip_clk(component, rx, false);
2110         }
2111
2112         return 0;
2113 }
2114
2115 static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
2116                                    struct rx_macro *rx, int event)
2117 {
2118         if (SND_SOC_DAPM_EVENT_ON(event)) {
2119                 /* Update Aux HPF control */
2120                 if (!rx->is_aux_hpf_on)
2121                         snd_soc_component_update_bits(component,
2122                                 CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00);
2123         }
2124
2125         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2126                 /* Reset to default (HPF=ON) */
2127                 snd_soc_component_update_bits(component,
2128                         CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04);
2129         }
2130
2131         return 0;
2132 }
2133
2134 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable)
2135 {
2136         if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0))
2137                 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC,
2138                                              CDC_RX_CLSH_CLK_EN_MASK, enable);
2139         if (rx->clsh_users < 0)
2140                 rx->clsh_users = 0;
2141 }
2142
2143 static int rx_macro_config_classh(struct snd_soc_component *component,
2144                                 struct rx_macro *rx,
2145                                 int interp_n, int event)
2146 {
2147         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2148                 rx_macro_enable_clsh_block(rx, false);
2149                 return 0;
2150         }
2151
2152         if (!SND_SOC_DAPM_EVENT_ON(event))
2153                 return 0;
2154
2155         rx_macro_enable_clsh_block(rx, true);
2156         if (interp_n == INTERP_HPHL ||
2157                 interp_n == INTERP_HPHR) {
2158                 /*
2159                  * These K1 values depend on the Headphone Impedance
2160                  * For now it is assumed to be 16 ohm
2161                  */
2162                 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0);
2163                 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB,
2164                                               CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0);
2165         }
2166         switch (interp_n) {
2167         case INTERP_HPHL:
2168                 if (rx->is_ear_mode_on)
2169                         snd_soc_component_update_bits(component,
2170                                 CDC_RX_CLSH_HPH_V_PA,
2171                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2172                 else
2173                         snd_soc_component_update_bits(component,
2174                                 CDC_RX_CLSH_HPH_V_PA,
2175                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2176                 snd_soc_component_update_bits(component,
2177                                 CDC_RX_CLSH_DECAY_CTRL,
2178                                 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2179                 snd_soc_component_write_field(component,
2180                                 CDC_RX_RX0_RX_PATH_CFG0,
2181                                 CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2182                 break;
2183         case INTERP_HPHR:
2184                 if (rx->is_ear_mode_on)
2185                         snd_soc_component_update_bits(component,
2186                                 CDC_RX_CLSH_HPH_V_PA,
2187                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2188                 else
2189                         snd_soc_component_update_bits(component,
2190                                 CDC_RX_CLSH_HPH_V_PA,
2191                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2192                 snd_soc_component_update_bits(component,
2193                                 CDC_RX_CLSH_DECAY_CTRL,
2194                                 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2195                 snd_soc_component_write_field(component,
2196                                 CDC_RX_RX1_RX_PATH_CFG0,
2197                                 CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2198                 break;
2199         case INTERP_AUX:
2200                 snd_soc_component_update_bits(component,
2201                                 CDC_RX_RX2_RX_PATH_CFG0,
2202                                 CDC_RX_RX2_DLY_Z_EN_MASK, 1);
2203                 snd_soc_component_write_field(component,
2204                                 CDC_RX_RX2_RX_PATH_CFG0,
2205                                 CDC_RX_RX2_CLSH_EN_MASK, 1);
2206                 break;
2207         }
2208
2209         return 0;
2210 }
2211
2212 static void rx_macro_hd2_control(struct snd_soc_component *component,
2213                                  u16 interp_idx, int event)
2214 {
2215         u16 hd2_scale_reg, hd2_enable_reg;
2216
2217         switch (interp_idx) {
2218         case INTERP_HPHL:
2219                 hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
2220                 hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
2221                 break;
2222         case INTERP_HPHR:
2223                 hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
2224                 hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
2225                 break;
2226         }
2227
2228         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2229                 snd_soc_component_update_bits(component, hd2_scale_reg,
2230                                 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14);
2231                 snd_soc_component_write_field(component, hd2_enable_reg,
2232                                               CDC_RX_RXn_HD2_EN_MASK, 1);
2233         }
2234
2235         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2236                 snd_soc_component_write_field(component, hd2_enable_reg,
2237                                               CDC_RX_RXn_HD2_EN_MASK, 0);
2238                 snd_soc_component_update_bits(component, hd2_scale_reg,
2239                                 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0);
2240         }
2241 }
2242
2243 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol,
2244                                struct snd_ctl_elem_value *ucontrol)
2245 {
2246         struct snd_soc_component *component =
2247                                 snd_soc_kcontrol_component(kcontrol);
2248         int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2249         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2250
2251         ucontrol->value.integer.value[0] = rx->comp_enabled[comp];
2252         return 0;
2253 }
2254
2255 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol,
2256                                struct snd_ctl_elem_value *ucontrol)
2257 {
2258         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2259         int comp = ((struct soc_mixer_control *)  kcontrol->private_value)->shift;
2260         int value = ucontrol->value.integer.value[0];
2261         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2262
2263         rx->comp_enabled[comp] = value;
2264
2265         return 0;
2266 }
2267
2268 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol,
2269                           struct snd_ctl_elem_value *ucontrol)
2270 {
2271         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2272         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2273         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2274
2275         ucontrol->value.integer.value[0] =
2276                         rx->rx_port_value[widget->shift];
2277         return 0;
2278 }
2279
2280 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol,
2281                             struct snd_ctl_elem_value *ucontrol)
2282 {
2283         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2284         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2285         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2286         struct snd_soc_dapm_update *update = NULL;
2287         u32 rx_port_value = ucontrol->value.integer.value[0];
2288         u32 aif_rst;
2289         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2290
2291         aif_rst = rx->rx_port_value[widget->shift];
2292         if (!rx_port_value) {
2293                 if (aif_rst == 0) {
2294                         dev_err(component->dev, "%s:AIF reset already\n", __func__);
2295                         return 0;
2296                 }
2297                 if (aif_rst > RX_MACRO_AIF4_PB) {
2298                         dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2299                         return 0;
2300                 }
2301         }
2302         rx->rx_port_value[widget->shift] = rx_port_value;
2303
2304         switch (rx_port_value) {
2305         case 0:
2306                 if (rx->active_ch_cnt[aif_rst]) {
2307                         clear_bit(widget->shift,
2308                                 &rx->active_ch_mask[aif_rst]);
2309                         rx->active_ch_cnt[aif_rst]--;
2310                 }
2311                 break;
2312         case 1:
2313         case 2:
2314         case 3:
2315         case 4:
2316                 set_bit(widget->shift,
2317                         &rx->active_ch_mask[rx_port_value]);
2318                 rx->active_ch_cnt[rx_port_value]++;
2319                 break;
2320         default:
2321                 dev_err(component->dev,
2322                         "%s:Invalid AIF_ID for RX_MACRO MUX %d\n",
2323                         __func__, rx_port_value);
2324                 goto err;
2325         }
2326
2327         snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2328                                         rx_port_value, e, update);
2329         return 0;
2330 err:
2331         return -EINVAL;
2332 }
2333
2334 static const struct snd_kcontrol_new rx_macro_rx0_mux =
2335                 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum,
2336                   rx_macro_mux_get, rx_macro_mux_put);
2337 static const struct snd_kcontrol_new rx_macro_rx1_mux =
2338                 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum,
2339                   rx_macro_mux_get, rx_macro_mux_put);
2340 static const struct snd_kcontrol_new rx_macro_rx2_mux =
2341                 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum,
2342                   rx_macro_mux_get, rx_macro_mux_put);
2343 static const struct snd_kcontrol_new rx_macro_rx3_mux =
2344                 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum,
2345                   rx_macro_mux_get, rx_macro_mux_put);
2346 static const struct snd_kcontrol_new rx_macro_rx4_mux =
2347                 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum,
2348                   rx_macro_mux_get, rx_macro_mux_put);
2349 static const struct snd_kcontrol_new rx_macro_rx5_mux =
2350                 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum,
2351                   rx_macro_mux_get, rx_macro_mux_put);
2352
2353 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol,
2354                                struct snd_ctl_elem_value *ucontrol)
2355 {
2356         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2357         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2358
2359         ucontrol->value.integer.value[0] = rx->is_ear_mode_on;
2360         return 0;
2361 }
2362
2363 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol,
2364                                struct snd_ctl_elem_value *ucontrol)
2365 {
2366         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2367         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2368
2369         rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true);
2370         return 0;
2371 }
2372
2373 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2374                                struct snd_ctl_elem_value *ucontrol)
2375 {
2376         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2377         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2378
2379         ucontrol->value.integer.value[0] = rx->hph_hd2_mode;
2380         return 0;
2381 }
2382
2383 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2384                                struct snd_ctl_elem_value *ucontrol)
2385 {
2386         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2387         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2388
2389         rx->hph_hd2_mode = ucontrol->value.integer.value[0];
2390         return 0;
2391 }
2392
2393 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2394                                struct snd_ctl_elem_value *ucontrol)
2395 {
2396         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2397         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2398
2399         ucontrol->value.integer.value[0] = rx->hph_pwr_mode;
2400         return 0;
2401 }
2402
2403 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2404                                struct snd_ctl_elem_value *ucontrol)
2405 {
2406         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2407         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2408
2409         rx->hph_pwr_mode = ucontrol->value.integer.value[0];
2410         return 0;
2411 }
2412
2413 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2414                                           struct snd_ctl_elem_value *ucontrol)
2415 {
2416         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2417         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2418
2419         ucontrol->value.integer.value[0] = rx->is_softclip_on;
2420
2421         return 0;
2422 }
2423
2424 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2425                                           struct snd_ctl_elem_value *ucontrol)
2426 {
2427         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2428         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2429
2430         rx->is_softclip_on = ucontrol->value.integer.value[0];
2431
2432         return 0;
2433 }
2434
2435 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol,
2436                                           struct snd_ctl_elem_value *ucontrol)
2437 {
2438         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2439         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2440
2441         ucontrol->value.integer.value[0] = rx->is_aux_hpf_on;
2442
2443         return 0;
2444 }
2445
2446 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol,
2447                                           struct snd_ctl_elem_value *ucontrol)
2448 {
2449         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2450         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2451
2452         rx->is_aux_hpf_on = ucontrol->value.integer.value[0];
2453
2454         return 0;
2455 }
2456
2457 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
2458                                         struct rx_macro *rx,
2459                                         u16 interp_idx, int event)
2460 {
2461         u16 hph_lut_bypass_reg;
2462         u16 hph_comp_ctrl7;
2463
2464         switch (interp_idx) {
2465         case INTERP_HPHL:
2466                 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT;
2467                 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7;
2468                 break;
2469         case INTERP_HPHR:
2470                 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT;
2471                 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7;
2472                 break;
2473         default:
2474                 return -EINVAL;
2475         }
2476
2477         if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2478                 if (interp_idx == INTERP_HPHL) {
2479                         if (rx->is_ear_mode_on)
2480                                 snd_soc_component_write_field(component,
2481                                         CDC_RX_RX0_RX_PATH_CFG1,
2482                                         CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
2483                         else
2484                                 snd_soc_component_write_field(component,
2485                                         hph_lut_bypass_reg,
2486                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2487                 } else {
2488                         snd_soc_component_write_field(component, hph_lut_bypass_reg,
2489                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2490                 }
2491                 if (rx->hph_pwr_mode)
2492                         snd_soc_component_write_field(component, hph_comp_ctrl7,
2493                                         CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0);
2494         }
2495
2496         if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2497                 snd_soc_component_write_field(component,
2498                                         CDC_RX_RX0_RX_PATH_CFG1,
2499                                         CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
2500                 snd_soc_component_update_bits(component, hph_lut_bypass_reg,
2501                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
2502                 snd_soc_component_write_field(component, hph_comp_ctrl7,
2503                                         CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1);
2504         }
2505
2506         return 0;
2507 }
2508
2509 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
2510                                       int event, int interp_idx)
2511 {
2512         u16 main_reg, dsm_reg, rx_cfg2_reg;
2513         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2514
2515         main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
2516         dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
2517         if (interp_idx == INTERP_AUX)
2518                 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
2519         rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
2520
2521         if (SND_SOC_DAPM_EVENT_ON(event)) {
2522                 if (rx->main_clk_users[interp_idx] == 0) {
2523                         /* Main path PGA mute enable */
2524                         snd_soc_component_write_field(component, main_reg,
2525                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2526                         snd_soc_component_write_field(component, dsm_reg,
2527                                                       CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1);
2528                         snd_soc_component_update_bits(component, rx_cfg2_reg,
2529                                         CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03);
2530                         rx_macro_load_compander_coeff(component, rx, interp_idx, event);
2531                         if (rx->hph_hd2_mode)
2532                                 rx_macro_hd2_control(component, interp_idx, event);
2533                         rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2534                         rx_macro_config_compander(component, rx, interp_idx, event);
2535                         if (interp_idx == INTERP_AUX) {
2536                                 rx_macro_config_softclip(component, rx, event);
2537                                 rx_macro_config_aux_hpf(component, rx, event);
2538                         }
2539                         rx_macro_config_classh(component, rx, interp_idx, event);
2540                 }
2541                 rx->main_clk_users[interp_idx]++;
2542         }
2543
2544         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2545                 rx->main_clk_users[interp_idx]--;
2546                 if (rx->main_clk_users[interp_idx] <= 0) {
2547                         rx->main_clk_users[interp_idx] = 0;
2548                         /* Main path PGA mute enable */
2549                         snd_soc_component_write_field(component, main_reg,
2550                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2551                         /* Clk Disable */
2552                         snd_soc_component_write_field(component, dsm_reg,
2553                                                       CDC_RX_RXn_DSM_CLK_EN_MASK, 0);
2554                         snd_soc_component_write_field(component, main_reg,
2555                                                       CDC_RX_PATH_CLK_EN_MASK, 0);
2556                         /* Reset enable and disable */
2557                         snd_soc_component_write_field(component, main_reg,
2558                                                       CDC_RX_PATH_RESET_EN_MASK, 1);
2559                         snd_soc_component_write_field(component, main_reg,
2560                                                       CDC_RX_PATH_RESET_EN_MASK, 0);
2561                         /* Reset rate to 48K*/
2562                         snd_soc_component_update_bits(component, main_reg,
2563                                                       CDC_RX_PATH_PCM_RATE_MASK,
2564                                                       0x04);
2565                         snd_soc_component_update_bits(component, rx_cfg2_reg,
2566                                                       CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00);
2567                         rx_macro_config_classh(component, rx, interp_idx, event);
2568                         rx_macro_config_compander(component, rx, interp_idx, event);
2569                         if (interp_idx ==  INTERP_AUX) {
2570                                 rx_macro_config_softclip(component, rx, event);
2571                                 rx_macro_config_aux_hpf(component, rx, event);
2572                         }
2573                         rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2574                         if (rx->hph_hd2_mode)
2575                                 rx_macro_hd2_control(component, interp_idx, event);
2576                 }
2577         }
2578
2579         return rx->main_clk_users[interp_idx];
2580 }
2581
2582 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
2583                                     struct snd_kcontrol *kcontrol, int event)
2584 {
2585         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2586         u16 gain_reg, mix_reg;
2587
2588         gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
2589         mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
2590
2591         switch (event) {
2592         case SND_SOC_DAPM_PRE_PMU:
2593                 rx_macro_enable_interp_clk(component, event, w->shift);
2594                 break;
2595         case SND_SOC_DAPM_POST_PMU:
2596                 snd_soc_component_write(component, gain_reg,
2597                                         snd_soc_component_read(component, gain_reg));
2598                 break;
2599         case SND_SOC_DAPM_POST_PMD:
2600                 /* Clk Disable */
2601                 snd_soc_component_update_bits(component, mix_reg,
2602                                               CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00);
2603                 rx_macro_enable_interp_clk(component, event, w->shift);
2604                 /* Reset enable and disable */
2605                 snd_soc_component_update_bits(component, mix_reg,
2606                                               CDC_RX_RXn_MIX_RESET_MASK,
2607                                               CDC_RX_RXn_MIX_RESET);
2608                 snd_soc_component_update_bits(component, mix_reg,
2609                                               CDC_RX_RXn_MIX_RESET_MASK, 0x00);
2610                 break;
2611         }
2612
2613         return 0;
2614 }
2615
2616 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
2617                                        struct snd_kcontrol *kcontrol, int event)
2618 {
2619         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2620
2621         switch (event) {
2622         case SND_SOC_DAPM_PRE_PMU:
2623                 rx_macro_enable_interp_clk(component, event, w->shift);
2624                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2625                                               CDC_RX_RXn_SIDETONE_EN_MASK, 1);
2626                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
2627                                               CDC_RX_PATH_CLK_EN_MASK, 1);
2628                 break;
2629         case SND_SOC_DAPM_POST_PMD:
2630                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2631                                               CDC_RX_RXn_SIDETONE_EN_MASK, 0);
2632                 rx_macro_enable_interp_clk(component, event, w->shift);
2633                 break;
2634         default:
2635                 break;
2636         }
2637         return 0;
2638 }
2639
2640 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
2641                                  struct snd_kcontrol *kcontrol, int event)
2642 {
2643         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2644
2645         switch (event) {
2646         case SND_SOC_DAPM_POST_PMU: /* fall through */
2647         case SND_SOC_DAPM_PRE_PMD:
2648                 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
2649                         snd_soc_component_write(component,
2650                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
2651                         snd_soc_component_read(component,
2652                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
2653                         snd_soc_component_write(component,
2654                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
2655                         snd_soc_component_read(component,
2656                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
2657                         snd_soc_component_write(component,
2658                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
2659                         snd_soc_component_read(component,
2660                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
2661                         snd_soc_component_write(component,
2662                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
2663                         snd_soc_component_read(component,
2664                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
2665                 } else {
2666                         snd_soc_component_write(component,
2667                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
2668                         snd_soc_component_read(component,
2669                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
2670                         snd_soc_component_write(component,
2671                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
2672                         snd_soc_component_read(component,
2673                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
2674                         snd_soc_component_write(component,
2675                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
2676                         snd_soc_component_read(component,
2677                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
2678                         snd_soc_component_write(component,
2679                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
2680                         snd_soc_component_read(component,
2681                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
2682                 }
2683                 break;
2684         }
2685         return 0;
2686 }
2687
2688 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2689                                    int iir_idx, int band_idx, int coeff_idx)
2690 {
2691         u32 value;
2692         int reg, b2_reg;
2693
2694         /* Address does not automatically update if reading */
2695         reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2696         b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2697
2698         snd_soc_component_write(component, reg,
2699                                 ((band_idx * BAND_MAX + coeff_idx) *
2700                                  sizeof(uint32_t)) & 0x7F);
2701
2702         value = snd_soc_component_read(component, b2_reg);
2703         snd_soc_component_write(component, reg,
2704                                 ((band_idx * BAND_MAX + coeff_idx)
2705                                  * sizeof(uint32_t) + 1) & 0x7F);
2706
2707         value |= (snd_soc_component_read(component, b2_reg) << 8);
2708         snd_soc_component_write(component, reg,
2709                                 ((band_idx * BAND_MAX + coeff_idx)
2710                                  * sizeof(uint32_t) + 2) & 0x7F);
2711
2712         value |= (snd_soc_component_read(component, b2_reg) << 16);
2713         snd_soc_component_write(component, reg,
2714                 ((band_idx * BAND_MAX + coeff_idx)
2715                 * sizeof(uint32_t) + 3) & 0x7F);
2716
2717         /* Mask bits top 2 bits since they are reserved */
2718         value |= (snd_soc_component_read(component, b2_reg) << 24);
2719         return value;
2720 }
2721
2722 static void set_iir_band_coeff(struct snd_soc_component *component,
2723                                int iir_idx, int band_idx, uint32_t value)
2724 {
2725         int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2726
2727         snd_soc_component_write(component, reg, (value & 0xFF));
2728         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2729         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2730         /* Mask top 2 bits, 7-8 are reserved */
2731         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2732 }
2733
2734 static int rx_macro_put_iir_band_audio_mixer(
2735                                         struct snd_kcontrol *kcontrol,
2736                                         struct snd_ctl_elem_value *ucontrol)
2737 {
2738         struct snd_soc_component *component =
2739                         snd_soc_kcontrol_component(kcontrol);
2740         struct wcd_iir_filter_ctl *ctl =
2741                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2742         struct soc_bytes_ext *params = &ctl->bytes_ext;
2743         int iir_idx = ctl->iir_idx;
2744         int band_idx = ctl->band_idx;
2745         u32 coeff[BAND_MAX];
2746         int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2747
2748         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2749
2750         /* Mask top bit it is reserved */
2751         /* Updates addr automatically for each B2 write */
2752         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2753                                                  sizeof(uint32_t)) & 0x7F);
2754
2755         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2756         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2757         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2758         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2759         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2760
2761         return 0;
2762 }
2763
2764 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2765                                     struct snd_ctl_elem_value *ucontrol)
2766 {
2767         struct snd_soc_component *component =
2768                         snd_soc_kcontrol_component(kcontrol);
2769         struct wcd_iir_filter_ctl *ctl =
2770                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2771         struct soc_bytes_ext *params = &ctl->bytes_ext;
2772         int iir_idx = ctl->iir_idx;
2773         int band_idx = ctl->band_idx;
2774         u32 coeff[BAND_MAX];
2775
2776         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2777         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2778         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2779         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2780         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2781
2782         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2783
2784         return 0;
2785 }
2786
2787 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
2788                                    struct snd_ctl_elem_info *ucontrol)
2789 {
2790         struct wcd_iir_filter_ctl *ctl =
2791                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2792         struct soc_bytes_ext *params = &ctl->bytes_ext;
2793
2794         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2795         ucontrol->count = params->max;
2796
2797         return 0;
2798 }
2799
2800 static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
2801         SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
2802                           -84, 40, digital_gain),
2803         SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
2804                           -84, 40, digital_gain),
2805         SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
2806                           -84, 40, digital_gain),
2807         SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
2808                           -84, 40, digital_gain),
2809         SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
2810                           -84, 40, digital_gain),
2811         SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
2812                           -84, 40, digital_gain),
2813
2814         SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
2815                 rx_macro_get_compander, rx_macro_set_compander),
2816         SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
2817                 rx_macro_get_compander, rx_macro_set_compander),
2818
2819         SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2820                 rx_macro_get_ear_mode, rx_macro_put_ear_mode),
2821
2822         SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2823                 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode),
2824
2825         SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum,
2826                 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode),
2827
2828         SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
2829                      rx_macro_soft_clip_enable_get,
2830                      rx_macro_soft_clip_enable_put),
2831         SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
2832                         rx_macro_aux_hpf_mode_get,
2833                         rx_macro_aux_hpf_mode_put),
2834
2835         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
2836                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
2837                 digital_gain),
2838         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
2839                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
2840                 digital_gain),
2841         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
2842                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
2843                 digital_gain),
2844         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
2845                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
2846                 digital_gain),
2847         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
2848                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
2849                 digital_gain),
2850         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
2851                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
2852                 digital_gain),
2853         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
2854                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
2855                 digital_gain),
2856         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
2857                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
2858                 digital_gain),
2859
2860         SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2861                    0, 1, 0),
2862         SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2863                    1, 1, 0),
2864         SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2865                    2, 1, 0),
2866         SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2867                    3, 1, 0),
2868         SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2869                    4, 1, 0),
2870         SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2871                    0, 1, 0),
2872         SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2873                    1, 1, 0),
2874         SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2875                    2, 1, 0),
2876         SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2877                    3, 1, 0),
2878         SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2879                    4, 1, 0),
2880
2881         RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
2882         RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
2883         RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
2884         RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
2885         RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
2886
2887         RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
2888         RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
2889         RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
2890         RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
2891         RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
2892
2893 };
2894
2895 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
2896                                 struct snd_kcontrol *kcontrol,
2897                                 int event)
2898 {
2899         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2900         u16 val, ec_hq_reg;
2901         int ec_tx = -1;
2902
2903         val = snd_soc_component_read(component,
2904                         CDC_RX_INP_MUX_RX_MIX_CFG4);
2905         if (!(strcmp(w->name, "RX MIX TX0 MUX")))
2906                 ec_tx = ((val & 0xf0) >> 0x4) - 1;
2907         else if (!(strcmp(w->name, "RX MIX TX1 MUX")))
2908                 ec_tx = (val & 0x0f) - 1;
2909
2910         val = snd_soc_component_read(component,
2911                         CDC_RX_INP_MUX_RX_MIX_CFG5);
2912         if (!(strcmp(w->name, "RX MIX TX2 MUX")))
2913                 ec_tx = (val & 0x0f) - 1;
2914
2915         if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) {
2916                 dev_err(component->dev, "%s: EC mix control not set correctly\n",
2917                         __func__);
2918                 return -EINVAL;
2919         }
2920         ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL +
2921                             0x40 * ec_tx;
2922         snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01);
2923         ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 +
2924                                 0x40 * ec_tx;
2925         /* default set to 48k */
2926         snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08);
2927
2928         return 0;
2929 }
2930
2931 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
2932         SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
2933                 SND_SOC_NOPM, 0, 0),
2934
2935         SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
2936                 SND_SOC_NOPM, 0, 0),
2937
2938         SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
2939                 SND_SOC_NOPM, 0, 0),
2940
2941         SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
2942                 SND_SOC_NOPM, 0, 0),
2943
2944         SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
2945                 SND_SOC_NOPM, 0, 0),
2946
2947         SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
2948                          &rx_macro_rx0_mux),
2949         SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
2950                          &rx_macro_rx1_mux),
2951         SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
2952                          &rx_macro_rx2_mux),
2953         SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
2954                          &rx_macro_rx3_mux),
2955         SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
2956                          &rx_macro_rx4_mux),
2957         SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
2958                          &rx_macro_rx5_mux),
2959
2960         SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2961         SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2962         SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
2963         SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
2964         SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
2965         SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
2966
2967         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
2968         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
2969         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
2970         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
2971         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
2972         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
2973         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
2974         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
2975
2976         SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
2977                            RX_MACRO_EC0_MUX, 0,
2978                            &rx_mix_tx0_mux, rx_macro_enable_echo,
2979                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2980         SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
2981                            RX_MACRO_EC1_MUX, 0,
2982                            &rx_mix_tx1_mux, rx_macro_enable_echo,
2983                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2984         SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
2985                            RX_MACRO_EC2_MUX, 0,
2986                            &rx_mix_tx2_mux, rx_macro_enable_echo,
2987                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2988
2989         SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
2990                 4, 0, NULL, 0, rx_macro_set_iir_gain,
2991                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2992         SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
2993                 4, 0, NULL, 0, rx_macro_set_iir_gain,
2994                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2995         SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
2996                 4, 0, NULL, 0),
2997         SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
2998                 4, 0, NULL, 0),
2999
3000         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3001                          &rx_int0_dem_inp_mux),
3002         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3003                          &rx_int1_dem_inp_mux),
3004
3005         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3006                 &rx_int0_2_mux, rx_macro_enable_mix_path,
3007                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3008                 SND_SOC_DAPM_POST_PMD),
3009         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3010                 &rx_int1_2_mux, rx_macro_enable_mix_path,
3011                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3012                 SND_SOC_DAPM_POST_PMD),
3013         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3014                 &rx_int2_2_mux, rx_macro_enable_mix_path,
3015                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3016                 SND_SOC_DAPM_POST_PMD),
3017
3018         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3019         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3020         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3021         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3022         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3023         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3024         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3025         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3026         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3027
3028         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3029                 &rx_int0_1_interp_mux, rx_macro_enable_main_path,
3030                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3031                 SND_SOC_DAPM_POST_PMD),
3032         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3033                 &rx_int1_1_interp_mux, rx_macro_enable_main_path,
3034                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3035                 SND_SOC_DAPM_POST_PMD),
3036         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3037                 &rx_int2_1_interp_mux, rx_macro_enable_main_path,
3038                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3039                 SND_SOC_DAPM_POST_PMD),
3040
3041         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3042                          &rx_int0_2_interp_mux),
3043         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3044                          &rx_int1_2_interp_mux),
3045         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3046                          &rx_int2_2_interp_mux),
3047
3048         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3049         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3050         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3051         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3052         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3053         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3054
3055         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3056                 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3057                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3058         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3059                 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3060                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3061         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3062                 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3063                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3064
3065         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3066         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3067         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3068
3069         SND_SOC_DAPM_OUTPUT("HPHL_OUT"),
3070         SND_SOC_DAPM_OUTPUT("HPHR_OUT"),
3071         SND_SOC_DAPM_OUTPUT("AUX_OUT"),
3072
3073         SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"),
3074         SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"),
3075         SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"),
3076         SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"),
3077
3078         SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
3079         rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3080 };
3081
3082 static const struct snd_soc_dapm_route rx_audio_map[] = {
3083         {"RX AIF1 PB", NULL, "RX_MCLK"},
3084         {"RX AIF2 PB", NULL, "RX_MCLK"},
3085         {"RX AIF3 PB", NULL, "RX_MCLK"},
3086         {"RX AIF4 PB", NULL, "RX_MCLK"},
3087
3088         {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3089         {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3090         {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3091         {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3092         {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3093         {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3094
3095         {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3096         {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3097         {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3098         {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3099         {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3100         {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3101
3102         {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3103         {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3104         {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3105         {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3106         {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3107         {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3108
3109         {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3110         {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3111         {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3112         {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3113         {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3114         {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3115
3116         {"RX_RX0", NULL, "RX_MACRO RX0 MUX"},
3117         {"RX_RX1", NULL, "RX_MACRO RX1 MUX"},
3118         {"RX_RX2", NULL, "RX_MACRO RX2 MUX"},
3119         {"RX_RX3", NULL, "RX_MACRO RX3 MUX"},
3120         {"RX_RX4", NULL, "RX_MACRO RX4 MUX"},
3121         {"RX_RX5", NULL, "RX_MACRO RX5 MUX"},
3122
3123         {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3124         {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3125         {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3126         {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3127         {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3128         {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3129         {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3130         {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3131         {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3132         {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3133         {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3134         {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3135         {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3136         {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3137         {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3138         {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3139         {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3140         {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3141         {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3142         {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3143         {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3144         {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3145         {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3146         {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3147         {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3148         {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3149         {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3150         {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3151         {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3152         {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3153
3154         {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3155         {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3156         {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3157         {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3158         {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3159         {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3160         {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3161         {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3162         {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3163         {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3164         {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3165         {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3166         {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3167         {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3168         {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3169         {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3170         {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3171         {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3172         {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3173         {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3174         {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3175         {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3176         {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3177         {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3178         {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3179         {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3180         {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3181         {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3182         {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3183         {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3184
3185         {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3186         {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3187         {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3188         {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3189         {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3190         {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3191         {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3192         {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3193         {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3194         {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3195         {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3196         {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3197         {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3198         {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3199         {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3200         {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3201         {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3202         {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3203         {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3204         {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3205         {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3206         {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3207         {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3208         {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3209         {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3210         {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3211         {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3212         {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3213         {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3214         {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3215
3216         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3217         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3218         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3219         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3220         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3221         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3222         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3223         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3224         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3225
3226         {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3227         {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3228         {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3229         {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3230         {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3231         {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3232         {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3233         {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3234         {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3235         {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3236         {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3237         {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3238         {"RX AIF_ECHO", NULL, "RX_MCLK"},
3239
3240         /* Mixing path INT0 */
3241         {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3242         {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3243         {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3244         {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3245         {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3246         {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3247         {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3248         {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3249
3250         /* Mixing path INT1 */
3251         {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3252         {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3253         {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3254         {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3255         {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3256         {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3257         {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3258         {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3259
3260         /* Mixing path INT2 */
3261         {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3262         {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3263         {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3264         {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3265         {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3266         {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3267         {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3268         {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3269
3270         {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3271         {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3272         {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3273         {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3274         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3275         {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3276         {"HPHL_OUT", NULL, "RX_MCLK"},
3277
3278         {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3279         {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3280         {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3281         {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3282         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3283         {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3284         {"HPHR_OUT", NULL, "RX_MCLK"},
3285
3286         {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3287
3288         {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3289         {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3290         {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3291         {"AUX_OUT", NULL, "RX INT2 MIX2"},
3292         {"AUX_OUT", NULL, "RX_MCLK"},
3293
3294         {"IIR0", NULL, "RX_MCLK"},
3295         {"IIR0", NULL, "IIR0 INP0 MUX"},
3296         {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3297         {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3298         {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3299         {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3300         {"IIR0 INP0 MUX", "RX0", "RX_RX0"},
3301         {"IIR0 INP0 MUX", "RX1", "RX_RX1"},
3302         {"IIR0 INP0 MUX", "RX2", "RX_RX2"},
3303         {"IIR0 INP0 MUX", "RX3", "RX_RX3"},
3304         {"IIR0 INP0 MUX", "RX4", "RX_RX4"},
3305         {"IIR0 INP0 MUX", "RX5", "RX_RX5"},
3306         {"IIR0", NULL, "IIR0 INP1 MUX"},
3307         {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3308         {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3309         {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3310         {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3311         {"IIR0 INP1 MUX", "RX0", "RX_RX0"},
3312         {"IIR0 INP1 MUX", "RX1", "RX_RX1"},
3313         {"IIR0 INP1 MUX", "RX2", "RX_RX2"},
3314         {"IIR0 INP1 MUX", "RX3", "RX_RX3"},
3315         {"IIR0 INP1 MUX", "RX4", "RX_RX4"},
3316         {"IIR0 INP1 MUX", "RX5", "RX_RX5"},
3317         {"IIR0", NULL, "IIR0 INP2 MUX"},
3318         {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3319         {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3320         {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3321         {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3322         {"IIR0 INP2 MUX", "RX0", "RX_RX0"},
3323         {"IIR0 INP2 MUX", "RX1", "RX_RX1"},
3324         {"IIR0 INP2 MUX", "RX2", "RX_RX2"},
3325         {"IIR0 INP2 MUX", "RX3", "RX_RX3"},
3326         {"IIR0 INP2 MUX", "RX4", "RX_RX4"},
3327         {"IIR0 INP2 MUX", "RX5", "RX_RX5"},
3328         {"IIR0", NULL, "IIR0 INP3 MUX"},
3329         {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3330         {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3331         {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3332         {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3333         {"IIR0 INP3 MUX", "RX0", "RX_RX0"},
3334         {"IIR0 INP3 MUX", "RX1", "RX_RX1"},
3335         {"IIR0 INP3 MUX", "RX2", "RX_RX2"},
3336         {"IIR0 INP3 MUX", "RX3", "RX_RX3"},
3337         {"IIR0 INP3 MUX", "RX4", "RX_RX4"},
3338         {"IIR0 INP3 MUX", "RX5", "RX_RX5"},
3339
3340         {"IIR1", NULL, "RX_MCLK"},
3341         {"IIR1", NULL, "IIR1 INP0 MUX"},
3342         {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3343         {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3344         {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3345         {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3346         {"IIR1 INP0 MUX", "RX0", "RX_RX0"},
3347         {"IIR1 INP0 MUX", "RX1", "RX_RX1"},
3348         {"IIR1 INP0 MUX", "RX2", "RX_RX2"},
3349         {"IIR1 INP0 MUX", "RX3", "RX_RX3"},
3350         {"IIR1 INP0 MUX", "RX4", "RX_RX4"},
3351         {"IIR1 INP0 MUX", "RX5", "RX_RX5"},
3352         {"IIR1", NULL, "IIR1 INP1 MUX"},
3353         {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3354         {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3355         {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3356         {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3357         {"IIR1 INP1 MUX", "RX0", "RX_RX0"},
3358         {"IIR1 INP1 MUX", "RX1", "RX_RX1"},
3359         {"IIR1 INP1 MUX", "RX2", "RX_RX2"},
3360         {"IIR1 INP1 MUX", "RX3", "RX_RX3"},
3361         {"IIR1 INP1 MUX", "RX4", "RX_RX4"},
3362         {"IIR1 INP1 MUX", "RX5", "RX_RX5"},
3363         {"IIR1", NULL, "IIR1 INP2 MUX"},
3364         {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3365         {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3366         {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3367         {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3368         {"IIR1 INP2 MUX", "RX0", "RX_RX0"},
3369         {"IIR1 INP2 MUX", "RX1", "RX_RX1"},
3370         {"IIR1 INP2 MUX", "RX2", "RX_RX2"},
3371         {"IIR1 INP2 MUX", "RX3", "RX_RX3"},
3372         {"IIR1 INP2 MUX", "RX4", "RX_RX4"},
3373         {"IIR1 INP2 MUX", "RX5", "RX_RX5"},
3374         {"IIR1", NULL, "IIR1 INP3 MUX"},
3375         {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3376         {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3377         {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3378         {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3379         {"IIR1 INP3 MUX", "RX0", "RX_RX0"},
3380         {"IIR1 INP3 MUX", "RX1", "RX_RX1"},
3381         {"IIR1 INP3 MUX", "RX2", "RX_RX2"},
3382         {"IIR1 INP3 MUX", "RX3", "RX_RX3"},
3383         {"IIR1 INP3 MUX", "RX4", "RX_RX4"},
3384         {"IIR1 INP3 MUX", "RX5", "RX_RX5"},
3385
3386         {"SRC0", NULL, "IIR0"},
3387         {"SRC1", NULL, "IIR1"},
3388         {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3389         {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3390         {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3391         {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3392         {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3393         {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3394 };
3395
3396 static int rx_macro_component_probe(struct snd_soc_component *component)
3397 {
3398         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
3399
3400         snd_soc_component_init_regmap(component, rx->regmap);
3401
3402         snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
3403                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3404                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3405         snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
3406                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3407                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3408         snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
3409                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3410                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3411         snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
3412                                       CDC_RX_DC_COEFF_SEL_MASK,
3413                                       CDC_RX_DC_COEFF_SEL_TWO);
3414         snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
3415                                       CDC_RX_DC_COEFF_SEL_MASK,
3416                                       CDC_RX_DC_COEFF_SEL_TWO);
3417         snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
3418                                       CDC_RX_DC_COEFF_SEL_MASK,
3419                                       CDC_RX_DC_COEFF_SEL_TWO);
3420
3421         rx->component = component;
3422
3423         return 0;
3424 }
3425
3426 static int swclk_gate_enable(struct clk_hw *hw)
3427 {
3428         struct rx_macro *rx = to_rx_macro(hw);
3429         int ret;
3430
3431         ret = clk_prepare_enable(rx->mclk);
3432         if (ret) {
3433                 dev_err(rx->dev, "unable to prepare mclk\n");
3434                 return ret;
3435         }
3436
3437         rx_macro_mclk_enable(rx, true);
3438         if (rx->reset_swr)
3439                 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3440                                    CDC_RX_SWR_RESET_MASK,
3441                                    CDC_RX_SWR_RESET);
3442
3443         regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3444                            CDC_RX_SWR_CLK_EN_MASK, 1);
3445
3446         if (rx->reset_swr)
3447                 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3448                                    CDC_RX_SWR_RESET_MASK, 0);
3449         rx->reset_swr = false;
3450
3451         return 0;
3452 }
3453
3454 static void swclk_gate_disable(struct clk_hw *hw)
3455 {
3456         struct rx_macro *rx = to_rx_macro(hw);
3457
3458         regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3459                            CDC_RX_SWR_CLK_EN_MASK, 0);
3460
3461         rx_macro_mclk_enable(rx, false);
3462         clk_disable_unprepare(rx->mclk);
3463 }
3464
3465 static int swclk_gate_is_enabled(struct clk_hw *hw)
3466 {
3467         struct rx_macro *rx = to_rx_macro(hw);
3468         int ret, val;
3469
3470         regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val);
3471         ret = val & BIT(0);
3472
3473         return ret;
3474 }
3475
3476 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
3477                                        unsigned long parent_rate)
3478 {
3479         return parent_rate / 2;
3480 }
3481
3482 static const struct clk_ops swclk_gate_ops = {
3483         .prepare = swclk_gate_enable,
3484         .unprepare = swclk_gate_disable,
3485         .is_enabled = swclk_gate_is_enabled,
3486         .recalc_rate = swclk_recalc_rate,
3487
3488 };
3489
3490 static int rx_macro_register_mclk_output(struct rx_macro *rx)
3491 {
3492         struct device *dev = rx->dev;
3493         const char *parent_clk_name = NULL;
3494         const char *clk_name = "lpass-rx-mclk";
3495         struct clk_hw *hw;
3496         struct clk_init_data init;
3497         int ret;
3498
3499         parent_clk_name = __clk_get_name(rx->npl);
3500
3501         init.name = clk_name;
3502         init.ops = &swclk_gate_ops;
3503         init.flags = 0;
3504         init.parent_names = &parent_clk_name;
3505         init.num_parents = 1;
3506         rx->hw.init = &init;
3507         hw = &rx->hw;
3508         ret = devm_clk_hw_register(rx->dev, hw);
3509         if (ret)
3510                 return ret;
3511
3512         return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
3513 }
3514
3515 static const struct snd_soc_component_driver rx_macro_component_drv = {
3516         .name = "RX-MACRO",
3517         .probe = rx_macro_component_probe,
3518         .controls = rx_macro_snd_controls,
3519         .num_controls = ARRAY_SIZE(rx_macro_snd_controls),
3520         .dapm_widgets = rx_macro_dapm_widgets,
3521         .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets),
3522         .dapm_routes = rx_audio_map,
3523         .num_dapm_routes = ARRAY_SIZE(rx_audio_map),
3524 };
3525
3526 static int rx_macro_probe(struct platform_device *pdev)
3527 {
3528         struct device *dev = &pdev->dev;
3529         struct rx_macro *rx;
3530         void __iomem *base;
3531         int ret;
3532
3533         rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL);
3534         if (!rx)
3535                 return -ENOMEM;
3536
3537         rx->macro = devm_clk_get_optional(dev, "macro");
3538         if (IS_ERR(rx->macro))
3539                 return PTR_ERR(rx->macro);
3540
3541         rx->dcodec = devm_clk_get_optional(dev, "dcodec");
3542         if (IS_ERR(rx->dcodec))
3543                 return PTR_ERR(rx->dcodec);
3544
3545         rx->mclk = devm_clk_get(dev, "mclk");
3546         if (IS_ERR(rx->mclk))
3547                 return PTR_ERR(rx->mclk);
3548
3549         rx->npl = devm_clk_get(dev, "npl");
3550         if (IS_ERR(rx->npl))
3551                 return PTR_ERR(rx->npl);
3552
3553         rx->fsgen = devm_clk_get(dev, "fsgen");
3554         if (IS_ERR(rx->fsgen))
3555                 return PTR_ERR(rx->fsgen);
3556
3557         base = devm_platform_ioremap_resource(pdev, 0);
3558         if (IS_ERR(base))
3559                 return PTR_ERR(base);
3560
3561         rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
3562         if (IS_ERR(rx->regmap))
3563                 return PTR_ERR(rx->regmap);
3564
3565         dev_set_drvdata(dev, rx);
3566
3567         rx->reset_swr = true;
3568         rx->dev = dev;
3569
3570         /* set MCLK and NPL rates */
3571         clk_set_rate(rx->mclk, MCLK_FREQ);
3572         clk_set_rate(rx->npl, 2 * MCLK_FREQ);
3573
3574         ret = clk_prepare_enable(rx->macro);
3575         if (ret)
3576                 goto err;
3577
3578         ret = clk_prepare_enable(rx->dcodec);
3579         if (ret)
3580                 goto err_dcodec;
3581
3582         ret = clk_prepare_enable(rx->mclk);
3583         if (ret)
3584                 goto err_mclk;
3585
3586         ret = clk_prepare_enable(rx->npl);
3587         if (ret)
3588                 goto err_npl;
3589
3590         ret = clk_prepare_enable(rx->fsgen);
3591         if (ret)
3592                 goto err_fsgen;
3593
3594         ret = rx_macro_register_mclk_output(rx);
3595         if (ret)
3596                 goto err_clkout;
3597
3598         ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
3599                                               rx_macro_dai,
3600                                               ARRAY_SIZE(rx_macro_dai));
3601         if (ret)
3602                 goto err_clkout;
3603
3604         return 0;
3605
3606 err_clkout:
3607         clk_disable_unprepare(rx->fsgen);
3608 err_fsgen:
3609         clk_disable_unprepare(rx->npl);
3610 err_npl:
3611         clk_disable_unprepare(rx->mclk);
3612 err_mclk:
3613         clk_disable_unprepare(rx->dcodec);
3614 err_dcodec:
3615         clk_disable_unprepare(rx->macro);
3616 err:
3617         return ret;
3618 }
3619
3620 static int rx_macro_remove(struct platform_device *pdev)
3621 {
3622         struct rx_macro *rx = dev_get_drvdata(&pdev->dev);
3623
3624         clk_disable_unprepare(rx->mclk);
3625         clk_disable_unprepare(rx->npl);
3626         clk_disable_unprepare(rx->fsgen);
3627         clk_disable_unprepare(rx->macro);
3628         clk_disable_unprepare(rx->dcodec);
3629
3630         return 0;
3631 }
3632
3633 static const struct of_device_id rx_macro_dt_match[] = {
3634         { .compatible = "qcom,sc7280-lpass-rx-macro" },
3635         { .compatible = "qcom,sm8250-lpass-rx-macro" },
3636         { }
3637 };
3638 MODULE_DEVICE_TABLE(of, rx_macro_dt_match);
3639
3640 static struct platform_driver rx_macro_driver = {
3641         .driver = {
3642                 .name = "rx_macro",
3643                 .of_match_table = rx_macro_dt_match,
3644                 .suppress_bind_attrs = true,
3645         },
3646         .probe = rx_macro_probe,
3647         .remove = rx_macro_remove,
3648 };
3649
3650 module_platform_driver(rx_macro_driver);
3651
3652 MODULE_DESCRIPTION("RX macro driver");
3653 MODULE_LICENSE("GPL");