sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/types.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/gpio.h>
  19 #include <linux/regmap.h>
  20 #include <linux/slab.h>
  21 #include <linux/acpi.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/property.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/of_device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/soc-dapm.h>
  32 #include <sound/initval.h>
  33 #include <sound/tlv.h>
  34 #include <dt-bindings/sound/cs42l42.h>
  35
  36 #include "cs42l42.h"
  37 #include "cirrus_legacy.h"
  38
  39 static const char * const cs42l42_supply_names[] = {
  40         "VA",
  41         "VP",
  42         "VCP",
  43         "VD_FILT",
  44         "VL",
  45 };
  46
  47 static const struct reg_default cs42l42_reg_defaults[] = {
  48         { CS42L42_FRZ_CTL,                      0x00 },
  49         { CS42L42_SRC_CTL,                      0x10 },
  50         { CS42L42_MCLK_CTL,                     0x02 },
  51         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  52         { CS42L42_SLOW_START_ENABLE,            0x70 },
  53         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  54         { CS42L42_I2C_STRETCH,                  0x03 },
  55         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  56         { CS42L42_PWR_CTL1,                     0xFF },
  57         { CS42L42_PWR_CTL2,                     0x84 },
  58         { CS42L42_PWR_CTL3,                     0x20 },
  59         { CS42L42_RSENSE_CTL1,                  0x40 },
  60         { CS42L42_RSENSE_CTL2,                  0x00 },
  61         { CS42L42_OSC_SWITCH,                   0x00 },
  62         { CS42L42_RSENSE_CTL3,                  0x1B },
  63         { CS42L42_TSENSE_CTL,                   0x1B },
  64         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  65         { CS42L42_HSDET_CTL1,                   0x77 },
  66         { CS42L42_HSDET_CTL2,                   0x00 },
  67         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  68         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  69         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  70         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  71         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  72         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  73         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  74         { CS42L42_FSYNC_P_UPPER,                0x00 },
  75         { CS42L42_ASP_CLK_CFG,                  0x00 },
  76         { CS42L42_ASP_FRM_CFG,                  0x10 },
  77         { CS42L42_FS_RATE_EN,                   0x00 },
  78         { CS42L42_IN_ASRC_CLK,                  0x00 },
  79         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  80         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  81         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  82         { CS42L42_MIXER_INT_MASK,               0x0F },
  83         { CS42L42_SRC_INT_MASK,                 0x0F },
  84         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  85         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  86         { CS42L42_CODEC_INT_MASK,               0x03 },
  87         { CS42L42_SRCPL_INT_MASK,               0x7F },
  88         { CS42L42_VPMON_INT_MASK,               0x01 },
  89         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  90         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  91         { CS42L42_PLL_CTL1,                     0x00 },
  92         { CS42L42_PLL_DIV_FRAC0,                0x00 },
  93         { CS42L42_PLL_DIV_FRAC1,                0x00 },
  94         { CS42L42_PLL_DIV_FRAC2,                0x00 },
  95         { CS42L42_PLL_DIV_INT,                  0x40 },
  96         { CS42L42_PLL_CTL3,                     0x10 },
  97         { CS42L42_PLL_CAL_RATIO,                0x80 },
  98         { CS42L42_PLL_CTL4,                     0x03 },
  99         { CS42L42_LOAD_DET_EN,                  0x00 },
 100         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 101         { CS42L42_WAKE_CTL,                     0xC0 },
 102         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 103         { CS42L42_TIPSENSE_CTL,                 0x02 },
 104         { CS42L42_MISC_DET_CTL,                 0x03 },
 105         { CS42L42_MIC_DET_CTL1,                 0x1F },
 106         { CS42L42_MIC_DET_CTL2,                 0x2F },
 107         { CS42L42_DET_INT1_MASK,                0xE0 },
 108         { CS42L42_DET_INT2_MASK,                0xFF },
 109         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 110         { CS42L42_ADC_CTL,                      0x00 },
 111         { CS42L42_ADC_VOLUME,                   0x00 },
 112         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 113         { CS42L42_DAC_CTL1,                     0x00 },
 114         { CS42L42_DAC_CTL2,                     0x02 },
 115         { CS42L42_HP_CTL,                       0x0D },
 116         { CS42L42_CLASSH_CTL,                   0x07 },
 117         { CS42L42_MIXER_CHA_VOL,                0x3F },
 118         { CS42L42_MIXER_ADC_VOL,                0x3F },
 119         { CS42L42_MIXER_CHB_VOL,                0x3F },
 120         { CS42L42_EQ_COEF_IN0,                  0x00 },
 121         { CS42L42_EQ_COEF_IN1,                  0x00 },
 122         { CS42L42_EQ_COEF_IN2,                  0x00 },
 123         { CS42L42_EQ_COEF_IN3,                  0x00 },
 124         { CS42L42_EQ_COEF_RW,                   0x00 },
 125         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 126         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 127         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 128         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 129         { CS42L42_EQ_INIT_STAT,                 0x00 },
 130         { CS42L42_EQ_START_FILT,                0x00 },
 131         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 132         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 133         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 134         { CS42L42_SP_RX_FS,                     0x8C },
 135         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 136         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 137         { CS42L42_SP_TX_FS,                     0xCC },
 138         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 139         { CS42L42_SRC_SDIN_FS,                  0x40 },
 140         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 141         { CS42L42_SPDIF_CTL1,                   0x01 },
 142         { CS42L42_SPDIF_CTL2,                   0x00 },
 143         { CS42L42_SPDIF_CTL3,                   0x00 },
 144         { CS42L42_SPDIF_CTL4,                   0x42 },
 145         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 146         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 147         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 148         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 149         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 150         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 151         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 152         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 153         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 154         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 155         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 156         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 157         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 158         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 159         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 160         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 161         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 162         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 163         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 164         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 165         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 166         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 167         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 168         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 169         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 170         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 171         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 172 };
 173
 174 bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 175 {
 176         switch (reg) {
 177         case CS42L42_PAGE_REGISTER:
 178         case CS42L42_DEVID_AB:
 179         case CS42L42_DEVID_CD:
 180         case CS42L42_DEVID_E:
 181         case CS42L42_FABID:
 182         case CS42L42_REVID:
 183         case CS42L42_FRZ_CTL:
 184         case CS42L42_SRC_CTL:
 185         case CS42L42_MCLK_STATUS:
 186         case CS42L42_MCLK_CTL:
 187         case CS42L42_SFTRAMP_RATE:
 188         case CS42L42_SLOW_START_ENABLE:
 189         case CS42L42_I2C_DEBOUNCE:
 190         case CS42L42_I2C_STRETCH:
 191         case CS42L42_I2C_TIMEOUT:
 192         case CS42L42_PWR_CTL1:
 193         case CS42L42_PWR_CTL2:
 194         case CS42L42_PWR_CTL3:
 195         case CS42L42_RSENSE_CTL1:
 196         case CS42L42_RSENSE_CTL2:
 197         case CS42L42_OSC_SWITCH:
 198         case CS42L42_OSC_SWITCH_STATUS:
 199         case CS42L42_RSENSE_CTL3:
 200         case CS42L42_TSENSE_CTL:
 201         case CS42L42_TSRS_INT_DISABLE:
 202         case CS42L42_TRSENSE_STATUS:
 203         case CS42L42_HSDET_CTL1:
 204         case CS42L42_HSDET_CTL2:
 205         case CS42L42_HS_SWITCH_CTL:
 206         case CS42L42_HS_DET_STATUS:
 207         case CS42L42_HS_CLAMP_DISABLE:
 208         case CS42L42_MCLK_SRC_SEL:
 209         case CS42L42_SPDIF_CLK_CFG:
 210         case CS42L42_FSYNC_PW_LOWER:
 211         case CS42L42_FSYNC_PW_UPPER:
 212         case CS42L42_FSYNC_P_LOWER:
 213         case CS42L42_FSYNC_P_UPPER:
 214         case CS42L42_ASP_CLK_CFG:
 215         case CS42L42_ASP_FRM_CFG:
 216         case CS42L42_FS_RATE_EN:
 217         case CS42L42_IN_ASRC_CLK:
 218         case CS42L42_OUT_ASRC_CLK:
 219         case CS42L42_PLL_DIV_CFG1:
 220         case CS42L42_ADC_OVFL_STATUS:
 221         case CS42L42_MIXER_STATUS:
 222         case CS42L42_SRC_STATUS:
 223         case CS42L42_ASP_RX_STATUS:
 224         case CS42L42_ASP_TX_STATUS:
 225         case CS42L42_CODEC_STATUS:
 226         case CS42L42_DET_INT_STATUS1:
 227         case CS42L42_DET_INT_STATUS2:
 228         case CS42L42_SRCPL_INT_STATUS:
 229         case CS42L42_VPMON_STATUS:
 230         case CS42L42_PLL_LOCK_STATUS:
 231         case CS42L42_TSRS_PLUG_STATUS:
 232         case CS42L42_ADC_OVFL_INT_MASK:
 233         case CS42L42_MIXER_INT_MASK:
 234         case CS42L42_SRC_INT_MASK:
 235         case CS42L42_ASP_RX_INT_MASK:
 236         case CS42L42_ASP_TX_INT_MASK:
 237         case CS42L42_CODEC_INT_MASK:
 238         case CS42L42_SRCPL_INT_MASK:
 239         case CS42L42_VPMON_INT_MASK:
 240         case CS42L42_PLL_LOCK_INT_MASK:
 241         case CS42L42_TSRS_PLUG_INT_MASK:
 242         case CS42L42_PLL_CTL1:
 243         case CS42L42_PLL_DIV_FRAC0:
 244         case CS42L42_PLL_DIV_FRAC1:
 245         case CS42L42_PLL_DIV_FRAC2:
 246         case CS42L42_PLL_DIV_INT:
 247         case CS42L42_PLL_CTL3:
 248         case CS42L42_PLL_CAL_RATIO:
 249         case CS42L42_PLL_CTL4:
 250         case CS42L42_LOAD_DET_RCSTAT:
 251         case CS42L42_LOAD_DET_DONE:
 252         case CS42L42_LOAD_DET_EN:
 253         case CS42L42_HSBIAS_SC_AUTOCTL:
 254         case CS42L42_WAKE_CTL:
 255         case CS42L42_ADC_DISABLE_MUTE:
 256         case CS42L42_TIPSENSE_CTL:
 257         case CS42L42_MISC_DET_CTL:
 258         case CS42L42_MIC_DET_CTL1:
 259         case CS42L42_MIC_DET_CTL2:
 260         case CS42L42_DET_STATUS1:
 261         case CS42L42_DET_STATUS2:
 262         case CS42L42_DET_INT1_MASK:
 263         case CS42L42_DET_INT2_MASK:
 264         case CS42L42_HS_BIAS_CTL:
 265         case CS42L42_ADC_CTL:
 266         case CS42L42_ADC_VOLUME:
 267         case CS42L42_ADC_WNF_HPF_CTL:
 268         case CS42L42_DAC_CTL1:
 269         case CS42L42_DAC_CTL2:
 270         case CS42L42_HP_CTL:
 271         case CS42L42_CLASSH_CTL:
 272         case CS42L42_MIXER_CHA_VOL:
 273         case CS42L42_MIXER_ADC_VOL:
 274         case CS42L42_MIXER_CHB_VOL:
 275         case CS42L42_EQ_COEF_IN0:
 276         case CS42L42_EQ_COEF_IN1:
 277         case CS42L42_EQ_COEF_IN2:
 278         case CS42L42_EQ_COEF_IN3:
 279         case CS42L42_EQ_COEF_RW:
 280         case CS42L42_EQ_COEF_OUT0:
 281         case CS42L42_EQ_COEF_OUT1:
 282         case CS42L42_EQ_COEF_OUT2:
 283         case CS42L42_EQ_COEF_OUT3:
 284         case CS42L42_EQ_INIT_STAT:
 285         case CS42L42_EQ_START_FILT:
 286         case CS42L42_EQ_MUTE_CTL:
 287         case CS42L42_SP_RX_CH_SEL:
 288         case CS42L42_SP_RX_ISOC_CTL:
 289         case CS42L42_SP_RX_FS:
 290         case CS42l42_SPDIF_CH_SEL:
 291         case CS42L42_SP_TX_ISOC_CTL:
 292         case CS42L42_SP_TX_FS:
 293         case CS42L42_SPDIF_SW_CTL1:
 294         case CS42L42_SRC_SDIN_FS:
 295         case CS42L42_SRC_SDOUT_FS:
 296         case CS42L42_SPDIF_CTL1:
 297         case CS42L42_SPDIF_CTL2:
 298         case CS42L42_SPDIF_CTL3:
 299         case CS42L42_SPDIF_CTL4:
 300         case CS42L42_ASP_TX_SZ_EN:
 301         case CS42L42_ASP_TX_CH_EN:
 302         case CS42L42_ASP_TX_CH_AP_RES:
 303         case CS42L42_ASP_TX_CH1_BIT_MSB:
 304         case CS42L42_ASP_TX_CH1_BIT_LSB:
 305         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 306         case CS42L42_ASP_TX_CH2_BIT_MSB:
 307         case CS42L42_ASP_TX_CH2_BIT_LSB:
 308         case CS42L42_ASP_RX_DAI0_EN:
 309         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 310         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 311         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 312         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 313         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 314         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 315         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 316         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 317         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 318         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 319         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 320         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 321         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 322         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 323         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 324         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 325         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 326         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 327         case CS42L42_SUB_REVID:
 328                 return true;
 329         default:
 330                 return false;
 331         }
 332 }
 333 EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE);
 334
 335 bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 336 {
 337         switch (reg) {
 338         case CS42L42_DEVID_AB:
 339         case CS42L42_DEVID_CD:
 340         case CS42L42_DEVID_E:
 341         case CS42L42_MCLK_STATUS:
 342         case CS42L42_OSC_SWITCH_STATUS:
 343         case CS42L42_TRSENSE_STATUS:
 344         case CS42L42_HS_DET_STATUS:
 345         case CS42L42_ADC_OVFL_STATUS:
 346         case CS42L42_MIXER_STATUS:
 347         case CS42L42_SRC_STATUS:
 348         case CS42L42_ASP_RX_STATUS:
 349         case CS42L42_ASP_TX_STATUS:
 350         case CS42L42_CODEC_STATUS:
 351         case CS42L42_DET_INT_STATUS1:
 352         case CS42L42_DET_INT_STATUS2:
 353         case CS42L42_SRCPL_INT_STATUS:
 354         case CS42L42_VPMON_STATUS:
 355         case CS42L42_PLL_LOCK_STATUS:
 356         case CS42L42_TSRS_PLUG_STATUS:
 357         case CS42L42_LOAD_DET_RCSTAT:
 358         case CS42L42_LOAD_DET_DONE:
 359         case CS42L42_DET_STATUS1:
 360         case CS42L42_DET_STATUS2:
 361                 return true;
 362         default:
 363                 return false;
 364         }
 365 }
 366 EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE);
 367
 368 const struct regmap_range_cfg cs42l42_page_range = {
 369         .name = "Pages",
 370         .range_min = 0,
 371         .range_max = CS42L42_MAX_REGISTER,
 372         .selector_reg = CS42L42_PAGE_REGISTER,
 373         .selector_mask = 0xff,
 374         .selector_shift = 0,
 375         .window_start = 0,
 376         .window_len = 256,
 377 };
 378 EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE);
 379
 380 const struct regmap_config cs42l42_regmap = {
 381         .reg_bits = 8,
 382         .val_bits = 8,
 383
 384         .readable_reg = cs42l42_readable_register,
 385         .volatile_reg = cs42l42_volatile_register,
 386
 387         .ranges = &cs42l42_page_range,
 388         .num_ranges = 1,
 389
 390         .max_register = CS42L42_MAX_REGISTER,
 391         .reg_defaults = cs42l42_reg_defaults,
 392         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 393         .cache_type = REGCACHE_RBTREE,
 394
 395         .use_single_read = true,
 396         .use_single_write = true,
 397 };
 398 EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE);
 399
 400 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 401 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 402
 403 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
 404                                   struct snd_ctl_elem_value *ucontrol)
 405 {
 406         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 407         u8 val;
 408
 409         /* all bits of SLOW_START_EN must change together */
 410         switch (ucontrol->value.integer.value[0]) {
 411         case 0:
 412                 val = 0;
 413                 break;
 414         case 1:
 415                 val = CS42L42_SLOW_START_EN_MASK;
 416                 break;
 417         default:
 418                 return -EINVAL;
 419         }
 420
 421         return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
 422                                              CS42L42_SLOW_START_EN_MASK, val);
 423 }
 424
 425 static const char * const cs42l42_hpf_freq_text[] = {
 426         "1.86Hz", "120Hz", "235Hz", "466Hz"
 427 };
 428
 429 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 430                             CS42L42_ADC_HPF_CF_SHIFT,
 431                             cs42l42_hpf_freq_text);
 432
 433 static const char * const cs42l42_wnf3_freq_text[] = {
 434         "160Hz", "180Hz", "200Hz", "220Hz",
 435         "240Hz", "260Hz", "280Hz", "300Hz"
 436 };
 437
 438 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 439                             CS42L42_ADC_WNF_CF_SHIFT,
 440                             cs42l42_wnf3_freq_text);
 441
 442 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 443         /* ADC Volume and Filter Controls */
 444         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 445                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 446         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 447                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 448         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 449                                 CS42L42_ADC_INV_SHIFT, true, false),
 450         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 451                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 452         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 453         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 454                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 455         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 456                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 457         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 458         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 459
 460         /* DAC Volume and Filter Controls */
 461         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 462                                 CS42L42_DACA_INV_SHIFT, true, false),
 463         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 464                                 CS42L42_DACB_INV_SHIFT, true, false),
 465         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 466                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 467         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 468                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 469                                 0x3f, 1, mixer_tlv),
 470
 471         SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
 472                         CS42L42_SLOW_START_EN_SHIFT, true, false,
 473                         snd_soc_get_volsw, cs42l42_slow_start_put),
 474 };
 475
 476 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
 477                              struct snd_kcontrol *kcontrol, int event)
 478 {
 479         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 480         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 481
 482         switch (event) {
 483         case SND_SOC_DAPM_PRE_PMU:
 484                 cs42l42->hp_adc_up_pending = true;
 485                 break;
 486         case SND_SOC_DAPM_POST_PMU:
 487                 /* Only need one delay if HP and ADC are both powering-up */
 488                 if (cs42l42->hp_adc_up_pending) {
 489                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
 490                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
 491                         cs42l42->hp_adc_up_pending = false;
 492                 }
 493                 break;
 494         default:
 495                 break;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 502         /* Playback Path */
 503         SND_SOC_DAPM_OUTPUT("HP"),
 504         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
 505                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 506         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 507         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 508         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 509
 510         /* Playback Requirements */
 511         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 512
 513         /* Capture Path */
 514         SND_SOC_DAPM_INPUT("HS"),
 515         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
 516                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 517         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 518         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 519
 520         /* Capture Requirements */
 521         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 522         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 523
 524         /* Playback/Capture Requirements */
 525         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 526 };
 527
 528 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 529         /* Playback Path */
 530         {"HP", NULL, "DAC"},
 531         {"DAC", NULL, "MIXER"},
 532         {"MIXER", NULL, "SDIN1"},
 533         {"MIXER", NULL, "SDIN2"},
 534         {"SDIN1", NULL, "Playback"},
 535         {"SDIN2", NULL, "Playback"},
 536
 537         /* Playback Requirements */
 538         {"SDIN1", NULL, "ASP DAI0"},
 539         {"SDIN2", NULL, "ASP DAI0"},
 540         {"SDIN1", NULL, "SCLK"},
 541         {"SDIN2", NULL, "SCLK"},
 542
 543         /* Capture Path */
 544         {"ADC", NULL, "HS"},
 545         { "SDOUT1", NULL, "ADC" },
 546         { "SDOUT2", NULL, "ADC" },
 547         { "Capture", NULL, "SDOUT1" },
 548         { "Capture", NULL, "SDOUT2" },
 549
 550         /* Capture Requirements */
 551         { "SDOUT1", NULL, "ASP DAO0" },
 552         { "SDOUT2", NULL, "ASP DAO0" },
 553         { "SDOUT1", NULL, "SCLK" },
 554         { "SDOUT2", NULL, "SCLK" },
 555         { "SDOUT1", NULL, "ASP TX EN" },
 556         { "SDOUT2", NULL, "ASP TX EN" },
 557 };
 558
 559 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 560 {
 561         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 562
 563         /* Prevent race with interrupt handler */
 564         mutex_lock(&cs42l42->irq_lock);
 565         cs42l42->jack = jk;
 566
 567         if (jk) {
 568                 switch (cs42l42->hs_type) {
 569                 case CS42L42_PLUG_CTIA:
 570                 case CS42L42_PLUG_OMTP:
 571                         snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
 572                         break;
 573                 case CS42L42_PLUG_HEADPHONE:
 574                         snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
 575                         break;
 576                 default:
 577                         break;
 578                 }
 579         }
 580         mutex_unlock(&cs42l42->irq_lock);
 581
 582         return 0;
 583 }
 584
 585 const struct snd_soc_component_driver cs42l42_soc_component = {
 586         .set_jack               = cs42l42_set_jack,
 587         .dapm_widgets           = cs42l42_dapm_widgets,
 588         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 589         .dapm_routes            = cs42l42_audio_map,
 590         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 591         .controls               = cs42l42_snd_controls,
 592         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 593         .idle_bias_on           = 1,
 594         .endianness             = 1,
 595 };
 596 EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE);
 597
 598 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 599 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 600         {
 601                 .reg = CS42L42_OSC_SWITCH,
 602                 .def = CS42L42_SCLK_PRESENT_MASK,
 603                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 604         },
 605 };
 606
 607 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 608 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 609         {
 610                 .reg = CS42L42_OSC_SWITCH,
 611                 .def = 0,
 612                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 613         },
 614 };
 615
 616 struct cs42l42_pll_params {
 617         u32 sclk;
 618         u8 mclk_src_sel;
 619         u8 sclk_prediv;
 620         u8 pll_div_int;
 621         u32 pll_div_frac;
 622         u8 pll_mode;
 623         u8 pll_divout;
 624         u32 mclk_int;
 625         u8 pll_cal_ratio;
 626         u8 n;
 627 };
 628
 629 /*
 630  * Common PLL Settings for given SCLK
 631  * Table 4-5 from the Datasheet
 632  */
 633 static const struct cs42l42_pll_params pll_ratio_table[] = {
 634         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 635         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 636         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 637         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 638         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 639         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 640         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 641         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 642         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 643         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 644         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 645         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 646         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 647         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 648         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 649         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 650         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 651         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 652 };
 653
 654 static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk)
 655 {
 656         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 657         int i;
 658         u32 fsync;
 659
 660         /* Don't reconfigure if there is an audio stream running */
 661         if (cs42l42->stream_use) {
 662                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
 663                         return 0;
 664                 else
 665                         return -EBUSY;
 666         }
 667
 668         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 669                 if (pll_ratio_table[i].sclk == clk) {
 670                         cs42l42->pll_config = i;
 671
 672                         /* Configure the internal sample rate */
 673                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 674                                         CS42L42_INTERNAL_FS_MASK,
 675                                         ((pll_ratio_table[i].mclk_int !=
 676                                         12000000) &&
 677                                         (pll_ratio_table[i].mclk_int !=
 678                                         24000000)) <<
 679                                         CS42L42_INTERNAL_FS_SHIFT);
 680
 681                         /* Set up the LRCLK */
 682                         fsync = clk / cs42l42->srate;
 683                         if (((fsync * cs42l42->srate) != clk)
 684                                 || ((fsync % 2) != 0)) {
 685                                 dev_err(component->dev,
 686                                         "Unsupported sclk %d/sample rate %d\n",
 687                                         clk,
 688                                         cs42l42->srate);
 689                                 return -EINVAL;
 690                         }
 691                         /* Set the LRCLK period */
 692                         snd_soc_component_update_bits(component,
 693                                         CS42L42_FSYNC_P_LOWER,
 694                                         CS42L42_FSYNC_PERIOD_MASK,
 695                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 696                                         CS42L42_FSYNC_PERIOD_SHIFT);
 697                         snd_soc_component_update_bits(component,
 698                                         CS42L42_FSYNC_P_UPPER,
 699                                         CS42L42_FSYNC_PERIOD_MASK,
 700                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 701                                         CS42L42_FSYNC_PERIOD_SHIFT);
 702                         /* Set the LRCLK to 50% duty cycle */
 703                         fsync = fsync / 2;
 704                         snd_soc_component_update_bits(component,
 705                                         CS42L42_FSYNC_PW_LOWER,
 706                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 707                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 708                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 709                         snd_soc_component_update_bits(component,
 710                                         CS42L42_FSYNC_PW_UPPER,
 711                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 712                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 713                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 714                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 715                                 /* Pass the clock straight through */
 716                                 snd_soc_component_update_bits(component,
 717                                         CS42L42_PLL_CTL1,
 718                                         CS42L42_PLL_START_MASK, 0);
 719                         } else {
 720                                 /* Configure PLL per table 4-5 */
 721                                 snd_soc_component_update_bits(component,
 722                                         CS42L42_PLL_DIV_CFG1,
 723                                         CS42L42_SCLK_PREDIV_MASK,
 724                                         pll_ratio_table[i].sclk_prediv
 725                                         << CS42L42_SCLK_PREDIV_SHIFT);
 726                                 snd_soc_component_update_bits(component,
 727                                         CS42L42_PLL_DIV_INT,
 728                                         CS42L42_PLL_DIV_INT_MASK,
 729                                         pll_ratio_table[i].pll_div_int
 730                                         << CS42L42_PLL_DIV_INT_SHIFT);
 731                                 snd_soc_component_update_bits(component,
 732                                         CS42L42_PLL_DIV_FRAC0,
 733                                         CS42L42_PLL_DIV_FRAC_MASK,
 734                                         CS42L42_FRAC0_VAL(
 735                                         pll_ratio_table[i].pll_div_frac)
 736                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 737                                 snd_soc_component_update_bits(component,
 738                                         CS42L42_PLL_DIV_FRAC1,
 739                                         CS42L42_PLL_DIV_FRAC_MASK,
 740                                         CS42L42_FRAC1_VAL(
 741                                         pll_ratio_table[i].pll_div_frac)
 742                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 743                                 snd_soc_component_update_bits(component,
 744                                         CS42L42_PLL_DIV_FRAC2,
 745                                         CS42L42_PLL_DIV_FRAC_MASK,
 746                                         CS42L42_FRAC2_VAL(
 747                                         pll_ratio_table[i].pll_div_frac)
 748                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 749                                 snd_soc_component_update_bits(component,
 750                                         CS42L42_PLL_CTL4,
 751                                         CS42L42_PLL_MODE_MASK,
 752                                         pll_ratio_table[i].pll_mode
 753                                         << CS42L42_PLL_MODE_SHIFT);
 754                                 snd_soc_component_update_bits(component,
 755                                         CS42L42_PLL_CTL3,
 756                                         CS42L42_PLL_DIVOUT_MASK,
 757                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 758                                         << CS42L42_PLL_DIVOUT_SHIFT);
 759                                 snd_soc_component_update_bits(component,
 760                                         CS42L42_PLL_CAL_RATIO,
 761                                         CS42L42_PLL_CAL_RATIO_MASK,
 762                                         pll_ratio_table[i].pll_cal_ratio
 763                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 764                         }
 765                         return 0;
 766                 }
 767         }
 768
 769         return -EINVAL;
 770 }
 771
 772 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
 773 {
 774         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 775         unsigned int fs;
 776
 777         /* Don't reconfigure if there is an audio stream running */
 778         if (cs42l42->stream_use)
 779                 return;
 780
 781         /* SRC MCLK must be as close as possible to 125 * sample rate */
 782         if (sample_rate <= 48000)
 783                 fs = CS42L42_CLK_IASRC_SEL_6;
 784         else
 785                 fs = CS42L42_CLK_IASRC_SEL_12;
 786
 787         /* Set the sample rates (96k or lower) */
 788         snd_soc_component_update_bits(component,
 789                                       CS42L42_FS_RATE_EN,
 790                                       CS42L42_FS_EN_MASK,
 791                                       (CS42L42_FS_EN_IASRC_96K |
 792                                        CS42L42_FS_EN_OASRC_96K) <<
 793                                       CS42L42_FS_EN_SHIFT);
 794
 795         snd_soc_component_update_bits(component,
 796                                       CS42L42_IN_ASRC_CLK,
 797                                       CS42L42_CLK_IASRC_SEL_MASK,
 798                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
 799         snd_soc_component_update_bits(component,
 800                                       CS42L42_OUT_ASRC_CLK,
 801                                       CS42L42_CLK_OASRC_SEL_MASK,
 802                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
 803 }
 804
 805 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 806 {
 807         struct snd_soc_component *component = codec_dai->component;
 808         u32 asp_cfg_val = 0;
 809
 810         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 811         case SND_SOC_DAIFMT_CBS_CFM:
 812                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 813                                 CS42L42_ASP_MODE_SHIFT;
 814                 break;
 815         case SND_SOC_DAIFMT_CBS_CFS:
 816                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 817                                 CS42L42_ASP_MODE_SHIFT;
 818                 break;
 819         default:
 820                 return -EINVAL;
 821         }
 822
 823         /* interface format */
 824         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 825         case SND_SOC_DAIFMT_I2S:
 826                 /*
 827                  * 5050 mode, frame starts on falling edge of LRCLK,
 828                  * frame delayed by 1.0 SCLKs
 829                  */
 830                 snd_soc_component_update_bits(component,
 831                                               CS42L42_ASP_FRM_CFG,
 832                                               CS42L42_ASP_STP_MASK |
 833                                               CS42L42_ASP_5050_MASK |
 834                                               CS42L42_ASP_FSD_MASK,
 835                                               CS42L42_ASP_5050_MASK |
 836                                               (CS42L42_ASP_FSD_1_0 <<
 837                                                 CS42L42_ASP_FSD_SHIFT));
 838                 break;
 839         default:
 840                 return -EINVAL;
 841         }
 842
 843         /* Bitclock/frame inversion */
 844         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 845         case SND_SOC_DAIFMT_NB_NF:
 846                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 847                 break;
 848         case SND_SOC_DAIFMT_NB_IF:
 849                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 850                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 851                 break;
 852         case SND_SOC_DAIFMT_IB_NF:
 853                 break;
 854         case SND_SOC_DAIFMT_IB_IF:
 855                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 856                 break;
 857         }
 858
 859         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 860                                                                       CS42L42_ASP_SCPOL_MASK |
 861                                                                       CS42L42_ASP_LCPOL_MASK,
 862                                                                       asp_cfg_val);
 863
 864         return 0;
 865 }
 866
 867 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 868 {
 869         struct snd_soc_component *component = dai->component;
 870         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 871
 872         /*
 873          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 874          * a standard I2S frame. If the machine driver sets SCLK it must be
 875          * legal.
 876          */
 877         if (cs42l42->sclk)
 878                 return 0;
 879
 880         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 881         return snd_pcm_hw_constraint_minmax(substream->runtime,
 882                                             SNDRV_PCM_HW_PARAM_RATE,
 883                                             44100, 96000);
 884 }
 885
 886 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 887                                 struct snd_pcm_hw_params *params,
 888                                 struct snd_soc_dai *dai)
 889 {
 890         struct snd_soc_component *component = dai->component;
 891         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 892         unsigned int channels = params_channels(params);
 893         unsigned int width = (params_width(params) / 8) - 1;
 894         unsigned int slot_width = 0;
 895         unsigned int val = 0;
 896         unsigned int bclk;
 897         int ret;
 898
 899         cs42l42->srate = params_rate(params);
 900
 901         if (cs42l42->bclk_ratio) {
 902                 /* machine driver has set the BCLK/samp-rate ratio */
 903                 bclk = cs42l42->bclk_ratio * params_rate(params);
 904         } else if (cs42l42->sclk) {
 905                 /* machine driver has set the SCLK */
 906                 bclk = cs42l42->sclk;
 907         } else {
 908                 /*
 909                  * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 910                  * more than assumed (which would result in overclocking).
 911                  */
 912                 if (params_width(params) == 24)
 913                         slot_width = 32;
 914
 915                 /* I2S frame always has multiple of 2 channels */
 916                 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2);
 917         }
 918
 919         switch (substream->stream) {
 920         case SNDRV_PCM_STREAM_CAPTURE:
 921                 /* channel 2 on high LRCLK */
 922                 val = CS42L42_ASP_TX_CH2_AP_MASK |
 923                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
 924                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 925
 926                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 927                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 928                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 929                 break;
 930         case SNDRV_PCM_STREAM_PLAYBACK:
 931                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 932                 /* channel 1 on low LRCLK */
 933                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 934                                                          CS42L42_ASP_RX_CH_AP_MASK |
 935                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 936                 /* Channel 2 on high LRCLK */
 937                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 938                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 939                                                          CS42L42_ASP_RX_CH_AP_MASK |
 940                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 941
 942                 /* Channel B comes from the last active channel */
 943                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 944                                               CS42L42_SP_RX_CHB_SEL_MASK,
 945                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 946
 947                 /* Both LRCLK slots must be enabled */
 948                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 949                                               CS42L42_ASP_RX0_CH_EN_MASK,
 950                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 951                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 952                 break;
 953         default:
 954                 break;
 955         }
 956
 957         ret = cs42l42_pll_config(component, bclk);
 958         if (ret)
 959                 return ret;
 960
 961         cs42l42_src_config(component, params_rate(params));
 962
 963         return 0;
 964 }
 965
 966 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 967                                 int clk_id, unsigned int freq, int dir)
 968 {
 969         struct snd_soc_component *component = dai->component;
 970         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 971         int i;
 972
 973         if (freq == 0) {
 974                 cs42l42->sclk = 0;
 975                 return 0;
 976         }
 977
 978         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 979                 if (pll_ratio_table[i].sclk == freq) {
 980                         cs42l42->sclk = freq;
 981                         return 0;
 982                 }
 983         }
 984
 985         dev_err(component->dev, "SCLK %u not supported\n", freq);
 986
 987         return -EINVAL;
 988 }
 989
 990 static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai,
 991                                 unsigned int bclk_ratio)
 992 {
 993         struct snd_soc_component *component = dai->component;
 994         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 995
 996         cs42l42->bclk_ratio = bclk_ratio;
 997
 998         return 0;
 999 }
1000
1001 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1002 {
1003         struct snd_soc_component *component = dai->component;
1004         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
1005         unsigned int regval;
1006         int ret;
1007
1008         if (mute) {
1009                 /* Mute the headphone */
1010                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1011                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1012                                                       CS42L42_HP_ANA_AMUTE_MASK |
1013                                                       CS42L42_HP_ANA_BMUTE_MASK,
1014                                                       CS42L42_HP_ANA_AMUTE_MASK |
1015                                                       CS42L42_HP_ANA_BMUTE_MASK);
1016
1017                 cs42l42->stream_use &= ~(1 << stream);
1018                 if (!cs42l42->stream_use) {
1019                         /*
1020                          * Switch to the internal oscillator.
1021                          * SCLK must remain running until after this clock switch.
1022                          * Without a source of clock the I2C bus doesn't work.
1023                          */
1024                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
1025                                                ARRAY_SIZE(cs42l42_to_osc_seq));
1026
1027                         /* Must disconnect PLL before stopping it */
1028                         snd_soc_component_update_bits(component,
1029                                                       CS42L42_MCLK_SRC_SEL,
1030                                                       CS42L42_MCLK_SRC_SEL_MASK,
1031                                                       0);
1032                         usleep_range(100, 200);
1033
1034                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1035                                                       CS42L42_PLL_START_MASK, 0);
1036                 }
1037         } else {
1038                 if (!cs42l42->stream_use) {
1039                         /* SCLK must be running before codec unmute.
1040                          *
1041                          * PLL must not be started with ADC and HP both off
1042                          * otherwise the FILT+ supply will not charge properly.
1043                          * DAPM widgets power-up before stream unmute so at least
1044                          * one of the "DAC" or "ADC" widgets will already have
1045                          * powered-up.
1046                          */
1047                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1048                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1049                                                               CS42L42_PLL_START_MASK, 1);
1050
1051                                 if (pll_ratio_table[cs42l42->pll_config].n > 1) {
1052                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1053                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
1054                                         regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
1055                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1056                                                                       CS42L42_PLL_DIVOUT_MASK,
1057                                                                       regval <<
1058                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1059                                 }
1060
1061                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1062                                                                CS42L42_PLL_LOCK_STATUS,
1063                                                                regval,
1064                                                                (regval & 1),
1065                                                                CS42L42_PLL_LOCK_POLL_US,
1066                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1067                                 if (ret < 0)
1068                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1069
1070                                 /* PLL must be running to drive glitchless switch logic */
1071                                 snd_soc_component_update_bits(component,
1072                                                               CS42L42_MCLK_SRC_SEL,
1073                                                               CS42L42_MCLK_SRC_SEL_MASK,
1074                                                               CS42L42_MCLK_SRC_SEL_MASK);
1075                         }
1076
1077                         /* Mark SCLK as present, turn off internal oscillator */
1078                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1079                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1080                 }
1081                 cs42l42->stream_use |= 1 << stream;
1082
1083                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1084                         /* Un-mute the headphone */
1085                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1086                                                       CS42L42_HP_ANA_AMUTE_MASK |
1087                                                       CS42L42_HP_ANA_BMUTE_MASK,
1088                                                       0);
1089                 }
1090         }
1091
1092         return 0;
1093 }
1094
1095 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1096                          SNDRV_PCM_FMTBIT_S24_LE |\
1097                          SNDRV_PCM_FMTBIT_S32_LE)
1098
1099 static const struct snd_soc_dai_ops cs42l42_ops = {
1100         .startup        = cs42l42_dai_startup,
1101         .hw_params      = cs42l42_pcm_hw_params,
1102         .set_fmt        = cs42l42_set_dai_fmt,
1103         .set_sysclk     = cs42l42_set_sysclk,
1104         .set_bclk_ratio = cs42l42_set_bclk_ratio,
1105         .mute_stream    = cs42l42_mute_stream,
1106 };
1107
1108 struct snd_soc_dai_driver cs42l42_dai = {
1109                 .name = "cs42l42",
1110                 .playback = {
1111                         .stream_name = "Playback",
1112                         .channels_min = 1,
1113                         .channels_max = 2,
1114                         .rates = SNDRV_PCM_RATE_8000_96000,
1115                         .formats = CS42L42_FORMATS,
1116                 },
1117                 .capture = {
1118                         .stream_name = "Capture",
1119                         .channels_min = 1,
1120                         .channels_max = 2,
1121                         .rates = SNDRV_PCM_RATE_8000_96000,
1122                         .formats = CS42L42_FORMATS,
1123                 },
1124                 .symmetric_rate = 1,
1125                 .symmetric_sample_bits = 1,
1126                 .ops = &cs42l42_ops,
1127 };
1128 EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE);
1129
1130 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1131 {
1132         unsigned int hs_det_status;
1133         unsigned int hs_det_comp1;
1134         unsigned int hs_det_comp2;
1135         unsigned int hs_det_sw;
1136
1137         /* Set hs detect to manual, active mode */
1138         regmap_update_bits(cs42l42->regmap,
1139                 CS42L42_HSDET_CTL2,
1140                 CS42L42_HSDET_CTRL_MASK |
1141                 CS42L42_HSDET_SET_MASK |
1142                 CS42L42_HSBIAS_REF_MASK |
1143                 CS42L42_HSDET_AUTO_TIME_MASK,
1144                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1145                 (0 << CS42L42_HSDET_SET_SHIFT) |
1146                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1147                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1148
1149         /* Configure HS DET comparator reference levels. */
1150         regmap_update_bits(cs42l42->regmap,
1151                                 CS42L42_HSDET_CTL1,
1152                                 CS42L42_HSDET_COMP1_LVL_MASK |
1153                                 CS42L42_HSDET_COMP2_LVL_MASK,
1154                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1155                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1156
1157         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1158         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1159
1160         msleep(100);
1161
1162         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1163
1164         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1165                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1166         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1167                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1168
1169         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1170         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1171
1172         msleep(100);
1173
1174         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1175
1176         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1177                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1178         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1179                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1180
1181         /* Use Comparator 1 with 1.25V Threshold. */
1182         switch (hs_det_comp1) {
1183         case CS42L42_HSDET_COMP_TYPE1:
1184                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1185                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1186                 break;
1187         case CS42L42_HSDET_COMP_TYPE2:
1188                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1189                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1190                 break;
1191         default:
1192                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1193                 switch (hs_det_comp2) {
1194                 case CS42L42_HSDET_COMP_TYPE1:
1195                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1196                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1197                         break;
1198                 case CS42L42_HSDET_COMP_TYPE2:
1199                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1200                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1201                         break;
1202                 case CS42L42_HSDET_COMP_TYPE3:
1203                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1204                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1205                         break;
1206                 default:
1207                         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1208                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
1209                         break;
1210                 }
1211         }
1212
1213         /* Set Switches */
1214         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1215
1216         /* Set HSDET mode to Manual—Disabled */
1217         regmap_update_bits(cs42l42->regmap,
1218                 CS42L42_HSDET_CTL2,
1219                 CS42L42_HSDET_CTRL_MASK |
1220                 CS42L42_HSDET_SET_MASK |
1221                 CS42L42_HSBIAS_REF_MASK |
1222                 CS42L42_HSDET_AUTO_TIME_MASK,
1223                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1224                 (0 << CS42L42_HSDET_SET_SHIFT) |
1225                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1226                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1227
1228         /* Configure HS DET comparator reference levels. */
1229         regmap_update_bits(cs42l42->regmap,
1230                                 CS42L42_HSDET_CTL1,
1231                                 CS42L42_HSDET_COMP1_LVL_MASK |
1232                                 CS42L42_HSDET_COMP2_LVL_MASK,
1233                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1234                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1235 }
1236
1237 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1238 {
1239         unsigned int hs_det_status;
1240         unsigned int int_status;
1241
1242         /* Read and save the hs detection result */
1243         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1244
1245         /* Mask the auto detect interrupt */
1246         regmap_update_bits(cs42l42->regmap,
1247                 CS42L42_CODEC_INT_MASK,
1248                 CS42L42_PDN_DONE_MASK |
1249                 CS42L42_HSDET_AUTO_DONE_MASK,
1250                 (1 << CS42L42_PDN_DONE_SHIFT) |
1251                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1252
1253
1254         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1255                                 CS42L42_HSDET_TYPE_SHIFT;
1256
1257         /* Set hs detect to automatic, disabled mode */
1258         regmap_update_bits(cs42l42->regmap,
1259                 CS42L42_HSDET_CTL2,
1260                 CS42L42_HSDET_CTRL_MASK |
1261                 CS42L42_HSDET_SET_MASK |
1262                 CS42L42_HSBIAS_REF_MASK |
1263                 CS42L42_HSDET_AUTO_TIME_MASK,
1264                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1265                 (2 << CS42L42_HSDET_SET_SHIFT) |
1266                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1267                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1268
1269         /* Run Manual detection if auto detect has not found a headset.
1270          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1271          * to ensure that a headset mic is detected in all cases.
1272          */
1273         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1274                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1275                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1276                 cs42l42_manual_hs_type_detect(cs42l42);
1277         }
1278
1279         /* Set up button detection */
1280         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1281               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1282                 /* Set auto HS bias settings to default */
1283                 regmap_update_bits(cs42l42->regmap,
1284                         CS42L42_HSBIAS_SC_AUTOCTL,
1285                         CS42L42_HSBIAS_SENSE_EN_MASK |
1286                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1287                         CS42L42_TIP_SENSE_EN_MASK |
1288                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1289                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1290                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1291                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1292                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1293
1294                 /* Set up hs detect level sensitivity */
1295                 regmap_update_bits(cs42l42->regmap,
1296                         CS42L42_MIC_DET_CTL1,
1297                         CS42L42_LATCH_TO_VP_MASK |
1298                         CS42L42_EVENT_STAT_SEL_MASK |
1299                         CS42L42_HS_DET_LEVEL_MASK,
1300                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1301                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1302                         (cs42l42->bias_thresholds[0] <<
1303                         CS42L42_HS_DET_LEVEL_SHIFT));
1304
1305                 /* Set auto HS bias settings to default */
1306                 regmap_update_bits(cs42l42->regmap,
1307                         CS42L42_HSBIAS_SC_AUTOCTL,
1308                         CS42L42_HSBIAS_SENSE_EN_MASK |
1309                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1310                         CS42L42_TIP_SENSE_EN_MASK |
1311                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1312                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1313                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1314                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1315                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1316
1317                 /* Turn on level detect circuitry */
1318                 regmap_update_bits(cs42l42->regmap,
1319                         CS42L42_MISC_DET_CTL,
1320                         CS42L42_HSBIAS_CTL_MASK |
1321                         CS42L42_PDN_MIC_LVL_DET_MASK,
1322                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1323                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1324
1325                 msleep(cs42l42->btn_det_init_dbnce);
1326
1327                 /* Clear any button interrupts before unmasking them */
1328                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1329                             &int_status);
1330
1331                 /* Unmask button detect interrupts */
1332                 regmap_update_bits(cs42l42->regmap,
1333                         CS42L42_DET_INT2_MASK,
1334                         CS42L42_M_DETECT_TF_MASK |
1335                         CS42L42_M_DETECT_FT_MASK |
1336                         CS42L42_M_HSBIAS_HIZ_MASK |
1337                         CS42L42_M_SHORT_RLS_MASK |
1338                         CS42L42_M_SHORT_DET_MASK,
1339                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1340                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1341                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1342                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1343                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1344         } else {
1345                 /* Make sure button detect and HS bias circuits are off */
1346                 regmap_update_bits(cs42l42->regmap,
1347                         CS42L42_MISC_DET_CTL,
1348                         CS42L42_HSBIAS_CTL_MASK |
1349                         CS42L42_PDN_MIC_LVL_DET_MASK,
1350                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1351                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1352         }
1353
1354         regmap_update_bits(cs42l42->regmap,
1355                                 CS42L42_DAC_CTL2,
1356                                 CS42L42_HPOUT_PULLDOWN_MASK |
1357                                 CS42L42_HPOUT_LOAD_MASK |
1358                                 CS42L42_HPOUT_CLAMP_MASK |
1359                                 CS42L42_DAC_HPF_EN_MASK |
1360                                 CS42L42_DAC_MON_EN_MASK,
1361                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1362                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1363                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1364                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1365                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1366
1367         /* Unmask tip sense interrupts */
1368         regmap_update_bits(cs42l42->regmap,
1369                 CS42L42_TSRS_PLUG_INT_MASK,
1370                 CS42L42_TS_PLUG_MASK |
1371                 CS42L42_TS_UNPLUG_MASK,
1372                 (0 << CS42L42_TS_PLUG_SHIFT) |
1373                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1374 }
1375
1376 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1377 {
1378         /* Mask tip sense interrupts */
1379         regmap_update_bits(cs42l42->regmap,
1380                                 CS42L42_TSRS_PLUG_INT_MASK,
1381                                 CS42L42_TS_PLUG_MASK |
1382                                 CS42L42_TS_UNPLUG_MASK,
1383                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1384                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1385
1386         /* Make sure button detect and HS bias circuits are off */
1387         regmap_update_bits(cs42l42->regmap,
1388                                 CS42L42_MISC_DET_CTL,
1389                                 CS42L42_HSBIAS_CTL_MASK |
1390                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1391                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1392                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1393
1394         /* Set auto HS bias settings to default */
1395         regmap_update_bits(cs42l42->regmap,
1396                                 CS42L42_HSBIAS_SC_AUTOCTL,
1397                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1398                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1399                                 CS42L42_TIP_SENSE_EN_MASK |
1400                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1401                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1402                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1403                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1404                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1405
1406         /* Set hs detect to manual, disabled mode */
1407         regmap_update_bits(cs42l42->regmap,
1408                                 CS42L42_HSDET_CTL2,
1409                                 CS42L42_HSDET_CTRL_MASK |
1410                                 CS42L42_HSDET_SET_MASK |
1411                                 CS42L42_HSBIAS_REF_MASK |
1412                                 CS42L42_HSDET_AUTO_TIME_MASK,
1413                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1414                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1415                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1416                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1417
1418         regmap_update_bits(cs42l42->regmap,
1419                                 CS42L42_DAC_CTL2,
1420                                 CS42L42_HPOUT_PULLDOWN_MASK |
1421                                 CS42L42_HPOUT_LOAD_MASK |
1422                                 CS42L42_HPOUT_CLAMP_MASK |
1423                                 CS42L42_DAC_HPF_EN_MASK |
1424                                 CS42L42_DAC_MON_EN_MASK,
1425                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1426                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1427                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1428                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1429                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1430
1431         /* Power up HS bias to 2.7V */
1432         regmap_update_bits(cs42l42->regmap,
1433                                 CS42L42_MISC_DET_CTL,
1434                                 CS42L42_HSBIAS_CTL_MASK |
1435                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1436                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1437                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1438
1439         /* Wait for HS bias to ramp up */
1440         msleep(cs42l42->hs_bias_ramp_time);
1441
1442         /* Unmask auto detect interrupt */
1443         regmap_update_bits(cs42l42->regmap,
1444                                 CS42L42_CODEC_INT_MASK,
1445                                 CS42L42_PDN_DONE_MASK |
1446                                 CS42L42_HSDET_AUTO_DONE_MASK,
1447                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1448                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1449
1450         /* Set hs detect to automatic, enabled mode */
1451         regmap_update_bits(cs42l42->regmap,
1452                                 CS42L42_HSDET_CTL2,
1453                                 CS42L42_HSDET_CTRL_MASK |
1454                                 CS42L42_HSDET_SET_MASK |
1455                                 CS42L42_HSBIAS_REF_MASK |
1456                                 CS42L42_HSDET_AUTO_TIME_MASK,
1457                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1458                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1459                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1460                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1461 }
1462
1463 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1464 {
1465         /* Mask button detect interrupts */
1466         regmap_update_bits(cs42l42->regmap,
1467                 CS42L42_DET_INT2_MASK,
1468                 CS42L42_M_DETECT_TF_MASK |
1469                 CS42L42_M_DETECT_FT_MASK |
1470                 CS42L42_M_HSBIAS_HIZ_MASK |
1471                 CS42L42_M_SHORT_RLS_MASK |
1472                 CS42L42_M_SHORT_DET_MASK,
1473                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1474                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1475                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1476                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1477                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1478
1479         /* Ground HS bias */
1480         regmap_update_bits(cs42l42->regmap,
1481                                 CS42L42_MISC_DET_CTL,
1482                                 CS42L42_HSBIAS_CTL_MASK |
1483                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1484                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1485                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1486
1487         /* Set auto HS bias settings to default */
1488         regmap_update_bits(cs42l42->regmap,
1489                                 CS42L42_HSBIAS_SC_AUTOCTL,
1490                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1491                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1492                                 CS42L42_TIP_SENSE_EN_MASK |
1493                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1494                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1495                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1496                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1497                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1498
1499         /* Set hs detect to manual, disabled mode */
1500         regmap_update_bits(cs42l42->regmap,
1501                                 CS42L42_HSDET_CTL2,
1502                                 CS42L42_HSDET_CTRL_MASK |
1503                                 CS42L42_HSDET_SET_MASK |
1504                                 CS42L42_HSBIAS_REF_MASK |
1505                                 CS42L42_HSDET_AUTO_TIME_MASK,
1506                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1507                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1508                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1509                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1510 }
1511
1512 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1513 {
1514         int bias_level;
1515         unsigned int detect_status;
1516
1517         /* Mask button detect interrupts */
1518         regmap_update_bits(cs42l42->regmap,
1519                 CS42L42_DET_INT2_MASK,
1520                 CS42L42_M_DETECT_TF_MASK |
1521                 CS42L42_M_DETECT_FT_MASK |
1522                 CS42L42_M_HSBIAS_HIZ_MASK |
1523                 CS42L42_M_SHORT_RLS_MASK |
1524                 CS42L42_M_SHORT_DET_MASK,
1525                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1526                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1527                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1528                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1529                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1530
1531         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1532                      cs42l42->btn_det_event_dbnce * 2000);
1533
1534         /* Test all 4 level detect biases */
1535         bias_level = 1;
1536         do {
1537                 /* Adjust button detect level sensitivity */
1538                 regmap_update_bits(cs42l42->regmap,
1539                         CS42L42_MIC_DET_CTL1,
1540                         CS42L42_LATCH_TO_VP_MASK |
1541                         CS42L42_EVENT_STAT_SEL_MASK |
1542                         CS42L42_HS_DET_LEVEL_MASK,
1543                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1544                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1545                         (cs42l42->bias_thresholds[bias_level] <<
1546                         CS42L42_HS_DET_LEVEL_SHIFT));
1547
1548                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1549                                 &detect_status);
1550         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1551                 (++bias_level < CS42L42_NUM_BIASES));
1552
1553         switch (bias_level) {
1554         case 1: /* Function C button press */
1555                 bias_level = SND_JACK_BTN_2;
1556                 dev_dbg(cs42l42->dev, "Function C button press\n");
1557                 break;
1558         case 2: /* Function B button press */
1559                 bias_level = SND_JACK_BTN_1;
1560                 dev_dbg(cs42l42->dev, "Function B button press\n");
1561                 break;
1562         case 3: /* Function D button press */
1563                 bias_level = SND_JACK_BTN_3;
1564                 dev_dbg(cs42l42->dev, "Function D button press\n");
1565                 break;
1566         case 4: /* Function A button press */
1567                 bias_level = SND_JACK_BTN_0;
1568                 dev_dbg(cs42l42->dev, "Function A button press\n");
1569                 break;
1570         default:
1571                 bias_level = 0;
1572                 break;
1573         }
1574
1575         /* Set button detect level sensitivity back to default */
1576         regmap_update_bits(cs42l42->regmap,
1577                 CS42L42_MIC_DET_CTL1,
1578                 CS42L42_LATCH_TO_VP_MASK |
1579                 CS42L42_EVENT_STAT_SEL_MASK |
1580                 CS42L42_HS_DET_LEVEL_MASK,
1581                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1582                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1583                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1584
1585         /* Clear any button interrupts before unmasking them */
1586         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1587                     &detect_status);
1588
1589         /* Unmask button detect interrupts */
1590         regmap_update_bits(cs42l42->regmap,
1591                 CS42L42_DET_INT2_MASK,
1592                 CS42L42_M_DETECT_TF_MASK |
1593                 CS42L42_M_DETECT_FT_MASK |
1594                 CS42L42_M_HSBIAS_HIZ_MASK |
1595                 CS42L42_M_SHORT_RLS_MASK |
1596                 CS42L42_M_SHORT_DET_MASK,
1597                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1598                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1599                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1600                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1601                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1602
1603         return bias_level;
1604 }
1605
1606 struct cs42l42_irq_params {
1607         u16 status_addr;
1608         u16 mask_addr;
1609         u8 mask;
1610 };
1611
1612 static const struct cs42l42_irq_params irq_params_table[] = {
1613         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1614                 CS42L42_ADC_OVFL_VAL_MASK},
1615         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1616                 CS42L42_MIXER_VAL_MASK},
1617         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1618                 CS42L42_SRC_VAL_MASK},
1619         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1620                 CS42L42_ASP_RX_VAL_MASK},
1621         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1622                 CS42L42_ASP_TX_VAL_MASK},
1623         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1624                 CS42L42_CODEC_VAL_MASK},
1625         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1626                 CS42L42_DET_INT_VAL1_MASK},
1627         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1628                 CS42L42_DET_INT_VAL2_MASK},
1629         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1630                 CS42L42_SRCPL_VAL_MASK},
1631         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1632                 CS42L42_VPMON_VAL_MASK},
1633         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1634                 CS42L42_PLL_LOCK_VAL_MASK},
1635         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1636                 CS42L42_TSRS_PLUG_VAL_MASK}
1637 };
1638
1639 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1640 {
1641         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1642         unsigned int stickies[12];
1643         unsigned int masks[12];
1644         unsigned int current_plug_status;
1645         unsigned int current_button_status;
1646         unsigned int i;
1647
1648         mutex_lock(&cs42l42->irq_lock);
1649         if (cs42l42->suspended || !cs42l42->init_done) {
1650                 mutex_unlock(&cs42l42->irq_lock);
1651                 return IRQ_NONE;
1652         }
1653
1654         /* Read sticky registers to clear interurpt */
1655         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1656                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1657                                 &(stickies[i]));
1658                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1659                                 &(masks[i]));
1660                 stickies[i] = stickies[i] & (~masks[i]) &
1661                                 irq_params_table[i].mask;
1662         }
1663
1664         /* Read tip sense status before handling type detect */
1665         current_plug_status = (stickies[11] &
1666                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1667                 CS42L42_TS_PLUG_SHIFT;
1668
1669         /* Read button sense status */
1670         current_button_status = stickies[7] &
1671                 (CS42L42_M_DETECT_TF_MASK |
1672                 CS42L42_M_DETECT_FT_MASK |
1673                 CS42L42_M_HSBIAS_HIZ_MASK);
1674
1675         /*
1676          * Check auto-detect status. Don't assume a previous unplug event has
1677          * cleared the flags. If the jack is unplugged and plugged during
1678          * system suspend there won't have been an unplug event.
1679          */
1680         if ((~masks[5]) & irq_params_table[5].mask) {
1681                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1682                         cs42l42_process_hs_type_detect(cs42l42);
1683                         switch (cs42l42->hs_type) {
1684                         case CS42L42_PLUG_CTIA:
1685                         case CS42L42_PLUG_OMTP:
1686                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1687                                                     SND_JACK_HEADSET |
1688                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1689                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1690                                 break;
1691                         case CS42L42_PLUG_HEADPHONE:
1692                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1693                                                     SND_JACK_HEADSET |
1694                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1695                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1696                                 break;
1697                         default:
1698                                 break;
1699                         }
1700                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1701                 }
1702         }
1703
1704         /* Check tip sense status */
1705         if ((~masks[11]) & irq_params_table[11].mask) {
1706                 switch (current_plug_status) {
1707                 case CS42L42_TS_PLUG:
1708                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1709                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1710                                 cs42l42_init_hs_type_detect(cs42l42);
1711                         }
1712                         break;
1713
1714                 case CS42L42_TS_UNPLUG:
1715                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1716                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1717                                 cs42l42_cancel_hs_type_detect(cs42l42);
1718
1719                                 snd_soc_jack_report(cs42l42->jack, 0,
1720                                                     SND_JACK_HEADSET |
1721                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1722                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1723
1724                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1725                         }
1726                         break;
1727
1728                 default:
1729                         cs42l42->plug_state = CS42L42_TS_TRANS;
1730                 }
1731         }
1732
1733         /* Check button detect status */
1734         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1735                 if (!(current_button_status &
1736                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1737
1738                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1739                                 dev_dbg(cs42l42->dev, "Button released\n");
1740                                 snd_soc_jack_report(cs42l42->jack, 0,
1741                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1742                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1743                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1744                                 snd_soc_jack_report(cs42l42->jack,
1745                                                     cs42l42_handle_button_press(cs42l42),
1746                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1747                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1748                         }
1749                 }
1750         }
1751
1752         mutex_unlock(&cs42l42->irq_lock);
1753
1754         return IRQ_HANDLED;
1755 }
1756
1757 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1758 {
1759         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1760                         CS42L42_ADC_OVFL_MASK,
1761                         (1 << CS42L42_ADC_OVFL_SHIFT));
1762
1763         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1764                         CS42L42_MIX_CHB_OVFL_MASK |
1765                         CS42L42_MIX_CHA_OVFL_MASK |
1766                         CS42L42_EQ_OVFL_MASK |
1767                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1768                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1769                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1770                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1771                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1772
1773         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1774                         CS42L42_SRC_ILK_MASK |
1775                         CS42L42_SRC_OLK_MASK |
1776                         CS42L42_SRC_IUNLK_MASK |
1777                         CS42L42_SRC_OUNLK_MASK,
1778                         (1 << CS42L42_SRC_ILK_SHIFT) |
1779                         (1 << CS42L42_SRC_OLK_SHIFT) |
1780                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1781                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1782
1783         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1784                         CS42L42_ASPRX_NOLRCK_MASK |
1785                         CS42L42_ASPRX_EARLY_MASK |
1786                         CS42L42_ASPRX_LATE_MASK |
1787                         CS42L42_ASPRX_ERROR_MASK |
1788                         CS42L42_ASPRX_OVLD_MASK,
1789                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1790                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1791                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1792                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1793                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1794
1795         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1796                         CS42L42_ASPTX_NOLRCK_MASK |
1797                         CS42L42_ASPTX_EARLY_MASK |
1798                         CS42L42_ASPTX_LATE_MASK |
1799                         CS42L42_ASPTX_SMERROR_MASK,
1800                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1801                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1802                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1803                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1804
1805         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1806                         CS42L42_PDN_DONE_MASK |
1807                         CS42L42_HSDET_AUTO_DONE_MASK,
1808                         (1 << CS42L42_PDN_DONE_SHIFT) |
1809                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1810
1811         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1812                         CS42L42_SRCPL_ADC_LK_MASK |
1813                         CS42L42_SRCPL_DAC_LK_MASK |
1814                         CS42L42_SRCPL_ADC_UNLK_MASK |
1815                         CS42L42_SRCPL_DAC_UNLK_MASK,
1816                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1817                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1818                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1819                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1820
1821         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1822                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1823                         CS42L42_TIP_SENSE_PLUG_MASK |
1824                         CS42L42_HSBIAS_SENSE_MASK,
1825                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1826                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1827                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1828
1829         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1830                         CS42L42_M_DETECT_TF_MASK |
1831                         CS42L42_M_DETECT_FT_MASK |
1832                         CS42L42_M_HSBIAS_HIZ_MASK |
1833                         CS42L42_M_SHORT_RLS_MASK |
1834                         CS42L42_M_SHORT_DET_MASK,
1835                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1836                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1837                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1838                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1839                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1840
1841         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1842                         CS42L42_VPMON_MASK,
1843                         (1 << CS42L42_VPMON_SHIFT));
1844
1845         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1846                         CS42L42_PLL_LOCK_MASK,
1847                         (1 << CS42L42_PLL_LOCK_SHIFT));
1848
1849         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1850                         CS42L42_RS_PLUG_MASK |
1851                         CS42L42_RS_UNPLUG_MASK |
1852                         CS42L42_TS_PLUG_MASK |
1853                         CS42L42_TS_UNPLUG_MASK,
1854                         (1 << CS42L42_RS_PLUG_SHIFT) |
1855                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1856                         (0 << CS42L42_TS_PLUG_SHIFT) |
1857                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1858 }
1859
1860 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1861 {
1862         unsigned int reg;
1863
1864         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1865
1866         /*
1867          * DETECT_MODE must always be 0 with ADC and HP both off otherwise the
1868          * FILT+ supply will not charge properly.
1869          */
1870         regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
1871                            CS42L42_DETECT_MODE_MASK, 0);
1872
1873         /* Latch analog controls to VP power domain */
1874         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1875                         CS42L42_LATCH_TO_VP_MASK |
1876                         CS42L42_EVENT_STAT_SEL_MASK |
1877                         CS42L42_HS_DET_LEVEL_MASK,
1878                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1879                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1880                         (cs42l42->bias_thresholds[0] <<
1881                         CS42L42_HS_DET_LEVEL_SHIFT));
1882
1883         /* Remove ground noise-suppression clamps */
1884         regmap_update_bits(cs42l42->regmap,
1885                         CS42L42_HS_CLAMP_DISABLE,
1886                         CS42L42_HS_CLAMP_DISABLE_MASK,
1887                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1888
1889         /* Enable the tip sense circuit */
1890         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1891                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1892
1893         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1894                         CS42L42_TIP_SENSE_CTRL_MASK |
1895                         CS42L42_TIP_SENSE_INV_MASK |
1896                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1897                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1898                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1899                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1900
1901         /* Save the initial status of the tip sense */
1902         regmap_read(cs42l42->regmap,
1903                           CS42L42_TSRS_PLUG_STATUS,
1904                           &reg);
1905         cs42l42->plug_state = (((char) reg) &
1906                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1907                       CS42L42_TS_PLUG_SHIFT;
1908 }
1909
1910 static const unsigned int threshold_defaults[] = {
1911         CS42L42_HS_DET_LEVEL_15,
1912         CS42L42_HS_DET_LEVEL_8,
1913         CS42L42_HS_DET_LEVEL_4,
1914         CS42L42_HS_DET_LEVEL_1
1915 };
1916
1917 static int cs42l42_handle_device_data(struct device *dev,
1918                                         struct cs42l42_private *cs42l42)
1919 {
1920         unsigned int val;
1921         u32 thresholds[CS42L42_NUM_BIASES];
1922         int ret;
1923         int i;
1924
1925         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1926         if (!ret) {
1927                 switch (val) {
1928                 case CS42L42_TS_INV_EN:
1929                 case CS42L42_TS_INV_DIS:
1930                         cs42l42->ts_inv = val;
1931                         break;
1932                 default:
1933                         dev_err(dev,
1934                                 "Wrong cirrus,ts-inv DT value %d\n",
1935                                 val);
1936                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1937                 }
1938         } else {
1939                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1940         }
1941
1942         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1943         if (!ret) {
1944                 switch (val) {
1945                 case CS42L42_TS_DBNCE_0:
1946                 case CS42L42_TS_DBNCE_125:
1947                 case CS42L42_TS_DBNCE_250:
1948                 case CS42L42_TS_DBNCE_500:
1949                 case CS42L42_TS_DBNCE_750:
1950                 case CS42L42_TS_DBNCE_1000:
1951                 case CS42L42_TS_DBNCE_1250:
1952                 case CS42L42_TS_DBNCE_1500:
1953                         cs42l42->ts_dbnc_rise = val;
1954                         break;
1955                 default:
1956                         dev_err(dev,
1957                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1958                                 val);
1959                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1960                 }
1961         } else {
1962                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1963         }
1964
1965         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1966                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1967                         (cs42l42->ts_dbnc_rise <<
1968                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1969
1970         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1971         if (!ret) {
1972                 switch (val) {
1973                 case CS42L42_TS_DBNCE_0:
1974                 case CS42L42_TS_DBNCE_125:
1975                 case CS42L42_TS_DBNCE_250:
1976                 case CS42L42_TS_DBNCE_500:
1977                 case CS42L42_TS_DBNCE_750:
1978                 case CS42L42_TS_DBNCE_1000:
1979                 case CS42L42_TS_DBNCE_1250:
1980                 case CS42L42_TS_DBNCE_1500:
1981                         cs42l42->ts_dbnc_fall = val;
1982                         break;
1983                 default:
1984                         dev_err(dev,
1985                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1986                                 val);
1987                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1988                 }
1989         } else {
1990                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1991         }
1992
1993         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1994                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1995                         (cs42l42->ts_dbnc_fall <<
1996                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1997
1998         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1999         if (!ret) {
2000                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
2001                         cs42l42->btn_det_init_dbnce = val;
2002                 else {
2003                         dev_err(dev,
2004                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
2005                                 val);
2006                         cs42l42->btn_det_init_dbnce =
2007                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
2008                 }
2009         } else {
2010                 cs42l42->btn_det_init_dbnce =
2011                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
2012         }
2013
2014         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
2015         if (!ret) {
2016                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
2017                         cs42l42->btn_det_event_dbnce = val;
2018                 else {
2019                         dev_err(dev,
2020                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
2021                         cs42l42->btn_det_event_dbnce =
2022                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2023                 }
2024         } else {
2025                 cs42l42->btn_det_event_dbnce =
2026                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2027         }
2028
2029         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
2030                                              thresholds, ARRAY_SIZE(thresholds));
2031         if (!ret) {
2032                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
2033                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
2034                                 cs42l42->bias_thresholds[i] = thresholds[i];
2035                         else {
2036                                 dev_err(dev,
2037                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
2038                                         thresholds[i]);
2039                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2040                         }
2041                 }
2042         } else {
2043                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2044                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
2045         }
2046
2047         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2048         if (!ret) {
2049                 switch (val) {
2050                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2051                         cs42l42->hs_bias_ramp_rate = val;
2052                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2053                         break;
2054                 case CS42L42_HSBIAS_RAMP_FAST:
2055                         cs42l42->hs_bias_ramp_rate = val;
2056                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2057                         break;
2058                 case CS42L42_HSBIAS_RAMP_SLOW:
2059                         cs42l42->hs_bias_ramp_rate = val;
2060                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2061                         break;
2062                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2063                         cs42l42->hs_bias_ramp_rate = val;
2064                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2065                         break;
2066                 default:
2067                         dev_err(dev,
2068                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2069                                 val);
2070                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2071                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2072                 }
2073         } else {
2074                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2075                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2076         }
2077
2078         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2079                         CS42L42_HSBIAS_RAMP_MASK,
2080                         (cs42l42->hs_bias_ramp_rate <<
2081                         CS42L42_HSBIAS_RAMP_SHIFT));
2082
2083         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2084                 cs42l42->hs_bias_sense_en = 0;
2085         else
2086                 cs42l42->hs_bias_sense_en = 1;
2087
2088         return 0;
2089 }
2090
2091 /* Datasheet suspend sequence */
2092 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = {
2093         REG_SEQ0(CS42L42_MIC_DET_CTL1,          0x9F),
2094         REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK,     0x01),
2095         REG_SEQ0(CS42L42_MIXER_INT_MASK,        0x0F),
2096         REG_SEQ0(CS42L42_SRC_INT_MASK,          0x0F),
2097         REG_SEQ0(CS42L42_ASP_RX_INT_MASK,       0x1F),
2098         REG_SEQ0(CS42L42_ASP_TX_INT_MASK,       0x0F),
2099         REG_SEQ0(CS42L42_CODEC_INT_MASK,        0x03),
2100         REG_SEQ0(CS42L42_SRCPL_INT_MASK,        0x7F),
2101         REG_SEQ0(CS42L42_VPMON_INT_MASK,        0x01),
2102         REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK,     0x01),
2103         REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK,    0x0F),
2104         REG_SEQ0(CS42L42_WAKE_CTL,              0xE1),
2105         REG_SEQ0(CS42L42_DET_INT1_MASK,         0xE0),
2106         REG_SEQ0(CS42L42_DET_INT2_MASK,         0xFF),
2107         REG_SEQ0(CS42L42_MIXER_CHA_VOL,         0x3F),
2108         REG_SEQ0(CS42L42_MIXER_ADC_VOL,         0x3F),
2109         REG_SEQ0(CS42L42_MIXER_CHB_VOL,         0x3F),
2110         REG_SEQ0(CS42L42_HP_CTL,                0x0F),
2111         REG_SEQ0(CS42L42_ASP_RX_DAI0_EN,        0x00),
2112         REG_SEQ0(CS42L42_ASP_CLK_CFG,           0x00),
2113         REG_SEQ0(CS42L42_HSDET_CTL2,            0x00),
2114         REG_SEQ0(CS42L42_PWR_CTL1,              0xFE),
2115         REG_SEQ0(CS42L42_PWR_CTL2,              0x8C),
2116         REG_SEQ0(CS42L42_DAC_CTL2,              0x02),
2117         REG_SEQ0(CS42L42_HS_CLAMP_DISABLE,      0x00),
2118         REG_SEQ0(CS42L42_MISC_DET_CTL,          0x03),
2119         REG_SEQ0(CS42L42_TIPSENSE_CTL,          0x02),
2120         REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL,     0x03),
2121         REG_SEQ0(CS42L42_PWR_CTL1,              0xFF)
2122 };
2123
2124 int cs42l42_suspend(struct device *dev)
2125 {
2126         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2127         unsigned int reg;
2128         u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
2129         int i, ret;
2130
2131         /*
2132          * Wait for threaded irq handler to be idle and stop it processing
2133          * future interrupts. This ensures a safe disable if the interrupt
2134          * is shared.
2135          */
2136         mutex_lock(&cs42l42->irq_lock);
2137         cs42l42->suspended = true;
2138
2139         /* Save register values that will be overwritten by shutdown sequence */
2140         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) {
2141                 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, &reg);
2142                 save_regs[i] = (u8)reg;
2143         }
2144
2145         /* Shutdown codec */
2146         regmap_multi_reg_write(cs42l42->regmap,
2147                                cs42l42_shutdown_seq,
2148                                ARRAY_SIZE(cs42l42_shutdown_seq));
2149
2150         /* All interrupt sources are now disabled */
2151         mutex_unlock(&cs42l42->irq_lock);
2152
2153         /* Wait for power-down complete */
2154         msleep(CS42L42_PDN_DONE_TIME_MS);
2155         ret = regmap_read_poll_timeout(cs42l42->regmap,
2156                                        CS42L42_CODEC_STATUS, reg,
2157                                        (reg & CS42L42_PDN_DONE_MASK),
2158                                        CS42L42_PDN_DONE_POLL_US,
2159                                        CS42L42_PDN_DONE_TIMEOUT_US);
2160         if (ret)
2161                 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret);
2162
2163         /* Discharge FILT+ */
2164         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2165                            CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK);
2166         msleep(CS42L42_FILT_DISCHARGE_TIME_MS);
2167
2168         regcache_cache_only(cs42l42->regmap, true);
2169         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2170         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2171
2172         /* Restore register values to the regmap cache */
2173         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i)
2174                 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]);
2175
2176         /* The cached address page register value is now stale */
2177         regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER);
2178
2179         dev_dbg(dev, "System suspended\n");
2180
2181         return 0;
2182
2183 }
2184 EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE);
2185
2186 int cs42l42_resume(struct device *dev)
2187 {
2188         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2189         int ret;
2190
2191         /*
2192          * If jack was unplugged and re-plugged during suspend it could
2193          * have changed type but the tip-sense state hasn't changed.
2194          * Force a plugged state to be re-evaluated.
2195          */
2196         if (cs42l42->plug_state != CS42L42_TS_UNPLUG)
2197                 cs42l42->plug_state = CS42L42_TS_TRANS;
2198
2199         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2200         if (ret != 0) {
2201                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
2202                 return ret;
2203         }
2204
2205         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2206         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2207
2208         dev_dbg(dev, "System resume powered up\n");
2209
2210         return 0;
2211 }
2212 EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE);
2213
2214 void cs42l42_resume_restore(struct device *dev)
2215 {
2216         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2217
2218         regcache_cache_only(cs42l42->regmap, false);
2219         regcache_mark_dirty(cs42l42->regmap);
2220
2221         mutex_lock(&cs42l42->irq_lock);
2222         /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
2223         regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
2224         regcache_sync(cs42l42->regmap);
2225
2226         cs42l42->suspended = false;
2227         mutex_unlock(&cs42l42->irq_lock);
2228
2229         dev_dbg(dev, "System resumed\n");
2230 }
2231 EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE);
2232
2233 static int __maybe_unused cs42l42_i2c_resume(struct device *dev)
2234 {
2235         int ret;
2236
2237         ret = cs42l42_resume(dev);
2238         if (ret)
2239                 return ret;
2240
2241         cs42l42_resume_restore(dev);
2242
2243         return 0;
2244 }
2245
2246 int cs42l42_common_probe(struct cs42l42_private *cs42l42,
2247                          const struct snd_soc_component_driver *component_drv,
2248                          struct snd_soc_dai_driver *dai)
2249 {
2250         int ret, i;
2251
2252         dev_set_drvdata(cs42l42->dev, cs42l42);
2253         mutex_init(&cs42l42->irq_lock);
2254
2255         BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies));
2256         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2257                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2258
2259         ret = devm_regulator_bulk_get(cs42l42->dev,
2260                                       ARRAY_SIZE(cs42l42->supplies),
2261                                       cs42l42->supplies);
2262         if (ret != 0) {
2263                 dev_err(cs42l42->dev,
2264                         "Failed to request supplies: %d\n", ret);
2265                 return ret;
2266         }
2267
2268         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2269                                     cs42l42->supplies);
2270         if (ret != 0) {
2271                 dev_err(cs42l42->dev,
2272                         "Failed to enable supplies: %d\n", ret);
2273                 return ret;
2274         }
2275
2276         /* Reset the Device */
2277         cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev,
2278                 "reset", GPIOD_OUT_LOW);
2279         if (IS_ERR(cs42l42->reset_gpio)) {
2280                 ret = PTR_ERR(cs42l42->reset_gpio);
2281                 goto err_disable_noreset;
2282         }
2283
2284         if (cs42l42->reset_gpio) {
2285                 dev_dbg(cs42l42->dev, "Found reset GPIO\n");
2286                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2287         }
2288         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2289
2290         /* Request IRQ if one was specified */
2291         if (cs42l42->irq) {
2292                 ret = request_threaded_irq(cs42l42->irq,
2293                                            NULL, cs42l42_irq_thread,
2294                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2295                                            "cs42l42", cs42l42);
2296                 if (ret) {
2297                         dev_err_probe(cs42l42->dev, ret,
2298                                 "Failed to request IRQ\n");
2299                         goto err_disable_noirq;
2300                 }
2301         }
2302
2303         /* Register codec now so it can EPROBE_DEFER */
2304         ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1);
2305         if (ret < 0)
2306                 goto err;
2307
2308         return 0;
2309
2310 err:
2311         if (cs42l42->irq)
2312                 free_irq(cs42l42->irq, cs42l42);
2313
2314 err_disable_noirq:
2315         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2316 err_disable_noreset:
2317         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2318
2319         return ret;
2320 }
2321 EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE);
2322
2323 int cs42l42_init(struct cs42l42_private *cs42l42)
2324 {
2325         unsigned int reg;
2326         int devid, ret;
2327
2328         /* initialize codec */
2329         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2330         if (devid < 0) {
2331                 ret = devid;
2332                 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret);
2333                 goto err_disable;
2334         }
2335
2336         if (devid != cs42l42->devid) {
2337                 ret = -ENODEV;
2338                 dev_err(cs42l42->dev,
2339                         "CS42L%x Device ID (%X). Expected %X\n",
2340                         cs42l42->devid & 0xff, devid, cs42l42->devid);
2341                 goto err_disable;
2342         }
2343
2344         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2345         if (ret < 0) {
2346                 dev_err(cs42l42->dev, "Get Revision ID failed\n");
2347                 goto err_shutdown;
2348         }
2349
2350         dev_info(cs42l42->dev,
2351                  "Cirrus Logic CS42L%x, Revision: %02X\n",
2352                  cs42l42->devid & 0xff, reg & 0xFF);
2353
2354         /* Power up the codec */
2355         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2356                         CS42L42_ASP_DAO_PDN_MASK |
2357                         CS42L42_ASP_DAI_PDN_MASK |
2358                         CS42L42_MIXER_PDN_MASK |
2359                         CS42L42_EQ_PDN_MASK |
2360                         CS42L42_HP_PDN_MASK |
2361                         CS42L42_ADC_PDN_MASK |
2362                         CS42L42_PDN_ALL_MASK,
2363                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2364                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2365                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2366                         (1 << CS42L42_EQ_PDN_SHIFT) |
2367                         (1 << CS42L42_HP_PDN_SHIFT) |
2368                         (1 << CS42L42_ADC_PDN_SHIFT) |
2369                         (0 << CS42L42_PDN_ALL_SHIFT));
2370
2371         ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42);
2372         if (ret != 0)
2373                 goto err_shutdown;
2374
2375         /* Setup headset detection */
2376         cs42l42_setup_hs_type_detect(cs42l42);
2377
2378         /*
2379          * Set init_done before unmasking interrupts so any triggered
2380          * immediately will be handled.
2381          */
2382         cs42l42->init_done = true;
2383
2384         /* Mask/Unmask Interrupts */
2385         cs42l42_set_interrupt_masks(cs42l42);
2386
2387         return 0;
2388
2389 err_shutdown:
2390         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2391         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2392         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2393
2394 err_disable:
2395         if (cs42l42->irq)
2396                 free_irq(cs42l42->irq, cs42l42);
2397
2398         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2399         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2400                                 cs42l42->supplies);
2401         return ret;
2402 }
2403 EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE);
2404
2405 void cs42l42_common_remove(struct cs42l42_private *cs42l42)
2406 {
2407         if (cs42l42->irq)
2408                 free_irq(cs42l42->irq, cs42l42);
2409
2410         /*
2411          * The driver might not have control of reset and power supplies,
2412          * so ensure that the chip internals are powered down.
2413          */
2414         if (cs42l42->init_done) {
2415                 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2416                 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2417                 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2418         }
2419
2420         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2421         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2422 }
2423 EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE);
2424
2425 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2426 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2427 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2428 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2429 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2430 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2431 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2432 MODULE_LICENSE("GPL");