sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/acpi.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/property.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38 #include "cirrus_legacy.h"
  39
  40 static const struct reg_default cs42l42_reg_defaults[] = {
  41         { CS42L42_FRZ_CTL,                      0x00 },
  42         { CS42L42_SRC_CTL,                      0x10 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_SLOW_START_ENABLE,            0x70 },
  46         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  47         { CS42L42_I2C_STRETCH,                  0x03 },
  48         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  49         { CS42L42_PWR_CTL1,                     0xFF },
  50         { CS42L42_PWR_CTL2,                     0x84 },
  51         { CS42L42_PWR_CTL3,                     0x20 },
  52         { CS42L42_RSENSE_CTL1,                  0x40 },
  53         { CS42L42_RSENSE_CTL2,                  0x00 },
  54         { CS42L42_OSC_SWITCH,                   0x00 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_HSDET_CTL1,                   0x77 },
  59         { CS42L42_HSDET_CTL2,                   0x00 },
  60         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  61         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  62         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  63         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  64         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  65         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  66         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  67         { CS42L42_FSYNC_P_UPPER,                0x00 },
  68         { CS42L42_ASP_CLK_CFG,                  0x00 },
  69         { CS42L42_ASP_FRM_CFG,                  0x10 },
  70         { CS42L42_FS_RATE_EN,                   0x00 },
  71         { CS42L42_IN_ASRC_CLK,                  0x00 },
  72         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  73         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  74         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  75         { CS42L42_MIXER_INT_MASK,               0x0F },
  76         { CS42L42_SRC_INT_MASK,                 0x0F },
  77         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  78         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  79         { CS42L42_CODEC_INT_MASK,               0x03 },
  80         { CS42L42_SRCPL_INT_MASK,               0x7F },
  81         { CS42L42_VPMON_INT_MASK,               0x01 },
  82         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  83         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  84         { CS42L42_PLL_CTL1,                     0x00 },
  85         { CS42L42_PLL_DIV_FRAC0,                0x00 },
  86         { CS42L42_PLL_DIV_FRAC1,                0x00 },
  87         { CS42L42_PLL_DIV_FRAC2,                0x00 },
  88         { CS42L42_PLL_DIV_INT,                  0x40 },
  89         { CS42L42_PLL_CTL3,                     0x10 },
  90         { CS42L42_PLL_CAL_RATIO,                0x80 },
  91         { CS42L42_PLL_CTL4,                     0x03 },
  92         { CS42L42_LOAD_DET_EN,                  0x00 },
  93         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
  94         { CS42L42_WAKE_CTL,                     0xC0 },
  95         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
  96         { CS42L42_TIPSENSE_CTL,                 0x02 },
  97         { CS42L42_MISC_DET_CTL,                 0x03 },
  98         { CS42L42_MIC_DET_CTL1,                 0x1F },
  99         { CS42L42_MIC_DET_CTL2,                 0x2F },
 100         { CS42L42_DET_INT1_MASK,                0xE0 },
 101         { CS42L42_DET_INT2_MASK,                0xFF },
 102         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 103         { CS42L42_ADC_CTL,                      0x00 },
 104         { CS42L42_ADC_VOLUME,                   0x00 },
 105         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 106         { CS42L42_DAC_CTL1,                     0x00 },
 107         { CS42L42_DAC_CTL2,                     0x02 },
 108         { CS42L42_HP_CTL,                       0x0D },
 109         { CS42L42_CLASSH_CTL,                   0x07 },
 110         { CS42L42_MIXER_CHA_VOL,                0x3F },
 111         { CS42L42_MIXER_ADC_VOL,                0x3F },
 112         { CS42L42_MIXER_CHB_VOL,                0x3F },
 113         { CS42L42_EQ_COEF_IN0,                  0x00 },
 114         { CS42L42_EQ_COEF_IN1,                  0x00 },
 115         { CS42L42_EQ_COEF_IN2,                  0x00 },
 116         { CS42L42_EQ_COEF_IN3,                  0x00 },
 117         { CS42L42_EQ_COEF_RW,                   0x00 },
 118         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 119         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 120         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 121         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 122         { CS42L42_EQ_INIT_STAT,                 0x00 },
 123         { CS42L42_EQ_START_FILT,                0x00 },
 124         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 125         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 126         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 127         { CS42L42_SP_RX_FS,                     0x8C },
 128         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 129         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 130         { CS42L42_SP_TX_FS,                     0xCC },
 131         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 132         { CS42L42_SRC_SDIN_FS,                  0x40 },
 133         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 134         { CS42L42_SPDIF_CTL1,                   0x01 },
 135         { CS42L42_SPDIF_CTL2,                   0x00 },
 136         { CS42L42_SPDIF_CTL3,                   0x00 },
 137         { CS42L42_SPDIF_CTL4,                   0x42 },
 138         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 139         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 140         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 141         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 142         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 143         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 144         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 145         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 146         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 147         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 148         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 149         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 150         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 151         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 152         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 153         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 154         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 155         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 156         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 157         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 158         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 159         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 160         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 161         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 162         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 163         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 164         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 165 };
 166
 167 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 168 {
 169         switch (reg) {
 170         case CS42L42_PAGE_REGISTER:
 171         case CS42L42_DEVID_AB:
 172         case CS42L42_DEVID_CD:
 173         case CS42L42_DEVID_E:
 174         case CS42L42_FABID:
 175         case CS42L42_REVID:
 176         case CS42L42_FRZ_CTL:
 177         case CS42L42_SRC_CTL:
 178         case CS42L42_MCLK_STATUS:
 179         case CS42L42_MCLK_CTL:
 180         case CS42L42_SFTRAMP_RATE:
 181         case CS42L42_SLOW_START_ENABLE:
 182         case CS42L42_I2C_DEBOUNCE:
 183         case CS42L42_I2C_STRETCH:
 184         case CS42L42_I2C_TIMEOUT:
 185         case CS42L42_PWR_CTL1:
 186         case CS42L42_PWR_CTL2:
 187         case CS42L42_PWR_CTL3:
 188         case CS42L42_RSENSE_CTL1:
 189         case CS42L42_RSENSE_CTL2:
 190         case CS42L42_OSC_SWITCH:
 191         case CS42L42_OSC_SWITCH_STATUS:
 192         case CS42L42_RSENSE_CTL3:
 193         case CS42L42_TSENSE_CTL:
 194         case CS42L42_TSRS_INT_DISABLE:
 195         case CS42L42_TRSENSE_STATUS:
 196         case CS42L42_HSDET_CTL1:
 197         case CS42L42_HSDET_CTL2:
 198         case CS42L42_HS_SWITCH_CTL:
 199         case CS42L42_HS_DET_STATUS:
 200         case CS42L42_HS_CLAMP_DISABLE:
 201         case CS42L42_MCLK_SRC_SEL:
 202         case CS42L42_SPDIF_CLK_CFG:
 203         case CS42L42_FSYNC_PW_LOWER:
 204         case CS42L42_FSYNC_PW_UPPER:
 205         case CS42L42_FSYNC_P_LOWER:
 206         case CS42L42_FSYNC_P_UPPER:
 207         case CS42L42_ASP_CLK_CFG:
 208         case CS42L42_ASP_FRM_CFG:
 209         case CS42L42_FS_RATE_EN:
 210         case CS42L42_IN_ASRC_CLK:
 211         case CS42L42_OUT_ASRC_CLK:
 212         case CS42L42_PLL_DIV_CFG1:
 213         case CS42L42_ADC_OVFL_STATUS:
 214         case CS42L42_MIXER_STATUS:
 215         case CS42L42_SRC_STATUS:
 216         case CS42L42_ASP_RX_STATUS:
 217         case CS42L42_ASP_TX_STATUS:
 218         case CS42L42_CODEC_STATUS:
 219         case CS42L42_DET_INT_STATUS1:
 220         case CS42L42_DET_INT_STATUS2:
 221         case CS42L42_SRCPL_INT_STATUS:
 222         case CS42L42_VPMON_STATUS:
 223         case CS42L42_PLL_LOCK_STATUS:
 224         case CS42L42_TSRS_PLUG_STATUS:
 225         case CS42L42_ADC_OVFL_INT_MASK:
 226         case CS42L42_MIXER_INT_MASK:
 227         case CS42L42_SRC_INT_MASK:
 228         case CS42L42_ASP_RX_INT_MASK:
 229         case CS42L42_ASP_TX_INT_MASK:
 230         case CS42L42_CODEC_INT_MASK:
 231         case CS42L42_SRCPL_INT_MASK:
 232         case CS42L42_VPMON_INT_MASK:
 233         case CS42L42_PLL_LOCK_INT_MASK:
 234         case CS42L42_TSRS_PLUG_INT_MASK:
 235         case CS42L42_PLL_CTL1:
 236         case CS42L42_PLL_DIV_FRAC0:
 237         case CS42L42_PLL_DIV_FRAC1:
 238         case CS42L42_PLL_DIV_FRAC2:
 239         case CS42L42_PLL_DIV_INT:
 240         case CS42L42_PLL_CTL3:
 241         case CS42L42_PLL_CAL_RATIO:
 242         case CS42L42_PLL_CTL4:
 243         case CS42L42_LOAD_DET_RCSTAT:
 244         case CS42L42_LOAD_DET_DONE:
 245         case CS42L42_LOAD_DET_EN:
 246         case CS42L42_HSBIAS_SC_AUTOCTL:
 247         case CS42L42_WAKE_CTL:
 248         case CS42L42_ADC_DISABLE_MUTE:
 249         case CS42L42_TIPSENSE_CTL:
 250         case CS42L42_MISC_DET_CTL:
 251         case CS42L42_MIC_DET_CTL1:
 252         case CS42L42_MIC_DET_CTL2:
 253         case CS42L42_DET_STATUS1:
 254         case CS42L42_DET_STATUS2:
 255         case CS42L42_DET_INT1_MASK:
 256         case CS42L42_DET_INT2_MASK:
 257         case CS42L42_HS_BIAS_CTL:
 258         case CS42L42_ADC_CTL:
 259         case CS42L42_ADC_VOLUME:
 260         case CS42L42_ADC_WNF_HPF_CTL:
 261         case CS42L42_DAC_CTL1:
 262         case CS42L42_DAC_CTL2:
 263         case CS42L42_HP_CTL:
 264         case CS42L42_CLASSH_CTL:
 265         case CS42L42_MIXER_CHA_VOL:
 266         case CS42L42_MIXER_ADC_VOL:
 267         case CS42L42_MIXER_CHB_VOL:
 268         case CS42L42_EQ_COEF_IN0:
 269         case CS42L42_EQ_COEF_IN1:
 270         case CS42L42_EQ_COEF_IN2:
 271         case CS42L42_EQ_COEF_IN3:
 272         case CS42L42_EQ_COEF_RW:
 273         case CS42L42_EQ_COEF_OUT0:
 274         case CS42L42_EQ_COEF_OUT1:
 275         case CS42L42_EQ_COEF_OUT2:
 276         case CS42L42_EQ_COEF_OUT3:
 277         case CS42L42_EQ_INIT_STAT:
 278         case CS42L42_EQ_START_FILT:
 279         case CS42L42_EQ_MUTE_CTL:
 280         case CS42L42_SP_RX_CH_SEL:
 281         case CS42L42_SP_RX_ISOC_CTL:
 282         case CS42L42_SP_RX_FS:
 283         case CS42l42_SPDIF_CH_SEL:
 284         case CS42L42_SP_TX_ISOC_CTL:
 285         case CS42L42_SP_TX_FS:
 286         case CS42L42_SPDIF_SW_CTL1:
 287         case CS42L42_SRC_SDIN_FS:
 288         case CS42L42_SRC_SDOUT_FS:
 289         case CS42L42_SPDIF_CTL1:
 290         case CS42L42_SPDIF_CTL2:
 291         case CS42L42_SPDIF_CTL3:
 292         case CS42L42_SPDIF_CTL4:
 293         case CS42L42_ASP_TX_SZ_EN:
 294         case CS42L42_ASP_TX_CH_EN:
 295         case CS42L42_ASP_TX_CH_AP_RES:
 296         case CS42L42_ASP_TX_CH1_BIT_MSB:
 297         case CS42L42_ASP_TX_CH1_BIT_LSB:
 298         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 299         case CS42L42_ASP_TX_CH2_BIT_MSB:
 300         case CS42L42_ASP_TX_CH2_BIT_LSB:
 301         case CS42L42_ASP_RX_DAI0_EN:
 302         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 303         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 304         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 305         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 306         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 307         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 308         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 309         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 310         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 311         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 312         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 313         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 314         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 315         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 316         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 317         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 318         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 319         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 320         case CS42L42_SUB_REVID:
 321                 return true;
 322         default:
 323                 return false;
 324         }
 325 }
 326
 327 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 328 {
 329         switch (reg) {
 330         case CS42L42_DEVID_AB:
 331         case CS42L42_DEVID_CD:
 332         case CS42L42_DEVID_E:
 333         case CS42L42_MCLK_STATUS:
 334         case CS42L42_OSC_SWITCH_STATUS:
 335         case CS42L42_TRSENSE_STATUS:
 336         case CS42L42_HS_DET_STATUS:
 337         case CS42L42_ADC_OVFL_STATUS:
 338         case CS42L42_MIXER_STATUS:
 339         case CS42L42_SRC_STATUS:
 340         case CS42L42_ASP_RX_STATUS:
 341         case CS42L42_ASP_TX_STATUS:
 342         case CS42L42_CODEC_STATUS:
 343         case CS42L42_DET_INT_STATUS1:
 344         case CS42L42_DET_INT_STATUS2:
 345         case CS42L42_SRCPL_INT_STATUS:
 346         case CS42L42_VPMON_STATUS:
 347         case CS42L42_PLL_LOCK_STATUS:
 348         case CS42L42_TSRS_PLUG_STATUS:
 349         case CS42L42_LOAD_DET_RCSTAT:
 350         case CS42L42_LOAD_DET_DONE:
 351         case CS42L42_DET_STATUS1:
 352         case CS42L42_DET_STATUS2:
 353                 return true;
 354         default:
 355                 return false;
 356         }
 357 }
 358
 359 static const struct regmap_range_cfg cs42l42_page_range = {
 360         .name = "Pages",
 361         .range_min = 0,
 362         .range_max = CS42L42_MAX_REGISTER,
 363         .selector_reg = CS42L42_PAGE_REGISTER,
 364         .selector_mask = 0xff,
 365         .selector_shift = 0,
 366         .window_start = 0,
 367         .window_len = 256,
 368 };
 369
 370 static const struct regmap_config cs42l42_regmap = {
 371         .reg_bits = 8,
 372         .val_bits = 8,
 373
 374         .readable_reg = cs42l42_readable_register,
 375         .volatile_reg = cs42l42_volatile_register,
 376
 377         .ranges = &cs42l42_page_range,
 378         .num_ranges = 1,
 379
 380         .max_register = CS42L42_MAX_REGISTER,
 381         .reg_defaults = cs42l42_reg_defaults,
 382         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 383         .cache_type = REGCACHE_RBTREE,
 384
 385         .use_single_read = true,
 386         .use_single_write = true,
 387 };
 388
 389 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 390 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 391
 392 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
 393                                   struct snd_ctl_elem_value *ucontrol)
 394 {
 395         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 396         u8 val;
 397
 398         /* all bits of SLOW_START_EN much change together */
 399         switch (ucontrol->value.integer.value[0]) {
 400         case 0:
 401                 val = 0;
 402                 break;
 403         case 1:
 404                 val = CS42L42_SLOW_START_EN_MASK;
 405                 break;
 406         default:
 407                 return -EINVAL;
 408         }
 409
 410         return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
 411                                              CS42L42_SLOW_START_EN_MASK, val);
 412 }
 413
 414 static const char * const cs42l42_hpf_freq_text[] = {
 415         "1.86Hz", "120Hz", "235Hz", "466Hz"
 416 };
 417
 418 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 419                             CS42L42_ADC_HPF_CF_SHIFT,
 420                             cs42l42_hpf_freq_text);
 421
 422 static const char * const cs42l42_wnf3_freq_text[] = {
 423         "160Hz", "180Hz", "200Hz", "220Hz",
 424         "240Hz", "260Hz", "280Hz", "300Hz"
 425 };
 426
 427 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 428                             CS42L42_ADC_WNF_CF_SHIFT,
 429                             cs42l42_wnf3_freq_text);
 430
 431 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 432         /* ADC Volume and Filter Controls */
 433         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 434                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 435         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 436                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 437         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 438                                 CS42L42_ADC_INV_SHIFT, true, false),
 439         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 440                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 441         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 442         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 443                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 444         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 445                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 446         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 447         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 448
 449         /* DAC Volume and Filter Controls */
 450         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 451                                 CS42L42_DACA_INV_SHIFT, true, false),
 452         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 453                                 CS42L42_DACB_INV_SHIFT, true, false),
 454         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 455                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 456         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 457                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 458                                 0x3f, 1, mixer_tlv),
 459
 460         SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
 461                         CS42L42_SLOW_START_EN_SHIFT, true, false,
 462                         snd_soc_get_volsw, cs42l42_slow_start_put),
 463 };
 464
 465 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
 466                              struct snd_kcontrol *kcontrol, int event)
 467 {
 468         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 469         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 470
 471         switch (event) {
 472         case SND_SOC_DAPM_PRE_PMU:
 473                 cs42l42->hp_adc_up_pending = true;
 474                 break;
 475         case SND_SOC_DAPM_POST_PMU:
 476                 /* Only need one delay if HP and ADC are both powering-up */
 477                 if (cs42l42->hp_adc_up_pending) {
 478                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
 479                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
 480                         cs42l42->hp_adc_up_pending = false;
 481                 }
 482                 break;
 483         default:
 484                 break;
 485         }
 486
 487         return 0;
 488 }
 489
 490 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 491         /* Playback Path */
 492         SND_SOC_DAPM_OUTPUT("HP"),
 493         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
 494                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 495         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 496         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 497         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 498
 499         /* Playback Requirements */
 500         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 501
 502         /* Capture Path */
 503         SND_SOC_DAPM_INPUT("HS"),
 504         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
 505                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 506         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 507         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 508
 509         /* Capture Requirements */
 510         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 511         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 512
 513         /* Playback/Capture Requirements */
 514         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 515 };
 516
 517 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 518         /* Playback Path */
 519         {"HP", NULL, "DAC"},
 520         {"DAC", NULL, "MIXER"},
 521         {"MIXER", NULL, "SDIN1"},
 522         {"MIXER", NULL, "SDIN2"},
 523         {"SDIN1", NULL, "Playback"},
 524         {"SDIN2", NULL, "Playback"},
 525
 526         /* Playback Requirements */
 527         {"SDIN1", NULL, "ASP DAI0"},
 528         {"SDIN2", NULL, "ASP DAI0"},
 529         {"SDIN1", NULL, "SCLK"},
 530         {"SDIN2", NULL, "SCLK"},
 531
 532         /* Capture Path */
 533         {"ADC", NULL, "HS"},
 534         { "SDOUT1", NULL, "ADC" },
 535         { "SDOUT2", NULL, "ADC" },
 536         { "Capture", NULL, "SDOUT1" },
 537         { "Capture", NULL, "SDOUT2" },
 538
 539         /* Capture Requirements */
 540         { "SDOUT1", NULL, "ASP DAO0" },
 541         { "SDOUT2", NULL, "ASP DAO0" },
 542         { "SDOUT1", NULL, "SCLK" },
 543         { "SDOUT2", NULL, "SCLK" },
 544         { "SDOUT1", NULL, "ASP TX EN" },
 545         { "SDOUT2", NULL, "ASP TX EN" },
 546 };
 547
 548 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 549 {
 550         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 551
 552         /* Prevent race with interrupt handler */
 553         mutex_lock(&cs42l42->irq_lock);
 554         cs42l42->jack = jk;
 555
 556         if (jk) {
 557                 switch (cs42l42->hs_type) {
 558                 case CS42L42_PLUG_CTIA:
 559                 case CS42L42_PLUG_OMTP:
 560                         snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
 561                         break;
 562                 case CS42L42_PLUG_HEADPHONE:
 563                         snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
 564                         break;
 565                 default:
 566                         break;
 567                 }
 568         }
 569         mutex_unlock(&cs42l42->irq_lock);
 570
 571         return 0;
 572 }
 573
 574 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 575         .set_jack               = cs42l42_set_jack,
 576         .dapm_widgets           = cs42l42_dapm_widgets,
 577         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 578         .dapm_routes            = cs42l42_audio_map,
 579         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 580         .controls               = cs42l42_snd_controls,
 581         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 582         .idle_bias_on           = 1,
 583         .endianness             = 1,
 584 };
 585
 586 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 587 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 588         {
 589                 .reg = CS42L42_OSC_SWITCH,
 590                 .def = CS42L42_SCLK_PRESENT_MASK,
 591                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 592         },
 593 };
 594
 595 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 596 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 597         {
 598                 .reg = CS42L42_OSC_SWITCH,
 599                 .def = 0,
 600                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 601         },
 602 };
 603
 604 struct cs42l42_pll_params {
 605         u32 sclk;
 606         u8 mclk_src_sel;
 607         u8 sclk_prediv;
 608         u8 pll_div_int;
 609         u32 pll_div_frac;
 610         u8 pll_mode;
 611         u8 pll_divout;
 612         u32 mclk_int;
 613         u8 pll_cal_ratio;
 614         u8 n;
 615 };
 616
 617 /*
 618  * Common PLL Settings for given SCLK
 619  * Table 4-5 from the Datasheet
 620  */
 621 static const struct cs42l42_pll_params pll_ratio_table[] = {
 622         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 623         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 624         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 625         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 626         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 627         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 628         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 629         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 630         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 631         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 632         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 633         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 634         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 635         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 636         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 637         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 638         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 639         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 640 };
 641
 642 static int cs42l42_pll_config(struct snd_soc_component *component)
 643 {
 644         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 645         int i;
 646         u32 clk;
 647         u32 fsync;
 648
 649         if (!cs42l42->sclk)
 650                 clk = cs42l42->bclk;
 651         else
 652                 clk = cs42l42->sclk;
 653
 654         /* Don't reconfigure if there is an audio stream running */
 655         if (cs42l42->stream_use) {
 656                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
 657                         return 0;
 658                 else
 659                         return -EBUSY;
 660         }
 661
 662         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 663                 if (pll_ratio_table[i].sclk == clk) {
 664                         cs42l42->pll_config = i;
 665
 666                         /* Configure the internal sample rate */
 667                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 668                                         CS42L42_INTERNAL_FS_MASK,
 669                                         ((pll_ratio_table[i].mclk_int !=
 670                                         12000000) &&
 671                                         (pll_ratio_table[i].mclk_int !=
 672                                         24000000)) <<
 673                                         CS42L42_INTERNAL_FS_SHIFT);
 674
 675                         /* Set up the LRCLK */
 676                         fsync = clk / cs42l42->srate;
 677                         if (((fsync * cs42l42->srate) != clk)
 678                                 || ((fsync % 2) != 0)) {
 679                                 dev_err(component->dev,
 680                                         "Unsupported sclk %d/sample rate %d\n",
 681                                         clk,
 682                                         cs42l42->srate);
 683                                 return -EINVAL;
 684                         }
 685                         /* Set the LRCLK period */
 686                         snd_soc_component_update_bits(component,
 687                                         CS42L42_FSYNC_P_LOWER,
 688                                         CS42L42_FSYNC_PERIOD_MASK,
 689                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 690                                         CS42L42_FSYNC_PERIOD_SHIFT);
 691                         snd_soc_component_update_bits(component,
 692                                         CS42L42_FSYNC_P_UPPER,
 693                                         CS42L42_FSYNC_PERIOD_MASK,
 694                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 695                                         CS42L42_FSYNC_PERIOD_SHIFT);
 696                         /* Set the LRCLK to 50% duty cycle */
 697                         fsync = fsync / 2;
 698                         snd_soc_component_update_bits(component,
 699                                         CS42L42_FSYNC_PW_LOWER,
 700                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 701                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 702                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 703                         snd_soc_component_update_bits(component,
 704                                         CS42L42_FSYNC_PW_UPPER,
 705                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 706                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 707                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 708                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 709                                 /* Pass the clock straight through */
 710                                 snd_soc_component_update_bits(component,
 711                                         CS42L42_PLL_CTL1,
 712                                         CS42L42_PLL_START_MASK, 0);
 713                         } else {
 714                                 /* Configure PLL per table 4-5 */
 715                                 snd_soc_component_update_bits(component,
 716                                         CS42L42_PLL_DIV_CFG1,
 717                                         CS42L42_SCLK_PREDIV_MASK,
 718                                         pll_ratio_table[i].sclk_prediv
 719                                         << CS42L42_SCLK_PREDIV_SHIFT);
 720                                 snd_soc_component_update_bits(component,
 721                                         CS42L42_PLL_DIV_INT,
 722                                         CS42L42_PLL_DIV_INT_MASK,
 723                                         pll_ratio_table[i].pll_div_int
 724                                         << CS42L42_PLL_DIV_INT_SHIFT);
 725                                 snd_soc_component_update_bits(component,
 726                                         CS42L42_PLL_DIV_FRAC0,
 727                                         CS42L42_PLL_DIV_FRAC_MASK,
 728                                         CS42L42_FRAC0_VAL(
 729                                         pll_ratio_table[i].pll_div_frac)
 730                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 731                                 snd_soc_component_update_bits(component,
 732                                         CS42L42_PLL_DIV_FRAC1,
 733                                         CS42L42_PLL_DIV_FRAC_MASK,
 734                                         CS42L42_FRAC1_VAL(
 735                                         pll_ratio_table[i].pll_div_frac)
 736                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 737                                 snd_soc_component_update_bits(component,
 738                                         CS42L42_PLL_DIV_FRAC2,
 739                                         CS42L42_PLL_DIV_FRAC_MASK,
 740                                         CS42L42_FRAC2_VAL(
 741                                         pll_ratio_table[i].pll_div_frac)
 742                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 743                                 snd_soc_component_update_bits(component,
 744                                         CS42L42_PLL_CTL4,
 745                                         CS42L42_PLL_MODE_MASK,
 746                                         pll_ratio_table[i].pll_mode
 747                                         << CS42L42_PLL_MODE_SHIFT);
 748                                 snd_soc_component_update_bits(component,
 749                                         CS42L42_PLL_CTL3,
 750                                         CS42L42_PLL_DIVOUT_MASK,
 751                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 752                                         << CS42L42_PLL_DIVOUT_SHIFT);
 753                                 snd_soc_component_update_bits(component,
 754                                         CS42L42_PLL_CAL_RATIO,
 755                                         CS42L42_PLL_CAL_RATIO_MASK,
 756                                         pll_ratio_table[i].pll_cal_ratio
 757                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 758                         }
 759                         return 0;
 760                 }
 761         }
 762
 763         return -EINVAL;
 764 }
 765
 766 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
 767 {
 768         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 769         unsigned int fs;
 770
 771         /* Don't reconfigure if there is an audio stream running */
 772         if (cs42l42->stream_use)
 773                 return;
 774
 775         /* SRC MCLK must be as close as possible to 125 * sample rate */
 776         if (sample_rate <= 48000)
 777                 fs = CS42L42_CLK_IASRC_SEL_6;
 778         else
 779                 fs = CS42L42_CLK_IASRC_SEL_12;
 780
 781         /* Set the sample rates (96k or lower) */
 782         snd_soc_component_update_bits(component,
 783                                       CS42L42_FS_RATE_EN,
 784                                       CS42L42_FS_EN_MASK,
 785                                       (CS42L42_FS_EN_IASRC_96K |
 786                                        CS42L42_FS_EN_OASRC_96K) <<
 787                                       CS42L42_FS_EN_SHIFT);
 788
 789         snd_soc_component_update_bits(component,
 790                                       CS42L42_IN_ASRC_CLK,
 791                                       CS42L42_CLK_IASRC_SEL_MASK,
 792                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
 793         snd_soc_component_update_bits(component,
 794                                       CS42L42_OUT_ASRC_CLK,
 795                                       CS42L42_CLK_OASRC_SEL_MASK,
 796                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
 797 }
 798
 799 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 800 {
 801         struct snd_soc_component *component = codec_dai->component;
 802         u32 asp_cfg_val = 0;
 803
 804         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 805         case SND_SOC_DAIFMT_CBS_CFM:
 806                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 807                                 CS42L42_ASP_MODE_SHIFT;
 808                 break;
 809         case SND_SOC_DAIFMT_CBS_CFS:
 810                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 811                                 CS42L42_ASP_MODE_SHIFT;
 812                 break;
 813         default:
 814                 return -EINVAL;
 815         }
 816
 817         /* interface format */
 818         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 819         case SND_SOC_DAIFMT_I2S:
 820                 /*
 821                  * 5050 mode, frame starts on falling edge of LRCLK,
 822                  * frame delayed by 1.0 SCLKs
 823                  */
 824                 snd_soc_component_update_bits(component,
 825                                               CS42L42_ASP_FRM_CFG,
 826                                               CS42L42_ASP_STP_MASK |
 827                                               CS42L42_ASP_5050_MASK |
 828                                               CS42L42_ASP_FSD_MASK,
 829                                               CS42L42_ASP_5050_MASK |
 830                                               (CS42L42_ASP_FSD_1_0 <<
 831                                                 CS42L42_ASP_FSD_SHIFT));
 832                 break;
 833         default:
 834                 return -EINVAL;
 835         }
 836
 837         /* Bitclock/frame inversion */
 838         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 839         case SND_SOC_DAIFMT_NB_NF:
 840                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 841                 break;
 842         case SND_SOC_DAIFMT_NB_IF:
 843                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 844                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 845                 break;
 846         case SND_SOC_DAIFMT_IB_NF:
 847                 break;
 848         case SND_SOC_DAIFMT_IB_IF:
 849                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 850                 break;
 851         }
 852
 853         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 854                                                                       CS42L42_ASP_SCPOL_MASK |
 855                                                                       CS42L42_ASP_LCPOL_MASK,
 856                                                                       asp_cfg_val);
 857
 858         return 0;
 859 }
 860
 861 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 862 {
 863         struct snd_soc_component *component = dai->component;
 864         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 865
 866         /*
 867          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 868          * a standard I2S frame. If the machine driver sets SCLK it must be
 869          * legal.
 870          */
 871         if (cs42l42->sclk)
 872                 return 0;
 873
 874         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 875         return snd_pcm_hw_constraint_minmax(substream->runtime,
 876                                             SNDRV_PCM_HW_PARAM_RATE,
 877                                             44100, 96000);
 878 }
 879
 880 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 881                                 struct snd_pcm_hw_params *params,
 882                                 struct snd_soc_dai *dai)
 883 {
 884         struct snd_soc_component *component = dai->component;
 885         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 886         unsigned int channels = params_channels(params);
 887         unsigned int width = (params_width(params) / 8) - 1;
 888         unsigned int val = 0;
 889         int ret;
 890
 891         cs42l42->srate = params_rate(params);
 892         cs42l42->bclk = snd_soc_params_to_bclk(params);
 893
 894         /* I2S frame always has 2 channels even for mono audio */
 895         if (channels == 1)
 896                 cs42l42->bclk *= 2;
 897
 898         /*
 899          * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 900          * more than assumed (which would result in overclocking).
 901          */
 902         if (params_width(params) == 24)
 903                 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
 904
 905         switch (substream->stream) {
 906         case SNDRV_PCM_STREAM_CAPTURE:
 907                 /* channel 2 on high LRCLK */
 908                 val = CS42L42_ASP_TX_CH2_AP_MASK |
 909                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
 910                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 911
 912                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 913                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 914                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 915                 break;
 916         case SNDRV_PCM_STREAM_PLAYBACK:
 917                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 918                 /* channel 1 on low LRCLK */
 919                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 920                                                          CS42L42_ASP_RX_CH_AP_MASK |
 921                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 922                 /* Channel 2 on high LRCLK */
 923                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 924                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 925                                                          CS42L42_ASP_RX_CH_AP_MASK |
 926                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 927
 928                 /* Channel B comes from the last active channel */
 929                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 930                                               CS42L42_SP_RX_CHB_SEL_MASK,
 931                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 932
 933                 /* Both LRCLK slots must be enabled */
 934                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 935                                               CS42L42_ASP_RX0_CH_EN_MASK,
 936                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 937                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 938                 break;
 939         default:
 940                 break;
 941         }
 942
 943         ret = cs42l42_pll_config(component);
 944         if (ret)
 945                 return ret;
 946
 947         cs42l42_src_config(component, params_rate(params));
 948
 949         return 0;
 950 }
 951
 952 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 953                                 int clk_id, unsigned int freq, int dir)
 954 {
 955         struct snd_soc_component *component = dai->component;
 956         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 957         int i;
 958
 959         if (freq == 0) {
 960                 cs42l42->sclk = 0;
 961                 return 0;
 962         }
 963
 964         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 965                 if (pll_ratio_table[i].sclk == freq) {
 966                         cs42l42->sclk = freq;
 967                         return 0;
 968                 }
 969         }
 970
 971         dev_err(component->dev, "SCLK %u not supported\n", freq);
 972
 973         return -EINVAL;
 974 }
 975
 976 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 977 {
 978         struct snd_soc_component *component = dai->component;
 979         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 980         unsigned int regval;
 981         int ret;
 982
 983         if (mute) {
 984                 /* Mute the headphone */
 985                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 986                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 987                                                       CS42L42_HP_ANA_AMUTE_MASK |
 988                                                       CS42L42_HP_ANA_BMUTE_MASK,
 989                                                       CS42L42_HP_ANA_AMUTE_MASK |
 990                                                       CS42L42_HP_ANA_BMUTE_MASK);
 991
 992                 cs42l42->stream_use &= ~(1 << stream);
 993                 if (!cs42l42->stream_use) {
 994                         /*
 995                          * Switch to the internal oscillator.
 996                          * SCLK must remain running until after this clock switch.
 997                          * Without a source of clock the I2C bus doesn't work.
 998                          */
 999                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
1000                                                ARRAY_SIZE(cs42l42_to_osc_seq));
1001
1002                         /* Must disconnect PLL before stopping it */
1003                         snd_soc_component_update_bits(component,
1004                                                       CS42L42_MCLK_SRC_SEL,
1005                                                       CS42L42_MCLK_SRC_SEL_MASK,
1006                                                       0);
1007                         usleep_range(100, 200);
1008
1009                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1010                                                       CS42L42_PLL_START_MASK, 0);
1011                 }
1012         } else {
1013                 if (!cs42l42->stream_use) {
1014                         /* SCLK must be running before codec unmute.
1015                          *
1016                          * PLL must not be started with ADC and HP both off
1017                          * otherwise the FILT+ supply will not charge properly.
1018                          * DAPM widgets power-up before stream unmute so at least
1019                          * one of the "DAC" or "ADC" widgets will already have
1020                          * powered-up.
1021                          */
1022                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1023                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1024                                                               CS42L42_PLL_START_MASK, 1);
1025
1026                                 if (pll_ratio_table[cs42l42->pll_config].n > 1) {
1027                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1028                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
1029                                         regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
1030                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1031                                                                       CS42L42_PLL_DIVOUT_MASK,
1032                                                                       regval <<
1033                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1034                                 }
1035
1036                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1037                                                                CS42L42_PLL_LOCK_STATUS,
1038                                                                regval,
1039                                                                (regval & 1),
1040                                                                CS42L42_PLL_LOCK_POLL_US,
1041                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1042                                 if (ret < 0)
1043                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1044
1045                                 /* PLL must be running to drive glitchless switch logic */
1046                                 snd_soc_component_update_bits(component,
1047                                                               CS42L42_MCLK_SRC_SEL,
1048                                                               CS42L42_MCLK_SRC_SEL_MASK,
1049                                                               CS42L42_MCLK_SRC_SEL_MASK);
1050                         }
1051
1052                         /* Mark SCLK as present, turn off internal oscillator */
1053                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1054                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1055                 }
1056                 cs42l42->stream_use |= 1 << stream;
1057
1058                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1059                         /* Un-mute the headphone */
1060                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1061                                                       CS42L42_HP_ANA_AMUTE_MASK |
1062                                                       CS42L42_HP_ANA_BMUTE_MASK,
1063                                                       0);
1064                 }
1065         }
1066
1067         return 0;
1068 }
1069
1070 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1071                          SNDRV_PCM_FMTBIT_S24_LE |\
1072                          SNDRV_PCM_FMTBIT_S32_LE)
1073
1074 static const struct snd_soc_dai_ops cs42l42_ops = {
1075         .startup        = cs42l42_dai_startup,
1076         .hw_params      = cs42l42_pcm_hw_params,
1077         .set_fmt        = cs42l42_set_dai_fmt,
1078         .set_sysclk     = cs42l42_set_sysclk,
1079         .mute_stream    = cs42l42_mute_stream,
1080 };
1081
1082 static struct snd_soc_dai_driver cs42l42_dai = {
1083                 .name = "cs42l42",
1084                 .playback = {
1085                         .stream_name = "Playback",
1086                         .channels_min = 1,
1087                         .channels_max = 2,
1088                         .rates = SNDRV_PCM_RATE_8000_96000,
1089                         .formats = CS42L42_FORMATS,
1090                 },
1091                 .capture = {
1092                         .stream_name = "Capture",
1093                         .channels_min = 1,
1094                         .channels_max = 2,
1095                         .rates = SNDRV_PCM_RATE_8000_96000,
1096                         .formats = CS42L42_FORMATS,
1097                 },
1098                 .symmetric_rate = 1,
1099                 .symmetric_sample_bits = 1,
1100                 .ops = &cs42l42_ops,
1101 };
1102
1103 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1104 {
1105         unsigned int hs_det_status;
1106         unsigned int hs_det_comp1;
1107         unsigned int hs_det_comp2;
1108         unsigned int hs_det_sw;
1109
1110         /* Set hs detect to manual, active mode */
1111         regmap_update_bits(cs42l42->regmap,
1112                 CS42L42_HSDET_CTL2,
1113                 CS42L42_HSDET_CTRL_MASK |
1114                 CS42L42_HSDET_SET_MASK |
1115                 CS42L42_HSBIAS_REF_MASK |
1116                 CS42L42_HSDET_AUTO_TIME_MASK,
1117                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1118                 (0 << CS42L42_HSDET_SET_SHIFT) |
1119                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1120                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1121
1122         /* Configure HS DET comparator reference levels. */
1123         regmap_update_bits(cs42l42->regmap,
1124                                 CS42L42_HSDET_CTL1,
1125                                 CS42L42_HSDET_COMP1_LVL_MASK |
1126                                 CS42L42_HSDET_COMP2_LVL_MASK,
1127                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1128                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1129
1130         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1131         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1132
1133         msleep(100);
1134
1135         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1136
1137         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1138                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1139         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1140                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1141
1142         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1143         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1144
1145         msleep(100);
1146
1147         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1148
1149         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1150                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1151         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1152                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1153
1154         /* Use Comparator 1 with 1.25V Threshold. */
1155         switch (hs_det_comp1) {
1156         case CS42L42_HSDET_COMP_TYPE1:
1157                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1158                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1159                 break;
1160         case CS42L42_HSDET_COMP_TYPE2:
1161                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1162                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1163                 break;
1164         default:
1165                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1166                 switch (hs_det_comp2) {
1167                 case CS42L42_HSDET_COMP_TYPE1:
1168                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1169                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1170                         break;
1171                 case CS42L42_HSDET_COMP_TYPE2:
1172                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1173                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1174                         break;
1175                 case CS42L42_HSDET_COMP_TYPE3:
1176                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1177                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1178                         break;
1179                 default:
1180                         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1181                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
1182                         break;
1183                 }
1184         }
1185
1186         /* Set Switches */
1187         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1188
1189         /* Set HSDET mode to Manual—Disabled */
1190         regmap_update_bits(cs42l42->regmap,
1191                 CS42L42_HSDET_CTL2,
1192                 CS42L42_HSDET_CTRL_MASK |
1193                 CS42L42_HSDET_SET_MASK |
1194                 CS42L42_HSBIAS_REF_MASK |
1195                 CS42L42_HSDET_AUTO_TIME_MASK,
1196                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1197                 (0 << CS42L42_HSDET_SET_SHIFT) |
1198                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1199                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1200
1201         /* Configure HS DET comparator reference levels. */
1202         regmap_update_bits(cs42l42->regmap,
1203                                 CS42L42_HSDET_CTL1,
1204                                 CS42L42_HSDET_COMP1_LVL_MASK |
1205                                 CS42L42_HSDET_COMP2_LVL_MASK,
1206                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1207                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1208 }
1209
1210 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1211 {
1212         unsigned int hs_det_status;
1213         unsigned int int_status;
1214
1215         /* Read and save the hs detection result */
1216         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1217
1218         /* Mask the auto detect interrupt */
1219         regmap_update_bits(cs42l42->regmap,
1220                 CS42L42_CODEC_INT_MASK,
1221                 CS42L42_PDN_DONE_MASK |
1222                 CS42L42_HSDET_AUTO_DONE_MASK,
1223                 (1 << CS42L42_PDN_DONE_SHIFT) |
1224                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1225
1226
1227         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1228                                 CS42L42_HSDET_TYPE_SHIFT;
1229
1230         /* Set hs detect to automatic, disabled mode */
1231         regmap_update_bits(cs42l42->regmap,
1232                 CS42L42_HSDET_CTL2,
1233                 CS42L42_HSDET_CTRL_MASK |
1234                 CS42L42_HSDET_SET_MASK |
1235                 CS42L42_HSBIAS_REF_MASK |
1236                 CS42L42_HSDET_AUTO_TIME_MASK,
1237                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1238                 (2 << CS42L42_HSDET_SET_SHIFT) |
1239                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1240                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1241
1242         /* Run Manual detection if auto detect has not found a headset.
1243          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1244          * to ensure that a headset mic is detected in all cases.
1245          */
1246         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1247                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1248                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1249                 cs42l42_manual_hs_type_detect(cs42l42);
1250         }
1251
1252         /* Set up button detection */
1253         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1254               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1255                 /* Set auto HS bias settings to default */
1256                 regmap_update_bits(cs42l42->regmap,
1257                         CS42L42_HSBIAS_SC_AUTOCTL,
1258                         CS42L42_HSBIAS_SENSE_EN_MASK |
1259                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1260                         CS42L42_TIP_SENSE_EN_MASK |
1261                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1262                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1263                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1264                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1265                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1266
1267                 /* Set up hs detect level sensitivity */
1268                 regmap_update_bits(cs42l42->regmap,
1269                         CS42L42_MIC_DET_CTL1,
1270                         CS42L42_LATCH_TO_VP_MASK |
1271                         CS42L42_EVENT_STAT_SEL_MASK |
1272                         CS42L42_HS_DET_LEVEL_MASK,
1273                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1274                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1275                         (cs42l42->bias_thresholds[0] <<
1276                         CS42L42_HS_DET_LEVEL_SHIFT));
1277
1278                 /* Set auto HS bias settings to default */
1279                 regmap_update_bits(cs42l42->regmap,
1280                         CS42L42_HSBIAS_SC_AUTOCTL,
1281                         CS42L42_HSBIAS_SENSE_EN_MASK |
1282                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1283                         CS42L42_TIP_SENSE_EN_MASK |
1284                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1285                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1286                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1287                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1288                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1289
1290                 /* Turn on level detect circuitry */
1291                 regmap_update_bits(cs42l42->regmap,
1292                         CS42L42_MISC_DET_CTL,
1293                         CS42L42_HSBIAS_CTL_MASK |
1294                         CS42L42_PDN_MIC_LVL_DET_MASK,
1295                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1296                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1297
1298                 msleep(cs42l42->btn_det_init_dbnce);
1299
1300                 /* Clear any button interrupts before unmasking them */
1301                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1302                             &int_status);
1303
1304                 /* Unmask button detect interrupts */
1305                 regmap_update_bits(cs42l42->regmap,
1306                         CS42L42_DET_INT2_MASK,
1307                         CS42L42_M_DETECT_TF_MASK |
1308                         CS42L42_M_DETECT_FT_MASK |
1309                         CS42L42_M_HSBIAS_HIZ_MASK |
1310                         CS42L42_M_SHORT_RLS_MASK |
1311                         CS42L42_M_SHORT_DET_MASK,
1312                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1313                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1314                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1315                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1316                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1317         } else {
1318                 /* Make sure button detect and HS bias circuits are off */
1319                 regmap_update_bits(cs42l42->regmap,
1320                         CS42L42_MISC_DET_CTL,
1321                         CS42L42_HSBIAS_CTL_MASK |
1322                         CS42L42_PDN_MIC_LVL_DET_MASK,
1323                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1324                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1325         }
1326
1327         regmap_update_bits(cs42l42->regmap,
1328                                 CS42L42_DAC_CTL2,
1329                                 CS42L42_HPOUT_PULLDOWN_MASK |
1330                                 CS42L42_HPOUT_LOAD_MASK |
1331                                 CS42L42_HPOUT_CLAMP_MASK |
1332                                 CS42L42_DAC_HPF_EN_MASK |
1333                                 CS42L42_DAC_MON_EN_MASK,
1334                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1335                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1336                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1337                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1338                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1339
1340         /* Unmask tip sense interrupts */
1341         regmap_update_bits(cs42l42->regmap,
1342                 CS42L42_TSRS_PLUG_INT_MASK,
1343                 CS42L42_TS_PLUG_MASK |
1344                 CS42L42_TS_UNPLUG_MASK,
1345                 (0 << CS42L42_TS_PLUG_SHIFT) |
1346                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1347 }
1348
1349 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1350 {
1351         /* Mask tip sense interrupts */
1352         regmap_update_bits(cs42l42->regmap,
1353                                 CS42L42_TSRS_PLUG_INT_MASK,
1354                                 CS42L42_TS_PLUG_MASK |
1355                                 CS42L42_TS_UNPLUG_MASK,
1356                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1357                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1358
1359         /* Make sure button detect and HS bias circuits are off */
1360         regmap_update_bits(cs42l42->regmap,
1361                                 CS42L42_MISC_DET_CTL,
1362                                 CS42L42_HSBIAS_CTL_MASK |
1363                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1364                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1365                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1366
1367         /* Set auto HS bias settings to default */
1368         regmap_update_bits(cs42l42->regmap,
1369                                 CS42L42_HSBIAS_SC_AUTOCTL,
1370                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1371                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1372                                 CS42L42_TIP_SENSE_EN_MASK |
1373                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1374                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1375                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1376                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1377                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1378
1379         /* Set hs detect to manual, disabled mode */
1380         regmap_update_bits(cs42l42->regmap,
1381                                 CS42L42_HSDET_CTL2,
1382                                 CS42L42_HSDET_CTRL_MASK |
1383                                 CS42L42_HSDET_SET_MASK |
1384                                 CS42L42_HSBIAS_REF_MASK |
1385                                 CS42L42_HSDET_AUTO_TIME_MASK,
1386                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1387                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1388                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1389                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1390
1391         regmap_update_bits(cs42l42->regmap,
1392                                 CS42L42_DAC_CTL2,
1393                                 CS42L42_HPOUT_PULLDOWN_MASK |
1394                                 CS42L42_HPOUT_LOAD_MASK |
1395                                 CS42L42_HPOUT_CLAMP_MASK |
1396                                 CS42L42_DAC_HPF_EN_MASK |
1397                                 CS42L42_DAC_MON_EN_MASK,
1398                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1399                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1400                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1401                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1402                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1403
1404         /* Power up HS bias to 2.7V */
1405         regmap_update_bits(cs42l42->regmap,
1406                                 CS42L42_MISC_DET_CTL,
1407                                 CS42L42_HSBIAS_CTL_MASK |
1408                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1409                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1410                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1411
1412         /* Wait for HS bias to ramp up */
1413         msleep(cs42l42->hs_bias_ramp_time);
1414
1415         /* Unmask auto detect interrupt */
1416         regmap_update_bits(cs42l42->regmap,
1417                                 CS42L42_CODEC_INT_MASK,
1418                                 CS42L42_PDN_DONE_MASK |
1419                                 CS42L42_HSDET_AUTO_DONE_MASK,
1420                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1421                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1422
1423         /* Set hs detect to automatic, enabled mode */
1424         regmap_update_bits(cs42l42->regmap,
1425                                 CS42L42_HSDET_CTL2,
1426                                 CS42L42_HSDET_CTRL_MASK |
1427                                 CS42L42_HSDET_SET_MASK |
1428                                 CS42L42_HSBIAS_REF_MASK |
1429                                 CS42L42_HSDET_AUTO_TIME_MASK,
1430                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1431                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1432                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1433                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1434 }
1435
1436 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1437 {
1438         /* Mask button detect interrupts */
1439         regmap_update_bits(cs42l42->regmap,
1440                 CS42L42_DET_INT2_MASK,
1441                 CS42L42_M_DETECT_TF_MASK |
1442                 CS42L42_M_DETECT_FT_MASK |
1443                 CS42L42_M_HSBIAS_HIZ_MASK |
1444                 CS42L42_M_SHORT_RLS_MASK |
1445                 CS42L42_M_SHORT_DET_MASK,
1446                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1447                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1448                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1449                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1450                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1451
1452         /* Ground HS bias */
1453         regmap_update_bits(cs42l42->regmap,
1454                                 CS42L42_MISC_DET_CTL,
1455                                 CS42L42_HSBIAS_CTL_MASK |
1456                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1457                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1458                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1459
1460         /* Set auto HS bias settings to default */
1461         regmap_update_bits(cs42l42->regmap,
1462                                 CS42L42_HSBIAS_SC_AUTOCTL,
1463                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1464                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1465                                 CS42L42_TIP_SENSE_EN_MASK |
1466                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1467                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1468                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1469                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1470                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1471
1472         /* Set hs detect to manual, disabled mode */
1473         regmap_update_bits(cs42l42->regmap,
1474                                 CS42L42_HSDET_CTL2,
1475                                 CS42L42_HSDET_CTRL_MASK |
1476                                 CS42L42_HSDET_SET_MASK |
1477                                 CS42L42_HSBIAS_REF_MASK |
1478                                 CS42L42_HSDET_AUTO_TIME_MASK,
1479                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1480                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1481                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1482                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1483 }
1484
1485 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1486 {
1487         int bias_level;
1488         unsigned int detect_status;
1489
1490         /* Mask button detect interrupts */
1491         regmap_update_bits(cs42l42->regmap,
1492                 CS42L42_DET_INT2_MASK,
1493                 CS42L42_M_DETECT_TF_MASK |
1494                 CS42L42_M_DETECT_FT_MASK |
1495                 CS42L42_M_HSBIAS_HIZ_MASK |
1496                 CS42L42_M_SHORT_RLS_MASK |
1497                 CS42L42_M_SHORT_DET_MASK,
1498                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1499                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1500                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1501                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1502                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1503
1504         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1505                      cs42l42->btn_det_event_dbnce * 2000);
1506
1507         /* Test all 4 level detect biases */
1508         bias_level = 1;
1509         do {
1510                 /* Adjust button detect level sensitivity */
1511                 regmap_update_bits(cs42l42->regmap,
1512                         CS42L42_MIC_DET_CTL1,
1513                         CS42L42_LATCH_TO_VP_MASK |
1514                         CS42L42_EVENT_STAT_SEL_MASK |
1515                         CS42L42_HS_DET_LEVEL_MASK,
1516                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1517                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1518                         (cs42l42->bias_thresholds[bias_level] <<
1519                         CS42L42_HS_DET_LEVEL_SHIFT));
1520
1521                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1522                                 &detect_status);
1523         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1524                 (++bias_level < CS42L42_NUM_BIASES));
1525
1526         switch (bias_level) {
1527         case 1: /* Function C button press */
1528                 bias_level = SND_JACK_BTN_2;
1529                 dev_dbg(cs42l42->dev, "Function C button press\n");
1530                 break;
1531         case 2: /* Function B button press */
1532                 bias_level = SND_JACK_BTN_1;
1533                 dev_dbg(cs42l42->dev, "Function B button press\n");
1534                 break;
1535         case 3: /* Function D button press */
1536                 bias_level = SND_JACK_BTN_3;
1537                 dev_dbg(cs42l42->dev, "Function D button press\n");
1538                 break;
1539         case 4: /* Function A button press */
1540                 bias_level = SND_JACK_BTN_0;
1541                 dev_dbg(cs42l42->dev, "Function A button press\n");
1542                 break;
1543         default:
1544                 bias_level = 0;
1545                 break;
1546         }
1547
1548         /* Set button detect level sensitivity back to default */
1549         regmap_update_bits(cs42l42->regmap,
1550                 CS42L42_MIC_DET_CTL1,
1551                 CS42L42_LATCH_TO_VP_MASK |
1552                 CS42L42_EVENT_STAT_SEL_MASK |
1553                 CS42L42_HS_DET_LEVEL_MASK,
1554                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1555                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1556                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1557
1558         /* Clear any button interrupts before unmasking them */
1559         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1560                     &detect_status);
1561
1562         /* Unmask button detect interrupts */
1563         regmap_update_bits(cs42l42->regmap,
1564                 CS42L42_DET_INT2_MASK,
1565                 CS42L42_M_DETECT_TF_MASK |
1566                 CS42L42_M_DETECT_FT_MASK |
1567                 CS42L42_M_HSBIAS_HIZ_MASK |
1568                 CS42L42_M_SHORT_RLS_MASK |
1569                 CS42L42_M_SHORT_DET_MASK,
1570                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1571                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1572                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1573                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1574                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1575
1576         return bias_level;
1577 }
1578
1579 struct cs42l42_irq_params {
1580         u16 status_addr;
1581         u16 mask_addr;
1582         u8 mask;
1583 };
1584
1585 static const struct cs42l42_irq_params irq_params_table[] = {
1586         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1587                 CS42L42_ADC_OVFL_VAL_MASK},
1588         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1589                 CS42L42_MIXER_VAL_MASK},
1590         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1591                 CS42L42_SRC_VAL_MASK},
1592         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1593                 CS42L42_ASP_RX_VAL_MASK},
1594         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1595                 CS42L42_ASP_TX_VAL_MASK},
1596         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1597                 CS42L42_CODEC_VAL_MASK},
1598         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1599                 CS42L42_DET_INT_VAL1_MASK},
1600         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1601                 CS42L42_DET_INT_VAL2_MASK},
1602         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1603                 CS42L42_SRCPL_VAL_MASK},
1604         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1605                 CS42L42_VPMON_VAL_MASK},
1606         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1607                 CS42L42_PLL_LOCK_VAL_MASK},
1608         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1609                 CS42L42_TSRS_PLUG_VAL_MASK}
1610 };
1611
1612 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1613 {
1614         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1615         unsigned int stickies[12];
1616         unsigned int masks[12];
1617         unsigned int current_plug_status;
1618         unsigned int current_button_status;
1619         unsigned int i;
1620
1621         mutex_lock(&cs42l42->irq_lock);
1622         if (cs42l42->suspended) {
1623                 mutex_unlock(&cs42l42->irq_lock);
1624                 return IRQ_NONE;
1625         }
1626
1627         /* Read sticky registers to clear interurpt */
1628         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1629                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1630                                 &(stickies[i]));
1631                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1632                                 &(masks[i]));
1633                 stickies[i] = stickies[i] & (~masks[i]) &
1634                                 irq_params_table[i].mask;
1635         }
1636
1637         /* Read tip sense status before handling type detect */
1638         current_plug_status = (stickies[11] &
1639                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1640                 CS42L42_TS_PLUG_SHIFT;
1641
1642         /* Read button sense status */
1643         current_button_status = stickies[7] &
1644                 (CS42L42_M_DETECT_TF_MASK |
1645                 CS42L42_M_DETECT_FT_MASK |
1646                 CS42L42_M_HSBIAS_HIZ_MASK);
1647
1648         /*
1649          * Check auto-detect status. Don't assume a previous unplug event has
1650          * cleared the flags. If the jack is unplugged and plugged during
1651          * system suspend there won't have been an unplug event.
1652          */
1653         if ((~masks[5]) & irq_params_table[5].mask) {
1654                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1655                         cs42l42_process_hs_type_detect(cs42l42);
1656                         switch (cs42l42->hs_type) {
1657                         case CS42L42_PLUG_CTIA:
1658                         case CS42L42_PLUG_OMTP:
1659                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1660                                                     SND_JACK_HEADSET |
1661                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1662                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1663                                 break;
1664                         case CS42L42_PLUG_HEADPHONE:
1665                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1666                                                     SND_JACK_HEADSET |
1667                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1668                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1669                                 break;
1670                         default:
1671                                 break;
1672                         }
1673                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1674                 }
1675         }
1676
1677         /* Check tip sense status */
1678         if ((~masks[11]) & irq_params_table[11].mask) {
1679                 switch (current_plug_status) {
1680                 case CS42L42_TS_PLUG:
1681                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1682                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1683                                 cs42l42_init_hs_type_detect(cs42l42);
1684                         }
1685                         break;
1686
1687                 case CS42L42_TS_UNPLUG:
1688                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1689                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1690                                 cs42l42_cancel_hs_type_detect(cs42l42);
1691
1692                                 snd_soc_jack_report(cs42l42->jack, 0,
1693                                                     SND_JACK_HEADSET |
1694                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1695                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1696
1697                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1698                         }
1699                         break;
1700
1701                 default:
1702                         cs42l42->plug_state = CS42L42_TS_TRANS;
1703                 }
1704         }
1705
1706         /* Check button detect status */
1707         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1708                 if (!(current_button_status &
1709                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1710
1711                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1712                                 dev_dbg(cs42l42->dev, "Button released\n");
1713                                 snd_soc_jack_report(cs42l42->jack, 0,
1714                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1715                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1716                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1717                                 snd_soc_jack_report(cs42l42->jack,
1718                                                     cs42l42_handle_button_press(cs42l42),
1719                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1720                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1721                         }
1722                 }
1723         }
1724
1725         mutex_unlock(&cs42l42->irq_lock);
1726
1727         return IRQ_HANDLED;
1728 }
1729
1730 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1731 {
1732         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1733                         CS42L42_ADC_OVFL_MASK,
1734                         (1 << CS42L42_ADC_OVFL_SHIFT));
1735
1736         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1737                         CS42L42_MIX_CHB_OVFL_MASK |
1738                         CS42L42_MIX_CHA_OVFL_MASK |
1739                         CS42L42_EQ_OVFL_MASK |
1740                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1741                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1742                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1743                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1744                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1745
1746         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1747                         CS42L42_SRC_ILK_MASK |
1748                         CS42L42_SRC_OLK_MASK |
1749                         CS42L42_SRC_IUNLK_MASK |
1750                         CS42L42_SRC_OUNLK_MASK,
1751                         (1 << CS42L42_SRC_ILK_SHIFT) |
1752                         (1 << CS42L42_SRC_OLK_SHIFT) |
1753                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1754                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1755
1756         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1757                         CS42L42_ASPRX_NOLRCK_MASK |
1758                         CS42L42_ASPRX_EARLY_MASK |
1759                         CS42L42_ASPRX_LATE_MASK |
1760                         CS42L42_ASPRX_ERROR_MASK |
1761                         CS42L42_ASPRX_OVLD_MASK,
1762                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1763                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1764                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1765                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1766                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1767
1768         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1769                         CS42L42_ASPTX_NOLRCK_MASK |
1770                         CS42L42_ASPTX_EARLY_MASK |
1771                         CS42L42_ASPTX_LATE_MASK |
1772                         CS42L42_ASPTX_SMERROR_MASK,
1773                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1774                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1775                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1776                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1777
1778         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1779                         CS42L42_PDN_DONE_MASK |
1780                         CS42L42_HSDET_AUTO_DONE_MASK,
1781                         (1 << CS42L42_PDN_DONE_SHIFT) |
1782                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1783
1784         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1785                         CS42L42_SRCPL_ADC_LK_MASK |
1786                         CS42L42_SRCPL_DAC_LK_MASK |
1787                         CS42L42_SRCPL_ADC_UNLK_MASK |
1788                         CS42L42_SRCPL_DAC_UNLK_MASK,
1789                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1790                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1791                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1792                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1793
1794         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1795                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1796                         CS42L42_TIP_SENSE_PLUG_MASK |
1797                         CS42L42_HSBIAS_SENSE_MASK,
1798                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1799                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1800                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1801
1802         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1803                         CS42L42_M_DETECT_TF_MASK |
1804                         CS42L42_M_DETECT_FT_MASK |
1805                         CS42L42_M_HSBIAS_HIZ_MASK |
1806                         CS42L42_M_SHORT_RLS_MASK |
1807                         CS42L42_M_SHORT_DET_MASK,
1808                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1809                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1810                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1811                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1812                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1813
1814         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1815                         CS42L42_VPMON_MASK,
1816                         (1 << CS42L42_VPMON_SHIFT));
1817
1818         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1819                         CS42L42_PLL_LOCK_MASK,
1820                         (1 << CS42L42_PLL_LOCK_SHIFT));
1821
1822         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1823                         CS42L42_RS_PLUG_MASK |
1824                         CS42L42_RS_UNPLUG_MASK |
1825                         CS42L42_TS_PLUG_MASK |
1826                         CS42L42_TS_UNPLUG_MASK,
1827                         (1 << CS42L42_RS_PLUG_SHIFT) |
1828                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1829                         (0 << CS42L42_TS_PLUG_SHIFT) |
1830                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1831 }
1832
1833 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1834 {
1835         unsigned int reg;
1836
1837         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1838
1839         /*
1840          * DETECT_MODE must always be 0 with ADC and HP both off otherwise the
1841          * FILT+ supply will not charge properly.
1842          */
1843         regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
1844                            CS42L42_DETECT_MODE_MASK, 0);
1845
1846         /* Latch analog controls to VP power domain */
1847         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1848                         CS42L42_LATCH_TO_VP_MASK |
1849                         CS42L42_EVENT_STAT_SEL_MASK |
1850                         CS42L42_HS_DET_LEVEL_MASK,
1851                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1852                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1853                         (cs42l42->bias_thresholds[0] <<
1854                         CS42L42_HS_DET_LEVEL_SHIFT));
1855
1856         /* Remove ground noise-suppression clamps */
1857         regmap_update_bits(cs42l42->regmap,
1858                         CS42L42_HS_CLAMP_DISABLE,
1859                         CS42L42_HS_CLAMP_DISABLE_MASK,
1860                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1861
1862         /* Enable the tip sense circuit */
1863         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1864                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1865
1866         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1867                         CS42L42_TIP_SENSE_CTRL_MASK |
1868                         CS42L42_TIP_SENSE_INV_MASK |
1869                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1870                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1871                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1872                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1873
1874         /* Save the initial status of the tip sense */
1875         regmap_read(cs42l42->regmap,
1876                           CS42L42_TSRS_PLUG_STATUS,
1877                           &reg);
1878         cs42l42->plug_state = (((char) reg) &
1879                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1880                       CS42L42_TS_PLUG_SHIFT;
1881 }
1882
1883 static const unsigned int threshold_defaults[] = {
1884         CS42L42_HS_DET_LEVEL_15,
1885         CS42L42_HS_DET_LEVEL_8,
1886         CS42L42_HS_DET_LEVEL_4,
1887         CS42L42_HS_DET_LEVEL_1
1888 };
1889
1890 static int cs42l42_handle_device_data(struct device *dev,
1891                                         struct cs42l42_private *cs42l42)
1892 {
1893         unsigned int val;
1894         u32 thresholds[CS42L42_NUM_BIASES];
1895         int ret;
1896         int i;
1897
1898         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1899         if (!ret) {
1900                 switch (val) {
1901                 case CS42L42_TS_INV_EN:
1902                 case CS42L42_TS_INV_DIS:
1903                         cs42l42->ts_inv = val;
1904                         break;
1905                 default:
1906                         dev_err(dev,
1907                                 "Wrong cirrus,ts-inv DT value %d\n",
1908                                 val);
1909                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1910                 }
1911         } else {
1912                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1913         }
1914
1915         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1916         if (!ret) {
1917                 switch (val) {
1918                 case CS42L42_TS_DBNCE_0:
1919                 case CS42L42_TS_DBNCE_125:
1920                 case CS42L42_TS_DBNCE_250:
1921                 case CS42L42_TS_DBNCE_500:
1922                 case CS42L42_TS_DBNCE_750:
1923                 case CS42L42_TS_DBNCE_1000:
1924                 case CS42L42_TS_DBNCE_1250:
1925                 case CS42L42_TS_DBNCE_1500:
1926                         cs42l42->ts_dbnc_rise = val;
1927                         break;
1928                 default:
1929                         dev_err(dev,
1930                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1931                                 val);
1932                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1933                 }
1934         } else {
1935                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1936         }
1937
1938         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1939                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1940                         (cs42l42->ts_dbnc_rise <<
1941                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1942
1943         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1944         if (!ret) {
1945                 switch (val) {
1946                 case CS42L42_TS_DBNCE_0:
1947                 case CS42L42_TS_DBNCE_125:
1948                 case CS42L42_TS_DBNCE_250:
1949                 case CS42L42_TS_DBNCE_500:
1950                 case CS42L42_TS_DBNCE_750:
1951                 case CS42L42_TS_DBNCE_1000:
1952                 case CS42L42_TS_DBNCE_1250:
1953                 case CS42L42_TS_DBNCE_1500:
1954                         cs42l42->ts_dbnc_fall = val;
1955                         break;
1956                 default:
1957                         dev_err(dev,
1958                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1959                                 val);
1960                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1961                 }
1962         } else {
1963                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1964         }
1965
1966         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1967                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1968                         (cs42l42->ts_dbnc_fall <<
1969                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1970
1971         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1972         if (!ret) {
1973                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1974                         cs42l42->btn_det_init_dbnce = val;
1975                 else {
1976                         dev_err(dev,
1977                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1978                                 val);
1979                         cs42l42->btn_det_init_dbnce =
1980                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1981                 }
1982         } else {
1983                 cs42l42->btn_det_init_dbnce =
1984                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1985         }
1986
1987         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1988         if (!ret) {
1989                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1990                         cs42l42->btn_det_event_dbnce = val;
1991                 else {
1992                         dev_err(dev,
1993                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1994                         cs42l42->btn_det_event_dbnce =
1995                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1996                 }
1997         } else {
1998                 cs42l42->btn_det_event_dbnce =
1999                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2000         }
2001
2002         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
2003                                              thresholds, ARRAY_SIZE(thresholds));
2004         if (!ret) {
2005                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
2006                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
2007                                 cs42l42->bias_thresholds[i] = thresholds[i];
2008                         else {
2009                                 dev_err(dev,
2010                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
2011                                         thresholds[i]);
2012                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2013                         }
2014                 }
2015         } else {
2016                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2017                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
2018         }
2019
2020         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2021         if (!ret) {
2022                 switch (val) {
2023                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2024                         cs42l42->hs_bias_ramp_rate = val;
2025                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2026                         break;
2027                 case CS42L42_HSBIAS_RAMP_FAST:
2028                         cs42l42->hs_bias_ramp_rate = val;
2029                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2030                         break;
2031                 case CS42L42_HSBIAS_RAMP_SLOW:
2032                         cs42l42->hs_bias_ramp_rate = val;
2033                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2034                         break;
2035                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2036                         cs42l42->hs_bias_ramp_rate = val;
2037                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2038                         break;
2039                 default:
2040                         dev_err(dev,
2041                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2042                                 val);
2043                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2044                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2045                 }
2046         } else {
2047                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2048                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2049         }
2050
2051         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2052                         CS42L42_HSBIAS_RAMP_MASK,
2053                         (cs42l42->hs_bias_ramp_rate <<
2054                         CS42L42_HSBIAS_RAMP_SHIFT));
2055
2056         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2057                 cs42l42->hs_bias_sense_en = 0;
2058         else
2059                 cs42l42->hs_bias_sense_en = 1;
2060
2061         return 0;
2062 }
2063
2064 /* Datasheet suspend sequence */
2065 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = {
2066         REG_SEQ0(CS42L42_MIC_DET_CTL1,          0x9F),
2067         REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK,     0x01),
2068         REG_SEQ0(CS42L42_MIXER_INT_MASK,        0x0F),
2069         REG_SEQ0(CS42L42_SRC_INT_MASK,          0x0F),
2070         REG_SEQ0(CS42L42_ASP_RX_INT_MASK,       0x1F),
2071         REG_SEQ0(CS42L42_ASP_TX_INT_MASK,       0x0F),
2072         REG_SEQ0(CS42L42_CODEC_INT_MASK,        0x03),
2073         REG_SEQ0(CS42L42_SRCPL_INT_MASK,        0x7F),
2074         REG_SEQ0(CS42L42_VPMON_INT_MASK,        0x01),
2075         REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK,     0x01),
2076         REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK,    0x0F),
2077         REG_SEQ0(CS42L42_WAKE_CTL,              0xE1),
2078         REG_SEQ0(CS42L42_DET_INT1_MASK,         0xE0),
2079         REG_SEQ0(CS42L42_DET_INT2_MASK,         0xFF),
2080         REG_SEQ0(CS42L42_MIXER_CHA_VOL,         0x3F),
2081         REG_SEQ0(CS42L42_MIXER_ADC_VOL,         0x3F),
2082         REG_SEQ0(CS42L42_MIXER_CHB_VOL,         0x3F),
2083         REG_SEQ0(CS42L42_HP_CTL,                0x0F),
2084         REG_SEQ0(CS42L42_ASP_RX_DAI0_EN,        0x00),
2085         REG_SEQ0(CS42L42_ASP_CLK_CFG,           0x00),
2086         REG_SEQ0(CS42L42_HSDET_CTL2,            0x00),
2087         REG_SEQ0(CS42L42_PWR_CTL1,              0xFE),
2088         REG_SEQ0(CS42L42_PWR_CTL2,              0x8C),
2089         REG_SEQ0(CS42L42_DAC_CTL2,              0x02),
2090         REG_SEQ0(CS42L42_HS_CLAMP_DISABLE,      0x00),
2091         REG_SEQ0(CS42L42_MISC_DET_CTL,          0x03),
2092         REG_SEQ0(CS42L42_TIPSENSE_CTL,          0x02),
2093         REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL,     0x03),
2094         REG_SEQ0(CS42L42_PWR_CTL1,              0xFF)
2095 };
2096
2097 static int __maybe_unused cs42l42_suspend(struct device *dev)
2098 {
2099         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2100         unsigned int reg;
2101         u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
2102         int i, ret;
2103
2104         /*
2105          * Wait for threaded irq handler to be idle and stop it processing
2106          * future interrupts. This ensures a safe disable if the interrupt
2107          * is shared.
2108          */
2109         mutex_lock(&cs42l42->irq_lock);
2110         cs42l42->suspended = true;
2111
2112         /* Save register values that will be overwritten by shutdown sequence */
2113         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) {
2114                 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, &reg);
2115                 save_regs[i] = (u8)reg;
2116         }
2117
2118         /* Shutdown codec */
2119         regmap_multi_reg_write(cs42l42->regmap,
2120                                cs42l42_shutdown_seq,
2121                                ARRAY_SIZE(cs42l42_shutdown_seq));
2122
2123         /* All interrupt sources are now disabled */
2124         mutex_unlock(&cs42l42->irq_lock);
2125
2126         /* Wait for power-down complete */
2127         msleep(CS42L42_PDN_DONE_TIME_MS);
2128         ret = regmap_read_poll_timeout(cs42l42->regmap,
2129                                        CS42L42_CODEC_STATUS, reg,
2130                                        (reg & CS42L42_PDN_DONE_MASK),
2131                                        CS42L42_PDN_DONE_POLL_US,
2132                                        CS42L42_PDN_DONE_TIMEOUT_US);
2133         if (ret)
2134                 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret);
2135
2136         /* Discharge FILT+ */
2137         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2138                            CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK);
2139         msleep(CS42L42_FILT_DISCHARGE_TIME_MS);
2140
2141         regcache_cache_only(cs42l42->regmap, true);
2142         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2143         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2144
2145         /* Restore register values to the regmap cache */
2146         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i)
2147                 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]);
2148
2149         /* The cached address page register value is now stale */
2150         regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER);
2151
2152         dev_dbg(dev, "System suspended\n");
2153
2154         return 0;
2155
2156 }
2157
2158 static int __maybe_unused cs42l42_resume(struct device *dev)
2159 {
2160         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2161         int ret;
2162
2163         /*
2164          * If jack was unplugged and re-plugged during suspend it could
2165          * have changed type but the tip-sense state hasn't changed.
2166          * Force a plugged state to be re-evaluated.
2167          */
2168         if (cs42l42->plug_state != CS42L42_TS_UNPLUG)
2169                 cs42l42->plug_state = CS42L42_TS_TRANS;
2170
2171         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2172         if (ret != 0) {
2173                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
2174                 return ret;
2175         }
2176
2177         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2178         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2179
2180         regcache_cache_only(cs42l42->regmap, false);
2181         regcache_mark_dirty(cs42l42->regmap);
2182
2183         mutex_lock(&cs42l42->irq_lock);
2184         /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
2185         regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
2186         regcache_sync(cs42l42->regmap);
2187
2188         cs42l42->suspended = false;
2189         mutex_unlock(&cs42l42->irq_lock);
2190
2191         dev_dbg(dev, "System resumed\n");
2192
2193         return 0;
2194 }
2195
2196 static int cs42l42_i2c_probe(struct i2c_client *i2c_client)
2197 {
2198         struct cs42l42_private *cs42l42;
2199         int ret, i, devid;
2200         unsigned int reg;
2201
2202         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
2203                                GFP_KERNEL);
2204         if (!cs42l42)
2205                 return -ENOMEM;
2206
2207         cs42l42->dev = &i2c_client->dev;
2208         i2c_set_clientdata(i2c_client, cs42l42);
2209         mutex_init(&cs42l42->irq_lock);
2210
2211         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
2212         if (IS_ERR(cs42l42->regmap)) {
2213                 ret = PTR_ERR(cs42l42->regmap);
2214                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
2215                 return ret;
2216         }
2217
2218         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2219                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2220
2221         ret = devm_regulator_bulk_get(&i2c_client->dev,
2222                                       ARRAY_SIZE(cs42l42->supplies),
2223                                       cs42l42->supplies);
2224         if (ret != 0) {
2225                 dev_err(&i2c_client->dev,
2226                         "Failed to request supplies: %d\n", ret);
2227                 return ret;
2228         }
2229
2230         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2231                                     cs42l42->supplies);
2232         if (ret != 0) {
2233                 dev_err(&i2c_client->dev,
2234                         "Failed to enable supplies: %d\n", ret);
2235                 return ret;
2236         }
2237
2238         /* Reset the Device */
2239         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
2240                 "reset", GPIOD_OUT_LOW);
2241         if (IS_ERR(cs42l42->reset_gpio)) {
2242                 ret = PTR_ERR(cs42l42->reset_gpio);
2243                 goto err_disable_noreset;
2244         }
2245
2246         if (cs42l42->reset_gpio) {
2247                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
2248                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2249         }
2250         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2251
2252         /* Request IRQ if one was specified */
2253         if (i2c_client->irq) {
2254                 ret = request_threaded_irq(i2c_client->irq,
2255                                            NULL, cs42l42_irq_thread,
2256                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2257                                            "cs42l42", cs42l42);
2258                 if (ret == -EPROBE_DEFER) {
2259                         goto err_disable_noirq;
2260                 } else if (ret != 0) {
2261                         dev_err(&i2c_client->dev,
2262                                 "Failed to request IRQ: %d\n", ret);
2263                         goto err_disable_noirq;
2264                 }
2265         }
2266
2267         /* initialize codec */
2268         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2269         if (devid < 0) {
2270                 ret = devid;
2271                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
2272                 goto err_disable;
2273         }
2274
2275         if (devid != CS42L42_CHIP_ID) {
2276                 ret = -ENODEV;
2277                 dev_err(&i2c_client->dev,
2278                         "CS42L42 Device ID (%X). Expected %X\n",
2279                         devid, CS42L42_CHIP_ID);
2280                 goto err_disable;
2281         }
2282
2283         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2284         if (ret < 0) {
2285                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
2286                 goto err_shutdown;
2287         }
2288
2289         dev_info(&i2c_client->dev,
2290                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
2291
2292         /* Power up the codec */
2293         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2294                         CS42L42_ASP_DAO_PDN_MASK |
2295                         CS42L42_ASP_DAI_PDN_MASK |
2296                         CS42L42_MIXER_PDN_MASK |
2297                         CS42L42_EQ_PDN_MASK |
2298                         CS42L42_HP_PDN_MASK |
2299                         CS42L42_ADC_PDN_MASK |
2300                         CS42L42_PDN_ALL_MASK,
2301                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2302                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2303                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2304                         (1 << CS42L42_EQ_PDN_SHIFT) |
2305                         (1 << CS42L42_HP_PDN_SHIFT) |
2306                         (1 << CS42L42_ADC_PDN_SHIFT) |
2307                         (0 << CS42L42_PDN_ALL_SHIFT));
2308
2309         ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
2310         if (ret != 0)
2311                 goto err_shutdown;
2312
2313         /* Setup headset detection */
2314         cs42l42_setup_hs_type_detect(cs42l42);
2315
2316         /* Mask/Unmask Interrupts */
2317         cs42l42_set_interrupt_masks(cs42l42);
2318
2319         /* Register codec for machine driver */
2320         ret = devm_snd_soc_register_component(&i2c_client->dev,
2321                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2322         if (ret < 0)
2323                 goto err_shutdown;
2324
2325         return 0;
2326
2327 err_shutdown:
2328         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2329         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2330         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2331
2332 err_disable:
2333         if (i2c_client->irq)
2334                 free_irq(i2c_client->irq, cs42l42);
2335
2336 err_disable_noirq:
2337         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2338 err_disable_noreset:
2339         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2340                                 cs42l42->supplies);
2341         return ret;
2342 }
2343
2344 static void cs42l42_i2c_remove(struct i2c_client *i2c_client)
2345 {
2346         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2347
2348         if (i2c_client->irq)
2349                 free_irq(i2c_client->irq, cs42l42);
2350
2351         /*
2352          * The driver might not have control of reset and power supplies,
2353          * so ensure that the chip internals are powered down.
2354          */
2355         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2356         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2357         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2358
2359         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2360         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2361 }
2362
2363 static const struct dev_pm_ops cs42l42_pm_ops = {
2364         SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_resume)
2365 };
2366
2367 #ifdef CONFIG_OF
2368 static const struct of_device_id cs42l42_of_match[] = {
2369         { .compatible = "cirrus,cs42l42", },
2370         {}
2371 };
2372 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2373 #endif
2374
2375 #ifdef CONFIG_ACPI
2376 static const struct acpi_device_id cs42l42_acpi_match[] = {
2377         {"10134242", 0,},
2378         {}
2379 };
2380 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2381 #endif
2382
2383 static const struct i2c_device_id cs42l42_id[] = {
2384         {"cs42l42", 0},
2385         {}
2386 };
2387
2388 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2389
2390 static struct i2c_driver cs42l42_i2c_driver = {
2391         .driver = {
2392                 .name = "cs42l42",
2393                 .pm = &cs42l42_pm_ops,
2394                 .of_match_table = of_match_ptr(cs42l42_of_match),
2395                 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2396                 },
2397         .id_table = cs42l42_id,
2398         .probe_new = cs42l42_i2c_probe,
2399         .remove = cs42l42_i2c_remove,
2400 };
2401
2402 module_i2c_driver(cs42l42_i2c_driver);
2403
2404 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2405 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2406 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2407 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2408 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2409 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2410 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2411 MODULE_LICENSE("GPL");