sound/soc/codecs/cs35l56.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Driver for Cirrus Logic CS35L56 smart amp
   4 //
   5 // Copyright (C) 2023 Cirrus Logic, Inc. and
   6 //                    Cirrus Logic International Semiconductor Ltd.
   7
   8 #include <linux/completion.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/math.h>
  15 #include <linux/module.h>
  16 #include <linux/pm.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/slab.h>
  21 #include <linux/soundwire/sdw.h>
  22 #include <linux/types.h>
  23 #include <linux/workqueue.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/tlv.h>
  29
  30 #include "wm_adsp.h"
  31 #include "cs35l56.h"
  32
  33 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w,
  34                              struct snd_kcontrol *kcontrol, int event);
  35
  36 static int cs35l56_mbox_send(struct cs35l56_private *cs35l56, unsigned int command)
  37 {
  38         unsigned int val;
  39         int ret;
  40
  41         regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
  42         ret = regmap_read_poll_timeout(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
  43                                        val, (val == 0),
  44                                        CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
  45         if (ret) {
  46                 dev_warn(cs35l56->dev, "MBOX command %#x failed: %d\n", command, ret);
  47                 return ret;
  48         }
  49
  50         return 0;
  51 }
  52
  53 static void cs35l56_wait_dsp_ready(struct cs35l56_private *cs35l56)
  54 {
  55         /* Wait for patching to complete */
  56         flush_work(&cs35l56->dsp_work);
  57 }
  58
  59 static int cs35l56_dspwait_get_volsw(struct snd_kcontrol *kcontrol,
  60                                      struct snd_ctl_elem_value *ucontrol)
  61 {
  62         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  63         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
  64
  65         cs35l56_wait_dsp_ready(cs35l56);
  66         return snd_soc_get_volsw(kcontrol, ucontrol);
  67 }
  68
  69 static int cs35l56_dspwait_put_volsw(struct snd_kcontrol *kcontrol,
  70                                      struct snd_ctl_elem_value *ucontrol)
  71 {
  72         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  73         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
  74
  75         cs35l56_wait_dsp_ready(cs35l56);
  76         return snd_soc_put_volsw(kcontrol, ucontrol);
  77 }
  78
  79 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0);
  80
  81 static const struct snd_kcontrol_new cs35l56_controls[] = {
  82         SOC_SINGLE_EXT("Speaker Switch",
  83                        CS35L56_MAIN_RENDER_USER_MUTE, 0, 1, 1,
  84                        cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw),
  85         SOC_SINGLE_S_EXT_TLV("Speaker Volume",
  86                              CS35L56_MAIN_RENDER_USER_VOLUME,
  87                              6, -400, 400, 9, 0,
  88                              cs35l56_dspwait_get_volsw,
  89                              cs35l56_dspwait_put_volsw,
  90                              vol_tlv),
  91         SOC_SINGLE_EXT("Posture Number", CS35L56_MAIN_POSTURE_NUMBER,
  92                        0, 255, 0,
  93                        cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw),
  94 };
  95
  96 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum,
  97                                   CS35L56_ASP1TX1_INPUT,
  98                                   0, CS35L56_ASP_TXn_SRC_MASK,
  99                                   cs35l56_tx_input_texts,
 100                                   cs35l56_tx_input_values);
 101
 102 static const struct snd_kcontrol_new asp1_tx1_mux =
 103         SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum);
 104
 105 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum,
 106                                   CS35L56_ASP1TX2_INPUT,
 107                                   0, CS35L56_ASP_TXn_SRC_MASK,
 108                                   cs35l56_tx_input_texts,
 109                                   cs35l56_tx_input_values);
 110
 111 static const struct snd_kcontrol_new asp1_tx2_mux =
 112         SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum);
 113
 114 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum,
 115                                   CS35L56_ASP1TX3_INPUT,
 116                                   0, CS35L56_ASP_TXn_SRC_MASK,
 117                                   cs35l56_tx_input_texts,
 118                                   cs35l56_tx_input_values);
 119
 120 static const struct snd_kcontrol_new asp1_tx3_mux =
 121         SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum);
 122
 123 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum,
 124                                   CS35L56_ASP1TX4_INPUT,
 125                                   0, CS35L56_ASP_TXn_SRC_MASK,
 126                                   cs35l56_tx_input_texts,
 127                                   cs35l56_tx_input_values);
 128
 129 static const struct snd_kcontrol_new asp1_tx4_mux =
 130         SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum);
 131
 132 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum,
 133                                 CS35L56_SWIRE_DP3_CH1_INPUT,
 134                                 0, CS35L56_SWIRETXn_SRC_MASK,
 135                                 cs35l56_tx_input_texts,
 136                                 cs35l56_tx_input_values);
 137
 138 static const struct snd_kcontrol_new sdw1_tx1_mux =
 139         SOC_DAPM_ENUM("SDW1TX1 SRC", cs35l56_sdw1tx1_enum);
 140
 141 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx2_enum,
 142                                 CS35L56_SWIRE_DP3_CH2_INPUT,
 143                                 0, CS35L56_SWIRETXn_SRC_MASK,
 144                                 cs35l56_tx_input_texts,
 145                                 cs35l56_tx_input_values);
 146
 147 static const struct snd_kcontrol_new sdw1_tx2_mux =
 148         SOC_DAPM_ENUM("SDW1TX2 SRC", cs35l56_sdw1tx2_enum);
 149
 150 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx3_enum,
 151                                 CS35L56_SWIRE_DP3_CH3_INPUT,
 152                                 0, CS35L56_SWIRETXn_SRC_MASK,
 153                                 cs35l56_tx_input_texts,
 154                                 cs35l56_tx_input_values);
 155
 156 static const struct snd_kcontrol_new sdw1_tx3_mux =
 157         SOC_DAPM_ENUM("SDW1TX3 SRC", cs35l56_sdw1tx3_enum);
 158
 159 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx4_enum,
 160                                 CS35L56_SWIRE_DP3_CH4_INPUT,
 161                                 0, CS35L56_SWIRETXn_SRC_MASK,
 162                                 cs35l56_tx_input_texts,
 163                                 cs35l56_tx_input_values);
 164
 165 static const struct snd_kcontrol_new sdw1_tx4_mux =
 166         SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum);
 167
 168 static int cs35l56_play_event(struct snd_soc_dapm_widget *w,
 169                               struct snd_kcontrol *kcontrol, int event)
 170 {
 171         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 172         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
 173         unsigned int val;
 174         int ret;
 175
 176         dev_dbg(cs35l56->dev, "play: %d\n", event);
 177
 178         switch (event) {
 179         case SND_SOC_DAPM_PRE_PMU:
 180                 /* Don't wait for ACK, we check in POST_PMU that it completed */
 181                 return regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
 182                                     CS35L56_MBOX_CMD_AUDIO_PLAY);
 183         case SND_SOC_DAPM_POST_PMU:
 184                 /* Wait for firmware to enter PS0 power state */
 185                 ret = regmap_read_poll_timeout(cs35l56->regmap,
 186                                                CS35L56_TRANSDUCER_ACTUAL_PS,
 187                                                val, (val == CS35L56_PS0),
 188                                                CS35L56_PS0_POLL_US,
 189                                                CS35L56_PS0_TIMEOUT_US);
 190                 if (ret)
 191                         dev_err(cs35l56->dev, "PS0 wait failed: %d\n", ret);
 192                 return ret;
 193         case SND_SOC_DAPM_POST_PMD:
 194                 return cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_AUDIO_PAUSE);
 195         default:
 196                 return 0;
 197         }
 198 }
 199
 200 static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = {
 201         SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0),
 202         SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0),
 203
 204         SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event,
 205                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 206
 207         SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0),
 208         SND_SOC_DAPM_OUTPUT("SPK"),
 209
 210         SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, cs35l56_dsp_event,
 211                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 212
 213         SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS35L56_ASP1_ENABLES1,
 214                             CS35L56_ASP_RX1_EN_SHIFT, 0),
 215         SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS35L56_ASP1_ENABLES1,
 216                             CS35L56_ASP_RX2_EN_SHIFT, 0),
 217         SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS35L56_ASP1_ENABLES1,
 218                              CS35L56_ASP_TX1_EN_SHIFT, 0),
 219         SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS35L56_ASP1_ENABLES1,
 220                              CS35L56_ASP_TX2_EN_SHIFT, 0),
 221         SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS35L56_ASP1_ENABLES1,
 222                              CS35L56_ASP_TX3_EN_SHIFT, 0),
 223         SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS35L56_ASP1_ENABLES1,
 224                              CS35L56_ASP_TX4_EN_SHIFT, 0),
 225
 226         SND_SOC_DAPM_MUX("ASP1 TX1 Source", SND_SOC_NOPM, 0, 0, &asp1_tx1_mux),
 227         SND_SOC_DAPM_MUX("ASP1 TX2 Source", SND_SOC_NOPM, 0, 0, &asp1_tx2_mux),
 228         SND_SOC_DAPM_MUX("ASP1 TX3 Source", SND_SOC_NOPM, 0, 0, &asp1_tx3_mux),
 229         SND_SOC_DAPM_MUX("ASP1 TX4 Source", SND_SOC_NOPM, 0, 0, &asp1_tx4_mux),
 230
 231         SND_SOC_DAPM_MUX("SDW1 TX1 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx1_mux),
 232         SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux),
 233         SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux),
 234         SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux),
 235
 236         SND_SOC_DAPM_SIGGEN("VMON ADC"),
 237         SND_SOC_DAPM_SIGGEN("IMON ADC"),
 238         SND_SOC_DAPM_SIGGEN("ERRVOL ADC"),
 239         SND_SOC_DAPM_SIGGEN("CLASSH ADC"),
 240         SND_SOC_DAPM_SIGGEN("VDDBMON ADC"),
 241         SND_SOC_DAPM_SIGGEN("VBSTMON ADC"),
 242         SND_SOC_DAPM_SIGGEN("TEMPMON ADC"),
 243 };
 244
 245 #define CS35L56_SRC_ROUTE(name) \
 246         { name" Source", "ASP1RX1", "ASP1RX1" }, \
 247         { name" Source", "ASP1RX2", "ASP1RX2" }, \
 248         { name" Source", "VMON", "VMON ADC" }, \
 249         { name" Source", "IMON", "IMON ADC" }, \
 250         { name" Source", "ERRVOL", "ERRVOL ADC" },   \
 251         { name" Source", "CLASSH", "CLASSH ADC" },   \
 252         { name" Source", "VDDBMON", "VDDBMON ADC" }, \
 253         { name" Source", "VBSTMON", "VBSTMON ADC" }, \
 254         { name" Source", "DSP1TX1", "DSP1" }, \
 255         { name" Source", "DSP1TX2", "DSP1" }, \
 256         { name" Source", "DSP1TX3", "DSP1" }, \
 257         { name" Source", "DSP1TX4", "DSP1" }, \
 258         { name" Source", "DSP1TX5", "DSP1" }, \
 259         { name" Source", "DSP1TX6", "DSP1" }, \
 260         { name" Source", "DSP1TX7", "DSP1" }, \
 261         { name" Source", "DSP1TX8", "DSP1" }, \
 262         { name" Source", "TEMPMON", "TEMPMON ADC" }, \
 263         { name" Source", "INTERPOLATOR", "AMP" }, \
 264         { name" Source", "SDW1RX1", "SDW1 Playback" }, \
 265         { name" Source", "SDW1RX2", "SDW1 Playback" },
 266
 267 static const struct snd_soc_dapm_route cs35l56_audio_map[] = {
 268         { "AMP", NULL, "VDD_B" },
 269         { "AMP", NULL, "VDD_AMP" },
 270
 271         { "ASP1 Playback", NULL, "PLAY" },
 272         { "SDW1 Playback", NULL, "PLAY" },
 273
 274         { "ASP1RX1", NULL, "ASP1 Playback" },
 275         { "ASP1RX2", NULL, "ASP1 Playback" },
 276         { "DSP1", NULL, "ASP1RX1" },
 277         { "DSP1", NULL, "ASP1RX2" },
 278         { "DSP1", NULL, "SDW1 Playback" },
 279         { "AMP", NULL, "DSP1" },
 280         { "SPK", NULL, "AMP" },
 281
 282         CS35L56_SRC_ROUTE("ASP1 TX1")
 283         CS35L56_SRC_ROUTE("ASP1 TX2")
 284         CS35L56_SRC_ROUTE("ASP1 TX3")
 285         CS35L56_SRC_ROUTE("ASP1 TX4")
 286
 287         { "ASP1TX1", NULL, "ASP1 TX1 Source" },
 288         { "ASP1TX2", NULL, "ASP1 TX2 Source" },
 289         { "ASP1TX3", NULL, "ASP1 TX3 Source" },
 290         { "ASP1TX4", NULL, "ASP1 TX4 Source" },
 291         { "ASP1 Capture", NULL, "ASP1TX1" },
 292         { "ASP1 Capture", NULL, "ASP1TX2" },
 293         { "ASP1 Capture", NULL, "ASP1TX3" },
 294         { "ASP1 Capture", NULL, "ASP1TX4" },
 295
 296         CS35L56_SRC_ROUTE("SDW1 TX1")
 297         CS35L56_SRC_ROUTE("SDW1 TX2")
 298         CS35L56_SRC_ROUTE("SDW1 TX3")
 299         CS35L56_SRC_ROUTE("SDW1 TX4")
 300         { "SDW1 Capture", NULL, "SDW1 TX1 Source" },
 301         { "SDW1 Capture", NULL, "SDW1 TX2 Source" },
 302         { "SDW1 Capture", NULL, "SDW1 TX3 Source" },
 303         { "SDW1 Capture", NULL, "SDW1 TX4 Source" },
 304 };
 305
 306 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w,
 307                              struct snd_kcontrol *kcontrol, int event)
 308 {
 309         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 310         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
 311
 312         dev_dbg(cs35l56->dev, "%s: %d\n", __func__, event);
 313
 314         return wm_adsp_event(w, kcontrol, event);
 315 }
 316
 317 irqreturn_t cs35l56_irq(int irq, void *data)
 318 {
 319         struct cs35l56_private *cs35l56 = data;
 320         unsigned int status1 = 0, status8 = 0, status20 = 0;
 321         unsigned int mask1, mask8, mask20;
 322         unsigned int val;
 323         int rv;
 324
 325         irqreturn_t ret = IRQ_NONE;
 326
 327         if (!cs35l56->init_done)
 328                 return IRQ_NONE;
 329
 330         mutex_lock(&cs35l56->irq_lock);
 331
 332         rv = pm_runtime_resume_and_get(cs35l56->dev);
 333         if (rv < 0) {
 334                 dev_err(cs35l56->dev, "irq: failed to get pm_runtime: %d\n", rv);
 335                 goto err_unlock;
 336         }
 337
 338         regmap_read(cs35l56->regmap, CS35L56_IRQ1_STATUS, &val);
 339         if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
 340                 dev_dbg(cs35l56->dev, "Spurious IRQ: no pending interrupt\n");
 341                 goto err;
 342         }
 343
 344         /* Ack interrupts */
 345         regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_1, &status1);
 346         regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_1, &mask1);
 347         status1 &= ~mask1;
 348         regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_1, status1);
 349
 350         regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_8, &status8);
 351         regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_8, &mask8);
 352         status8 &= ~mask8;
 353         regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_8, status8);
 354
 355         regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_20, &status20);
 356         regmap_read(cs35l56->regmap, CS35L56_IRQ1_MASK_20, &mask20);
 357         status20 &= ~mask20;
 358         /* We don't want EINT20 but they default to unmasked: force mask */
 359         regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
 360
 361         dev_dbg(cs35l56->dev, "%s: %#x %#x\n", __func__, status1, status8);
 362
 363         /* Check to see if unmasked bits are active */
 364         if (!status1 && !status8 && !status20)
 365                 goto err;
 366
 367         if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
 368                 dev_crit(cs35l56->dev, "Amp short error\n");
 369
 370         if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
 371                 dev_crit(cs35l56->dev, "Overtemp error\n");
 372
 373         ret = IRQ_HANDLED;
 374
 375 err:
 376         pm_runtime_put(cs35l56->dev);
 377 err_unlock:
 378         mutex_unlock(&cs35l56->irq_lock);
 379
 380         return ret;
 381 }
 382 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_CORE);
 383
 384 int cs35l56_irq_request(struct cs35l56_private *cs35l56, int irq)
 385 {
 386         int ret;
 387
 388         if (!irq)
 389                 return 0;
 390
 391         ret = devm_request_threaded_irq(cs35l56->dev, irq, NULL, cs35l56_irq,
 392                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
 393                                         "cs35l56", cs35l56);
 394         if (!ret)
 395                 cs35l56->irq = irq;
 396         else
 397                 dev_err(cs35l56->dev, "Failed to get IRQ: %d\n", ret);
 398
 399         return ret;
 400 }
 401 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_CORE);
 402
 403 static int cs35l56_asp_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 404 {
 405         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component);
 406         unsigned int val;
 407
 408         dev_dbg(cs35l56->dev, "%s: %#x\n", __func__, fmt);
 409
 410         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 411         case SND_SOC_DAIFMT_CBC_CFC:
 412                 break;
 413         default:
 414                 dev_err(cs35l56->dev, "Unsupported clock source mode\n");
 415                 return -EINVAL;
 416         }
 417
 418         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 419         case SND_SOC_DAIFMT_DSP_A:
 420                 val = CS35L56_ASP_FMT_DSP_A << CS35L56_ASP_FMT_SHIFT;
 421                 cs35l56->tdm_mode = true;
 422                 break;
 423         case SND_SOC_DAIFMT_I2S:
 424                 val = CS35L56_ASP_FMT_I2S << CS35L56_ASP_FMT_SHIFT;
 425                 cs35l56->tdm_mode = false;
 426                 break;
 427         default:
 428                 dev_err(cs35l56->dev, "Unsupported DAI format\n");
 429                 return -EINVAL;
 430         }
 431
 432         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 433         case SND_SOC_DAIFMT_NB_IF:
 434                 val |= CS35L56_ASP_FSYNC_INV_MASK;
 435                 break;
 436         case SND_SOC_DAIFMT_IB_NF:
 437                 val |= CS35L56_ASP_BCLK_INV_MASK;
 438                 break;
 439         case SND_SOC_DAIFMT_IB_IF:
 440                 val |= CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK;
 441                 break;
 442         case SND_SOC_DAIFMT_NB_NF:
 443                 break;
 444         default:
 445                 dev_err(cs35l56->dev, "Invalid clock invert\n");
 446                 return -EINVAL;
 447         }
 448
 449         regmap_update_bits(cs35l56->regmap,
 450                            CS35L56_ASP1_CONTROL2,
 451                            CS35L56_ASP_FMT_MASK |
 452                            CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK,
 453                            val);
 454
 455         /* Hi-Z DOUT in unused slots and when all TX are disabled */
 456         regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL3,
 457                            CS35L56_ASP1_DOUT_HIZ_CTRL_MASK,
 458                            CS35L56_ASP_UNUSED_HIZ_OFF_HIZ);
 459
 460         return 0;
 461 }
 462
 463 static void cs35l56_set_asp_slot_positions(struct cs35l56_private *cs35l56,
 464                                            unsigned int reg, unsigned long mask)
 465 {
 466         unsigned int reg_val, channel_shift;
 467         int bit_num;
 468
 469         /* Init all slots to 63 */
 470         switch (reg) {
 471         case CS35L56_ASP1_FRAME_CONTROL1:
 472                 reg_val = 0x3f3f3f3f;
 473                 break;
 474         case CS35L56_ASP1_FRAME_CONTROL5:
 475                 reg_val = 0x3f3f3f;
 476                 break;
 477         }
 478
 479         /* Enable consecutive TX1..TXn for each of the slots set in mask */
 480         channel_shift = 0;
 481         for_each_set_bit(bit_num, &mask, 32) {
 482                 reg_val &= ~(0x3f << channel_shift);
 483                 reg_val |= bit_num << channel_shift;
 484                 channel_shift += 8;
 485         }
 486
 487         regmap_write(cs35l56->regmap, reg, reg_val);
 488 }
 489
 490 static int cs35l56_asp_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 491                                         unsigned int rx_mask, int slots, int slot_width)
 492 {
 493         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
 494
 495         if ((slots == 0) || (slot_width == 0)) {
 496                 dev_dbg(cs35l56->dev, "tdm config cleared\n");
 497                 cs35l56->asp_slot_width = 0;
 498                 cs35l56->asp_slot_count = 0;
 499                 return 0;
 500         }
 501
 502         if (slot_width > (CS35L56_ASP_RX_WIDTH_MASK >> CS35L56_ASP_RX_WIDTH_SHIFT)) {
 503                 dev_err(cs35l56->dev, "tdm invalid slot width %d\n", slot_width);
 504                 return -EINVAL;
 505         }
 506
 507         /* More than 32 slots would give an unsupportable BCLK frequency */
 508         if (slots > 32) {
 509                 dev_err(cs35l56->dev, "tdm invalid slot count %d\n", slots);
 510                 return -EINVAL;
 511         }
 512
 513         cs35l56->asp_slot_width = (u8)slot_width;
 514         cs35l56->asp_slot_count = (u8)slots;
 515
 516         // Note: rx/tx is from point of view of the CPU end
 517         if (tx_mask == 0)
 518                 tx_mask = 0x3;  // ASPRX1/RX2 in slots 0 and 1
 519
 520         if (rx_mask == 0)
 521                 rx_mask = 0xf;  // ASPTX1..TX4 in slots 0..3
 522
 523         cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL1, rx_mask);
 524         cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL5, tx_mask);
 525
 526         dev_dbg(cs35l56->dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n",
 527                 cs35l56->asp_slot_width, cs35l56->asp_slot_count, tx_mask, rx_mask);
 528
 529         return 0;
 530 }
 531
 532 static int cs35l56_asp_dai_hw_params(struct snd_pcm_substream *substream,
 533                                      struct snd_pcm_hw_params *params,
 534                                      struct snd_soc_dai *dai)
 535 {
 536         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
 537         unsigned int rate = params_rate(params);
 538         u8 asp_width, asp_wl;
 539
 540         asp_wl = params_width(params);
 541         if (cs35l56->asp_slot_width)
 542                 asp_width = cs35l56->asp_slot_width;
 543         else
 544                 asp_width = asp_wl;
 545
 546         dev_dbg(cs35l56->dev, "%s: wl=%d, width=%d, rate=%d", __func__, asp_wl, asp_width, rate);
 547
 548         if (!cs35l56->sysclk_set) {
 549                 unsigned int slots = cs35l56->asp_slot_count;
 550                 unsigned int bclk_freq;
 551                 int freq_id;
 552
 553                 if (slots == 0) {
 554                         slots = params_channels(params);
 555
 556                         /* I2S always has an even number of slots */
 557                         if (!cs35l56->tdm_mode)
 558                                 slots = round_up(slots, 2);
 559                 }
 560
 561                 bclk_freq = asp_width * slots * rate;
 562                 freq_id = cs35l56_get_bclk_freq_id(bclk_freq);
 563                 if (freq_id < 0) {
 564                         dev_err(cs35l56->dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq);
 565                         return -EINVAL;
 566                 }
 567
 568                 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL1,
 569                                    CS35L56_ASP_BCLK_FREQ_MASK,
 570                                    freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT);
 571         }
 572
 573         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 574                 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL2,
 575                                    CS35L56_ASP_RX_WIDTH_MASK, asp_width <<
 576                                    CS35L56_ASP_RX_WIDTH_SHIFT);
 577                 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_DATA_CONTROL5,
 578                                    CS35L56_ASP_RX_WL_MASK, asp_wl);
 579         } else {
 580                 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL2,
 581                                    CS35L56_ASP_TX_WIDTH_MASK, asp_width <<
 582                                    CS35L56_ASP_TX_WIDTH_SHIFT);
 583                 regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_DATA_CONTROL1,
 584                                    CS35L56_ASP_TX_WL_MASK, asp_wl);
 585         }
 586
 587         return 0;
 588 }
 589
 590 static int cs35l56_asp_dai_set_sysclk(struct snd_soc_dai *dai,
 591                                       int clk_id, unsigned int freq, int dir)
 592 {
 593         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
 594         int freq_id;
 595
 596         if (freq == 0) {
 597                 cs35l56->sysclk_set = false;
 598                 return 0;
 599         }
 600
 601         freq_id = cs35l56_get_bclk_freq_id(freq);
 602         if (freq_id < 0)
 603                 return freq_id;
 604
 605         regmap_update_bits(cs35l56->regmap, CS35L56_ASP1_CONTROL1,
 606                            CS35L56_ASP_BCLK_FREQ_MASK,
 607                            freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT);
 608         cs35l56->sysclk_set = true;
 609
 610         return 0;
 611 }
 612
 613 static const struct snd_soc_dai_ops cs35l56_ops = {
 614         .set_fmt = cs35l56_asp_dai_set_fmt,
 615         .set_tdm_slot = cs35l56_asp_dai_set_tdm_slot,
 616         .hw_params = cs35l56_asp_dai_hw_params,
 617         .set_sysclk = cs35l56_asp_dai_set_sysclk,
 618 };
 619
 620 static void cs35l56_sdw_dai_shutdown(struct snd_pcm_substream *substream,
 621                                      struct snd_soc_dai *dai)
 622 {
 623         snd_soc_dai_set_dma_data(dai, substream, NULL);
 624 }
 625
 626 static int cs35l56_sdw_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 627                                         unsigned int rx_mask, int slots, int slot_width)
 628 {
 629         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
 630
 631         /* rx/tx are from point of view of the CPU end so opposite to our rx/tx */
 632         cs35l56->rx_mask = tx_mask;
 633         cs35l56->tx_mask = rx_mask;
 634
 635         return 0;
 636 }
 637
 638 static int cs35l56_sdw_dai_hw_params(struct snd_pcm_substream *substream,
 639                                      struct snd_pcm_hw_params *params,
 640                                      struct snd_soc_dai *dai)
 641 {
 642         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
 643         struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
 644         struct sdw_stream_config sconfig;
 645         struct sdw_port_config pconfig;
 646         int ret;
 647
 648         dev_dbg(cs35l56->dev, "%s: rate %d\n", __func__, params_rate(params));
 649
 650         if (!cs35l56->init_done)
 651                 return -ENODEV;
 652
 653         if (!sdw_stream)
 654                 return -EINVAL;
 655
 656         memset(&sconfig, 0, sizeof(sconfig));
 657         memset(&pconfig, 0, sizeof(pconfig));
 658
 659         sconfig.frame_rate = params_rate(params);
 660         sconfig.bps = snd_pcm_format_width(params_format(params));
 661
 662         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 663                 sconfig.direction = SDW_DATA_DIR_RX;
 664                 pconfig.num = CS35L56_SDW1_PLAYBACK_PORT;
 665                 pconfig.ch_mask = cs35l56->rx_mask;
 666         } else {
 667                 sconfig.direction = SDW_DATA_DIR_TX;
 668                 pconfig.num = CS35L56_SDW1_CAPTURE_PORT;
 669                 pconfig.ch_mask = cs35l56->tx_mask;
 670         }
 671
 672         if (pconfig.ch_mask == 0) {
 673                 sconfig.ch_count = params_channels(params);
 674                 pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0);
 675         } else {
 676                 sconfig.ch_count = hweight32(pconfig.ch_mask);
 677         }
 678
 679         ret = sdw_stream_add_slave(cs35l56->sdw_peripheral, &sconfig, &pconfig,
 680                                    1, sdw_stream);
 681         if (ret) {
 682                 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
 683                 return ret;
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream,
 690                                    struct snd_soc_dai *dai)
 691 {
 692         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);
 693         struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
 694
 695         if (!cs35l56->sdw_peripheral)
 696                 return -EINVAL;
 697
 698         sdw_stream_remove_slave(cs35l56->sdw_peripheral, sdw_stream);
 699
 700         return 0;
 701 }
 702
 703 static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai,
 704                                       void *sdw_stream, int direction)
 705 {
 706         snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
 707
 708         return 0;
 709 }
 710
 711 static const struct snd_soc_dai_ops cs35l56_sdw_dai_ops = {
 712         .set_tdm_slot = cs35l56_sdw_dai_set_tdm_slot,
 713         .shutdown = cs35l56_sdw_dai_shutdown,
 714         .hw_params = cs35l56_sdw_dai_hw_params,
 715         .hw_free = cs35l56_sdw_dai_hw_free,
 716         .set_stream = cs35l56_sdw_dai_set_stream,
 717 };
 718
 719 static struct snd_soc_dai_driver cs35l56_dai[] = {
 720         {
 721                 .name = "cs35l56-asp1",
 722                 .id = 0,
 723                 .playback = {
 724                         .stream_name = "ASP1 Playback",
 725                         .channels_min = 1,
 726                         .channels_max = 2,
 727                         .rates = CS35L56_RATES,
 728                         .formats = CS35L56_RX_FORMATS,
 729                 },
 730                 .capture = {
 731                         .stream_name = "ASP1 Capture",
 732                         .channels_min = 1,
 733                         .channels_max = 4,
 734                         .rates = CS35L56_RATES,
 735                         .formats = CS35L56_TX_FORMATS,
 736                 },
 737                 .ops = &cs35l56_ops,
 738                 .symmetric_rate = 1,
 739                 .symmetric_sample_bits = 1,
 740         },
 741         {
 742                 .name = "cs35l56-sdw1",
 743                 .id = 1,
 744                 .playback = {
 745                         .stream_name = "SDW1 Playback",
 746                         .channels_min = 1,
 747                         .channels_max = 2,
 748                         .rates = CS35L56_RATES,
 749                         .formats = CS35L56_RX_FORMATS,
 750                 },
 751                 .capture = {
 752                         .stream_name = "SDW1 Capture",
 753                         .channels_min = 1,
 754                         .channels_max = 4,
 755                         .rates = CS35L56_RATES,
 756                         .formats = CS35L56_TX_FORMATS,
 757                 },
 758                 .symmetric_rate = 1,
 759                 .ops = &cs35l56_sdw_dai_ops,
 760         }
 761 };
 762
 763 static int cs35l56_wait_for_firmware_boot(struct cs35l56_private *cs35l56)
 764 {
 765         unsigned int reg;
 766         unsigned int val;
 767         int ret;
 768
 769         if (cs35l56->rev < CS35L56_REVID_B0)
 770                 reg = CS35L56_DSP1_HALO_STATE_A1;
 771         else
 772                 reg = CS35L56_DSP1_HALO_STATE;
 773
 774         ret = regmap_read_poll_timeout(cs35l56->regmap, reg,
 775                                        val,
 776                                        (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
 777                                        CS35L56_HALO_STATE_POLL_US,
 778                                        CS35L56_HALO_STATE_TIMEOUT_US);
 779
 780         if ((ret < 0) && (ret != -ETIMEDOUT)) {
 781                 dev_err(cs35l56->dev, "Failed to read HALO_STATE: %d\n", ret);
 782                 return ret;
 783         }
 784
 785         if ((ret == -ETIMEDOUT) || (val != CS35L56_HALO_STATE_BOOT_DONE)) {
 786                 dev_err(cs35l56->dev, "Firmware boot fail: HALO_STATE=%#x\n", val);
 787                 return -EIO;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static inline void cs35l56_wait_min_reset_pulse(void)
 794 {
 795         /* Satisfy minimum reset pulse width spec */
 796         usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
 797 }
 798
 799 static const struct reg_sequence cs35l56_system_reset_seq[] = {
 800         REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
 801 };
 802
 803 static void cs35l56_system_reset(struct cs35l56_private *cs35l56)
 804 {
 805         cs35l56->soft_resetting = true;
 806
 807         /*
 808          * Must enter cache-only first so there can't be any more register
 809          * accesses other than the controlled system reset sequence below.
 810          */
 811         regcache_cache_only(cs35l56->regmap, true);
 812         regmap_multi_reg_write_bypassed(cs35l56->regmap,
 813                                         cs35l56_system_reset_seq,
 814                                         ARRAY_SIZE(cs35l56_system_reset_seq));
 815
 816         /* On SoundWire the registers won't be accessible until it re-enumerates. */
 817         if (cs35l56->sdw_peripheral)
 818                 return;
 819
 820         usleep_range(CS35L56_CONTROL_PORT_READY_US, CS35L56_CONTROL_PORT_READY_US + 400);
 821         regcache_cache_only(cs35l56->regmap, false);
 822 }
 823
 824 static void cs35l56_secure_patch(struct cs35l56_private *cs35l56)
 825 {
 826         int ret;
 827
 828         /* Use wm_adsp to load and apply the firmware patch and coefficient files */
 829         ret = wm_adsp_power_up(&cs35l56->dsp);
 830         if (ret)
 831                 dev_dbg(cs35l56->dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret);
 832         else
 833                 cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_AUDIO_REINIT);
 834 }
 835
 836 static void cs35l56_patch(struct cs35l56_private *cs35l56)
 837 {
 838         unsigned int reg;
 839         unsigned int val;
 840         int ret;
 841
 842         /*
 843          * Disable SoundWire interrupts to prevent race with IRQ work.
 844          * Setting sdw_irq_no_unmask prevents the handler re-enabling
 845          * the SoundWire interrupt.
 846          */
 847         if (cs35l56->sdw_peripheral) {
 848                 cs35l56->sdw_irq_no_unmask = true;
 849                 flush_work(&cs35l56->sdw_irq_work);
 850                 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
 851                 sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1);
 852                 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
 853                 flush_work(&cs35l56->sdw_irq_work);
 854         }
 855
 856         ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_SHUTDOWN);
 857         if (ret)
 858                 goto err;
 859
 860         if (cs35l56->rev < CS35L56_REVID_B0)
 861                 reg = CS35L56_DSP1_PM_CUR_STATE_A1;
 862         else
 863                 reg = CS35L56_DSP1_PM_CUR_STATE;
 864
 865         ret = regmap_read_poll_timeout(cs35l56->regmap, reg,
 866                                        val, (val == CS35L56_HALO_STATE_SHUTDOWN),
 867                                        CS35L56_HALO_STATE_POLL_US,
 868                                        CS35L56_HALO_STATE_TIMEOUT_US);
 869         if (ret < 0)
 870                 dev_err(cs35l56->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
 871                         val, ret);
 872
 873         /* Use wm_adsp to load and apply the firmware patch and coefficient files */
 874         ret = wm_adsp_power_up(&cs35l56->dsp);
 875         if (ret) {
 876                 dev_dbg(cs35l56->dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret);
 877                 goto err;
 878         }
 879
 880         mutex_lock(&cs35l56->irq_lock);
 881
 882         init_completion(&cs35l56->init_completion);
 883
 884         cs35l56_system_reset(cs35l56);
 885
 886         if (cs35l56->sdw_peripheral) {
 887                 /*
 888                  * The system-reset causes the CS35L56 to detach from the bus.
 889                  * Wait for the manager to re-enumerate the CS35L56 and
 890                  * cs35l56_init() to run again.
 891                  */
 892                 if (!wait_for_completion_timeout(&cs35l56->init_completion,
 893                                                  msecs_to_jiffies(5000))) {
 894                         dev_err(cs35l56->dev, "%s: init_completion timed out (SDW)\n", __func__);
 895                         goto err_unlock;
 896                 }
 897         } else if (cs35l56_init(cs35l56)) {
 898                 goto err_unlock;
 899         }
 900
 901         regmap_clear_bits(cs35l56->regmap, CS35L56_PROTECTION_STATUS, CS35L56_FIRMWARE_MISSING);
 902         cs35l56->fw_patched = true;
 903
 904 err_unlock:
 905         mutex_unlock(&cs35l56->irq_lock);
 906 err:
 907         /* Re-enable SoundWire interrupts */
 908         if (cs35l56->sdw_peripheral) {
 909                 cs35l56->sdw_irq_no_unmask = false;
 910                 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1,
 911                                 CS35L56_SDW_INT_MASK_CODEC_IRQ);
 912         }
 913 }
 914
 915 static void cs35l56_dsp_work(struct work_struct *work)
 916 {
 917         struct cs35l56_private *cs35l56 = container_of(work,
 918                                                        struct cs35l56_private,
 919                                                        dsp_work);
 920
 921         if (!cs35l56->init_done)
 922                 return;
 923
 924         pm_runtime_get_sync(cs35l56->dev);
 925
 926         /*
 927          * When the device is running in secure mode the firmware files can
 928          * only contain insecure tunings and therefore we do not need to
 929          * shutdown the firmware to apply them and can use the lower cost
 930          * reinit sequence instead.
 931          */
 932         if (cs35l56->secured)
 933                 cs35l56_secure_patch(cs35l56);
 934         else
 935                 cs35l56_patch(cs35l56);
 936
 937         pm_runtime_mark_last_busy(cs35l56->dev);
 938         pm_runtime_put_autosuspend(cs35l56->dev);
 939 }
 940
 941 static int cs35l56_component_probe(struct snd_soc_component *component)
 942 {
 943         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
 944         struct dentry *debugfs_root = component->debugfs_root;
 945
 946         BUILD_BUG_ON(ARRAY_SIZE(cs35l56_tx_input_texts) != ARRAY_SIZE(cs35l56_tx_input_values));
 947
 948         if (!wait_for_completion_timeout(&cs35l56->init_completion,
 949                                          msecs_to_jiffies(5000))) {
 950                 dev_err(cs35l56->dev, "%s: init_completion timed out\n", __func__);
 951                 return -ENODEV;
 952         }
 953
 954         cs35l56->component = component;
 955         wm_adsp2_component_probe(&cs35l56->dsp, component);
 956
 957         debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->init_done);
 958         debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->can_hibernate);
 959         debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->fw_patched);
 960
 961         queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work);
 962
 963         return 0;
 964 }
 965
 966 static void cs35l56_component_remove(struct snd_soc_component *component)
 967 {
 968         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
 969
 970         cancel_work_sync(&cs35l56->dsp_work);
 971 }
 972
 973 static int cs35l56_set_bias_level(struct snd_soc_component *component,
 974                                   enum snd_soc_bias_level level)
 975 {
 976         struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);
 977
 978         switch (level) {
 979         case SND_SOC_BIAS_STANDBY:
 980                 /*
 981                  * Wait for patching to complete when transitioning from
 982                  * BIAS_OFF to BIAS_STANDBY
 983                  */
 984                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
 985                         cs35l56_wait_dsp_ready(cs35l56);
 986
 987                 break;
 988         default:
 989                 break;
 990         }
 991
 992         return 0;
 993 }
 994
 995 static const struct snd_soc_component_driver soc_component_dev_cs35l56 = {
 996         .probe = cs35l56_component_probe,
 997         .remove = cs35l56_component_remove,
 998
 999         .dapm_widgets = cs35l56_dapm_widgets,
1000         .num_dapm_widgets = ARRAY_SIZE(cs35l56_dapm_widgets),
1001         .dapm_routes = cs35l56_audio_map,
1002         .num_dapm_routes = ARRAY_SIZE(cs35l56_audio_map),
1003         .controls = cs35l56_controls,
1004         .num_controls = ARRAY_SIZE(cs35l56_controls),
1005
1006         .set_bias_level = cs35l56_set_bias_level,
1007
1008         .suspend_bias_off = 1, /* see cs35l56_system_resume() */
1009 };
1010
1011 static const struct reg_sequence cs35l56_hibernate_seq[] = {
1012         /* This must be the last register access */
1013         REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW),
1014 };
1015
1016 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
1017         REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
1018 };
1019
1020 int cs35l56_runtime_suspend(struct device *dev)
1021 {
1022         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1023         unsigned int val;
1024         int ret;
1025
1026         if (!cs35l56->init_done)
1027                 return 0;
1028
1029         /* Firmware must have entered a power-save state */
1030         ret = regmap_read_poll_timeout(cs35l56->regmap,
1031                                        CS35L56_TRANSDUCER_ACTUAL_PS,
1032                                        val, (val >= CS35L56_PS3),
1033                                        CS35L56_PS3_POLL_US,
1034                                        CS35L56_PS3_TIMEOUT_US);
1035         if (ret)
1036                 dev_warn(cs35l56->dev, "PS3 wait failed: %d\n", ret);
1037
1038         /* Clear BOOT_DONE so it can be used to detect a reboot */
1039         regmap_write(cs35l56->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
1040
1041         if (!cs35l56->can_hibernate) {
1042                 regcache_cache_only(cs35l56->regmap, true);
1043                 dev_dbg(dev, "Suspended: no hibernate");
1044
1045                 return 0;
1046         }
1047
1048         /*
1049          * Enable auto-hibernate. If it is woken by some other wake source
1050          * it will automatically return to hibernate.
1051          */
1052         cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE);
1053
1054         /*
1055          * Must enter cache-only first so there can't be any more register
1056          * accesses other than the controlled hibernate sequence below.
1057          */
1058         regcache_cache_only(cs35l56->regmap, true);
1059
1060         regmap_multi_reg_write_bypassed(cs35l56->regmap,
1061                                         cs35l56_hibernate_seq,
1062                                         ARRAY_SIZE(cs35l56_hibernate_seq));
1063
1064         dev_dbg(dev, "Suspended: hibernate");
1065
1066         return 0;
1067 }
1068 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend, SND_SOC_CS35L56_CORE);
1069
1070 static int __maybe_unused cs35l56_runtime_resume_i2c_spi(struct device *dev)
1071 {
1072         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1073
1074         if (!cs35l56->init_done)
1075                 return 0;
1076
1077         return cs35l56_runtime_resume_common(cs35l56);
1078 }
1079
1080 int cs35l56_runtime_resume_common(struct cs35l56_private *cs35l56)
1081 {
1082         unsigned int val;
1083         int ret;
1084
1085         if (!cs35l56->can_hibernate)
1086                 goto out_sync;
1087
1088         if (!cs35l56->sdw_peripheral) {
1089                 /*
1090                  * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C.
1091                  * Must be done before releasing cache-only.
1092                  */
1093                 regmap_multi_reg_write_bypassed(cs35l56->regmap,
1094                                                 cs35l56_hibernate_wake_seq,
1095                                                 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
1096
1097                 usleep_range(CS35L56_CONTROL_PORT_READY_US,
1098                              CS35L56_CONTROL_PORT_READY_US + 400);
1099         }
1100
1101 out_sync:
1102         regcache_cache_only(cs35l56->regmap, false);
1103
1104         ret = cs35l56_wait_for_firmware_boot(cs35l56);
1105         if (ret) {
1106                 dev_err(cs35l56->dev, "Hibernate wake failed: %d\n", ret);
1107                 goto err;
1108         }
1109
1110         ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
1111         if (ret)
1112                 goto err;
1113
1114         /* BOOT_DONE will be 1 if the amp reset */
1115         regmap_read(cs35l56->regmap, CS35L56_IRQ1_EINT_4, &val);
1116         if (val & CS35L56_OTP_BOOT_DONE_MASK) {
1117                 dev_dbg(cs35l56->dev, "Registers reset in suspend\n");
1118                 regcache_mark_dirty(cs35l56->regmap);
1119         }
1120
1121         regcache_sync(cs35l56->regmap);
1122
1123         dev_dbg(cs35l56->dev, "Resumed");
1124
1125         return 0;
1126
1127 err:
1128         regmap_write(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
1129                      CS35L56_MBOX_CMD_HIBERNATE_NOW);
1130
1131         regcache_cache_only(cs35l56->regmap, true);
1132
1133         return ret;
1134 }
1135 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_CORE);
1136
1137 static int cs35l56_is_fw_reload_needed(struct cs35l56_private *cs35l56)
1138 {
1139         unsigned int val;
1140         int ret;
1141
1142         /* Nothing to re-patch if we haven't done any patching yet. */
1143         if (!cs35l56->fw_patched)
1144                 return false;
1145
1146         /*
1147          * If we have control of RESET we will have asserted it so the firmware
1148          * will need re-patching.
1149          */
1150         if (cs35l56->reset_gpio)
1151                 return true;
1152
1153         /*
1154          * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
1155          * can't be used here to test for memory retention.
1156          * Assume that tuning must be re-loaded.
1157          */
1158         if (cs35l56->secured)
1159                 return true;
1160
1161         ret = pm_runtime_resume_and_get(cs35l56->dev);
1162         if (ret) {
1163                 dev_err(cs35l56->dev, "Failed to runtime_get: %d\n", ret);
1164                 return ret;
1165         }
1166
1167         ret = regmap_read(cs35l56->regmap, CS35L56_PROTECTION_STATUS, &val);
1168         if (ret)
1169                 dev_err(cs35l56->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
1170         else
1171                 ret = !!(val & CS35L56_FIRMWARE_MISSING);
1172
1173         pm_runtime_put_autosuspend(cs35l56->dev);
1174
1175         return ret;
1176 }
1177
1178 int cs35l56_system_suspend(struct device *dev)
1179 {
1180         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1181
1182         dev_dbg(dev, "system_suspend\n");
1183
1184         if (cs35l56->component)
1185                 flush_work(&cs35l56->dsp_work);
1186
1187         /*
1188          * The interrupt line is normally shared, but after we start suspending
1189          * we can't check if our device is the source of an interrupt, and can't
1190          * clear it. Prevent this race by temporarily disabling the parent irq
1191          * until we reach _no_irq.
1192          */
1193         if (cs35l56->irq)
1194                 disable_irq(cs35l56->irq);
1195
1196         return pm_runtime_force_suspend(dev);
1197 }
1198 EXPORT_SYMBOL_GPL(cs35l56_system_suspend);
1199
1200 int cs35l56_system_suspend_late(struct device *dev)
1201 {
1202         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1203
1204         dev_dbg(dev, "system_suspend_late\n");
1205
1206         /*
1207          * Assert RESET before removing supplies.
1208          * RESET is usually shared by all amps so it must not be asserted until
1209          * all driver instances have done their suspend() stage.
1210          */
1211         if (cs35l56->reset_gpio) {
1212                 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0);
1213                 cs35l56_wait_min_reset_pulse();
1214         }
1215
1216         regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
1217
1218         return 0;
1219 }
1220 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_late);
1221
1222 int cs35l56_system_suspend_no_irq(struct device *dev)
1223 {
1224         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1225
1226         dev_dbg(dev, "system_suspend_no_irq\n");
1227
1228         /* Handlers are now disabled so the parent IRQ can safely be re-enabled. */
1229         if (cs35l56->irq)
1230                 enable_irq(cs35l56->irq);
1231
1232         return 0;
1233 }
1234 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_no_irq);
1235
1236 int cs35l56_system_resume_no_irq(struct device *dev)
1237 {
1238         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1239
1240         dev_dbg(dev, "system_resume_no_irq\n");
1241
1242         /*
1243          * WAKE interrupts unmask if the CS35L56 hibernates, which can cause
1244          * spurious interrupts, and the interrupt line is normally shared.
1245          * We can't check if our device is the source of an interrupt, and can't
1246          * clear it, until it has fully resumed. Prevent this race by temporarily
1247          * disabling the parent irq until we complete resume().
1248          */
1249         if (cs35l56->irq)
1250                 disable_irq(cs35l56->irq);
1251
1252         return 0;
1253 }
1254 EXPORT_SYMBOL_GPL(cs35l56_system_resume_no_irq);
1255
1256 int cs35l56_system_resume_early(struct device *dev)
1257 {
1258         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1259         int ret;
1260
1261         dev_dbg(dev, "system_resume_early\n");
1262
1263         /* Ensure a spec-compliant RESET pulse. */
1264         if (cs35l56->reset_gpio) {
1265                 gpiod_set_value_cansleep(cs35l56->reset_gpio, 0);
1266                 cs35l56_wait_min_reset_pulse();
1267         }
1268
1269         /* Enable supplies before releasing RESET. */
1270         ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
1271         if (ret) {
1272                 dev_err(dev, "system_resume_early failed to enable supplies: %d\n", ret);
1273                 return ret;
1274         }
1275
1276         /* Release shared RESET before drivers start resume(). */
1277         gpiod_set_value_cansleep(cs35l56->reset_gpio, 1);
1278
1279         return 0;
1280 }
1281 EXPORT_SYMBOL_GPL(cs35l56_system_resume_early);
1282
1283 int cs35l56_system_resume(struct device *dev)
1284 {
1285         struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
1286         int ret;
1287
1288         dev_dbg(dev, "system_resume\n");
1289
1290         /* Undo pm_runtime_force_suspend() before re-enabling the irq */
1291         ret = pm_runtime_force_resume(dev);
1292         if (cs35l56->irq)
1293                 enable_irq(cs35l56->irq);
1294
1295         if (ret)
1296                 return ret;
1297
1298         /* Firmware won't have been loaded if the component hasn't probed */
1299         if (!cs35l56->component)
1300                 return 0;
1301
1302         ret = cs35l56_is_fw_reload_needed(cs35l56);
1303         dev_dbg(cs35l56->dev, "fw_reload_needed: %d\n", ret);
1304         if (ret < 1)
1305                 return ret;
1306
1307         cs35l56->fw_patched = false;
1308         queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work);
1309
1310         /*
1311          * suspend_bias_off ensures we are now in BIAS_OFF so there will be
1312          * a BIAS_OFF->BIAS_STANDBY transition to complete dsp patching.
1313          */
1314
1315         return 0;
1316 }
1317 EXPORT_SYMBOL_GPL(cs35l56_system_resume);
1318
1319 static int cs35l56_dsp_init(struct cs35l56_private *cs35l56)
1320 {
1321         struct wm_adsp *dsp;
1322         int ret;
1323
1324         cs35l56->dsp_wq = create_singlethread_workqueue("cs35l56-dsp");
1325         if (!cs35l56->dsp_wq)
1326                 return -ENOMEM;
1327
1328         INIT_WORK(&cs35l56->dsp_work, cs35l56_dsp_work);
1329
1330         dsp = &cs35l56->dsp;
1331         dsp->part = "cs35l56";
1332         dsp->cs_dsp.num = 1;
1333         dsp->cs_dsp.type = WMFW_HALO;
1334         dsp->cs_dsp.rev = 0;
1335         dsp->fw = 12;
1336         dsp->cs_dsp.dev = cs35l56->dev;
1337         dsp->cs_dsp.regmap = cs35l56->regmap;
1338         dsp->cs_dsp.base = CS35L56_DSP1_CORE_BASE;
1339         dsp->cs_dsp.base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
1340         dsp->cs_dsp.mem = cs35l56_dsp1_regions;
1341         dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
1342         dsp->cs_dsp.no_core_startstop = true;
1343         dsp->wmfw_optional = true;
1344
1345         dev_dbg(cs35l56->dev, "DSP system name: '%s'\n", dsp->system_name);
1346
1347         ret = wm_halo_init(dsp);
1348         if (ret != 0) {
1349                 dev_err(cs35l56->dev, "wm_halo_init failed\n");
1350                 return ret;
1351         }
1352
1353         return 0;
1354 }
1355
1356 static int cs35l56_get_firmware_uid(struct cs35l56_private *cs35l56)
1357 {
1358         struct device *dev = cs35l56->dev;
1359         const char *prop;
1360         int ret;
1361
1362         ret = device_property_read_string(dev, "cirrus,firmware-uid", &prop);
1363         /* If bad sw node property, return 0 and fallback to legacy firmware path */
1364         if (ret < 0)
1365                 return 0;
1366
1367         cs35l56->dsp.system_name = devm_kstrdup(dev, prop, GFP_KERNEL);
1368         if (cs35l56->dsp.system_name == NULL)
1369                 return -ENOMEM;
1370
1371         dev_dbg(dev, "Firmware UID: %s\n", cs35l56->dsp.system_name);
1372
1373         return 0;
1374 }
1375
1376 int cs35l56_common_probe(struct cs35l56_private *cs35l56)
1377 {
1378         int ret;
1379
1380         init_completion(&cs35l56->init_completion);
1381         mutex_init(&cs35l56->irq_lock);
1382
1383         dev_set_drvdata(cs35l56->dev, cs35l56);
1384
1385         cs35l56_fill_supply_names(cs35l56->supplies);
1386         ret = devm_regulator_bulk_get(cs35l56->dev, ARRAY_SIZE(cs35l56->supplies),
1387                                       cs35l56->supplies);
1388         if (ret != 0)
1389                 return dev_err_probe(cs35l56->dev, ret, "Failed to request supplies\n");
1390
1391         /* Reset could be controlled by the BIOS or shared by multiple amps */
1392         cs35l56->reset_gpio = devm_gpiod_get_optional(cs35l56->dev, "reset", GPIOD_OUT_LOW);
1393         if (IS_ERR(cs35l56->reset_gpio)) {
1394                 ret = PTR_ERR(cs35l56->reset_gpio);
1395                 /*
1396                  * If RESET is shared the first amp to probe will grab the reset
1397                  * line and reset all the amps
1398                  */
1399                 if (ret != -EBUSY)
1400                         return dev_err_probe(cs35l56->dev, ret, "Failed to get reset GPIO\n");
1401
1402                 dev_info(cs35l56->dev, "Reset GPIO busy, assume shared reset\n");
1403                 cs35l56->reset_gpio = NULL;
1404         }
1405
1406         ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
1407         if (ret != 0)
1408                 return dev_err_probe(cs35l56->dev, ret, "Failed to enable supplies\n");
1409
1410         if (cs35l56->reset_gpio) {
1411                 cs35l56_wait_min_reset_pulse();
1412                 gpiod_set_value_cansleep(cs35l56->reset_gpio, 1);
1413         }
1414
1415         ret = cs35l56_get_firmware_uid(cs35l56);
1416         if (ret != 0)
1417                 goto err;
1418
1419         ret = cs35l56_dsp_init(cs35l56);
1420         if (ret < 0) {
1421                 dev_err_probe(cs35l56->dev, ret, "DSP init failed\n");
1422                 goto err;
1423         }
1424
1425         ret = devm_snd_soc_register_component(cs35l56->dev,
1426                                               &soc_component_dev_cs35l56,
1427                                               cs35l56_dai, ARRAY_SIZE(cs35l56_dai));
1428         if (ret < 0) {
1429                 dev_err_probe(cs35l56->dev, ret, "Register codec failed\n");
1430                 goto err;
1431         }
1432
1433         return 0;
1434
1435 err:
1436         gpiod_set_value_cansleep(cs35l56->reset_gpio, 0);
1437         regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
1438
1439         return ret;
1440 }
1441 EXPORT_SYMBOL_NS_GPL(cs35l56_common_probe, SND_SOC_CS35L56_CORE);
1442
1443 int cs35l56_init(struct cs35l56_private *cs35l56)
1444 {
1445         int ret;
1446         unsigned int devid, revid, otpid, secured;
1447
1448         /*
1449          * Check whether the actions associated with soft reset or one time
1450          * init need to be performed.
1451          */
1452         if (cs35l56->soft_resetting)
1453                 goto post_soft_reset;
1454
1455         if (cs35l56->init_done)
1456                 return 0;
1457
1458         pm_runtime_set_autosuspend_delay(cs35l56->dev, 100);
1459         pm_runtime_use_autosuspend(cs35l56->dev);
1460         pm_runtime_set_active(cs35l56->dev);
1461         pm_runtime_enable(cs35l56->dev);
1462
1463         /*
1464          * If the system is not using a reset_gpio then issue a
1465          * dummy read to force a wakeup.
1466          */
1467         if (!cs35l56->reset_gpio)
1468                 regmap_read(cs35l56->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid);
1469
1470         /* Wait for control port to be ready (datasheet tIRS). */
1471         usleep_range(CS35L56_CONTROL_PORT_READY_US,
1472                      CS35L56_CONTROL_PORT_READY_US + 400);
1473
1474         /*
1475          * The HALO_STATE register is in different locations on Ax and B0
1476          * devices so the REVID needs to be determined before waiting for the
1477          * firmware to boot.
1478          */
1479         ret = regmap_read(cs35l56->regmap, CS35L56_REVID, &revid);
1480         if (ret < 0) {
1481                 dev_err(cs35l56->dev, "Get Revision ID failed\n");
1482                 return ret;
1483         }
1484         cs35l56->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
1485
1486         ret = cs35l56_wait_for_firmware_boot(cs35l56);
1487         if (ret)
1488                 return ret;
1489
1490         ret = regmap_read(cs35l56->regmap, CS35L56_DEVID, &devid);
1491         if (ret < 0) {
1492                 dev_err(cs35l56->dev, "Get Device ID failed\n");
1493                 return ret;
1494         }
1495         devid &= CS35L56_DEVID_MASK;
1496
1497         switch (devid) {
1498         case 0x35A56:
1499                 break;
1500         default:
1501                 dev_err(cs35l56->dev, "Unknown device %x\n", devid);
1502                 return ret;
1503         }
1504
1505         ret = regmap_read(cs35l56->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
1506         if (ret) {
1507                 dev_err(cs35l56->dev, "Get Secure status failed\n");
1508                 return ret;
1509         }
1510
1511         /* When any bus is restricted treat the device as secured */
1512         if (secured & CS35L56_RESTRICTED_MASK)
1513                 cs35l56->secured = true;
1514
1515         ret = regmap_read(cs35l56->regmap, CS35L56_OTPID, &otpid);
1516         if (ret < 0) {
1517                 dev_err(cs35l56->dev, "Get OTP ID failed\n");
1518                 return ret;
1519         }
1520
1521         dev_info(cs35l56->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n",
1522                  cs35l56->secured ? "s" : "", cs35l56->rev, otpid);
1523
1524         /* Populate the DSP information with the revision and security state */
1525         cs35l56->dsp.part = devm_kasprintf(cs35l56->dev, GFP_KERNEL, "cs35l56%s-%02x",
1526                                            cs35l56->secured ? "s" : "", cs35l56->rev);
1527         if (!cs35l56->dsp.part)
1528                 return -ENOMEM;
1529
1530         /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
1531         regmap_write(cs35l56->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
1532         regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_1,
1533                            CS35L56_AMP_SHORT_ERR_EINT1_MASK,
1534                            0);
1535         regmap_update_bits(cs35l56->regmap, CS35L56_IRQ1_MASK_8,
1536                            CS35L56_TEMP_ERR_EINT1_MASK,
1537                            0);
1538
1539         if (!cs35l56->reset_gpio) {
1540                 dev_dbg(cs35l56->dev, "No reset gpio: using soft reset\n");
1541                 cs35l56_system_reset(cs35l56);
1542                 if (cs35l56->sdw_peripheral) {
1543                         /* Keep alive while we wait for re-enumeration */
1544                         pm_runtime_get_noresume(cs35l56->dev);
1545                         return 0;
1546                 }
1547         }
1548
1549 post_soft_reset:
1550         if (cs35l56->soft_resetting) {
1551                 cs35l56->soft_resetting = false;
1552
1553                 /* Done re-enumerating after one-time init so release the keep-alive */
1554                 if (cs35l56->sdw_peripheral && !cs35l56->init_done)
1555                         pm_runtime_put_noidle(cs35l56->dev);
1556
1557                 regcache_mark_dirty(cs35l56->regmap);
1558                 ret = cs35l56_wait_for_firmware_boot(cs35l56);
1559                 if (ret)
1560                         return ret;
1561
1562                 dev_dbg(cs35l56->dev, "Firmware rebooted after soft reset\n");
1563         }
1564
1565         /* Disable auto-hibernate so that runtime_pm has control */
1566         ret = cs35l56_mbox_send(cs35l56, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
1567         if (ret)
1568                 return ret;
1569
1570         /* Populate soft registers in the regmap cache */
1571         cs35l56_reread_firmware_registers(cs35l56->dev, cs35l56->regmap);
1572
1573         /* Registers could be dirty after soft reset or SoundWire enumeration */
1574         regcache_sync(cs35l56->regmap);
1575
1576         cs35l56->init_done = true;
1577         complete(&cs35l56->init_completion);
1578
1579         return 0;
1580 }
1581 EXPORT_SYMBOL_NS_GPL(cs35l56_init, SND_SOC_CS35L56_CORE);
1582
1583 void cs35l56_remove(struct cs35l56_private *cs35l56)
1584 {
1585         cs35l56->init_done = false;
1586
1587         /*
1588          * WAKE IRQs unmask if CS35L56 hibernates so free the handler to
1589          * prevent it racing with remove().
1590          */
1591         if (cs35l56->irq)
1592                 devm_free_irq(cs35l56->dev, cs35l56->irq, cs35l56);
1593
1594         flush_workqueue(cs35l56->dsp_wq);
1595         destroy_workqueue(cs35l56->dsp_wq);
1596
1597         pm_runtime_suspend(cs35l56->dev);
1598         pm_runtime_disable(cs35l56->dev);
1599
1600         regcache_cache_only(cs35l56->regmap, true);
1601
1602         gpiod_set_value_cansleep(cs35l56->reset_gpio, 0);
1603         regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies);
1604 }
1605 EXPORT_SYMBOL_NS_GPL(cs35l56_remove, SND_SOC_CS35L56_CORE);
1606
1607 const struct dev_pm_ops cs35l56_pm_ops_i2c_spi = {
1608         SET_RUNTIME_PM_OPS(cs35l56_runtime_suspend, cs35l56_runtime_resume_i2c_spi, NULL)
1609         SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend, cs35l56_system_resume)
1610         LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early)
1611         NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_no_irq, cs35l56_system_resume_no_irq)
1612 };
1613 EXPORT_SYMBOL_NS_GPL(cs35l56_pm_ops_i2c_spi, SND_SOC_CS35L56_CORE);
1614
1615 MODULE_DESCRIPTION("ASoC CS35L56 driver");
1616 MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
1617 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1618 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
1619 MODULE_LICENSE("GPL");