sound/soc/codecs/cs35l41.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
   4 //
   5 // Copyright 2017-2021 Cirrus Logic, Inc.
   6 //
   7 // Author: David Rhodes <david.rhodes@cirrus.com>
   8
   9 #include <linux/acpi.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/property.h>
  19 #include <sound/initval.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/soc.h>
  23 #include <sound/soc-dapm.h>
  24 #include <sound/tlv.h>
  25
  26 #include "cs35l41.h"
  27
  28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
  29         "VA",
  30         "VP",
  31 };
  32
  33 struct cs35l41_pll_sysclk_config {
  34         int freq;
  35         int clk_cfg;
  36 };
  37
  38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
  39         { 32768,        0x00 },
  40         { 8000,         0x01 },
  41         { 11025,        0x02 },
  42         { 12000,        0x03 },
  43         { 16000,        0x04 },
  44         { 22050,        0x05 },
  45         { 24000,        0x06 },
  46         { 32000,        0x07 },
  47         { 44100,        0x08 },
  48         { 48000,        0x09 },
  49         { 88200,        0x0A },
  50         { 96000,        0x0B },
  51         { 128000,       0x0C },
  52         { 176400,       0x0D },
  53         { 192000,       0x0E },
  54         { 256000,       0x0F },
  55         { 352800,       0x10 },
  56         { 384000,       0x11 },
  57         { 512000,       0x12 },
  58         { 705600,       0x13 },
  59         { 750000,       0x14 },
  60         { 768000,       0x15 },
  61         { 1000000,      0x16 },
  62         { 1024000,      0x17 },
  63         { 1200000,      0x18 },
  64         { 1411200,      0x19 },
  65         { 1500000,      0x1A },
  66         { 1536000,      0x1B },
  67         { 2000000,      0x1C },
  68         { 2048000,      0x1D },
  69         { 2400000,      0x1E },
  70         { 2822400,      0x1F },
  71         { 3000000,      0x20 },
  72         { 3072000,      0x21 },
  73         { 3200000,      0x22 },
  74         { 4000000,      0x23 },
  75         { 4096000,      0x24 },
  76         { 4800000,      0x25 },
  77         { 5644800,      0x26 },
  78         { 6000000,      0x27 },
  79         { 6144000,      0x28 },
  80         { 6250000,      0x29 },
  81         { 6400000,      0x2A },
  82         { 6500000,      0x2B },
  83         { 6750000,      0x2C },
  84         { 7526400,      0x2D },
  85         { 8000000,      0x2E },
  86         { 8192000,      0x2F },
  87         { 9600000,      0x30 },
  88         { 11289600,     0x31 },
  89         { 12000000,     0x32 },
  90         { 12288000,     0x33 },
  91         { 12500000,     0x34 },
  92         { 12800000,     0x35 },
  93         { 13000000,     0x36 },
  94         { 13500000,     0x37 },
  95         { 19200000,     0x38 },
  96         { 22579200,     0x39 },
  97         { 24000000,     0x3A },
  98         { 24576000,     0x3B },
  99         { 25000000,     0x3C },
 100         { 25600000,     0x3D },
 101         { 26000000,     0x3E },
 102         { 27000000,     0x3F },
 103 };
 104
 105 struct cs35l41_fs_mon_config {
 106         int freq;
 107         unsigned int fs1;
 108         unsigned int fs2;
 109 };
 110
 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
 112         { 32768,        2254,   3754 },
 113         { 8000,         9220,   15364 },
 114         { 11025,        6148,   10244 },
 115         { 12000,        6148,   10244 },
 116         { 16000,        4612,   7684 },
 117         { 22050,        3076,   5124 },
 118         { 24000,        3076,   5124 },
 119         { 32000,        2308,   3844 },
 120         { 44100,        1540,   2564 },
 121         { 48000,        1540,   2564 },
 122         { 88200,        772,    1284 },
 123         { 96000,        772,    1284 },
 124         { 128000,       580,    964 },
 125         { 176400,       388,    644 },
 126         { 192000,       388,    644 },
 127         { 256000,       292,    484 },
 128         { 352800,       196,    324 },
 129         { 384000,       196,    324 },
 130         { 512000,       148,    244 },
 131         { 705600,       100,    164 },
 132         { 750000,       100,    164 },
 133         { 768000,       100,    164 },
 134         { 1000000,      76,     124 },
 135         { 1024000,      76,     124 },
 136         { 1200000,      64,     104 },
 137         { 1411200,      52,     84 },
 138         { 1500000,      52,     84 },
 139         { 1536000,      52,     84 },
 140         { 2000000,      40,     64 },
 141         { 2048000,      40,     64 },
 142         { 2400000,      34,     54 },
 143         { 2822400,      28,     44 },
 144         { 3000000,      28,     44 },
 145         { 3072000,      28,     44 },
 146         { 3200000,      27,     42 },
 147         { 4000000,      22,     34 },
 148         { 4096000,      22,     34 },
 149         { 4800000,      19,     29 },
 150         { 5644800,      16,     24 },
 151         { 6000000,      16,     24 },
 152         { 6144000,      16,     24 },
 153         { 12288000,     0,      0 },
 154 };
 155
 156 static int cs35l41_get_fs_mon_config_index(int freq)
 157 {
 158         int i;
 159
 160         for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
 161                 if (cs35l41_fs_mon[i].freq == freq)
 162                         return i;
 163         }
 164
 165         return -EINVAL;
 166 }
 167
 168 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
 169                 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
 170                 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
 171 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0);
 172
 173 static const struct snd_kcontrol_new dre_ctrl =
 174         SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
 175
 176 static const char * const cs35l41_pcm_sftramp_text[] =  {
 177         "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
 178 };
 179
 180 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
 181                             CS35L41_AMP_DIG_VOL_CTRL, 0,
 182                             cs35l41_pcm_sftramp_text);
 183
 184 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
 185                                   struct snd_kcontrol *kcontrol, int event)
 186 {
 187         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 188         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 189         int ret;
 190
 191         switch (event) {
 192         case SND_SOC_DAPM_PRE_PMU:
 193                 if (cs35l41->dsp.cs_dsp.booted)
 194                         return 0;
 195
 196                 return wm_adsp_early_event(w, kcontrol, event);
 197         case SND_SOC_DAPM_PRE_PMD:
 198                 if (cs35l41->dsp.preloaded)
 199                         return 0;
 200
 201                 if (cs35l41->dsp.cs_dsp.running) {
 202                         ret = wm_adsp_event(w, kcontrol, event);
 203                         if (ret)
 204                                 return ret;
 205                 }
 206
 207                 return wm_adsp_early_event(w, kcontrol, event);
 208         default:
 209                 return 0;
 210         }
 211 }
 212
 213 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
 214                                 struct snd_kcontrol *kcontrol, int event)
 215 {
 216         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 217         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 218         unsigned int fw_status;
 219         int ret;
 220
 221         switch (event) {
 222         case SND_SOC_DAPM_POST_PMU:
 223                 if (!cs35l41->dsp.cs_dsp.running)
 224                         return wm_adsp_event(w, kcontrol, event);
 225
 226                 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status);
 227                 if (ret < 0) {
 228                         dev_err(cs35l41->dev,
 229                                 "Failed to read firmware status: %d\n", ret);
 230                         return ret;
 231                 }
 232
 233                 switch (fw_status) {
 234                 case CSPL_MBOX_STS_RUNNING:
 235                 case CSPL_MBOX_STS_PAUSED:
 236                         break;
 237                 default:
 238                         dev_err(cs35l41->dev, "Firmware status is invalid: %u\n",
 239                                 fw_status);
 240                         return -EINVAL;
 241                 }
 242
 243                 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
 244                                                  CSPL_MBOX_CMD_RESUME);
 245         case SND_SOC_DAPM_PRE_PMD:
 246                 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
 247                                                  CSPL_MBOX_CMD_PAUSE);
 248         default:
 249                 return 0;
 250         }
 251 }
 252
 253 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
 254 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
 255 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
 256                                   CS35L41_DAC_PCM1_SRC,
 257                                   0, CS35L41_ASP_SOURCE_MASK,
 258                                   cs35l41_pcm_source_texts,
 259                                   cs35l41_pcm_source_values);
 260
 261 static const struct snd_kcontrol_new pcm_source_mux =
 262         SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
 263
 264 static const char * const cs35l41_tx_input_texts[] = {
 265         "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
 266         "VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
 267 };
 268
 269 static const unsigned int cs35l41_tx_input_values[] = {
 270         0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
 271         CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
 272         CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
 273 };
 274
 275 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
 276                                   CS35L41_ASP_TX1_SRC,
 277                                   0, CS35L41_ASP_SOURCE_MASK,
 278                                   cs35l41_tx_input_texts,
 279                                   cs35l41_tx_input_values);
 280
 281 static const struct snd_kcontrol_new asp_tx1_mux =
 282         SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
 283
 284 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
 285                                   CS35L41_ASP_TX2_SRC,
 286                                   0, CS35L41_ASP_SOURCE_MASK,
 287                                   cs35l41_tx_input_texts,
 288                                   cs35l41_tx_input_values);
 289
 290 static const struct snd_kcontrol_new asp_tx2_mux =
 291         SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
 292
 293 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
 294                                   CS35L41_ASP_TX3_SRC,
 295                                   0, CS35L41_ASP_SOURCE_MASK,
 296                                   cs35l41_tx_input_texts,
 297                                   cs35l41_tx_input_values);
 298
 299 static const struct snd_kcontrol_new asp_tx3_mux =
 300         SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
 301
 302 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
 303                                   CS35L41_ASP_TX4_SRC,
 304                                   0, CS35L41_ASP_SOURCE_MASK,
 305                                   cs35l41_tx_input_texts,
 306                                   cs35l41_tx_input_values);
 307
 308 static const struct snd_kcontrol_new asp_tx4_mux =
 309         SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
 310
 311 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum,
 312                                   CS35L41_DSP1_RX1_SRC,
 313                                   0, CS35L41_ASP_SOURCE_MASK,
 314                                   cs35l41_tx_input_texts,
 315                                   cs35l41_tx_input_values);
 316
 317 static const struct snd_kcontrol_new dsp_rx1_mux =
 318         SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum);
 319
 320 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum,
 321                                   CS35L41_DSP1_RX2_SRC,
 322                                   0, CS35L41_ASP_SOURCE_MASK,
 323                                   cs35l41_tx_input_texts,
 324                                   cs35l41_tx_input_values);
 325
 326 static const struct snd_kcontrol_new dsp_rx2_mux =
 327         SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum);
 328
 329 static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
 330         SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
 331                           3, 0x4CF, 0x391, dig_vol_tlv),
 332         SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
 333                        amp_gain_tlv),
 334         SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
 335         SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
 336         SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
 337         SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
 338         SOC_SINGLE("Aux Noise Gate CH1 Switch",
 339                    CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
 340         SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
 341                    CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
 342         SOC_SINGLE("Aux Noise Gate CH1 Threshold",
 343                    CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
 344         SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
 345                    CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
 346         SOC_SINGLE("Aux Noise Gate CH2 Switch",
 347                    CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
 348         SOC_SINGLE("Aux Noise Gate CH2 Threshold",
 349                    CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
 350         SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
 351         SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
 352         SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
 353                    CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
 354         SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
 355                    CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
 356         WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
 357         WM_ADSP_FW_CONTROL("DSP1", 0),
 358 };
 359
 360 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable)
 361 {
 362         switch (cs35l41->hw_cfg.bst_type) {
 363         case CS35L41_INT_BOOST:
 364         case CS35L41_SHD_BOOST_ACTV:
 365                 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF;
 366                 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
 367                                 enable << CS35L41_BST_EN_SHIFT);
 368                 break;
 369         default:
 370                 break;
 371         }
 372 }
 373
 374
 375 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit,
 376                                   unsigned int rel_err_bit)
 377 {
 378         regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit);
 379         regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 380         regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit);
 381         regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0);
 382 }
 383
 384 static irqreturn_t cs35l41_irq(int irq, void *data)
 385 {
 386         struct cs35l41_private *cs35l41 = data;
 387         unsigned int status[4] = { 0, 0, 0, 0 };
 388         unsigned int masks[4] = { 0, 0, 0, 0 };
 389         int ret = IRQ_NONE;
 390         unsigned int i;
 391
 392         pm_runtime_get_sync(cs35l41->dev);
 393
 394         for (i = 0; i < ARRAY_SIZE(status); i++) {
 395                 regmap_read(cs35l41->regmap,
 396                             CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
 397                             &status[i]);
 398                 regmap_read(cs35l41->regmap,
 399                             CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
 400                             &masks[i]);
 401         }
 402
 403         /* Check to see if unmasked bits are active */
 404         if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
 405             !(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
 406                 goto done;
 407
 408         if (status[3] & CS35L41_OTP_BOOT_DONE) {
 409                 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
 410                                    CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
 411         }
 412
 413         /*
 414          * The following interrupts require a
 415          * protection release cycle to get the
 416          * speaker out of Safe-Mode.
 417          */
 418         if (status[0] & CS35L41_AMP_SHORT_ERR) {
 419                 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
 420                 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS);
 421                 ret = IRQ_HANDLED;
 422         }
 423
 424         if (status[0] & CS35L41_TEMP_WARN) {
 425                 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
 426                 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS);
 427                 ret = IRQ_HANDLED;
 428         }
 429
 430         if (status[0] & CS35L41_TEMP_ERR) {
 431                 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
 432                 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS);
 433                 ret = IRQ_HANDLED;
 434         }
 435
 436         if (status[0] & CS35L41_BST_OVP_ERR) {
 437                 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
 438                 cs35l41_boost_enable(cs35l41, 0);
 439                 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS);
 440                 cs35l41_boost_enable(cs35l41, 1);
 441                 ret = IRQ_HANDLED;
 442         }
 443
 444         if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
 445                 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
 446                 cs35l41_boost_enable(cs35l41, 0);
 447                 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS);
 448                 cs35l41_boost_enable(cs35l41, 1);
 449                 ret = IRQ_HANDLED;
 450         }
 451
 452         if (status[0] & CS35L41_BST_SHORT_ERR) {
 453                 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
 454                 cs35l41_boost_enable(cs35l41, 0);
 455                 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS);
 456                 cs35l41_boost_enable(cs35l41, 1);
 457                 ret = IRQ_HANDLED;
 458         }
 459
 460         if (status[2] & CS35L41_PLL_LOCK) {
 461                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK);
 462
 463                 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV ||
 464                     cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS) {
 465                         ret = cs35l41_mdsync_up(cs35l41->regmap);
 466                         if (ret)
 467                                 dev_err(cs35l41->dev, "MDSYNC-up failed: %d\n", ret);
 468                         else
 469                                 dev_dbg(cs35l41->dev, "MDSYNC-up done\n");
 470
 471                         dev_dbg(cs35l41->dev, "PUP-done status: %d\n",
 472                                 !!(status[0] & CS35L41_PUP_DONE_MASK));
 473                 }
 474
 475                 ret = IRQ_HANDLED;
 476         }
 477
 478 done:
 479         pm_runtime_mark_last_busy(cs35l41->dev);
 480         pm_runtime_put_autosuspend(cs35l41->dev);
 481
 482         return ret;
 483 }
 484
 485 static const struct reg_sequence cs35l41_pup_patch[] = {
 486         { CS35L41_TEST_KEY_CTL, 0x00000055 },
 487         { CS35L41_TEST_KEY_CTL, 0x000000AA },
 488         { 0x00002084, 0x002F1AA0 },
 489         { CS35L41_TEST_KEY_CTL, 0x000000CC },
 490         { CS35L41_TEST_KEY_CTL, 0x00000033 },
 491 };
 492
 493 static const struct reg_sequence cs35l41_pdn_patch[] = {
 494         { CS35L41_TEST_KEY_CTL, 0x00000055 },
 495         { CS35L41_TEST_KEY_CTL, 0x000000AA },
 496         { 0x00002084, 0x002F1AA3 },
 497         { CS35L41_TEST_KEY_CTL, 0x000000CC },
 498         { CS35L41_TEST_KEY_CTL, 0x00000033 },
 499 };
 500
 501 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
 502                                   struct snd_kcontrol *kcontrol, int event)
 503 {
 504         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 505         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 506         int ret = 0;
 507
 508         switch (event) {
 509         case SND_SOC_DAPM_PRE_PMU:
 510                 regmap_multi_reg_write_bypassed(cs35l41->regmap,
 511                                                 cs35l41_pup_patch,
 512                                                 ARRAY_SIZE(cs35l41_pup_patch));
 513
 514                 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
 515                                             1, cs35l41->dsp.cs_dsp.running);
 516                 break;
 517         case SND_SOC_DAPM_POST_PMD:
 518                 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
 519                                             0, cs35l41->dsp.cs_dsp.running);
 520
 521                 regmap_multi_reg_write_bypassed(cs35l41->regmap,
 522                                                 cs35l41_pdn_patch,
 523                                                 ARRAY_SIZE(cs35l41_pdn_patch));
 524                 break;
 525         default:
 526                 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
 527                 ret = -EINVAL;
 528         }
 529
 530         return ret;
 531 }
 532
 533 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
 534         SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
 535         SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
 536                               cs35l41_dsp_preload_ev,
 537                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
 538         SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
 539                                cs35l41_dsp_audio_ev,
 540                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 541
 542         SND_SOC_DAPM_OUTPUT("SPK"),
 543
 544         SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
 545         SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
 546         SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
 547         SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
 548         SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
 549         SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
 550
 551         SND_SOC_DAPM_SIGGEN("VSENSE"),
 552         SND_SOC_DAPM_SIGGEN("ISENSE"),
 553         SND_SOC_DAPM_SIGGEN("VP"),
 554         SND_SOC_DAPM_SIGGEN("VBST"),
 555         SND_SOC_DAPM_SIGGEN("TEMP"),
 556
 557         SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0),
 558         SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0),
 559         SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0),
 560         SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0),
 561         SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0),
 562
 563         SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 564         SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 565         SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 566         SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 567         SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 568
 569         SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
 570
 571         SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
 572                                cs35l41_main_amp_event,
 573                                SND_SOC_DAPM_POST_PMD |  SND_SOC_DAPM_PRE_PMU),
 574
 575         SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
 576         SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
 577         SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
 578         SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
 579         SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux),
 580         SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux),
 581         SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
 582         SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
 583 };
 584
 585 static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
 586         {"DSP RX1 Source", "ASPRX1", "ASPRX1"},
 587         {"DSP RX1 Source", "ASPRX2", "ASPRX2"},
 588         {"DSP RX2 Source", "ASPRX1", "ASPRX1"},
 589         {"DSP RX2 Source", "ASPRX2", "ASPRX2"},
 590
 591         {"DSP1", NULL, "DSP RX1 Source"},
 592         {"DSP1", NULL, "DSP RX2 Source"},
 593
 594         {"ASP TX1 Source", "VMON", "VMON ADC"},
 595         {"ASP TX1 Source", "IMON", "IMON ADC"},
 596         {"ASP TX1 Source", "VPMON", "VPMON ADC"},
 597         {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
 598         {"ASP TX1 Source", "DSPTX1", "DSP1"},
 599         {"ASP TX1 Source", "DSPTX2", "DSP1"},
 600         {"ASP TX1 Source", "ASPRX1", "ASPRX1" },
 601         {"ASP TX1 Source", "ASPRX2", "ASPRX2" },
 602         {"ASP TX2 Source", "VMON", "VMON ADC"},
 603         {"ASP TX2 Source", "IMON", "IMON ADC"},
 604         {"ASP TX2 Source", "VPMON", "VPMON ADC"},
 605         {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
 606         {"ASP TX2 Source", "DSPTX1", "DSP1"},
 607         {"ASP TX2 Source", "DSPTX2", "DSP1"},
 608         {"ASP TX2 Source", "ASPRX1", "ASPRX1" },
 609         {"ASP TX2 Source", "ASPRX2", "ASPRX2" },
 610         {"ASP TX3 Source", "VMON", "VMON ADC"},
 611         {"ASP TX3 Source", "IMON", "IMON ADC"},
 612         {"ASP TX3 Source", "VPMON", "VPMON ADC"},
 613         {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
 614         {"ASP TX3 Source", "DSPTX1", "DSP1"},
 615         {"ASP TX3 Source", "DSPTX2", "DSP1"},
 616         {"ASP TX3 Source", "ASPRX1", "ASPRX1" },
 617         {"ASP TX3 Source", "ASPRX2", "ASPRX2" },
 618         {"ASP TX4 Source", "VMON", "VMON ADC"},
 619         {"ASP TX4 Source", "IMON", "IMON ADC"},
 620         {"ASP TX4 Source", "VPMON", "VPMON ADC"},
 621         {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
 622         {"ASP TX4 Source", "DSPTX1", "DSP1"},
 623         {"ASP TX4 Source", "DSPTX2", "DSP1"},
 624         {"ASP TX4 Source", "ASPRX1", "ASPRX1" },
 625         {"ASP TX4 Source", "ASPRX2", "ASPRX2" },
 626         {"ASPTX1", NULL, "ASP TX1 Source"},
 627         {"ASPTX2", NULL, "ASP TX2 Source"},
 628         {"ASPTX3", NULL, "ASP TX3 Source"},
 629         {"ASPTX4", NULL, "ASP TX4 Source"},
 630         {"AMP Capture", NULL, "ASPTX1"},
 631         {"AMP Capture", NULL, "ASPTX2"},
 632         {"AMP Capture", NULL, "ASPTX3"},
 633         {"AMP Capture", NULL, "ASPTX4"},
 634
 635         {"DSP1", NULL, "VMON"},
 636         {"DSP1", NULL, "IMON"},
 637         {"DSP1", NULL, "VPMON"},
 638         {"DSP1", NULL, "VBSTMON"},
 639         {"DSP1", NULL, "TEMPMON"},
 640
 641         {"VMON ADC", NULL, "VMON"},
 642         {"IMON ADC", NULL, "IMON"},
 643         {"VPMON ADC", NULL, "VPMON"},
 644         {"VBSTMON ADC", NULL, "VBSTMON"},
 645         {"TEMPMON ADC", NULL, "TEMPMON"},
 646
 647         {"VMON ADC", NULL, "VSENSE"},
 648         {"IMON ADC", NULL, "ISENSE"},
 649         {"VPMON ADC", NULL, "VP"},
 650         {"VBSTMON ADC", NULL, "VBST"},
 651         {"TEMPMON ADC", NULL, "TEMP"},
 652
 653         {"DSP1 Preload", NULL, "DSP1 Preloader"},
 654         {"DSP1", NULL, "DSP1 Preloader"},
 655
 656         {"ASPRX1", NULL, "AMP Playback"},
 657         {"ASPRX2", NULL, "AMP Playback"},
 658         {"DRE", "Switch", "CLASS H"},
 659         {"Main AMP", NULL, "CLASS H"},
 660         {"Main AMP", NULL, "DRE"},
 661         {"SPK", NULL, "Main AMP"},
 662
 663         {"PCM Source", "ASP", "ASPRX1"},
 664         {"PCM Source", "DSP", "DSP1"},
 665         {"CLASS H", NULL, "PCM Source"},
 666 };
 667
 668 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n,
 669                                    unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot)
 670 {
 671         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 672
 673         return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot);
 674 }
 675
 676 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 677 {
 678         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 679         unsigned int daifmt = 0;
 680
 681         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 682         case SND_SOC_DAIFMT_CBP_CFP:
 683                 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK;
 684                 break;
 685         case SND_SOC_DAIFMT_CBC_CFC:
 686                 break;
 687         default:
 688                 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n");
 689                 return -EINVAL;
 690         }
 691
 692         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 693         case SND_SOC_DAIFMT_DSP_A:
 694                 break;
 695         case SND_SOC_DAIFMT_I2S:
 696                 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT;
 697                 break;
 698         default:
 699                 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n");
 700                 return -EINVAL;
 701         }
 702
 703         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 704         case SND_SOC_DAIFMT_NB_IF:
 705                 daifmt |= CS35L41_LRCLK_INV_MASK;
 706                 break;
 707         case SND_SOC_DAIFMT_IB_NF:
 708                 daifmt |= CS35L41_SCLK_INV_MASK;
 709                 break;
 710         case SND_SOC_DAIFMT_IB_IF:
 711                 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK;
 712                 break;
 713         case SND_SOC_DAIFMT_NB_NF:
 714                 break;
 715         default:
 716                 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n");
 717                 return -EINVAL;
 718         }
 719
 720         return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
 721                                   CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK |
 722                                   CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK |
 723                                   CS35L41_SCLK_INV_MASK, daifmt);
 724 }
 725
 726 struct cs35l41_global_fs_config {
 727         int rate;
 728         int fs_cfg;
 729 };
 730
 731 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
 732         { 12000,        0x01 },
 733         { 24000,        0x02 },
 734         { 48000,        0x03 },
 735         { 96000,        0x04 },
 736         { 192000,       0x05 },
 737         { 11025,        0x09 },
 738         { 22050,        0x0A },
 739         { 44100,        0x0B },
 740         { 88200,        0x0C },
 741         { 176400,       0x0D },
 742         { 8000,         0x11 },
 743         { 16000,        0x12 },
 744         { 32000,        0x13 },
 745 };
 746
 747 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
 748                                  struct snd_pcm_hw_params *params,
 749                                  struct snd_soc_dai *dai)
 750 {
 751         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 752         unsigned int rate = params_rate(params);
 753         u8 asp_wl;
 754         int i;
 755
 756         for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
 757                 if (rate == cs35l41_fs_rates[i].rate)
 758                         break;
 759         }
 760
 761         if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
 762                 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate);
 763                 return -EINVAL;
 764         }
 765
 766         asp_wl = params_width(params);
 767
 768         if (i < ARRAY_SIZE(cs35l41_fs_rates))
 769                 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
 770                                    CS35L41_GLOBAL_FS_MASK,
 771                                    cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
 772
 773         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 774                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
 775                                    CS35L41_ASP_WIDTH_RX_MASK,
 776                                    asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
 777                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
 778                                    CS35L41_ASP_RX_WL_MASK,
 779                                    asp_wl << CS35L41_ASP_RX_WL_SHIFT);
 780         } else {
 781                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
 782                                    CS35L41_ASP_WIDTH_TX_MASK,
 783                                    asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
 784                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
 785                                    CS35L41_ASP_TX_WL_MASK,
 786                                    asp_wl << CS35L41_ASP_TX_WL_SHIFT);
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int cs35l41_get_clk_config(int freq)
 793 {
 794         int i;
 795
 796         for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
 797                 if (cs35l41_pll_sysclk[i].freq == freq)
 798                         return cs35l41_pll_sysclk[i].clk_cfg;
 799         }
 800
 801         return -EINVAL;
 802 }
 803
 804 static const unsigned int cs35l41_src_rates[] = {
 805         8000, 12000, 11025, 16000, 22050, 24000, 32000,
 806         44100, 48000, 88200, 96000, 176400, 192000
 807 };
 808
 809 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = {
 810         .count = ARRAY_SIZE(cs35l41_src_rates),
 811         .list = cs35l41_src_rates,
 812 };
 813
 814 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
 815                                struct snd_soc_dai *dai)
 816 {
 817         if (substream->runtime)
 818                 return snd_pcm_hw_constraint_list(substream->runtime, 0,
 819                                                   SNDRV_PCM_HW_PARAM_RATE,
 820                                                   &cs35l41_constraints);
 821         return 0;
 822 }
 823
 824 static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
 825                                         int clk_id, int source,
 826                                         unsigned int freq, int dir)
 827 {
 828         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 829         int extclk_cfg, clksrc;
 830
 831         switch (clk_id) {
 832         case CS35L41_CLKID_SCLK:
 833                 clksrc = CS35L41_PLLSRC_SCLK;
 834                 break;
 835         case CS35L41_CLKID_LRCLK:
 836                 clksrc = CS35L41_PLLSRC_LRCLK;
 837                 break;
 838         case CS35L41_CLKID_MCLK:
 839                 clksrc = CS35L41_PLLSRC_MCLK;
 840                 break;
 841         default:
 842                 dev_err(cs35l41->dev, "Invalid CLK Config\n");
 843                 return -EINVAL;
 844         }
 845
 846         extclk_cfg = cs35l41_get_clk_config(freq);
 847
 848         if (extclk_cfg < 0) {
 849                 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
 850                         extclk_cfg, freq);
 851                 return -EINVAL;
 852         }
 853
 854         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 855                            CS35L41_PLL_OPENLOOP_MASK,
 856                            1 << CS35L41_PLL_OPENLOOP_SHIFT);
 857         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 858                            CS35L41_REFCLK_FREQ_MASK,
 859                            extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
 860         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 861                            CS35L41_PLL_CLK_EN_MASK,
 862                            0 << CS35L41_PLL_CLK_EN_SHIFT);
 863         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 864                            CS35L41_PLL_CLK_SEL_MASK, clksrc);
 865         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 866                            CS35L41_PLL_OPENLOOP_MASK,
 867                            0 << CS35L41_PLL_OPENLOOP_SHIFT);
 868         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 869                            CS35L41_PLL_CLK_EN_MASK,
 870                            1 << CS35L41_PLL_CLK_EN_SHIFT);
 871
 872         return 0;
 873 }
 874
 875 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
 876                                   int clk_id, unsigned int freq, int dir)
 877 {
 878         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 879         unsigned int fs1_val;
 880         unsigned int fs2_val;
 881         unsigned int val;
 882         int fsindex;
 883
 884         fsindex = cs35l41_get_fs_mon_config_index(freq);
 885         if (fsindex < 0) {
 886                 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
 887                 return -EINVAL;
 888         }
 889
 890         dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
 891
 892         if (freq <= 6144000) {
 893                 /* Use the lookup table */
 894                 fs1_val = cs35l41_fs_mon[fsindex].fs1;
 895                 fs2_val = cs35l41_fs_mon[fsindex].fs2;
 896         } else {
 897                 /* Use hard-coded values */
 898                 fs1_val = 0x10;
 899                 fs2_val = 0x24;
 900         }
 901
 902         val = fs1_val;
 903         val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
 904         regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
 905
 906         return 0;
 907 }
 908
 909 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
 910 {
 911         struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
 912         int ret;
 913
 914         if (!hw_cfg->valid)
 915                 return -EINVAL;
 916
 917         if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
 918                 return -EINVAL;
 919
 920         /* Required */
 921         ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
 922         if (ret)
 923                 return ret;
 924
 925         /* Optional */
 926         if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0)
 927                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK,
 928                                    hw_cfg->dout_hiz);
 929
 930         return 0;
 931 }
 932
 933 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = {
 934         {"Main AMP", NULL, "VSPK"},
 935 };
 936
 937 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = {
 938         SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0),
 939 };
 940
 941 static int cs35l41_component_probe(struct snd_soc_component *component)
 942 {
 943         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 944         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 945         int ret;
 946
 947         if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) {
 948                 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget,
 949                                                 ARRAY_SIZE(cs35l41_ext_bst_widget));
 950                 if (ret)
 951                         return ret;
 952
 953                 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes,
 954                                               ARRAY_SIZE(cs35l41_ext_bst_routes));
 955                 if (ret)
 956                         return ret;
 957         }
 958
 959         return wm_adsp2_component_probe(&cs35l41->dsp, component);
 960 }
 961
 962 static void cs35l41_component_remove(struct snd_soc_component *component)
 963 {
 964         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 965
 966         wm_adsp2_component_remove(&cs35l41->dsp, component);
 967 }
 968
 969 static const struct snd_soc_dai_ops cs35l41_ops = {
 970         .startup = cs35l41_pcm_startup,
 971         .set_fmt = cs35l41_set_dai_fmt,
 972         .hw_params = cs35l41_pcm_hw_params,
 973         .set_sysclk = cs35l41_dai_set_sysclk,
 974         .set_channel_map = cs35l41_set_channel_map,
 975 };
 976
 977 static struct snd_soc_dai_driver cs35l41_dai[] = {
 978         {
 979                 .name = "cs35l41-pcm",
 980                 .id = 0,
 981                 .playback = {
 982                         .stream_name = "AMP Playback",
 983                         .channels_min = 1,
 984                         .channels_max = 2,
 985                         .rates = SNDRV_PCM_RATE_KNOT,
 986                         .formats = CS35L41_RX_FORMATS,
 987                 },
 988                 .capture = {
 989                         .stream_name = "AMP Capture",
 990                         .channels_min = 1,
 991                         .channels_max = 4,
 992                         .rates = SNDRV_PCM_RATE_KNOT,
 993                         .formats = CS35L41_TX_FORMATS,
 994                 },
 995                 .ops = &cs35l41_ops,
 996                 .symmetric_rate = 1,
 997         },
 998 };
 999
1000 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
1001         .name = "cs35l41-codec",
1002         .probe = cs35l41_component_probe,
1003         .remove = cs35l41_component_remove,
1004
1005         .dapm_widgets = cs35l41_dapm_widgets,
1006         .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
1007         .dapm_routes = cs35l41_audio_map,
1008         .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
1009
1010         .controls = cs35l41_aud_controls,
1011         .num_controls = ARRAY_SIZE(cs35l41_aud_controls),
1012         .set_sysclk = cs35l41_component_set_sysclk,
1013
1014         .endianness = 1,
1015 };
1016
1017 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg)
1018 {
1019         struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
1020         struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
1021         unsigned int val;
1022         int ret;
1023
1024         /* Some ACPI systems received the Shared Boost feature before the upstream driver,
1025          * leaving those systems with deprecated _DSD properties.
1026          * To correctly configure those systems add shared-boost-active and shared-boost-passive
1027          * properties mapped to the correct value in boost-type.
1028          * These two are not DT properties and should not be used in new systems designs.
1029          */
1030         if (device_property_read_bool(dev, "cirrus,shared-boost-active")) {
1031                 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV;
1032         } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) {
1033                 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS;
1034         } else {
1035                 ret = device_property_read_u32(dev, "cirrus,boost-type", &val);
1036                 if (ret >= 0)
1037                         hw_cfg->bst_type = val;
1038         }
1039
1040         ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
1041         if (ret >= 0)
1042                 hw_cfg->bst_ipk = val;
1043         else
1044                 hw_cfg->bst_ipk = -1;
1045
1046         ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
1047         if (ret >= 0)
1048                 hw_cfg->bst_ind = val;
1049         else
1050                 hw_cfg->bst_ind = -1;
1051
1052         ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
1053         if (ret >= 0)
1054                 hw_cfg->bst_cap = val;
1055         else
1056                 hw_cfg->bst_cap = -1;
1057
1058         ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
1059         if (ret >= 0)
1060                 hw_cfg->dout_hiz = val;
1061         else
1062                 hw_cfg->dout_hiz = -1;
1063
1064         /* GPIO1 Pin Config */
1065         gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert");
1066         gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable");
1067         ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val);
1068         if (ret >= 0) {
1069                 gpio1->func = val;
1070                 gpio1->valid = true;
1071         }
1072
1073         /* GPIO2 Pin Config */
1074         gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert");
1075         gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable");
1076         ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val);
1077         if (ret >= 0) {
1078                 gpio2->func = val;
1079                 gpio2->valid = true;
1080         }
1081
1082         hw_cfg->valid = true;
1083
1084         return 0;
1085 }
1086
1087 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
1088 {
1089         struct wm_adsp *dsp;
1090         int ret;
1091
1092         dsp = &cs35l41->dsp;
1093         dsp->part = "cs35l41";
1094         dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
1095         dsp->toggle_preload = true;
1096
1097         cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);
1098
1099         ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
1100         if (ret < 0)
1101                 return ret;
1102
1103         ret = wm_halo_init(dsp);
1104         if (ret) {
1105                 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret);
1106                 return ret;
1107         }
1108
1109         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC,
1110                            CS35L41_INPUT_SRC_VPMON);
1111         if (ret < 0) {
1112                 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret);
1113                 goto err_dsp;
1114         }
1115         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC,
1116                            CS35L41_INPUT_SRC_CLASSH);
1117         if (ret < 0) {
1118                 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret);
1119                 goto err_dsp;
1120         }
1121         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,
1122                            CS35L41_INPUT_SRC_TEMPMON);
1123         if (ret < 0) {
1124                 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret);
1125                 goto err_dsp;
1126         }
1127         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,
1128                            CS35L41_INPUT_SRC_RSVD);
1129         if (ret < 0) {
1130                 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret);
1131                 goto err_dsp;
1132         }
1133
1134         return 0;
1135
1136 err_dsp:
1137         wm_adsp2_remove(dsp);
1138
1139         return ret;
1140 }
1141
1142 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
1143 {
1144         acpi_handle handle = ACPI_HANDLE(cs35l41->dev);
1145         const char *sub;
1146
1147         /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */
1148         if (!handle)
1149                 return 0;
1150
1151         sub = acpi_get_subsystem_id(handle);
1152         if (IS_ERR(sub)) {
1153                 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */
1154                 if (PTR_ERR(sub) == -ENODATA)
1155                         return 0;
1156                 else
1157                         return PTR_ERR(sub);
1158         }
1159
1160         cs35l41->dsp.system_name = sub;
1161         dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name);
1162
1163         return 0;
1164 }
1165
1166 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg)
1167 {
1168         u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
1169         int irq_pol = 0;
1170         int ret;
1171
1172         if (hw_cfg) {
1173                 cs35l41->hw_cfg = *hw_cfg;
1174         } else {
1175                 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg);
1176                 if (ret != 0)
1177                         return ret;
1178         }
1179
1180         for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
1181                 cs35l41->supplies[i].supply = cs35l41_supplies[i];
1182
1183         ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
1184                                       cs35l41->supplies);
1185         if (ret != 0) {
1186                 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret);
1187                 return ret;
1188         }
1189
1190         ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1191         if (ret != 0) {
1192                 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret);
1193                 return ret;
1194         }
1195
1196         /* returning NULL can be an option if in stereo mode */
1197         cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
1198                                                       GPIOD_OUT_LOW);
1199         if (IS_ERR(cs35l41->reset_gpio)) {
1200                 ret = PTR_ERR(cs35l41->reset_gpio);
1201                 cs35l41->reset_gpio = NULL;
1202                 if (ret == -EBUSY) {
1203                         dev_info(cs35l41->dev,
1204                                  "Reset line busy, assuming shared reset\n");
1205                 } else {
1206                         dev_err(cs35l41->dev,
1207                                 "Failed to get reset GPIO: %d\n", ret);
1208                         goto err;
1209                 }
1210         }
1211         if (cs35l41->reset_gpio) {
1212                 /* satisfy minimum reset pulse width spec */
1213                 usleep_range(2000, 2100);
1214                 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
1215         }
1216
1217         usleep_range(2000, 2100);
1218
1219         ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4,
1220                                        int_status, int_status & CS35L41_OTP_BOOT_DONE,
1221                                        1000, 100000);
1222         if (ret) {
1223                 dev_err(cs35l41->dev,
1224                         "Failed waiting for OTP_BOOT_DONE: %d\n", ret);
1225                 goto err;
1226         }
1227
1228         regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
1229         if (int_status & CS35L41_OTP_BOOT_ERR) {
1230                 dev_err(cs35l41->dev, "OTP Boot error\n");
1231                 ret = -EINVAL;
1232                 goto err;
1233         }
1234
1235         ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, &regid);
1236         if (ret < 0) {
1237                 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret);
1238                 goto err;
1239         }
1240
1241         ret = regmap_read(cs35l41->regmap, CS35L41_REVID, &reg_revid);
1242         if (ret < 0) {
1243                 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret);
1244                 goto err;
1245         }
1246
1247         mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
1248
1249         /* CS35L41 will have even MTLREVID
1250          * CS35L41R will have odd MTLREVID
1251          */
1252         chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
1253         if (regid != chipid_match) {
1254                 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
1255                         regid, chipid_match);
1256                 ret = -ENODEV;
1257                 goto err;
1258         }
1259
1260         cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1261
1262         ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
1263         if (ret)
1264                 goto err;
1265
1266         ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
1267         if (ret < 0) {
1268                 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret);
1269                 goto err;
1270         }
1271
1272         cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1273
1274         irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg);
1275
1276         /* Set interrupt masks for critical errors */
1277         regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
1278                      CS35L41_INT1_MASK_DEFAULT);
1279         if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1280             cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1281                 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1282                                    0 << CS35L41_INT3_PLL_LOCK_SHIFT);
1283
1284         ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
1285                                         IRQF_ONESHOT | IRQF_SHARED | irq_pol,
1286                                         "cs35l41", cs35l41);
1287         if (ret != 0) {
1288                 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
1289                 goto err;
1290         }
1291
1292         ret = cs35l41_set_pdata(cs35l41);
1293         if (ret < 0) {
1294                 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret);
1295                 goto err;
1296         }
1297
1298         ret = cs35l41_acpi_get_name(cs35l41);
1299         if (ret < 0)
1300                 goto err;
1301
1302         ret = cs35l41_dsp_init(cs35l41);
1303         if (ret < 0)
1304                 goto err;
1305
1306         pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
1307         pm_runtime_use_autosuspend(cs35l41->dev);
1308         pm_runtime_mark_last_busy(cs35l41->dev);
1309         pm_runtime_set_active(cs35l41->dev);
1310         pm_runtime_get_noresume(cs35l41->dev);
1311         pm_runtime_enable(cs35l41->dev);
1312
1313         ret = devm_snd_soc_register_component(cs35l41->dev,
1314                                               &soc_component_dev_cs35l41,
1315                                               cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
1316         if (ret < 0) {
1317                 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret);
1318                 goto err_pm;
1319         }
1320
1321         pm_runtime_put_autosuspend(cs35l41->dev);
1322
1323         dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
1324                  regid, reg_revid);
1325
1326         return 0;
1327
1328 err_pm:
1329         pm_runtime_disable(cs35l41->dev);
1330         pm_runtime_put_noidle(cs35l41->dev);
1331
1332         wm_adsp2_remove(&cs35l41->dsp);
1333 err:
1334         cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1335         regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1336         gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1337
1338         return ret;
1339 }
1340 EXPORT_SYMBOL_GPL(cs35l41_probe);
1341
1342 void cs35l41_remove(struct cs35l41_private *cs35l41)
1343 {
1344         pm_runtime_get_sync(cs35l41->dev);
1345         pm_runtime_disable(cs35l41->dev);
1346
1347         regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
1348         if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1349             cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1350                 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1351                                    1 << CS35L41_INT3_PLL_LOCK_SHIFT);
1352         kfree(cs35l41->dsp.system_name);
1353         wm_adsp2_remove(&cs35l41->dsp);
1354         cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1355
1356         pm_runtime_put_noidle(cs35l41->dev);
1357
1358         regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1359         gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1360 }
1361 EXPORT_SYMBOL_GPL(cs35l41_remove);
1362
1363 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev)
1364 {
1365         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1366
1367         dev_dbg(cs35l41->dev, "Runtime suspend\n");
1368
1369         if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1370                 return 0;
1371
1372         cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1373
1374         regcache_cache_only(cs35l41->regmap, true);
1375         regcache_mark_dirty(cs35l41->regmap);
1376
1377         return 0;
1378 }
1379
1380 static int __maybe_unused cs35l41_runtime_resume(struct device *dev)
1381 {
1382         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1383         int ret;
1384
1385         dev_dbg(cs35l41->dev, "Runtime resume\n");
1386
1387         if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1388                 return 0;
1389
1390         regcache_cache_only(cs35l41->regmap, false);
1391
1392         ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
1393         if (ret)
1394                 return ret;
1395
1396         /* Test key needs to be unlocked to allow the OTP settings to re-apply */
1397         cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1398         ret = regcache_sync(cs35l41->regmap);
1399         cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1400         if (ret) {
1401                 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
1402                 return ret;
1403         }
1404         cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
1405
1406         return 0;
1407 }
1408
1409 static int __maybe_unused cs35l41_sys_suspend(struct device *dev)
1410 {
1411         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1412
1413         dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n");
1414         disable_irq(cs35l41->irq);
1415
1416         return 0;
1417 }
1418
1419 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev)
1420 {
1421         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1422
1423         dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n");
1424         enable_irq(cs35l41->irq);
1425
1426         return 0;
1427 }
1428
1429 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev)
1430 {
1431         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1432
1433         dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n");
1434         disable_irq(cs35l41->irq);
1435
1436         return 0;
1437 }
1438
1439 static int __maybe_unused cs35l41_sys_resume(struct device *dev)
1440 {
1441         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1442
1443         dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n");
1444         enable_irq(cs35l41->irq);
1445
1446         return 0;
1447 }
1448
1449 const struct dev_pm_ops cs35l41_pm_ops = {
1450         SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL)
1451
1452         SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume)
1453         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq)
1454 };
1455 EXPORT_SYMBOL_GPL(cs35l41_pm_ops);
1456
1457 MODULE_DESCRIPTION("ASoC CS35L41 driver");
1458 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
1459 MODULE_LICENSE("GPL");